Hi Mitch,
In general, I like the idea of removing some of the pointless/awkward
templates we have in gem5. I would definitely support moving in this
direction. However, I really dislike the idea of reviewing a 32k line
patch. Reviewing such a patch would be a headache and I suspect RB would
Hi Alex,
I had a quick look trying to reproduce the problem, but didn't manage to
do so. However, I remember this being a problem when I initially
developed the KVM stuff. I don't think it is related to changeset
5c2ecad1a3c9, instead I'd suspect it's something that happened before that.
In
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In general, I like the idea of having a proper, architected, page table
On July 14, 2014, 7:36 p.m., Andreas Sandberg wrote:
In general, I like the idea of having a proper, architected, page table in
SE-mode. Long-term, this could hopefully mean that we can get rid of many
of the differences between SE- and FS-mode.
High-level comments:
* Write a
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Could you split this into two (or potentially three) different patches?
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Overall, I think this patch looks good and the refactoring is a
On 16/07/14 11:01, Jiuyue Ma via gem5-dev wrote:
On July 15, 2014, 1:26 p.m., Andreas Sandberg wrote:
Could you split this into two (or potentially three) different patches?
The PCI/ISA bus ID fixes look fine and should definitely go upstream ASAP. As
far as I'm concerned that particular
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Ship it!
Thanks for taking the time to fix this! This looks good, I'm
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Thanks for fixing this!
The changeset looks good, but I'd
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I'm sorry I didn't spot this earlier, but it seems like you forgot to
On July 17, 2014, 10:35 a.m., Andreas Sandberg wrote:
I'm sorry I didn't spot this earlier, but it seems like you forgot to
include the ethernet device's interrupt in the MP table. See the interrupt
declaration for pci_dev4_inta for an example. Without that entry, Linux
won't be able
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Ship it!
LGTM. Thanks for fixing this!
- Andreas Sandberg
On July
changeset 84b4d6af0ecc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=84b4d6af0ecc
description:
util: Fix state leakage in the SortIncludes style verifier
There are cases where the state of a SortIncludes object gets messed
up and leaks between
changeset c7187ee80868 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c7187ee80868
description:
scons: Build the branch predictor for all CPUs
The branch predictor is normally only built when a CPU that uses a
branch predictor is built. The list of
changeset ef888b246cd0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ef888b246cd0
description:
base: Remove unused M5_PRAGMA_NORETURN
The M5_PRAGMA_NORETURN macro was only used in for
__exit_message. Since the macro only holds a stub definition and
changeset faa9dfc465ef in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=faa9dfc465ef
description:
power: Remove unused private members to fix compile-time warning
Certain versions of clang complain about unused private members if
they are not used.
changeset 362875aec1ba in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=362875aec1ba
description:
scons: Silence clang 3.4 warnings on Ubuntu 12.04
This changeset fixes three types of warnings that occur in clang 3.4
on Ubuntu 12.04:
*
changeset 4cbfdcdb2144 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4cbfdcdb2144
description:
cpu: Don't forward declare RefCountingPtr
RefCountingPtr is sometimes forward declared to avoid having to
include refcnt.hh. This does not work since we
changeset 5b67e1bdf6ad in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5b67e1bdf6ad
description:
mips: Remove unused private members to fix compile-time warning
Certain versions of clang complain about unused private members if
they are not used. This
Hi Everyone,
I have a change I'd like to make to the gem5 coding style that I believe
will improve our code quality.
Currently, the gem5 coding style mandates that includes are grouped four
different blocks (alphabetical ordering within a block):
* Python headers
* C system/stdlib includes
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src/arch/x86/pagetable.hh
http://reviews.gem5.org/r/2319/#comment4785
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src/mem/multi_level_page_table.hh
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Ship it!
src/sim/process.hh
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I'm really not happy about the use of kvm-specific ports magic here. It
changeset e475a7861078 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e475a7861078
description:
sparc: Fixup bit ordering in the PSTATE bit union
The order of the MSB and LSB bit of the mm field in the PSTATE union
is wrong. Any access to this field
changeset 4593282280e4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4593282280e4
description:
base: Add a static assert to check bit union ranges
If a bit field in a bit union specified as BitfieldLSB, MSB instead
of BitfieldMSB, LSB the code
changeset 62c95c428a3d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=62c95c428a3d
description:
style: Fixup strange semantics in hg m5style
The 'hg m5style' command had some rather strange semantics. When
called without arguments, it applied the
changeset 56772eb01583 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=56772eb01583
description:
base: Add compiler macros for C++11 final/override
Add the macros M5_ATTR_FINAL and M5_ATTR_OVERRIDE which are defined to
final and override respectively
changeset b58f6afe14c5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b58f6afe14c5
description:
style: Add support for a style ignore list and ignore ext/
There are some directories within the repository where we don't want
to enforce our coding
changeset 933dfb9d8279 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=933dfb9d8279
description:
base: Replace the internal varargs stuff with C++11 constructs
We currently use our own home-baked support for type-safe variadic
functions. This is
,
Steve
On Tue, Aug 26, 2014 at 8:14 AM, Andreas Sandberg via gem5-dev
gem5-dev@gem5.org wrote:
changeset 62c95c428a3d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=62c95c428a3d
description:
style: Fixup strange semantics in hg m5style
The 'hg m5style
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Looks good. Thanks for addressing the issues I raised earlier!
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Ship It!
- Andreas Sandberg
On Aug. 25, 2014, 10:10 p.m.,
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I looked into this tool a couple of months ago. At the time, I
changeset 4207f9bfcceb in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4207f9bfcceb
description:
arch, cpu: Factor out the ExecContext into a proper base class
We currently generate and compile one version of the ISA code per CPU
model. This is
On Sept. 1, 2014, 6:14 p.m., Andreas Sandberg wrote:
.clang-format, line 18
http://reviews.gem5.org/r/2372/diff/1/?file=41128#file41128line18
Has this changed name? The clang documentation lists
DerivePointerAlignment, but not DerivePointerBinding.
Nilay Vaish wrote:
changeset e2c43045a81b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e2c43045a81b
description:
sim: Automatically unregister probe listeners
The ProbeListener base class automatically registers itself with a
probe manager. Currently, the class does
changeset 280cc9b0794f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=280cc9b0794f
description:
sim: Fix resource leak in BaseGlobalEvent
Static analysis revealed that BaseGlobalEvent::barrier was never
deallocated. This changeset solves this leak by
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Ship it!
Ship It!
- Andreas Sandberg
On Sept. 16, 2014, 4:37 p.m.,
On Sept. 19, 2014, 10 a.m., Andreas Sandberg wrote:
Ship It!
Just a minor thing: You should get rid of the SegInit keyword on the summary
line since that's not in the list of recognized keywords.
- Andreas
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src/arch/x86/tlb.cc
http://reviews.gem5.org/r/2313/#comment4848
changeset 8a7724f13288 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8a7724f13288
description:
dev: Refactor terminal-UART interface to make it more generic
The terminal currently assumes that the transport to the guest always
inherits from the Uart
changeset a26a20060ba3 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a26a20060ba3
description:
dev, pci: Implement basic VirtIO support
This patch adds support for VirtIO over the PCI bus. It does so by
providing the following new SimObjects:
changeset 4a501e0f7540 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4a501e0f7540
description:
dev: Add support for 9p proxying over VirtIO
This patch adds support for 9p filesystem proxying over VirtIO. It can
currently operate by connecting to a
changeset 42d0d62ee057 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=42d0d62ee057
description:
dev: Add a VirtIO console device model
diffstat:
src/dev/virtio/SConscript |3 +
src/dev/virtio/VirtIOConsole.py | 51 +
changeset 28bc070b5a86 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=28bc070b5a86
description:
dev: Add a VirtIO block device model
diffstat:
src/dev/virtio/SConscript |3 +
src/dev/virtio/VirtIOBlock.py | 50 +++
src/dev/virtio/block.cc |
changeset 2a0fe8bca031 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2a0fe8bca031
description:
cpu: Probe points for basic PMU stats
This changeset adds probe points that can be used to implement PMU
counters for CPU stats. The following probes are
changeset 20443473c68a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=20443473c68a
description:
sim: Add typedefs for PMU probe points
In order to show make PMU probe points usable across different PMU
implementations, we want a common probe
changeset e975e8afba8b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e975e8afba8b
description:
cpu: Add branch predictor PMU probe points
This changeset adds probe points that can be used to implement PMU
counters for branch predictor stats. The
changeset a42b8d98fddc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a42b8d98fddc
description:
arm: Add helper methods to setup architected PMU events
diffstat:
src/arch/arm/ArmPMU.py | 53 ++
1 files changed, 53
changeset 810f5a48a920 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=810f5a48a920
description:
sim: Add support for serializing BitUnionXX
BitUnion instances can normally not be used with the SERIALIZE_SCALAR
and UNSERIALIZE_SCALAR macros due to the
changeset afeb5cdb3907 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=afeb5cdb3907
description:
arm: Add a model of an ARM PMUv3
This class implements a subset of the ARM PMU v3 specification as
described in the ARMv8 reference manual. It supports
changeset 25c5da51bbe0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=25c5da51bbe0
description:
arm: Add TLB PMU probes
This changeset adds probe points that can be used to implement PMU
counters for TLB stats. The following probes are supported:
changeset 5d4ebc92d32e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5d4ebc92d32e
description:
ext: Update fputils to rev 6a47fd8358
This patch updates fputils to the latest revision (6a47fd8358) from
the upstream repository
On Nov. 18, 2014, 10:43 p.m., Gabe Black wrote:
util/m5/m5ops.h, line 57
http://reviews.gem5.org/r/2313/diff/4/?file=42082#file42082line57
Why do we need psuedo ops for syscalls when there are actual syscall
instructions? The same goes for page faults. I'm not saying I know that
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src/arch/arm/pseudo_inst.cc
http://reviews.gem5.org/r/2313/#comment4939
On 18/11/14 13:22, Steve Reinhardt via gem5-dev wrote:
I haven't looked at the code in question, so I'm just going by what I've
seen in this email thread. However, it seems like there ought to be some
alternative solutions here. I like the general direction Andreas is going,
though it would be
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The change itself makes sense, but I'd really prefer if we could avoid
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src/cpu/kvm/vm.hh
http://reviews.gem5.org/r/2510/#comment4940
The
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src/dev/x86/Pc.py
http://reviews.gem5.org/r/2515/#comment4946
I
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Ship It!
- Andreas Sandberg
On Nov. 19, 2014, 11:51 p.m.,
I just ran into some issues with kvm on x86. It seems like changeset
1bd64b294fe4 (x86: add LongModeAddressSize function to cpuid) breaks
Linux running in kvm. It seems like the offending change makes cpuid
report the virtual and physical address length as 255 bits, which
clearly doesn't make
Thanks! I should have checked the upstream commit log.
//Andreas
On 26/11/14 13:54, Gabe Black via gem5-dev wrote:
I already fixed it. The change should be checked in, I think.
Gabe
On Nov 26, 2014 5:52 AM, Andreas Sandberg via gem5-dev gem5-dev@gem5.org
wrote:
I just ran into some issues
On 04/12/14 16:10, Nilay Vaish via gem5-dev wrote:
I have been trying to run ht kvm cpu when using multiple cores. With
single threaded simulation, the simulation stops making progress if the
simulated system has more than 4 cores. With multi-threaded simulation, I
do not see any progress even
:
This is somewhat tangential, but are you saying the simulator is
multithreaded now? Or just your simulation?
Gabe
On Thu, Dec 4, 2014 at 10:03 AM, Andreas Sandberg via gem5-dev
gem5-dev@gem5.org wrote:
On 04/12/14 16:10, Nilay Vaish via gem5-dev wrote:
I have been trying to run ht kvm cpu when
changeset 6099331da328 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6099331da328
description:
dev: Add response sanity checks in PioPort
Add an assert in the PioPort that checks if a response packet from a
device has the right flags set before
changeset 4e09ae443c96 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4e09ae443c96
description:
arm: Fix decoding of PMXEVTYPER_EL0 and PMCCFILTR_EL0
The aarch64 system register decoder is currently not decoding
PMXEVTYPER_EL0 and PMCCFILTR_EL0
changeset 3499de20ab3a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3499de20ab3a
description:
dev: Correctly transform packets into responses
The VirtIO devices didn't correctly set the response flags in memory
packets. This changeset adds the
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Ship it!
I'm still not happy with the setupMemSlot()/disableMemSlot()
changeset ae5582819481 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ae5582819481
description:
arm: Add support for filtering in the PMU
This patch adds support for filtering events in the PMU. In order to
do so, it updates the ISADevice base class
changeset 5fae03bd840a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5fae03bd840a
description:
arm: Clean up and document decoder API
This changeset adds more documentation to the ArmISA::Decoder class
and restructures it slightly to make API groups
changeset 3bba9f2d0c7d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3bba9f2d0c7d
description:
arm: Raise an alignment fault if a PC has illegal alignment
We currently don't handle unaligned PCs correctly. There is one check
for unaligned PCs in the
changeset e2f9644a7738 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e2f9644a7738
description:
style: Update the style checker to handle new include order
As of August 2014, the gem5 style guide mandates that a source file's
primary header is
changeset a3cf30302e19 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a3cf30302e19
description:
sim: Remove test for non-NULL this in Event
The method Event::initialized() tests if this != NULL as a part of the
expression that tests if an event is
changeset e2716d523716 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e2716d523716
description:
dev: Correctly clear interrupts in VirtIO PCI
Correctly clear the PCI interrupt belonging to a VirtIO device when
the ISR register is read.
diffstat:
changeset d1d95f0f4563 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1d95f0f4563
description:
dev: Remove unused system pointer in the Platform base class
The Platform base class contains a pointer to an instance of the
System which is never
changeset ab81a0feab55 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ab81a0feab55
description:
style: Fix broken m5format command
The m5format command didn't actually work due to parameter handling
issues and missing language detection. This
changeset 276da6265ab8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=276da6265ab8
description:
sim: Move the BaseTLB to src/arch/generic/
The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.
changeset 65da28dee7cf in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=65da28dee7cf
description:
style: Fix incorrect style checker option name
The style used to support the option -w to automatically fix white
space issues. However, this option was
changeset 1922f9d2ac01 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1922f9d2ac01
description:
base: Add compiler macros to add deprecation warnings
Gcc and clang both provide an attribute that can be used to flag a
function as deprecated at compile
On Jan. 27, 2015, 11:57 p.m., Joel Hestness wrote:
util/sort_includes.py, line 151
http://reviews.gem5.org/r/2614/diff/1/?file=43359#file43359line151
This and lines 154+155 are tricky to read also. The old code was much
clearer/easier to step through. Is it important for the code
On Dec. 12, 2014, 10:24 p.m., Gabe Black wrote:
While it's definitely nice to get these into regular C++ instead of the ISA
language, my concern is that these aren't really pseudo instructions. They
are in the sense that they're instructions that wouldn't exist outside of
the
changeset b5e5068fcb26 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b5e5068fcb26
description:
arm: Merge ISA files with pseudo instructions
This changeset moves the pseudo instructions used to signal unknown
instructions and unimplemented
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Ooops, that was probably my fault.. Thanks for fixing!
-
changeset 4ed87af2930f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4ed87af2930f
description:
dev, arm: Clean up PL011 and rewrite interrupt handling
The ARM PL011 UART model didn't clear and raise interrupts
correctly. This changeset rewrites the
changeset fe09d1bc6721 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fe09d1bc6721
description:
arm: Correctly access the stack pointer in GDB
We curently use INTREG_X31 instead of INTREG_SPX when accessing the
stack pointer in GDB. gem5 normally
changeset f7d17d8a854c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f7d17d8a854c
description:
arm: Fix broken page table permissions checks in remote GDB
The remote GDB interface currently doesn't check if translations are
valid before reading
changeset 890269a13188 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=890269a13188
description:
arm: Don't truncate 16-bit ASIDs to 8 bits
The ISA code sometimes stores 16-bit ASIDs as 8-bit unsigned integers
and has a couple of inverted checks that
+ Ciro, Richard
Hi Everyone,
Thanks for pointing this out and submitting a fix.
Richard/Ciro/Giacomo: Could one of you review this so we can merge the fix?
Thanks,
Andreas
On 31/08/2020 05:41, Bobby Bruce wrote:
Hey Gabe,
Iru Cai made a fix for this a week or so ago:
Hi All,
I just had a quick look at the excellent new documentation section on
the gem5 website. A big thanks to everyone who has worked on making that
a reality!
One thing that I noticed when browsing the documentation is hosted in
the website repo and not the code repo. Would it make sense to
I would probably be more in favour of a split email+Slack/Teams
approach. Email works well for most discussion, but I like the quick
more informal communication in a chat system. I have generally been very
happy with the way Slack has worked when I have contributed to Zephyr in
my spare time. As
Hi Gabe,
As far as I know, we aren't keeping the Mercurial server in sync with the git
repo any more. I can't see any reason to keep Mercurial-related cruft in the
new repo.
Cheers,
Andreas
On 05/07/2020 02:08, Gabe Black via gem5-dev wrote:
Hi folks. Have we officially dropped support for
swer questions.
Gabe
On Thu, Jul 2, 2020 at 9:45 AM Andreas Sandberg via gem5-dev
mailto:gem5-dev@gem5.org>> wrote:
I would probably be more in favour of a split email+Slack/Teams
approach. Email works well for most discussion, but I like the quick
more informal communication in a cha
On 06/07/2020 19:37, Jason Lowe-Power wrote:
On Mon, Jul 6, 2020 at 11:22 AM Andreas Sandberg via gem5-dev
mailto:gem5-dev@gem5.org>> wrote:
Hi Bobby,
Can't we solve some of these issues by just moving the mailinglist to a better system
with good archiving? That should solve both th
Hi Everyone,
I have just posted a series of patches [1] that get rid of 'six' as a
dependency in gem5. However, there is still a dependency on six coming
from testlib. What's the process there? Should we fix it upstream and
backport it or is testlib now effectively a gem5 project?
Cheers,
wrote:
Hi Andreas,
There is no upstream for testlib. It's a purely gem5 project. We should fix it
in tree.
Jason
On Tue, Jan 26, 2021 at 4:56 AM Andreas Sandberg via gem5-dev
mailto:gem5-dev@gem5.org>> wrote:
Hi Everyone,
I have just posted a series of patches [1] that get rid o
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