[gem5-dev] Change in gem5/gem5[develop]: base: Dump page table over RSP
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47719 )
Change subject: base: Dump page table over RSP
..
base: Dump page table over RSP
Add a non-standard extension to the RSP protocol: the "." command
requests a dump of the simulated page table.
The dump consists of concatenated records, one record per page table
entry. Each record contains the entry's "virtual" value written as
hex, followed by a colon (:), followed by the entry's "physical" value
written as hex, followed by a semicolon (;).
At the time of writing, one practical use of this feature (in
combination with the "shared_backstore" parameter) is extremely fast
Miranda-Ingalls simulation of JIT compilers.
Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47719
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/mem/page_table.cc
M src/mem/page_table.hh
4 files changed, 27 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index f2ecfcc..c3353b7 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -153,6 +153,7 @@
#include "mem/port.hh"
#include "mem/port_proxy.hh"
#include "sim/full_system.hh"
+#include "sim/process.hh"
#include "sim/system.hh"
namespace gem5
@@ -872,6 +873,8 @@
{ 'z', { "KGDB_CLR_HW_BKPT", ::cmdClrHwBkpt } },
// insert breakpoint or watchpoint
{ 'Z', { "KGDB_SET_HW_BKPT", ::cmdSetHwBkpt } },
+// non-standard RSP extension: dump page table
+{ '.', { "GET_PAGE_TABLE", ::cmdDumpPageTable } },
};
bool
@@ -1219,6 +1222,13 @@
}
bool
+BaseRemoteGDB::cmdDumpPageTable(GdbCommand::Context )
+{
+send(tc->getProcessPtr()->pTable->externalize().c_str());
+return true;
+}
+
+bool
BaseRemoteGDB::cmdAsyncStep(GdbCommand::Context )
{
const char *p = ctx.data;
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index eb0661d..1089607 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -336,6 +336,7 @@
bool cmdAsyncStep(GdbCommand::Context );
bool cmdClrHwBkpt(GdbCommand::Context );
bool cmdSetHwBkpt(GdbCommand::Context );
+bool cmdDumpPageTable(GdbCommand::Context );
struct QuerySetCommand
{
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index a311a0a..6e27c30 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -206,4 +206,14 @@
}
}
+const std::string
+EmulationPageTable::externalize() const
+{
+std::stringstream ss;
+for (PTable::const_iterator it=pTable.begin(); it != pTable.end();
++it) {
+ss << std::hex << it->first << ":" << it->second.paddr << ";";
+}
+return ss.str();
+}
+
} // namespace gem5
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 900d446..c115a41 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -162,6 +162,12 @@
*/
Fault translate(const RequestPtr );
+/**
+ * Dump all items in the pTable, to a concatenation of strings of the
form
+ *Addr:Entry;
+ */
+const std::string externalize() const;
+
void getMappings(std::vector> *addr_mappings);
void serialize(CheckpointOut ) const override;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47719
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
Gerrit-Change-Number: 47719
Gerrit-PatchSet: 2
Gerrit-Owner: Boris Shingarov
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: cpu: Check for instruction-count events before fetch
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27587 )
Change subject: cpu: Check for instruction-count events before fetch
..
cpu: Check for instruction-count events before fetch
Instruction fetch should not commence if there already is an
instruction-count event in the queue.
The most conspicuous scenario where this leads to obvious breakage,
is guest debugging. Imagine the first bytes in the program pointed to
by _start are invalid instruction encoding, and we pass the --wait-gdb
flag. Then in GDB we set $pc to point to valid instructions, and we
"continue". gem5 will abort with "invalid instruction".
This is not how real targets behave: neither software- (e.g. ptrace)
based debuggers, nor low-level (e.g. OpenOCD or XMD connected over
JTAG to debug early initialization code eg when the MMU has not been
switched on yet, etc.) Fetching should start from where $pc was set
to. This patch tries to model this behavior.
Change-Id: Ibce6fdbbb082edf1073ae96745bc7867878f99ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27587
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/base.hh
M src/cpu/simple/timing.cc
4 files changed, 11 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4b9b773..12accc3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -646,6 +646,8 @@
return;
}
+serviceInstCountEvents();
+
Fault fault = NoFault;
TheISA::PCState pcState = thread->pcState();
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 0a4595c..135094f 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -302,6 +302,12 @@
instRequestorId(), instAddr);
}
+void
+BaseSimpleCPU::serviceInstCountEvents()
+{
+SimpleExecContext _info = *threadInfo[curThread];
+t_info.thread->comInstEventQueue.serviceEvents(t_info.numInst);
+}
void
BaseSimpleCPU::preExecute()
@@ -316,9 +322,6 @@
t_info.setPredicate(true);
t_info.setMemAccPredicate(true);
-// check for instruction-count-based events
-thread->comInstEventQueue.serviceEvents(t_info.numInst);
-
// decode the instruction
TheISA::PCState pcState = thread->pcState();
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 8117138..cee786d 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -130,6 +130,7 @@
public:
void checkForInterrupts();
void setupFetchRequest(const RequestPtr );
+void serviceInstCountEvents();
void preExecute();
void postExecute();
void advancePC(const Fault );
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ad0e039..76bc1af 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -805,6 +805,8 @@
if (tryCompleteDrain())
return;
+serviceInstCountEvents();
+
if (_status == BaseSimpleCPU::Running) {
// kick off fetch of next instruction... callback from icache
// response will cause that instruction to be executed,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/27587
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibce6fdbbb082edf1073ae96745bc7867878f99ca
Gerrit-Change-Number: 27587
Gerrit-PatchSet: 4
Gerrit-Owner: Boris Shingarov
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base: Dump page table over RSP
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47719 )
Change subject: base: Dump page table over RSP
..
base: Dump page table over RSP
Add a non-standard extension to the RSP protocol: the "." command
requests a dump of the simulated page table.
The dump consists of concatenated records, one record per page table
entry. Each record contains the entry's "virtual" value written as
hex, followed by a colon (:), followed by the entry's "physical" value
written as hex, followed by a semicolon (;).
At the time of writing, one practical use of this feature (in
combination with the "shared_backstore" parameter) is extremely fast
Miranda-Ingalls simulation of JIT compilers.
Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
M src/mem/page_table.cc
M src/mem/page_table.hh
4 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index f2ecfcc..c3353b7 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -153,6 +153,7 @@
#include "mem/port.hh"
#include "mem/port_proxy.hh"
#include "sim/full_system.hh"
+#include "sim/process.hh"
#include "sim/system.hh"
namespace gem5
@@ -872,6 +873,8 @@
{ 'z', { "KGDB_CLR_HW_BKPT", ::cmdClrHwBkpt } },
// insert breakpoint or watchpoint
{ 'Z', { "KGDB_SET_HW_BKPT", ::cmdSetHwBkpt } },
+// non-standard RSP extension: dump page table
+{ '.', { "GET_PAGE_TABLE", ::cmdDumpPageTable } },
};
bool
@@ -1219,6 +1222,13 @@
}
bool
+BaseRemoteGDB::cmdDumpPageTable(GdbCommand::Context )
+{
+send(tc->getProcessPtr()->pTable->externalize().c_str());
+return true;
+}
+
+bool
BaseRemoteGDB::cmdAsyncStep(GdbCommand::Context )
{
const char *p = ctx.data;
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index eb0661d..1089607 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -336,6 +336,7 @@
bool cmdAsyncStep(GdbCommand::Context );
bool cmdClrHwBkpt(GdbCommand::Context );
bool cmdSetHwBkpt(GdbCommand::Context );
+bool cmdDumpPageTable(GdbCommand::Context );
struct QuerySetCommand
{
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index a311a0a..6e27c30 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -206,4 +206,14 @@
}
}
+const std::string
+EmulationPageTable::externalize() const
+{
+std::stringstream ss;
+for (PTable::const_iterator it=pTable.begin(); it != pTable.end();
++it) {
+ss << std::hex << it->first << ":" << it->second.paddr << ";";
+}
+return ss.str();
+}
+
} // namespace gem5
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 900d446..c115a41 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -162,6 +162,12 @@
*/
Fault translate(const RequestPtr );
+/**
+ * Dump all items in the pTable, to a concatenation of strings of the
form
+ *Addr:Entry;
+ */
+const std::string externalize() const;
+
void getMappings(std::vector> *addr_mappings);
void serialize(CheckpointOut ) const override;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47719
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I333ed11d4ce671251d0b93cddae3bbcea44ea4ca
Gerrit-Change-Number: 47719
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor process initialization
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40941 )
Change subject: arch-power: Refactor process initialization
..
arch-power: Refactor process initialization
This generalizes parts of the process initialization
routines in preparation for multi-mode support and
adds flexibility in terms of data types and byte order
used for setting up the environment corresponding to
the mode in use.
Change-Id: Ia9efb93d044682af8b0f0809bca64a17570bf197
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40941
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/process.cc
M src/arch/power/process.hh
2 files changed, 24 insertions(+), 20 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index a9a28b3..bc63146 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -81,13 +81,16 @@
{
Process::initState();
-argsInit(sizeof(uint32_t), PageBytes);
+argsInit(PageBytes);
}
+template
void
-PowerProcess::argsInit(int intSize, int pageSize)
+PowerProcess::argsInit(int pageSize)
{
-std::vector> auxv;
+int intSize = sizeof(IntType);
+ByteOrder byteOrder = objFile->getByteOrder();
+std::vector> auxv;
std::string filename;
if (argv.size() < 1)
@@ -106,7 +109,7 @@
//Auxilliary vectors are loaded only for elf formatted executables.
auto *elfObject = dynamic_cast(objFile);
if (elfObject) {
-uint32_t features = 0;
+IntType features = 0;
//Bits which describe the system hardware capabilities
//XXX Figure out what these should be
@@ -209,15 +212,15 @@
roundUp(memState->getStackSize(),
pageSize), "stack");
// map out initial stack contents
-uint32_t sentry_base = memState->getStackBase() - sentry_size;
-uint32_t aux_data_base = sentry_base - aux_data_size;
-uint32_t env_data_base = aux_data_base - env_data_size;
-uint32_t arg_data_base = env_data_base - arg_data_size;
-uint32_t platform_base = arg_data_base - platform_size;
-uint32_t auxv_array_base = platform_base - aux_array_size -
aux_padding;
-uint32_t envp_array_base = auxv_array_base - envp_array_size;
-uint32_t argv_array_base = envp_array_base - argv_array_size;
-uint32_t argc_base = argv_array_base - argc_size;
+IntType sentry_base = memState->getStackBase() - sentry_size;
+IntType aux_data_base = sentry_base - aux_data_size;
+IntType env_data_base = aux_data_base - env_data_size;
+IntType arg_data_base = env_data_base - arg_data_size;
+IntType platform_base = arg_data_base - platform_size;
+IntType auxv_array_base = platform_base - aux_array_size - aux_padding;
+IntType envp_array_base = auxv_array_base - envp_array_size;
+IntType argv_array_base = envp_array_base - argv_array_size;
+IntType argc_base = argv_array_base - argc_size;
DPRINTF(Stack, "The addresses of items on the initial stack:\n");
DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
@@ -233,11 +236,11 @@
// write contents to stack
// figure out argc
-uint32_t argc = argv.size();
-uint32_t guestArgc = htobe(argc);
+IntType argc = argv.size();
+IntType guestArgc = htog(argc, byteOrder);
//Write out the sentry void *
-uint32_t sentry_NULL = 0;
+IntType sentry_NULL = 0;
initVirtMem->writeBlob(sentry_base, _NULL, sentry_size);
//Fix up the aux vectors which point to other data
@@ -256,7 +259,7 @@
//Copy the aux stuff
Addr auxv_array_end = auxv_array_base;
for (const auto : auxv) {
-initVirtMem->write(auxv_array_end, aux, ByteOrder::big);
+initVirtMem->write(auxv_array_end, aux, byteOrder);
auxv_array_end += sizeof(aux);
}
//Write out the terminating zeroed auxilliary vector
@@ -265,9 +268,9 @@
auxv_array_end += sizeof(zero);
copyStringArray(envp, envp_array_base, env_data_base,
-ByteOrder::big, *initVirtMem);
+byteOrder, *initVirtMem);
copyStringArray(argv, argv_array_base, arg_data_base,
-ByteOrder::big, *initVirtMem);
+byteOrder, *initVirtMem);
initVirtMem->writeBlob(argc_base, , intSize);
diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh
index 210bce2..9f2ce4b 100644
--- a/src/arch/power/process.hh
+++ b/src/arch/power/process.hh
@@ -49,7 +49,8 @@
public:
PowerProcess(const ProcessParams , loader::ObjectFile *objFile);
-void argsInit(int intSize, int pageSize);
+template
+void argsInit(int pageSize);
};
} // namespace gem5
--
To view, visit
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Update copyrights
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40948 ) Change subject: arch-power: Update copyrights .. arch-power: Update copyrights Change-Id: Ifabd1e7178b5250767a2b560b57570512b732278 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40948 Reviewed-by: Boris Shingarov Maintainer: Boris Shingarov Tested-by: kokoro --- M src/arch/power/SConscript M src/arch/power/decoder.hh M src/arch/power/insts/branch.cc M src/arch/power/insts/branch.hh M src/arch/power/insts/integer.cc M src/arch/power/insts/integer.hh M src/arch/power/insts/mem.cc M src/arch/power/insts/mem.hh M src/arch/power/isa.hh M src/arch/power/isa/bitfields.isa M src/arch/power/isa/decoder.isa M src/arch/power/isa/formats/branch.isa M src/arch/power/isa/formats/integer.isa M src/arch/power/isa/formats/mem.isa M src/arch/power/isa/formats/unimp.isa M src/arch/power/isa/formats/unknown.isa M src/arch/power/isa/formats/util.isa M src/arch/power/isa/operands.isa M src/arch/power/linux/se_workload.cc M src/arch/power/page_size.hh M src/arch/power/process.cc M src/arch/power/process.hh M src/arch/power/regs/int.hh M src/arch/power/regs/misc.hh M src/arch/power/remote_gdb.cc M src/arch/power/remote_gdb.hh M src/arch/power/types.hh M src/arch/power/vecregs.hh 28 files changed, 28 insertions(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript index 52a607d..74b2c81 100644 --- a/src/arch/power/SConscript +++ b/src/arch/power/SConscript @@ -2,6 +2,7 @@ # Copyright (c) 2009 The University of Edinburgh # Copyright (c) 2020 LabWare +# Copyright (c) 2021 IBM Corporation # All rights reserved. # # Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh index 20726a0..c30af91 100644 --- a/src/arch/power/decoder.hh +++ b/src/arch/power/decoder.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2012 Google + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc index a1b6d8c..8992143 100644 --- a/src/arch/power/insts/branch.cc +++ b/src/arch/power/insts/branch.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh index cad91c2..1359086 100644 --- a/src/arch/power/insts/branch.hh +++ b/src/arch/power/insts/branch.hh @@ -1,5 +1,6 @@ /* Copyright (c) 2007-2008 The Florida State University * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc index 7798d40..cf065a1 100644 --- a/src/arch/power/insts/integer.cc +++ b/src/arch/power/insts/integer.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh index 2e34876..1c298a0 100644 --- a/src/arch/power/insts/integer.hh +++ b/src/arch/power/insts/integer.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc index 7e44fd8..1f6700e 100644 --- a/src/arch/power/insts/mem.cc +++ b/src/arch/power/insts/mem.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh index 6fcfb12..732ea11 100644 --- a/src/arch/power/insts/mem.hh +++ b/src/arch/power/insts/mem.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 The University of Edinburgh + * Copyright (c) 2021 IBM Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index 784f368..d563ebe 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -1,6 +1,7 @@ /* * Copyright (c) 2009 The Regents of The University of Michigan * Copyright (c) 2009 The University of Edinburgh + *
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix load-store timing sequence
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40947 )
Change subject: arch-power: Fix load-store timing sequence
..
arch-power: Fix load-store timing sequence
To properly implement load-store instructions for use with
the TimingSimpleCPU model, the initiateAcc() part of the
instruction should only be responsible for performing the
effective address computation and then initiating memory
access.
The completeAcc() part of the instruction should then be
responsible for setting the condition register flags or
updating the base register based on the outcome of the
memory access. This fixes the following instructions:
* Load Byte and Zero with Update (lbzu)
* Load Halfword and Zero with Update (lhzu)
* Load Halfword Algebraic with Update (lhau)
* Load Word and Zero with Update (lwzu)
* Load Doubleword with Update (ldu)
* Load Floating Single with Update (lfsu)
* Load Floating Double with Update (lfdu)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Halfword and Zero with Update Indexed (lhzux)
* Load Halfword Algebraic with Update Indexed (lhaux)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word Algebraic with Update Indexed (lwaux)
* Load Doubleword with Update Indexed (ldux)
* Load Floating Single with Update Indexed (lfsux)
* Load Floating Double with Update Indexed (lfdux)
* Load Byte And Reserve Indexed (lbarx)
* Load Halfword And Reserve Indexed (lharx)
* Load Word And Reserve Indexed (lwarx)
* Load Doubleword And Reserve Indexed (ldarx)
* Store Byte with Update (stbu)
* Store Halfword with Update (sthu)
* Store Word with Update (stwu)
* Store Doubleword with Update (stdu)
* Store Byte with Update Indexed (stbux)
* Store Halfword with Update Indexed (sthux)
* Store Word with Update Indexed (stwux)
* Store Doubleword with Update Indexed (stdux)
* Store Byte Conditional Indexed (stbcx.)
* Store Halfword Conditional Indexed (sthcx.)
* Store Word Conditional Indexed (stwcx.)
* Store Doubleword Conditional Indexed (stdcx.)
* Store Floating Single with Update (stfsu)
* Store Floating Double with Update (stdsu)
* Store Floating Single with Update Indexed (stfsux)
* Store Floating Double with Update Indexed (stfdux)
Change-Id: If5f720619ec3c40a90c1362a9dfc8cc204e57acf
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40947
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/formats/util.isa
3 files changed, 73 insertions(+), 55 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 461e2cb..a40fbca 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -333,10 +333,8 @@
4: IntTrapOp::tw({{ Ra_sw }}, {{ Rb_sw }});
format LoadIndexOp {
-20: lwarx({{
-Rt = Mem_uw;
-Rsv = 1; RsvLen = 4; RsvAddr = EA;
-}});
+20: lwarx({{ Rt = Mem_uw; }},
+ {{ Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
21: ldx({{ Rt = Mem; }});
23: lwzx({{ Rt = Mem_uw; }});
@@ -373,10 +371,8 @@
cr = makeCRFieldUnsigned((uint32_t)Ra, (uint32_t)Rb,
xer.so);
}});
-52: LoadIndexOp::lbarx({{
-Rt = Mem_ub;
-Rsv = 1; RsvLen = 1; RsvAddr = EA;
-}});
+52: LoadIndexOp::lbarx({{ Rt = Mem_ub; }},
+ {{ Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
53: LoadIndexUpdateOp::ldux({{ Rt = Mem; }});
55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
@@ -389,17 +385,13 @@
68: IntTrapOp::td({{ Ra }}, {{ Rb }});
format LoadIndexOp {
-84: ldarx({{
-Rt = Mem_ud;
-Rsv = 1; RsvLen = 8; RsvAddr = EA;
-}});
+84: ldarx({{ Rt = Mem_ud; }},
+ {{ Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
87: lbzx({{ Rt = Mem_ub; }});
-116: lharx({{
-Rt = Mem_uh;
-Rsv = 1; RsvLen = 2; RsvAddr = EA;
-}});
+116: lharx({{ Rt = Mem_uh;}},
+ {{ Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
}
119: LoadIndexUpdateOp::lbzux({{ Rt = Mem_ub; }});
@@ -424,8 +416,9 @@
format StoreIndexOp {
149: stdx({{ Mem = Rs }});
150: stwcx({{
-bool store_performed = false;
Mem_uw = Rs_uw;
+}}, {{
+bool store_performed = false;
if (Rsv) {
if (RsvLen == 4) {
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add support for trapping user faults
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47359 )
Change subject: arch-power: Add support for trapping user faults
..
arch-power: Add support for trapping user faults
This adds support for trapping into GDB when user-mode
faults such as those pertaining to alignment (SIGBUS),
traps (SIGTRAP) and unimplemented opcodes (SIGILL) are
encountered.
Change-Id: Ieb557abd4173b5acb4be6f0c30964aea1eba71a5
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47359
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/SConscript
A src/arch/power/faults.cc
M src/arch/power/faults.hh
M src/arch/power/isa/formats/integer.isa
M src/arch/power/isa/formats/unknown.isa
M src/arch/power/tlb.cc
6 files changed, 89 insertions(+), 10 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 720455c..52a607d 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -34,6 +34,7 @@
# Scons bug id: 2006 M5 Bug id: 308
Dir('isa/formats')
Source('decoder.cc')
+Source('faults.cc')
Source('insts/branch.cc')
Source('insts/mem.cc')
Source('insts/integer.cc')
diff --git a/src/arch/power/faults.cc b/src/arch/power/faults.cc
new file mode 100644
index 000..3b8851e
--- /dev/null
+++ b/src/arch/power/faults.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2021 IBM Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/power/faults.hh"
+
+#include
+
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+
+namespace gem5
+{
+
+namespace PowerISA
+{
+
+void
+UnimplementedOpcodeFault::invoke(ThreadContext *tc, const StaticInstPtr
)
+{
+panic_if(tc->getSystemPtr()->trapToGdb(SIGILL, tc->contextId()),
+ "Unimplemented opcode encountered at virtual address %#x\n",
+ tc->pcState().pc());
+}
+
+void
+AlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr )
+{
+panic_if(!tc->getSystemPtr()->trapToGdb(SIGBUS, tc->contextId()),
+ "Alignment fault when accessing virtual address %#x\n",
vaddr);
+}
+
+void
+TrapFault::invoke(ThreadContext *tc, const StaticInstPtr )
+{
+panic_if(tc->getSystemPtr()->trapToGdb(SIGTRAP, tc->contextId()),
+ "Trap encountered at virtual address %#x\n",
+ tc->pcState().pc());
+}
+
+} // namespace PowerISA
+
+} // namespace gem5
diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index edfcc8f..037 100644
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -63,6 +63,9 @@
: PowerFault("Unimplemented Opcode")
{
}
+
+void invoke(ThreadContext *tc, const StaticInstPtr =
+nullStaticInstPtr) override;
};
@@ -78,11 +81,16 @@
class AlignmentFault : public PowerFault
{
+ private:
+Addr vaddr;
public:
-AlignmentFault()
-: PowerFault("Alignment")
+AlignmentFault(Addr va)
+: PowerFault("Alignment"), vaddr(va)
{
}
+
+void invoke(ThreadContext *tc, const StaticInstPtr =
+nullStaticInstPtr) override;
};
@@ -93,6 +101,9 @@
: PowerFault("Trap")
{
}
+
+void invoke(ThreadContext *tc, const StaticInstPtr =
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add multi-mode debugging support
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40946 )
Change subject: arch-power: Add multi-mode debugging support
..
arch-power: Add multi-mode debugging support
This adds multi-mode support for remote debugging via GDB
with the addition of the XML target description files for
both 32-bit and 64-bit variants of the Power architecture.
Proper byte order conversions have also been added.
MSR has now been modeled to some extent but it is still
not exposed by getRegs() since its a privileged register
that cannot be modified from userspace. Similarly, the
target descriptions require FPSCR to also be part of the
payload and hence, it has been added too.
Change-Id: I156fdccb791f161959dbb2c3dd8ab1e510d9cd4b
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40946
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
A ext/gdb-xml/power-core.xml
A ext/gdb-xml/power-fpu.xml
D ext/gdb-xml/power.xml
A ext/gdb-xml/power64-core.xml
A ext/gdb-xml/powerpc-32.xml
A ext/gdb-xml/powerpc-64.xml
M src/arch/power/SConscript
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
9 files changed, 319 insertions(+), 115 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/gdb-xml/power-core.xml b/ext/gdb-xml/power-core.xml
new file mode 100644
index 000..6cf57b1
--- /dev/null
+++ b/ext/gdb-xml/power-core.xml
@@ -0,0 +1,49 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/ext/gdb-xml/power-fpu.xml b/ext/gdb-xml/power-fpu.xml
new file mode 100644
index 000..145eede
--- /dev/null
+++ b/ext/gdb-xml/power-fpu.xml
@@ -0,0 +1,44 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/ext/gdb-xml/power.xml b/ext/gdb-xml/power.xml
deleted file mode 100644
index da5a07c..000
--- a/ext/gdb-xml/power.xml
+++ /dev/null
@@ -1,92 +0,0 @@
-
-
-
-
-
- powerpc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/ext/gdb-xml/power64-core.xml b/ext/gdb-xml/power64-core.xml
new file mode 100644
index 000..cd5bc6d
--- /dev/null
+++ b/ext/gdb-xml/power64-core.xml
@@ -0,0 +1,49 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/ext/gdb-xml/powerpc-32.xml b/ext/gdb-xml/powerpc-32.xml
new file mode 100644
index 000..a537f92
--- /dev/null
+++ b/ext/gdb-xml/powerpc-32.xml
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+ powerpc:common
+
+
+
diff --git a/ext/gdb-xml/powerpc-64.xml b/ext/gdb-xml/powerpc-64.xml
new file mode 100644
index 000..a762f8c
--- /dev/null
+++ b/ext/gdb-xml/powerpc-64.xml
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+ powerpc:common64
+
+
+
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 24bf5db..720455c 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -59,4 +59,8 @@
ISADesc('isa/main.isa')
-GdbXml('power.xml', 'gdb_xml_power')
+GdbXml('power-core.xml', 'gdb_xml_power_core')
+GdbXml('power64-core.xml', 'gdb_xml_power64_core')
+GdbXml('power-fpu.xml', 'gdb_xml_power_fpu')
+GdbXml('powerpc-32.xml', 'gdb_xml_powerpc_32')
+GdbXml('powerpc-64.xml', 'gdb_xml_powerpc_64')
diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index 886a840..5536879 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -136,7 +136,12 @@
#include
-#include "blobs/gdb_xml_power.hh"
+#include "arch/power/regs/misc.hh"
+#include "blobs/gdb_xml_power64_core.hh"
+#include "blobs/gdb_xml_power_core.hh"
+#include "blobs/gdb_xml_power_fpu.hh"
+#include "blobs/gdb_xml_powerpc_32.hh"
+#include "blobs/gdb_xml_powerpc_64.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
@@ -149,7 +154,7 @@
using namespace PowerISA;
RemoteGDB::RemoteGDB(System *_system, int _port)
-: BaseRemoteGDB(_system, _port), regCache(this)
+: BaseRemoteGDB(_system, _port), regCache32(this), regCache64(this)
{
}
@@ -173,22 +178,26 @@
{
DPRINTF(GDBAcc, "getRegs in remotegdb \n");
+Msr msr = context->readIntReg(INTREG_MSR);
+ByteOrder order = (msr.le ?
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix process initialization
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40945 ) Change subject: arch-power: Fix process initialization .. arch-power: Fix process initialization During process initialization, special purpose registers should either be explicitly set or cleared. These contain flag bits which might have unforseen side effects on the execution of a program. Change-Id: If7c5af9a93283a53717cc8cbba4bf373a7e40560 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40945 Reviewed-by: Boris Shingarov Maintainer: Boris Shingarov Tested-by: kokoro --- M src/arch/power/process.cc 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc index 8ac5946..27f7607 100644 --- a/src/arch/power/process.cc +++ b/src/arch/power/process.cc @@ -338,6 +338,10 @@ //Set the stack pointer register tc->setIntReg(StackPointerReg, stack_min); +//Reset the special-purpose registers +for (int i = 0; i < NumIntSpecialRegs; i++) +tc->setIntReg(NumIntArchRegs + i, 0); + //Set the machine status for a typical userspace Msr msr = 0; msr.sf = is64bit; 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40945 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If7c5af9a93283a53717cc8cbba4bf373a7e40560 Gerrit-Change-Number: 40945 Gerrit-PatchSet: 12 Gerrit-Owner: Sandipan Das Gerrit-Reviewer: Boris Shingarov Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add multi-mode support
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40944 )
Change subject: arch-power: Add multi-mode support
..
arch-power: Add multi-mode support
This adds multi-mode support and allows the simulator to
read, interpret and execute 32bit and 64-bit, big and
little endian binaries in syscall emulation mode.
During process initialization, a minimal set of hardware
capabilities are also advertised by the simulator to show
support for 64-bit mode and little endian byte order.
This also adds some fixups specific to 64-bit ELF ABI v1
that readjust the entry point and symbol table due to the
use of function descriptors.
Change-Id: I124339eff7b70dbd14e50ff970340c88c13bd0ad
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40944
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/PowerSeWorkload.py
M src/arch/power/linux/se_workload.cc
M src/arch/power/process.cc
M src/arch/power/regs/int.hh
M src/base/loader/elf_object.cc
M src/base/loader/object_file.cc
M src/base/loader/object_file.hh
7 files changed, 100 insertions(+), 18 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/PowerSeWorkload.py
b/src/arch/power/PowerSeWorkload.py
index ef7bbb5..2b081f2 100644
--- a/src/arch/power/PowerSeWorkload.py
+++ b/src/arch/power/PowerSeWorkload.py
@@ -40,5 +40,5 @@
@classmethod
def _is_compatible_with(cls, obj):
-return obj.get_arch() == 'power' and \
+return obj.get_arch() in ('power', 'power64') and \
obj.get_op_sys() in ('linux', 'unknown')
diff --git a/src/arch/power/linux/se_workload.cc
b/src/arch/power/linux/se_workload.cc
index 75eb210..815a145 100644
--- a/src/arch/power/linux/se_workload.cc
+++ b/src/arch/power/linux/se_workload.cc
@@ -50,7 +50,9 @@
Process *
load(const ProcessParams , loader::ObjectFile *obj) override
{
-if (obj->getArch() != loader::Power)
+auto arch = obj->getArch();
+
+if (arch != loader::Power && arch != loader::Power64)
return nullptr;
auto opsys = obj->getOpSys();
@@ -60,7 +62,10 @@
opsys = loader::Linux;
}
-if (opsys != loader::Linux)
+if ((arch == loader::Power && opsys != loader::Linux) ||
+(arch == loader::Power64 &&
+ opsys != loader::LinuxPower64ABIv1 &&
+ opsys != loader::LinuxPower64ABIv2))
return nullptr;
return new PowerProcess(params, obj);
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 688cc1e..8ac5946 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -82,7 +82,55 @@
{
Process::initState();
-argsInit(PageBytes);
+if (objFile->getArch() == loader::Power)
+argsInit(PageBytes);
+else
+argsInit(PageBytes);
+
+// Fix up entry point and symbol table for 64-bit ELF ABI v1
+if (objFile->getOpSys() != loader::LinuxPower64ABIv1)
+return;
+
+// Fix entry point address and the base TOC pointer by looking the
+// the function descriptor in the .opd section
+Addr entryPoint, tocBase;
+ByteOrder byteOrder = objFile->getByteOrder();
+ThreadContext *tc = system->threads[contextIds[0]];
+
+// The first doubleword of the descriptor contains the address of the
+// entry point of the function
+initVirtMem->readBlob(getStartPC(), , sizeof(Addr));
+
+// Update the PC state
+auto pc = tc->pcState();
+pc.byteOrder(byteOrder);
+pc.set(gtoh(entryPoint, byteOrder));
+tc->pcState(pc);
+
+// The second doubleword of the descriptor contains the TOC base
+// address for the function
+initVirtMem->readBlob(getStartPC() + 8, , sizeof(Addr));
+tc->setIntReg(TOCPointerReg, gtoh(tocBase, byteOrder));
+
+// Fix symbol table entries as they would otherwise point to the
+// function descriptor rather than the actual entry point address
+auto *symbolTable = new loader::SymbolTable;
+
+for (auto sym : loader::debugSymbolTable) {
+Addr entry;
+loader::Symbol symbol = sym;
+
+// Try to read entry point from function descriptor
+if (initVirtMem->tryReadBlob(sym.address, , sizeof(Addr)))
+symbol.address = gtoh(entry, byteOrder);
+
+symbolTable->insert(symbol);
+}
+
+// Replace the current debug symbol table
+loader::debugSymbolTable.clear();
+loader::debugSymbolTable.insert(*symbolTable);
+delete symbolTable;
}
template
@@ -91,6 +139,8 @@
{
int intSize = sizeof(IntType);
ByteOrder byteOrder = objFile->getByteOrder();
+bool is64bit = (objFile->getArch() == loader::Power64);
+bool isLittleEndian = (byteOrder ==
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add hardware features
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40942 )
Change subject: arch-power: Add hardware features
..
arch-power: Add hardware features
This adds definitions for the hardware feature bits that
are currently available from the AT_HWCAP and AT_HWCAP2
auxv entries for the Power architecture. These are being
defined for future use.
Change-Id: I8214a4a26c502b1b0f31837069084b2e7cb31c51
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40942
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/process.hh
1 file changed, 41 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh
index 9f2ce4b..ea5e957 100644
--- a/src/arch/power/process.hh
+++ b/src/arch/power/process.hh
@@ -55,4 +55,45 @@
} // namespace gem5
+enum PowerHWCAPFeature
+{
+HWCAP_FEATURE_32 = 1ULL << 31,// Always set for powerpc64
+HWCAP_FEATURE_64 = 1ULL << 30,// Always set for powerpc64
+HWCAP_FEATURE_HAS_ALTIVEC = 1ULL << 28,
+HWCAP_FEATURE_HAS_FPU = 1ULL << 27,
+HWCAP_FEATURE_HAS_MMU = 1ULL << 26,
+HWCAP_FEATURE_UNIFIED_CACHE = 1ULL << 24,
+HWCAP_FEATURE_NO_TB = 1ULL << 20, // 601/403gx have no timebase
+HWCAP_FEATURE_POWER4 = 1ULL << 19,// POWER4 ISA 2.00
+HWCAP_FEATURE_POWER5 = 1ULL << 18,// POWER5 ISA 2.02
+HWCAP_FEATURE_POWER5_PLUS = 1ULL << 17, // POWER5+ ISA 2.03
+HWCAP_FEATURE_CELL_BE = 1ULL << 16, // CELL Broadband Engine
+HWCAP_FEATURE_BOOKE = 1ULL << 15, // ISA Category Embedded
+HWCAP_FEATURE_SMT = 1ULL << 14, // Simultaneous
Multi-Threading
+HWCAP_FEATURE_ICACHE_SNOOP = 1ULL << 13,
+HWCAP_FEATURE_ARCH_2_05 = 1ULL << 12, // ISA 2.05
+HWCAP_FEATURE_PA6T = 1ULL << 11, // PA Semi 6T Core
+HWCAP_FEATURE_HAS_DFP = 1ULL << 10, // Decimal FP Unit
+HWCAP_FEATURE_POWER6_EXT = 1ULL << 9, // P6 + mffgpr/mftgpr
+HWCAP_FEATURE_ARCH_2_06 = 1ULL << 8, // ISA 2.06
+HWCAP_FEATURE_HAS_VSX = 1ULL << 7,// P7 Vector Extension
+HWCAP_FEATURE_PSERIES_PERFMON_COMPAT = 1ULL << 6,
+HWCAP_FEATURE_TRUE_LE = 1ULL << 1,
+HWCAP_FEATURE_PPC_LE = 1ULL << 0
+};
+
+enum PowerHWCAP2Feature
+{
+HWCAP2_FEATURE_ARCH_2_07 = 1ULL << 31,// ISA 2.07
+HWCAP2_FEATURE_HAS_HTM = 1ULL << 30, // Hardware Transactional
Memory
+HWCAP2_FEATURE_HAS_DSCR = 1ULL << 29, // Data Stream Control
Register
+HWCAP2_FEATURE_HAS_EBB = 1ULL << 28, // Event Base Branching
+HWCAP2_FEATURE_HAS_ISEL = 1ULL << 27, // Integer Select
+HWCAP2_FEATURE_HAS_TAR = 1ULL << 26, // Target Address Register
+HWCAP2_FEATURE_HAS_VCRYPTO = 1ULL << 25, // Vector AES category
+HWCAP2_FEATURE_HTM_NOSC = 1ULL << 24,
+HWCAP2_FEATURE_ARCH_3_00 = 1ULL << 23,// ISA 3.0
+HWCAP2_FEATURE_HAS_IEEE128 = 1ULL << 22, // VSX IEEE Binary Float
128-bit
+};
+
#endif // __POWER_PROCESS_HH__
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40942
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8214a4a26c502b1b0f31837069084b2e7cb31c51
Gerrit-Change-Number: 40942
Gerrit-PatchSet: 12
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add MSR and associated dependencies
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40943 )
Change subject: arch-power: Add MSR and associated dependencies
..
arch-power: Add MSR and associated dependencies
This adds the definition of the Machine State Register
(MSR) in preparation for multi-mode support. The MSR
has bits that define the state of the processor. This
defines all the bitfields and sets the ones that are
typically used for userspace environments.
In preparation for multi-mode support, the SF and LE
bits are used by instructions to check if the simulation
is running in 64-bit mode and if memory accesses are to
be performed in little endian byte order respectively.
This introduces changes in areas such as target address
computation for branch instructions, carry and overflow
computation for arithmetic instructions, etc.
Change-Id: If9ac69415ca85b0c873bd8579e7d1bd2219eac62
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40943
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/operands.isa
M src/arch/power/process.cc
M src/arch/power/regs/int.hh
M src/arch/power/regs/misc.hh
9 files changed, 127 insertions(+), 41 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index ca52d83..a1b6d8c 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -27,6 +27,8 @@
*/
#include "arch/power/insts/branch.hh"
+#include "arch/power/regs/int.hh"
+#include "arch/power/regs/misc.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
@@ -54,12 +56,17 @@
PowerISA::PCState
-BranchOp::branchTarget(const PowerISA::PCState ) const
+BranchOp::branchTarget(ThreadContext *tc) const
{
+Msr msr = tc->readIntReg(INTREG_MSR);
+Addr addr;
+
if (aa)
-return li;
+addr = li;
else
-return pc.pc() + li;
+addr = tc->pcState().pc() + li;
+
+return msr.sf ? addr : addr & UINT32_MAX;
}
@@ -97,13 +104,17 @@
PowerISA::PCState
-BranchDispCondOp::branchTarget(const PowerISA::PCState ) const
+BranchDispCondOp::branchTarget(ThreadContext *tc) const
{
-if (aa) {
-return bd;
-} else {
-return pc.pc() + bd;
-}
+Msr msr = tc->readIntReg(INTREG_MSR);
+Addr addr;
+
+if (aa)
+addr = bd;
+else
+addr = tc->pcState().pc() + bd;
+
+return msr.sf ? addr : addr & UINT32_MAX;
}
@@ -146,8 +157,9 @@
PowerISA::PCState
BranchRegCondOp::branchTarget(ThreadContext *tc) const
{
-Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
-return addr & -4ULL;
+Msr msr = tc->readIntReg(INTREG_MSR);
+Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index()) & -4ULL;
+return msr.sf ? addr : addr & UINT32_MAX;
}
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 5c5982c..cad91c2 100644
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -87,7 +87,7 @@
{
}
-PowerISA::PCState branchTarget(const PowerISA::PCState ) const
override;
+PowerISA::PCState branchTarget(ThreadContext *tc) const override;
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
@@ -158,7 +158,7 @@
{
}
-PowerISA::PCState branchTarget(const PowerISA::PCState ) const
override;
+PowerISA::PCState branchTarget(ThreadContext *tc) const override;
/// Explicitly import the otherwise hidden branchTarget
using StaticInst::branchTarget;
diff --git a/src/arch/power/isa/formats/branch.isa
b/src/arch/power/isa/formats/branch.isa
index b970bc0..efb5f06 100644
--- a/src/arch/power/isa/formats/branch.isa
+++ b/src/arch/power/isa/formats/branch.isa
@@ -87,11 +87,11 @@
# Check the condition register (CR) allows the branch to be taken.
def GetCondCode(br_code):
-cond_code = 'if (condOk(CR)) {\n'
+cond_code = 'Msr msr = MSR;\n'
+cond_code += 'if (condOk(CR)) {\n'
cond_code += '' + br_code + '\n'
-cond_code += '} else {\n'
-cond_code += 'NIA = NIA;\n'
cond_code += '}\n'
+cond_code += 'NIA = msr.sf ? NIA : NIA & UINT32_MAX;\n'
return cond_code
# Check the condition register (CR) and count register (CTR) allow the
@@ -99,11 +99,11 @@
# register too. This takes place in ctrOk within BranchCondOp classes.
def GetCtrCondCode(br_code):
cond_code = 'uint64_t ctr = CTR;\n'
+cond_code += 'Msr msr = MSR;\n'
cond_code += 'if (ctrOk(ctr) && condOk(CR)) {\n'
cond_code
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add byte order attribute for PC state
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40940 )
Change subject: arch-power: Add byte order attribute for PC state
..
arch-power: Add byte order attribute for PC state
This adds byte order as an attribute for PC state by
introducing a new PCState class. The decoder can now
fetch instructions bytes in the specified byte order
in preparation for multi-mode support.
Change-Id: I917333df88114a733cc5a8077cc420d5328f608b
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40940
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/decoder.hh
M src/arch/power/pcstate.hh
2 files changed, 37 insertions(+), 2 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index 4e0c92b..20726a0 100644
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -68,7 +68,7 @@
void
moreBytes(const PCState , Addr fetchPC)
{
-emi = betoh(emi);
+emi = gtoh(emi, pc.byteOrder());
instDone = true;
}
diff --git a/src/arch/power/pcstate.hh b/src/arch/power/pcstate.hh
index 9553c73..d0757839 100644
--- a/src/arch/power/pcstate.hh
+++ b/src/arch/power/pcstate.hh
@@ -30,6 +30,8 @@
#define __ARCH_POWER_PCSTATE_HH__
#include "arch/generic/types.hh"
+#include "arch/power/types.hh"
+#include "enums/ByteOrder.hh"
namespace gem5
{
@@ -37,7 +39,40 @@
namespace PowerISA
{
-typedef GenericISA::SimplePCState<4> PCState;
+class PCState : public GenericISA::SimplePCState<4>
+{
+ private:
+typedef GenericISA::SimplePCState<4> Base;
+ByteOrder guestByteOrder = ByteOrder::big;
+
+ public:
+PCState()
+{}
+
+void
+set(Addr val)
+{
+Base::set(val);
+npc(val + 4);
+}
+
+PCState(Addr val)
+{
+set(val);
+}
+
+ByteOrder
+byteOrder() const
+{
+return guestByteOrder;
+}
+
+void
+byteOrder(ByteOrder order)
+{
+guestByteOrder = order;
+}
+};
} // namespace PowerISA
} // namespace gem5
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40940
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I917333df88114a733cc5a8077cc420d5328f608b
Gerrit-Change-Number: 40940
Gerrit-PatchSet: 11
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base: Add byte order attribute for object files
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40939 )
Change subject: base: Add byte order attribute for object files
..
base: Add byte order attribute for object files
This adds byte order as an attribute for object files by
introducing new members to the ObjectFile class. This is
populated by the looking at the ELF headers.
Change-Id: Ibe55699175cc0295e0c9d49bdbe02e580988bc4f
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40939
Reviewed-by: Daniel Carvalho
Maintainer: Daniel Carvalho
Tested-by: kokoro
---
M src/base/loader/elf_object.cc
M src/base/loader/elf_object.hh
M src/base/loader/object_file.hh
3 files changed, 14 insertions(+), 0 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc
index 489a4c0..e7fba63 100644
--- a/src/base/loader/elf_object.cc
+++ b/src/base/loader/elf_object.cc
@@ -114,6 +114,7 @@
determineArch();
determineOpSys();
+determineByteOrder();
entry = ehdr.e_entry;
_programHeaderCount = ehdr.e_phnum;
@@ -326,6 +327,15 @@
}
void
+ElfObject::determineByteOrder()
+{
+auto edata = ehdr.e_ident[EI_DATA];
+if (edata == ELFDATANONE)
+panic("invalid ELF data encoding");
+byteOrder = (edata == ELFDATA2MSB) ? ByteOrder::big :
ByteOrder::little;
+}
+
+void
ElfObject::handleLoadableSegment(GElf_Phdr phdr, int seg_num)
{
auto name = std::to_string(seg_num);
diff --git a/src/base/loader/elf_object.hh b/src/base/loader/elf_object.hh
index 797ff1f..7e7b739 100644
--- a/src/base/loader/elf_object.hh
+++ b/src/base/loader/elf_object.hh
@@ -66,6 +66,7 @@
void determineArch();
void determineOpSys();
+void determineByteOrder();
void handleLoadableSegment(GElf_Phdr phdr, int seg_num);
// These values are provided to a linux process by the kernel, so we
diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh
index 443dfb9..5e767de 100644
--- a/src/base/loader/object_file.hh
+++ b/src/base/loader/object_file.hh
@@ -38,6 +38,7 @@
#include "base/loader/symtab.hh"
#include "base/logging.hh"
#include "base/types.hh"
+#include "enums/ByteOrder.hh"
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
@@ -80,6 +81,7 @@
protected:
Arch arch = UnknownArch;
OpSys opSys = UnknownOpSys;
+ByteOrder byteOrder = ByteOrder::little;
SymbolTable _symtab;
@@ -106,6 +108,7 @@
Arch getArch() const { return arch; }
OpSys getOpSys() const { return opSys; }
+ByteOrder getByteOrder() const { return byteOrder; }
const SymbolTable () const { return _symtab; }
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40939
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibe55699175cc0295e0c9d49bdbe02e580988bc4f
Gerrit-Change-Number: 40939
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: kokoro
Gerrit-CC: Gabe Black
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor argument registers
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40938 )
Change subject: arch-power: Refactor argument registers
..
arch-power: Refactor argument registers
This reintroduces the argument register constants that
were removed in commit 7bb456f02 ("arch-power: Delete
unused register related constants"), adds a definition
for the sixth argument register and switches to these
constants to specify the arguments used by the system
call ABI.
Change-Id: I5804f4d2b27a04d0e7b69132e5abce5761b239f5
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40938
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/regs/int.hh
M src/arch/power/se_workload.cc
2 files changed, 12 insertions(+), 1 deletion(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
index 2d6a16b..f66be59 100644
--- a/src/arch/power/regs/int.hh
+++ b/src/arch/power/regs/int.hh
@@ -43,6 +43,12 @@
// Semantically meaningful register indices
const int ReturnValueReg = 3;
+const int ArgumentReg0 = 3;
+const int ArgumentReg1 = 4;
+const int ArgumentReg2 = 5;
+const int ArgumentReg3 = 6;
+const int ArgumentReg4 = 7;
+const int ArgumentReg5 = 8;
const int StackPointerReg = 1;
enum MiscIntRegNums
diff --git a/src/arch/power/se_workload.cc b/src/arch/power/se_workload.cc
index 31ff243..40179f1 100644
--- a/src/arch/power/se_workload.cc
+++ b/src/arch/power/se_workload.cc
@@ -31,7 +31,12 @@
{
const std::vector SEWorkload::SyscallABI::ArgumentRegs = {
-3, 4, 5, 6, 7, 8
+ArgumentReg0,
+ArgumentReg1,
+ArgumentReg2,
+ArgumentReg3,
+ArgumentReg4,
+ArgumentReg5
};
} // namespace PowerISA
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40938
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5804f4d2b27a04d0e7b69132e5abce5761b239f5
Gerrit-Change-Number: 40938
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add move condition field instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40936 )
Change subject: arch-power: Add move condition field instructions
..
arch-power: Add move condition field instructions
This adds the following instructions.
* Move to CR from XER Extended (mcrxrx)
* Move To One Condition Register Field (mtocrf)
* Move From One Condition Register Field (mfocrf)
Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40936
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
1 file changed, 24 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 4307b25..d752630 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -638,6 +638,14 @@
567: LoadIndexUpdateOp::lfsux({{ Ft_sf = Mem_sf; }});
570: IntLogicOp::cnttzd({{ Ra = findTrailingZeros(Rs); }}, true);
+
+576: IntOp::mcrxrx({{
+uint8_t res;
+Xer xer = XER;
+res = (xer.ov << 3) | (xer.ov32 << 2) | (xer.ca << 1) |
xer.ca32;
+CR = insertCRField(CR, BF, res);
+}});
+
598: MiscOp::sync({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
599: LoadIndexOp::lfdx({{ Ft = Mem_df; }});
631: LoadIndexUpdateOp::lfdux({{ Ft = Mem_df; }});
@@ -980,6 +988,14 @@
format IntOp {
19: decode S {
0: mfcr({{ Rt = CR; }});
+
+1: mfocrf({{
+int count = popCount(FXM);
+uint64_t mask = 0xf << (4 *
findMsbSet(FXM));
+if (count == 1) {
+Rt = CR & mask;
+}
+}});
}
144: decode S {
@@ -992,6 +1008,14 @@
}
CR = (Rs & mask) | (CR & ~mask);
}});
+
+1: mtocrf({{
+int count = popCount(FXM);
+uint32_t mask = 0xf << (4 *
findMsbSet(FXM));
+if (count == 1) {
+CR = (Rs & mask) | (CR & ~mask);
+}
+}});
}
339: decode SPR {
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40936
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Gerrit-Change-Number: 40936
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix move condition field instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40935 )
Change subject: arch-power: Fix move condition field instructions
..
arch-power: Fix move condition field instructions
This introduces the S field for X form instructions which
is used to specify signed versus unsigned comparison. The
Power ISA does not specify a formal name for the third
1-bit opcode field required for decoding XFX form move to
and from CR field instructions, the S field can be used
to achieve the same as it has the same span and position.
This fixes the following instructions.
* Move To Condition Register Fields (mtcrf)
* Move From Condition Register (mfcr)
Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40935
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/decoder.isa
2 files changed, 14 insertions(+), 9 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/bitfields.isa
b/src/arch/power/isa/bitfields.isa
index 3bfea53..276242e 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -73,6 +73,7 @@
// FXM field for mtcrf instruction
def bitfield FXM <19:12>;
+def bitfield S <20>;
// Branch fields
def bitfield BO<25:21>;
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 6c73b28..4307b25 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -978,17 +978,21 @@
default: decode XFX_XO {
format IntOp {
-19: mfcr({{ Rt = CR; }});
+19: decode S {
+0: mfcr({{ Rt = CR; }});
+}
-144: mtcrf({{
-uint32_t mask = 0;
-for (int i = 0; i < 8; ++i) {
-if (((FXM >> i) & 0x1) == 0x1) {
-mask |= 0xf << (4 * i);
+144: decode S {
+0: mtcrf({{
+uint32_t mask = 0;
+for (int i = 0; i < 8; ++i) {
+if (bits(FXM, i)) {
+mask |= 0xf << (4 * i);
+}
}
-}
-CR = (Rs & mask) | (CR & ~mask);
-}});
+CR = (Rs & mask) | (CR & ~mask);
+}});
+}
339: decode SPR {
0x20: mfxer({{ Rt = XER; }});
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40935
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63
Gerrit-Change-Number: 40935
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add time base instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40937 )
Change subject: arch-power: Add time base instructions
..
arch-power: Add time base instructions
This models a pseudo time base using the simulator ticks
and adds the following instructions.
* Move From Time Base (mftb)
* Move From Time Base Upper (mftbu)
Change-Id: Idb619ec3179b2a85925998282075bde8651c68c2
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40937
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/insts/integer.cc
M src/arch/power/isa/decoder.isa
2 files changed, 8 insertions(+), 2 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 7795b50..18a72ab 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -46,13 +46,17 @@
myMnemonic == "mtxer" ||
myMnemonic == "mtlr" ||
myMnemonic == "mtctr" ||
-myMnemonic == "mttar") {
+myMnemonic == "mttar" ||
+myMnemonic == "mttb" ||
+myMnemonic == "mttbu") {
printDest = false;
} else if (myMnemonic == "mfcr" ||
myMnemonic == "mfxer" ||
myMnemonic == "mflr" ||
myMnemonic == "mfctr" ||
- myMnemonic == "mftar") {
+ myMnemonic == "mftar" ||
+ myMnemonic == "mftb" ||
+ myMnemonic == "mftbu") {
printSrcs = false;
}
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index d752630..461e2cb 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -1023,6 +1023,8 @@
0x100: mflr({{ Rt = LR; }});
0x120: mfctr({{ Rt = CTR; }});
0x1f9: mftar({{ Rt = TAR; }});
+0x188: mftb({{ Rt = curTick(); }});
+0x1a8: mftbu({{ Rt_uw = curTick() >> 32; }});
}
467: decode SPR {
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40937
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idb619ec3179b2a85925998282075bde8651c68c2
Gerrit-Change-Number: 40937
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add trap instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40934 )
Change subject: arch-power: Add trap instructions
..
arch-power: Add trap instructions
This introduces new classes and new formats for D and X
form instructions, the TO field that is used to encode
the trap conditions and adds the following instructions.
* Trap Word Immediate (twi)
* Trap Word (tw)
* Trap Doubleword Immediate (tdi)
* Trap Doubleword (td)
Change-Id: I029147ef643c2ee6794426e5e90af4d75f22e92e
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40934
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/faults.hh
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/types.hh
6 files changed, 225 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh
index e20ef8e..806f958 100644
--- a/src/arch/power/faults.hh
+++ b/src/arch/power/faults.hh
@@ -82,6 +82,16 @@
}
};
+
+class TrapFault : public PowerFault
+{
+ public:
+TrapFault()
+: PowerFault("Trap")
+{
+}
+};
+
} // namespace PowerISA
#endif // __ARCH_POWER_FAULTS_HH__
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 3203507..7795b50 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -820,3 +820,99 @@
return ss.str();
}
+
+
+std::string
+IntTrapOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::string ext;
+std::stringstream ss;
+bool printSrcs = true;
+bool printCond = false;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+if (myMnemonic == "tw" &&
+(srcRegIdx(0).index() == 0) && (srcRegIdx(1).index() == 0)) {
+myMnemonic = "trap";
+printSrcs = false;
+} else {
+ext = suffix();
+if (!ext.empty() &&
+(myMnemonic == "tw" || myMnemonic == "td")) {
+myMnemonic += ext;
+} else {
+printCond = true;
+}
+}
+
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the trap condition
+if (printCond)
+ss << (int) to;
+
+// Print the source registers
+if (printSrcs) {
+if (_numSrcRegs > 0) {
+if (printCond)
+ss << ", ";
+printReg(ss, srcRegIdx(0));
+}
+
+if (_numSrcRegs > 1) {
+ss << ", ";
+printReg(ss, srcRegIdx(1));
+}
+}
+
+return ss.str();
+}
+
+
+std::string
+IntImmTrapOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::string ext;
+std::stringstream ss;
+bool printCond = false;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+ext = suffix();
+if (!ext.empty()) {
+if (myMnemonic == "twi") {
+myMnemonic = "tw" + ext + "i";
+} else if (myMnemonic == "tdi") {
+myMnemonic = "td" + ext + "i";
+} else {
+printCond = true;
+}
+} else {
+printCond = true;
+}
+
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the trap condition
+if (printCond)
+ss << (int) to;
+
+// Print the source registers
+if (_numSrcRegs > 0) {
+if (printCond)
+ss << ", ";
+printReg(ss, srcRegIdx(0));
+}
+
+// Print the immediate value
+ss << ", " << si;
+
+return ss.str();
+}
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 69bc633..600fdf4 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -713,6 +713,82 @@
Addr pc, const Loader::SymbolTable *symtab) const override;
};
+
+/**
+ * Class for integer trap operations.
+ */
+class IntTrapOp : public IntOp
+{
+ protected:
+uint8_t to;
+
+/// Constructor
+IntTrapOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntOp(mnem, _machInst, __opClass),
+to(machInst.to)
+{
+}
+
+inline bool
+checkTrap(int64_t a, int64_t b) const
+{
+if (((to & 0x10) && (a < b)) ||
+((to & 0x08) && (a > b)) ||
+((to & 0x04) && (a == b)) ||
+((to & 0x02) && ((uint64_t)a < (uint64_t)b)) ||
+((to & 0x01) && ((uint64_t)a > (uint64_t)b))) {
+return true;
+}
+
+return false;
+}
+
+inline std::string
+suffix() const
+{
+std::string str;
+
+switch (to) {
+case
[gem5-dev] Change in gem5/gem5[develop]: configs: Fix waiting on remote debugger
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47360 )
Change subject: configs: Fix waiting on remote debugger
..
configs: Fix waiting on remote debugger
Commit 2c75e58cac ("sim,cpu: Move the remote GDB stub
into the workload.") moved "wait_for_remote_gdb" to the
Workload class. That breaks se.py since it continues to
rely on that being a property of BaseCPU. This ensures
that the property is now set via the current Workload
instance instead.
Also, owing to its boolean nature, the argument should
ideally not expect any additional values. Hence, it is
associated with the "store_true" action.
Change-Id: I4a00b29d283df36ebf833c9125651cd6deb52a4f
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47360
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M configs/common/Options.py
M configs/example/se.py
2 files changed, 2 insertions(+), 3 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 75c60a8..31ac120 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -455,7 +455,7 @@
"to be used in syscall emulation."
"Usage: gem5.opt [...] --redirects /dir1=/path/"
"to/host/dir1 --redirects
/dir2=/path/to/host/dir2")
-parser.add_argument("--wait-gdb", default=False,
+parser.add_argument("--wait-gdb", default=False, action='store_true',
help="Wait for remote GDB to connect.")
diff --git a/configs/example/se.py b/configs/example/se.py
index 65acf6a..7b161e1 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -264,8 +264,7 @@
system.workload = SEWorkload.init_compatible(mp0_path)
if args.wait_gdb:
-for cpu in system.cpu:
-cpu.wait_for_remote_gdb = True
+system.workload.wait_for_remote_gdb = True
root = Root(full_system = False, system = system)
Simulation.run(args, root, system, FutureClass)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47360
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4a00b29d283df36ebf833c9125651cd6deb52a4f
Gerrit-Change-Number: 47360
Gerrit-PatchSet: 3
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: Gabe Black
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add doubleword multiply-add instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40905 )
Change subject: arch-power: Add doubleword multiply-add instructions
..
arch-power: Add doubleword multiply-add instructions
This introduces 128-bit addition helpers and adds the
following instructions.
* Multiply-Add Low Doubleword (maddld)
* Multiply-Add High Doubleword (maddhd)
* Multiply-Add High Doubleword Unsigned (maddhdu)
Change-Id: I04e6ea5fb4978b341a6e648424de2930ad41f449
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40905
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
4 files changed, 134 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 25c8691..61b7f08 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -117,6 +117,7 @@
{
std::stringstream ss;
bool printSecondSrc = true;
+bool printThirdSrc = false;
// Generate the correct mnemonic
std::string myMnemonic(mnemonic);
@@ -128,6 +129,10 @@
myMnemonic == "subfze" ||
myMnemonic == "neg") {
printSecondSrc = false;
+} else if (myMnemonic == "maddhd" ||
+ myMnemonic == "maddhdu" ||
+ myMnemonic == "maddld") {
+printThirdSrc = true;
}
// Additional characters depending on isa bits being set
@@ -151,6 +156,12 @@
if (_numSrcRegs > 1 && printSecondSrc) {
ss << ", ";
printReg(ss, srcRegIdx(1));
+
+// Print the third source register
+if (_numSrcRegs > 2 && printThirdSrc) {
+ss << ", ";
+printReg(ss, srcRegIdx(2));
+}
}
}
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 95f1598..fccb7cf 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -134,6 +134,52 @@
{
}
+/* Compute 128-bit sum of 128-bit to 64-bit unsigned integer addition
*/
+inline std::tuple
+add(uint64_t ralo, uint64_t rahi, uint64_t rb) const
+{
+uint64_t slo, shi;
+#if defined(__SIZEOF_INT128__)
+__uint128_t ra = ((__uint128_t)rahi << 64) | ralo;
+__uint128_t sum = ra + rb;
+slo = sum;
+shi = sum >> 64;
+#else
+shi = rahi + ((ralo + rb) < ralo);
+slo = ralo + rb;
+#endif
+return std::make_tuple(slo, shi);
+}
+
+/* Compute 128-bit sum of 128-bit to 64-bit signed integer addition */
+inline std::tuple
+add(uint64_t ralo, int64_t rahi, int64_t rb) const
+{
+uint64_t slo;
+int64_t shi;
+#if defined(__SIZEOF_INT128__)
+__int128_t ra = ((__int128_t)rahi << 64) | ralo;
+__int128_t sum = (__int128_t)ra + rb;
+slo = sum;
+shi = sum >> 64;
+#else
+if (rb < 0) {
+shi = rahi - 1;
+slo = ralo + rb;
+if (slo < rb) {
+shi++;
+}
+} else {
+shi = rahi;
+slo = ralo + rb;
+if (slo < rb) {
+shi++;
+}
+}
+#endif
+return std::make_tuple(slo, shi);
+}
+
/**
* Compute 128-bit product of 64-bit unsigned integer multiplication
* based on https://stackoverflow.com/a/28904636
@@ -177,6 +223,48 @@
return std::make_tuple(plo, (int64_t)phi);
}
+/**
+ * Compute 128-bit result of 64-bit unsigned integer multiplication
+ * followed by addition
+ */
+inline std::tuple
+multiplyAdd(uint64_t ra, uint64_t rb, uint64_t rc) const
+{
+uint64_t rlo, rhi;
+#if defined(__SIZEOF_INT128__)
+__uint128_t res = ((__uint128_t)ra * rb) + rc;
+rlo = res;
+rhi = res >> 64;
+#else
+uint64_t plo, phi;
+std::tie(plo, phi) = multiply(ra, rb);
+std::tie(rlo, rhi) = add(plo, phi, rc);
+#endif
+return std::make_tuple(rlo, rhi);
+}
+
+/**
+ * Compute 128-bit result of 64-bit signed integer multiplication
+ * followed by addition
+ */
+inline std::tuple
+multiplyAdd(int64_t ra, int64_t rb, int64_t rc) const
+{
+uint64_t rlo;
+int64_t rhi;
+#if defined(__SIZEOF_INT128__)
+__int128_t res = (__int128_t)ra * rb + rc;
+rlo = res;
+rhi = res >> 64;
+#else
+uint64_t plo;
+int64_t phi;
+std::tie(plo, phi) = multiply(ra, rb);
+std::tie(rlo, rhi) =
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add fields for VA form instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40904 )
Change subject: arch-power: Add fields for VA form instructions
..
arch-power: Add fields for VA form instructions
This introduces the extended opcode field for VA form
instructions and the RC field that specifes a GPR to
be used as a register operand.
Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40904
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/operands.isa
2 files changed, 4 insertions(+), 1 deletion(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/bitfields.isa
b/src/arch/power/isa/bitfields.isa
index 84a3a2c..8783081 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -38,6 +38,7 @@
def bitfield A_XO <5:1>;
def bitfield DS_XO <1:0>;
def bitfield DX_XO <5:1>;
+def bitfield VA_XO <5:0>;
def bitfield X_XO <10:1>;
def bitfield XFL_XO<10:1>;
def bitfield XFX_XO<10:1>;
@@ -47,6 +48,7 @@
// Register fields
def bitfield RA<20:16>;
def bitfield RB<15:11>;
+def bitfield RC<10:6>;
def bitfield RS<25:21>;
def bitfield RT<25:21>;
def bitfield FRA <20:16>;
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index 8cb39eb..7d85749 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -44,7 +44,8 @@
'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
-'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
+'Rc': ('IntReg', 'ud', 'RC', 'IsInteger', 4),
+'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 5),
# General Purpose Floating Point Reg Operands
'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40904
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Gerrit-Change-Number: 40904
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add doubleword multiply instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40903 )
Change subject: arch-power: Add doubleword multiply instructions
..
arch-power: Add doubleword multiply instructions
This introduces 128-bit multiplication helpers and adds
the following instructions.
* Multiply Low Doubleword (mulld[o][.])
* Multiply High Doubleword (mulhd[.])
* Multiply High Doubleword Unsigned (mulhdu[.])
Change-Id: Id579c95468ffe5fe7b5164579ec1dfb18f0b3ab3
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40903
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
2 files changed, 85 insertions(+), 16 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index aafbbec..95f1598 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -134,6 +134,49 @@
{
}
+/**
+ * Compute 128-bit product of 64-bit unsigned integer multiplication
+ * based on https://stackoverflow.com/a/28904636
+ */
+inline std::tuple
+multiply(uint64_t ra, uint64_t rb) const
+{
+uint64_t plo, phi;
+#if defined(__SIZEOF_INT128__)
+__uint128_t prod = (__uint128_t)ra * rb;
+plo = prod;
+phi = prod >> 64;
+#else
+uint64_t ralo = (uint32_t)ra, rahi = ra >> 32;
+uint64_t rblo = (uint32_t)rb, rbhi = rb >> 32;
+uint64_t pp0 = ralo * rblo;
+uint64_t pp1 = rahi * rblo;
+uint64_t pp2 = ralo * rbhi;
+uint64_t pp3 = rahi * rbhi;
+uint64_t c = ((uint32_t)pp1) + ((uint32_t)pp2) + (pp0 >> 32);
+phi = pp3 + (pp2 >> 32) + (pp1 >> 32) + (c >> 32);
+plo = (c << 32) | ((uint32_t)pp0);
+#endif
+return std::make_tuple(plo, phi);
+}
+
+/* Compute 128-bit product of 64-bit signed integer multiplication */
+inline std::tuple
+multiply(int64_t ra, int64_t rb) const
+{
+uint64_t plo, phi;
+#if defined(__SIZEOF_INT128__)
+__int128_t prod = (__int128_t)ra * rb;
+plo = prod;
+phi = prod >> 64;
+#else
+std::tie(plo, phi) = multiply((uint64_t)ra, (uint64_t)rb);
+if (rb < 0) phi -= (uint64_t)ra;
+if (ra < 0) phi -= (uint64_t)rb;
+#endif
+return std::make_tuple(plo, (int64_t)phi);
+}
+
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
};
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index beacd6f..b4c90fc 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -483,10 +483,15 @@
// These instructions are of XO form with bit 21 as the OE bit.
default: decode XO_XO {
-format IntSumOp {
-8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }}, true);
-10: addc({{ Ra }}, {{ Rb }}, computeCA = true);
-}
+8: IntSumOp::subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }}, true);
+
+9: IntArithCheckRcOp::mulhdu({{
+uint64_t res;
+std::tie(std::ignore, res) = multiply(Ra, Rb);
+Rt = res;
+}});
+
+10: IntSumOp::addc({{ Ra }}, {{ Rb }}, computeCA = true);
11: IntArithCheckRcOp::mulhwu({{
uint64_t res = (uint64_t)Ra_uw * Rb_uw;
@@ -496,11 +501,19 @@
40: IntSumOp::subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
-75: IntArithCheckRcOp::mulhw({{
-uint64_t res = (int64_t)Ra_sw * Rb_sw;
-res = res >> 32;
-Rt = res;
-}});
+format IntArithCheckRcOp {
+73: mulhd({{
+int64_t res;
+std::tie(std::ignore, res) = multiply(Ra_sd, Rb_sd);
+Rt = res;
+}});
+
+75: mulhw({{
+uint64_t res = (int64_t)Ra_sw * Rb_sw;
+res = res >> 32;
+Rt = res;
+}});
+}
format IntSumOp {
104: neg({{ ~Ra }}, {{ 1 }});
@@ -512,13 +525,26 @@
234: addme({{ Ra }}, {{ -1ULL }}, {{ xer.ca }}, true);
}
-235: IntArithCheckRcOp::mullw({{
-int64_t res = (int64_t)Ra_sw * Rb_sw;
-if (res != (int32_t)res) {
-setOV = true;
-}
-Rt = res;
-}}, true);
+format IntArithCheckRcOp {
+233: mulld({{
+int64_t src1 = Ra_sd;
+int64_t src2 = Rb_sd;
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add PC-relative arithmetic instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40902 )
Change subject: arch-power: Add PC-relative arithmetic instructions
..
arch-power: Add PC-relative arithmetic instructions
This adds the following instructions.
* Add PC Immediate Shifted (addpcis)
Change-Id: Ib88b8e123ffb328e6f692e0fddb237e420ce38a7
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40902
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
4 files changed, 81 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 2035b5c..25c8691 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -219,6 +219,51 @@
std::string
+IntDispArithOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+bool printSrcs = true;
+bool printDisp = true;
+bool negateDisp = false;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+if (myMnemonic == "addpcis") {
+printSrcs = false;
+if (d == 0) {
+myMnemonic = "lnia";
+printDisp = false;
+} else if (d < 0) {
+myMnemonic = "subpcis";
+negateDisp = true;
+}
+}
+
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the first destination only
+if (_numDestRegs > 0)
+printReg(ss, destRegIdx(0));
+
+// Print the source register
+if (_numSrcRegs > 0 && printSrcs) {
+if (_numDestRegs > 0)
+ss << ", ";
+printReg(ss, srcRegIdx(0));
+}
+
+// Print the displacement
+if (printDisp)
+ss << ", " << (negateDisp ? -d : d);
+
+return ss.str();
+}
+
+
+std::string
IntShiftOp::generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const
{
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index daef626..aafbbec 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -161,6 +161,27 @@
/**
+ * Class for integer arithmetic operations with displacement.
+ */
+class IntDispArithOp : public IntArithOp
+{
+ protected:
+
+int64_t d;
+
+/// Constructor
+IntDispArithOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntArithOp(mnem, _machInst, __opClass),
+d(sext<16>((machInst.d0 << 6) | (machInst.d1 << 1) | machInst.d2))
+{
+}
+
+std::string generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const override;
+};
+
+
+/**
* Class for integer operations with a shift.
*/
class IntShiftOp : public IntOp
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index cc3b9f4..beacd6f 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -163,6 +163,10 @@
528: bcctr({{ NIA = CTR & -4ULL; }});
560: bctar({{ NIA = TAR & -4ULL; }}, true);
}
+
+default: decode DX_XO {
+2: IntDispArithOp::addpcis({{ Rt = NIA + (d << 16); }});
+}
}
format IntRotateOp {
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 8583ba0..183c08b 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -168,6 +168,17 @@
}};
+// Integer instructions with displacement that perform arithmetic.
+// There are no control flags to set.
+def format IntDispArithOp(code, inst_flags = []) {{
+
+# Generate the class
+(header_output, decoder_output, decode_block, exec_output) = \
+GenAluOp(name, Name, 'IntDispArithOp', code, inst_flags,
BasicDecode,
+ BasicConstructor)
+}};
+
+
// Integer instructions that perform logic operations. The result is
// always written into Ra. All instructions have 2 versions depending on
// whether the Rc bit is set to compute the CR0 code. This is determined
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40902
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib88b8e123ffb328e6f692e0fddb237e420ce38a7
Gerrit-Change-Number: 40902
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Jason
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add fields for DX form instructions
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40901 ) Change subject: arch-power: Add fields for DX form instructions .. arch-power: Add fields for DX form instructions This introduces the extended opcode field for DS form instructions and the fields d0, d1 and d2 which are concatenated for specifying a signed integer immediate operand. Change-Id: Id60e85d79f9157d680f813bf90ab6e1e064253a9 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40901 Reviewed-by: Boris Shingarov Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/arch/power/isa/bitfields.isa M src/arch/power/types.hh 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa index 771a822..84a3a2c 100644 --- a/src/arch/power/isa/bitfields.isa +++ b/src/arch/power/isa/bitfields.isa @@ -37,6 +37,7 @@ def bitfield PO<31:26>; def bitfield A_XO <5:1>; def bitfield DS_XO <1:0>; +def bitfield DX_XO <5:1>; def bitfield X_XO <10:1>; def bitfield XFL_XO<10:1>; def bitfield XFX_XO<10:1>; diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index 354da59..6f55821 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -55,6 +55,9 @@ Bitfield<15, 0> ui; Bitfield<15, 0> d; Bitfield<15, 2> ds; +Bitfield<15, 6> d0; +Bitfield<20, 16> d1; +Bitfield< 1, 0> d2; // Special purpose register identifier Bitfield<20, 11> spr; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40901 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id60e85d79f9157d680f813bf90ab6e1e064253a9 Gerrit-Change-Number: 40901 Gerrit-PatchSet: 7 Gerrit-Owner: Sandipan Das Gerrit-Reviewer: Boris Shingarov Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix disassembly for arithmetic instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40900 )
Change subject: arch-power: Fix disassembly for arithmetic instructions
..
arch-power: Fix disassembly for arithmetic instructions
This fixes disassembly generated for integer add and subtract
arithmetic instructions based on the type of operands and the
special use cases for which the Power ISA provides extended
mnemonics.
Change-Id: I89b8271994e4d4b7b16efad170af5eeb5ee1aa10
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40900
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
2 files changed, 122 insertions(+), 26 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 7da5bf5..2035b5c 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -68,15 +68,13 @@
ccprintf(ss, "%-10s ", myMnemonic);
// Print the first destination only
-if (_numDestRegs > 0 && printDest) {
+if (_numDestRegs > 0 && printDest)
printReg(ss, destRegIdx(0));
-}
// Print the (possibly) two source registers
if (_numSrcRegs > 0 && printSrcs) {
-if (_numDestRegs > 0 && printDest) {
+if (_numDestRegs > 0 && printDest)
ss << ", ";
-}
printReg(ss, srcRegIdx(0));
if (_numSrcRegs > 1 && printSecondSrc) {
ss << ", ";
@@ -93,27 +91,16 @@
{
std::stringstream ss;
-// Generate the correct mnemonic
-std::string myMnemonic(mnemonic);
-
-// Special cases
-if (!myMnemonic.compare("addi") && _numSrcRegs == 0) {
-myMnemonic = "li";
-} else if (!myMnemonic.compare("addis") && _numSrcRegs == 0) {
-myMnemonic = "lis";
-}
-ccprintf(ss, "%-10s ", myMnemonic);
+ccprintf(ss, "%-10s ", mnemonic);
// Print the first destination only
-if (_numDestRegs > 0) {
+if (_numDestRegs > 0)
printReg(ss, destRegIdx(0));
-}
// Print the source register
if (_numSrcRegs > 0) {
-if (_numDestRegs > 0) {
+if (_numDestRegs > 0)
ss << ", ";
-}
printReg(ss, srcRegIdx(0));
}
@@ -125,6 +112,113 @@
std::string
+IntArithOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+bool printSecondSrc = true;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+if (myMnemonic == "addme" ||
+myMnemonic == "addze" ||
+myMnemonic == "subfme" ||
+myMnemonic == "subfze" ||
+myMnemonic == "neg") {
+printSecondSrc = false;
+}
+
+// Additional characters depending on isa bits being set
+if (oe)
+myMnemonic = myMnemonic + "o";
+if (rc)
+myMnemonic = myMnemonic + ".";
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the first destination only
+if (_numDestRegs > 0)
+printReg(ss, destRegIdx(0));
+
+// Print the first source register
+if (_numSrcRegs > 0) {
+if (_numDestRegs > 0)
+ss << ", ";
+printReg(ss, srcRegIdx(0));
+
+// Print the second source register
+if (_numSrcRegs > 1 && printSecondSrc) {
+ss << ", ";
+printReg(ss, srcRegIdx(1));
+}
+}
+
+return ss.str();
+}
+
+
+std::string
+IntImmArithOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+bool negateImm = false;
+
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+
+// Special cases
+if (myMnemonic == "addi") {
+if (_numSrcRegs == 0) {
+myMnemonic = "li";
+} else if (si < 0) {
+myMnemonic = "subi";
+negateImm = true;
+}
+} else if (myMnemonic == "addis") {
+if (_numSrcRegs == 0) {
+myMnemonic = "lis";
+} else if (si < 0) {
+myMnemonic = "subis";
+negateImm = true;
+}
+} else if (myMnemonic == "addic" && si < 0) {
+myMnemonic = "subic";
+negateImm = true;
+} else if (myMnemonic == "addic_") {
+if (si < 0) {
+myMnemonic = "subic.";
+negateImm = true;
+} else {
+myMnemonic = "addic.";
+}
+}
+
+ccprintf(ss, "%-10s ", myMnemonic);
+
+// Print the first destination only
+if (_numDestRegs > 0)
+printReg(ss, destRegIdx(0));
+
+// Print the source register
+if (_numSrcRegs > 0) {
+if (_numDestRegs > 0)
+ss << ", ";
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix arithmetic instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40899 )
Change subject: arch-power: Fix arithmetic instructions
..
arch-power: Fix arithmetic instructions
The latest Power ISA introduces two new bits that record
carry and overflow out of bit 31 of the result, namely
CA32 and OV32 respectively, thereby changing the behaviour
of the add and subtract instructions that set them. Also,
now that 64-bit registers are being used, the nature of
the result, i.e. less than, greater than or equal to zero,
must be set by a 64-bit signed comparison of the result
to zero. This fixes the following instructions.
* Add Immediate (addi)
* Add Immediate Shifted (addis)
* Add (add[o][.])
* Subtract From (subf[o][.])
* Add Immediate Carrying (addic)
* Add Immediate Carrying and Record (addic.)
* Subtract From Immediate Carrying (subfic)
* Add Carrying (addc[o][.])
* Subtract From Carrying (subfc[o][.])
* Add Extended (adde[o][.])
* Subtract From Extended (subfe[o][.])
* Add to Zero Extended (addze[o][.])
* Subtract From Zero Extended (subfze[o][.])
* Negate (neg[o][.])
* Multiply Low Immediate (mulli)
* Multiply Low Word (mullw[o][.])
* Multiply High Word (mulhw[.])
* Multiply High Word Unsigned (mulhwu[.])
* Divide Word (divw[o][.])
* Divide Word Unsigned (divwu[o][.])
Change-Id: I8c79f1dca8b19010ed7b734d7ec9bb598df428c3
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40899
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/regs/misc.hh
3 files changed, 33 insertions(+), 17 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e993a7b..cc3b9f4 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -38,9 +38,8 @@
format IntImmArithOp {
7: mulli({{
-int32_t src = Ra_sw;
-int64_t prod = src * si;
-Rt = (uint32_t)prod;
+int64_t res = Ra_sd * si;
+Rt = res;
}});
8: subfic({{
@@ -486,15 +485,17 @@
}
11: IntArithCheckRcOp::mulhwu({{
-uint64_t prod = Ra_ud * Rb_ud;
-Rt = prod >> 32;
+uint64_t res = (uint64_t)Ra_uw * Rb_uw;
+res = res >> 32;
+Rt = res;
}});
40: IntSumOp::subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
75: IntArithCheckRcOp::mulhw({{
-int64_t prod = Ra_sd * Rb_sd;
-Rt = prod >> 32;
+uint64_t res = (int64_t)Ra_sw * Rb_sw;
+res = res >> 32;
+Rt = res;
}});
format IntSumOp {
@@ -508,19 +509,19 @@
}
235: IntArithCheckRcOp::mullw({{
-int64_t prod = Ra_sd * Rb_sd;
-Rt = prod;
-if (prod != (int32_t)prod) {
+int64_t res = (int64_t)Ra_sw * Rb_sw;
+if (res != (int32_t)res) {
setOV = true;
}
+Rt = res;
}}, true);
266: IntSumOp::add({{ Ra }}, {{ Rb }});
format IntArithCheckRcOp {
459: divwu({{
-uint32_t src1 = Ra_sw;
-uint32_t src2 = Rb_sw;
+uint32_t src1 = Ra_uw;
+uint32_t src2 = Rb_uw;
if (src2 != 0) {
Rt = src1 / src2;
} else {
@@ -532,9 +533,8 @@
491: divw({{
int32_t src1 = Ra_sw;
int32_t src2 = Rb_sw;
-if ((src1 != 0x8000 || src2 != 0x)
-&& src2 != 0) {
-Rt = src1 / src2;
+if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
+Rt = (uint32_t)(src1 / src2);
} else {
Rt = 0;
setOV = true;
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index b0840ce..8583ba0 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -44,28 +44,42 @@
'''
computeCACode = '''
-if (findCarry(32, %(result)s, %(inputa)s, %(inputb)s)) {
+if (findCarry(64, %(result)s, %(inputa)s, %(inputb)s)) {
xer.ca = 1;
} else {
xer.ca = 0;
}
+
+if (findCarry(32, %(result)s, %(inputa)s, %(inputb)s)) {
+xer.ca32 = 1;
+} else {
+xer.ca32 = 0;
+}
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor arithmetic instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40898 )
Change subject: arch-power: Refactor arithmetic instructions
..
arch-power: Refactor arithmetic instructions
This changes the base classes for integer arithmetic
instructions and introduces two new classes that are used
to distinguish between instructions using register and
immediate operands.
Decoding has also been consolidated using formats that can
generate code after determining if an instruction records
carry and overflow and also if it records the nature of the
result, i.e. lesser than, greater than or equal to zero.
However, for multiply and divide instructions, the code to
determine if an overflow has occurred has been moved to the
instruction definition itself. The formats have also been
updated to make use of the new base classes.
Change-Id: I23d70ac4bad4d25d876308db0b3564c092bf574c
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40898
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/floating.hh
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/fp.isa
M src/arch/power/isa/formats/integer.isa
M src/arch/power/types.hh
7 files changed, 176 insertions(+), 173 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/floating.hh
b/src/arch/power/insts/floating.hh
index 02dbbb2..ef06901 100644
--- a/src/arch/power/insts/floating.hh
+++ b/src/arch/power/insts/floating.hh
@@ -43,11 +43,12 @@
{
protected:
-bool rcSet;
+bool rc;
/// Constructor
FloatOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : PowerStaticInst(mnem, _machInst, __opClass)
+ : PowerStaticInst(mnem, _machInst, __opClass),
+rc(machInst.rc)
{
}
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index a65d7b7..7da5bf5 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -61,8 +61,10 @@
}
// Additional characters depending on isa bits being set
-if (oeSet) myMnemonic = myMnemonic + "o";
-if (rcSet) myMnemonic = myMnemonic + ".";
+if (oe)
+myMnemonic = myMnemonic + "o";
+if (rc)
+myMnemonic = myMnemonic + ".";
ccprintf(ss, "%-10s ", myMnemonic);
// Print the first destination only
@@ -116,7 +118,7 @@
}
// Print the immediate value last
-ss << ", " << (int32_t)imm;
+ss << ", " << (int32_t)si;
return ss.str();
}
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 04222a1..a25e65c 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -51,8 +51,8 @@
{
protected:
-bool rcSet;
-bool oeSet;
+bool rc;
+bool oe;
// Needed for srawi only
uint32_t sh;
@@ -60,7 +60,8 @@
/// Constructor
IntOp(const char *mnem, MachInst _machInst, OpClass __opClass)
: PowerStaticInst(mnem, _machInst, __opClass),
-rcSet(false), oeSet(false)
+rc(machInst.rc),
+oe(machInst.oe)
{
}
@@ -104,14 +105,14 @@
{
protected:
-int32_t imm;
-uint32_t uimm;
+int32_t si;
+uint32_t ui;
/// Constructor
IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
: IntOp(mnem, _machInst, __opClass),
-imm(sext<16>(machInst.si)),
-uimm(machInst.si)
+si(sext<16>(machInst.si)),
+ui(machInst.si)
{
}
@@ -121,6 +122,39 @@
/**
+ * Class for integer arithmetic operations.
+ */
+class IntArithOp : public IntOp
+{
+ protected:
+
+/// Constructor
+IntArithOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntOp(mnem, _machInst, __opClass)
+{
+}
+};
+
+
+/**
+ * Class for integer immediate arithmetic operations.
+ */
+class IntImmArithOp : public IntArithOp
+{
+ protected:
+
+int32_t si;
+
+/// Constructor
+IntImmArithOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntArithOp(mnem, _machInst, __opClass),
+si(sext<16>(machInst.si))
+{
+}
+};
+
+
+/**
* Class for integer operations with a shift.
*/
class IntShiftOp : public IntOp
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 3f51386..e993a7b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -39,42 +39,48 @@
format IntImmArithOp {
7: mulli({{
int32_t src = Ra_sw;
-int64_t prod = src * imm;
+int64_t prod = src * si;
Rt = (uint32_t)prod;
}});
-8: subfic({{ int32_t src = ~Ra; Rt = src + imm +
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add atomic load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40897 )
Change subject: arch-power: Add atomic load-store instructions
..
arch-power: Add atomic load-store instructions
This adds the following instructions.
* Load Byte And Reserve Indexed (lbarx)
* Load Halfword And Reserve Indexed (lharx)
* Load Doubleword And Reserve Indexed (ldarx)
* Store Byte Conditional Indexed (stbcx.)
* Store Halfword Conditional Indexed (sthcx.)
* Store Doubleword Conditional Indexed (stdcx.)
Change-Id: Ie85d57e7e111f06dd0f17f9f4d0953be44ef5fb8
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40897
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
1 file changed, 80 insertions(+), 3 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index d0d3dc9..3f51386 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -224,10 +224,29 @@
CR = insertCRField(CR, BF, cr);
}});
+52: LoadIndexOp::lbarx({{
+Rt = Mem_ub;
+Rsv = 1; RsvLen = 1; RsvAddr = EA;
+}});
+
53: LoadIndexUpdateOp::ldux({{ Rt = Mem; }});
55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
60: IntLogicOp::andc({{ Ra = Rs & ~Rb; }});
-87: LoadIndexOp::lbzx({{ Rt = Mem_ub; }});
+
+format LoadIndexOp {
+84: ldarx({{
+Rt = Mem_ud;
+Rsv = 1; RsvLen = 8; RsvAddr = EA;
+}});
+
+87: lbzx({{ Rt = Mem_ub; }});
+
+116: lharx({{
+Rt = Mem_uh;
+Rsv = 1; RsvLen = 2; RsvAddr = EA;
+}});
+}
+
119: LoadIndexUpdateOp::lbzux({{ Rt = Mem_ub; }});
124: IntLogicOp::nor({{ Ra = ~(Rs | Rb); }});
@@ -258,7 +277,27 @@
183: stwux({{ Mem_uw = Rs_uw; }});
}
-215: StoreIndexOp::stbx({{ Mem_ub = Rs_ub; }});
+format StoreIndexOp {
+214: stdcx({{
+bool store_performed = false;
+Mem = Rs;
+if (Rsv) {
+if (RsvLen == 8) {
+if (RsvAddr == EA) {
+store_performed = true;
+}
+}
+}
+Xer xer = XER;
+Cr cr = CR;
+cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
+CR = cr;
+Rsv = 0;
+}});
+
+215: stbx({{ Mem_ub = Rs_ub; }});
+}
+
246: MiscOp::dcbtst({{ }});
247: StoreIndexUpdateOp::stbux({{ Mem_ub = Rs_ub; }});
278: MiscOp::dcbt({{ }});
@@ -319,10 +358,48 @@
660: stdbrx({{ Mem = swap_byte(Rs); }});
662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
663: stfsx({{ Mem_sf = Fs_sf; }});
+
+694: stbcx({{
+bool store_performed = false;
+Mem_ub = Rs_ub;
+if (Rsv) {
+if (RsvLen == 1) {
+if (RsvAddr == EA) {
+store_performed = true;
+}
+}
+}
+Xer xer = XER;
+Cr cr = CR;
+cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
+CR = cr;
+Rsv = 0;
+}});
}
695: StoreIndexUpdateOp::stfsux({{ Mem_sf = Fs_sf; }});
-727: StoreIndexOp::stfdx({{ Mem_df = Fs; }});
+
+format StoreIndexOp {
+726: sthcx({{
+bool store_performed = false;
+Mem_uh = Rs_uh;
+if (Rsv) {
+if (RsvLen == 2) {
+if (RsvAddr == EA) {
+store_performed = true;
+}
+}
+}
+Xer xer = XER;
+Cr cr = CR;
+cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
+CR = cr;
+Rsv = 0;
+}});
+
+727: stfdx({{ Mem_df = Fs; }});
+}
+
759: StoreIndexUpdateOp::stfdux({{ Mem_df = Fs; }});
790: LoadIndexOp::lhbrx({{ Rt = swap_byte(Mem_uh); }});
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40897
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie85d57e7e111f06dd0f17f9f4d0953be44ef5fb8
Gerrit-Change-Number: 40897
Gerrit-PatchSet:
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add doubleword load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40895 )
Change subject: arch-power: Add doubleword load-store instructions
..
arch-power: Add doubleword load-store instructions
This introduces new formats for DS form instructions and
adds the following instructions.
* Load Doubleword (ld)
* Load Doubleword Indexed (ldx)
* Load Doubleword with Update (ldu)
* Load Doubleword with Update Indexed (ldux)
* Store Doubleword (std)
* Store Doubleword Indexed (stdx)
* Store Doubleword with Update (stdu)
* Store Doubleword with Update Indexed (stdux)
Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40895
Reviewed-by: Boris Shingarov
Reviewed-by: lkcl
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
2 files changed, 57 insertions(+), 1 deletion(-)
Approvals:
Boris Shingarov: Looks good to me, approved
lkcl: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index c81e65b..d0d3dc9 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -201,6 +201,7 @@
Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
+21: ldx({{ Rt = Mem; }});
23: lwzx({{ Rt = Mem_uw; }});
}
@@ -223,6 +224,7 @@
CR = insertCRField(CR, BF, cr);
}});
+53: LoadIndexUpdateOp::ldux({{ Rt = Mem; }});
55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
60: IntLogicOp::andc({{ Ra = Rs & ~Rb; }});
87: LoadIndexOp::lbzx({{ Rt = Mem_ub; }});
@@ -230,6 +232,7 @@
124: IntLogicOp::nor({{ Ra = ~(Rs | Rb); }});
format StoreIndexOp {
+149: stdx({{ Mem = Rs }});
150: stwcx({{
bool store_performed = false;
Mem_uw = Rs_uw;
@@ -250,7 +253,11 @@
151: stwx({{ Mem_uw = Rs_uw; }});
}
-183: StoreIndexUpdateOp::stwux({{ Mem = Rs; }});
+format StoreIndexUpdateOp {
+181: stdux({{ Mem = Rs; }});
+183: stwux({{ Mem_uw = Rs_uw; }});
+}
+
215: StoreIndexOp::stbx({{ Mem_ub = Rs_ub; }});
246: MiscOp::dcbtst({{ }});
247: StoreIndexUpdateOp::stbux({{ Mem_ub = Rs_ub; }});
@@ -543,6 +550,8 @@
55: StoreDispUpdateOp::stfdu({{ Mem_df = Fs; }});
58: decode DS_XO {
+0: LoadDispShiftOp::ld({{ Rt = Mem; }});
+1: LoadDispShiftUpdateOp::ldu({{ Rt = Mem; }});
2: LoadDispShiftOp::lwa({{ Rt = Mem_sw; }});
}
@@ -559,6 +568,11 @@
}
}
+62: decode DS_XO {
+0: StoreDispShiftOp::std({{ Mem = Rs; }});
+1: StoreDispShiftUpdateOp::stdu({{ Mem = Rs; }});
+}
+
63: decode A_XO {
format FloatArithOp {
20: fsub({{ Ft = Fa - Fb; }});
diff --git a/src/arch/power/isa/formats/mem.isa
b/src/arch/power/isa/formats/mem.isa
index d2b3ab7..4886296 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -311,6 +311,16 @@
}};
+def format StoreDispShiftOp(memacc_code,
+ea_code = {{ EA = Ra + (ds << 2); }},
+ea_code_ra0 = {{ EA = (ds << 2); }},
+mem_flags = [], inst_flags = []) {{
+(header_output, decoder_output, decode_block, exec_output) = \
+GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+ 'MemDispShiftOp', 'Store', mem_flags, inst_flags)
+}};
+
+
def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + d; }},
mem_flags = [], inst_flags = []) {{
@@ -339,3 +349,35 @@
decode_template = CheckRaZeroDecode,
exec_template_base = 'Store')
}};
+
+
+def format LoadDispShiftUpdateOp(memacc_code,
+ ea_code = {{ EA = Ra + (ds << 2); }},
+ mem_flags = [], inst_flags = []) {{
+
+# Add in the update code
+memacc_code += 'Ra = EA;'
+
+# Generate the class
+(header_output, decoder_output, decode_block, exec_output) = \
+LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
+ base_class = 'MemDispShiftOp',
+ decode_template = CheckRaRtDecode,
+ exec_template_base = 'Load')
+}};
+
+
+def format StoreDispShiftUpdateOp(memacc_code,
+ ea_code = {{ EA = Ra + (ds << 2); }},
+ mem_flags = [], inst_flags = []) {{
+
+# Add in the update code
+memacc_code += 'Ra = EA;'
+
+# Generate the class
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix disassembly for load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40894 )
Change subject: arch-power: Fix disassembly for load-store instructions
..
arch-power: Fix disassembly for load-store instructions
This fixes disassembly generated for load-store instructions
based on how the base classess that are used to distinguish
between the types of operands used by these instructions.
Change-Id: I5a0f8644cdc6fec934475536861ad342c0a1fb4c
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40894
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/insts/mem.cc
M src/arch/power/insts/mem.hh
2 files changed, 157 insertions(+), 4 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
index 3275623..a2954f8 100644
--- a/src/arch/power/insts/mem.cc
+++ b/src/arch/power/insts/mem.cc
@@ -38,6 +38,7 @@
return csprintf("%-10s", mnemonic);
}
+
std::string
MemDispOp::generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const
@@ -59,16 +60,162 @@
// Print the data register for a store
else {
-printReg(ss, srcRegIdx(1));
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
}
// Print the displacement
ss << ", " << d;
-
-// Print the address register
ss << "(";
-printReg(ss, srcRegIdx(0));
+
+// Print the address register for a load
+if (!flags[IsStore]) {
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
+
+// The address register is skipped if it is R0
+else {
+ss << "0";
+}
+}
+
+// Print the address register for a store
+else {
+if (_numSrcRegs > 1) {
+printReg(ss, srcRegIdx(1));
+}
+
+// The address register is skipped if it is R0
+else {
+ss << "0";
+}
+}
+
ss << ")";
return ss.str();
}
+
+
+std::string
+MemDispShiftOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+
+ccprintf(ss, "%-10s ", mnemonic);
+
+// Print the destination only for a load
+if (!flags[IsStore]) {
+if (_numDestRegs > 0) {
+
+// If the instruction updates the source register with the
+// EA, then this source register is placed in position 0,
+// therefore we print the last destination register.
+printReg(ss, destRegIdx(_numDestRegs-1));
+}
+}
+
+// Print the data register for a store
+else {
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
+}
+
+// Print the displacement
+ss << ", " << (ds << 2);
+ss << "(";
+
+// Print the address register for a load
+if (!flags[IsStore]) {
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
+
+// The address register is skipped if it is R0
+else {
+ss << "0";
+}
+}
+
+// Print the address register for a store
+else {
+if (_numSrcRegs > 1) {
+printReg(ss, srcRegIdx(1));
+}
+
+// The address register is skipped if it is R0
+else {
+ss << "0";
+}
+}
+
+ss << ")";
+
+return ss.str();
+}
+
+
+std::string
+MemIndexOp::generateDisassembly(
+Addr pc, const Loader::SymbolTable *symtab) const
+{
+std::stringstream ss;
+
+ccprintf(ss, "%-10s ", mnemonic);
+
+// Print the destination only for a load
+if (!flags[IsStore]) {
+if (_numDestRegs > 0) {
+
+// If the instruction updates the source register with the
+// EA, then this source register is placed in position 0,
+// therefore we print the last destination register.
+printReg(ss, destRegIdx(_numDestRegs-1));
+}
+}
+
+// Print the data register for a store
+else {
+if (_numSrcRegs > 0) {
+printReg(ss, srcRegIdx(0));
+}
+}
+
+ss << ", ";
+
+// Print the address registers for a load
+if (!flags[IsStore]) {
+if (_numSrcRegs > 1) {
+printReg(ss, srcRegIdx(0));
+ss << ", ";
+printReg(ss, srcRegIdx(1));
+}
+
+// The first address register is skipped if it is R0
+else if (_numSrcRegs > 0) {
+ss << "0, ";
+printReg(ss, srcRegIdx(0));
+}
+}
+
+// Print the address registers for a store
+else {
+if (_numSrcRegs > 2) {
+printReg(ss, srcRegIdx(1));
+ss << ", ";
+printReg(ss, srcRegIdx(2));
+}
+
+
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40893 )
Change subject: arch-power: Fix load-store instructions
..
arch-power: Fix load-store instructions
Now that 64-bit registers and operands are being used, the
instructions for words must read or write just one word at
a time. This fixes the following instructions.
* Load Word and Zero (lwz)
* Load Word and Zero Indexed (lwzx)
* Load Word and Zero with Update (lwzu)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word And Reserve Indexed (lwarx)
* Store Word (stw)
* Store Word Indexed (stwx)
* Store Word with Update (stwu)
* Store Word with Update Indexed (stwux)
* Store Word Conditional Indexed (stwcx.)
This also fixes decoding of load-store update instructions
for some special scenarios when RA is zero or RA and RT
are the same. In such cases, the instruction is considered
invalid.
Change-Id: I6787d3614ba8f1b1cbf30a49f85ef422324d7c21
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40893
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/formats/util.isa
3 files changed, 37 insertions(+), 9 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 0cf6201..c81e65b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -196,8 +196,12 @@
}});
format LoadIndexOp {
-20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
-23: lwzx({{ Rt = Mem; }});
+20: lwarx({{
+Rt = Mem_uw;
+Rsv = 1; RsvLen = 4; RsvAddr = EA;
+}});
+
+23: lwzx({{ Rt = Mem_uw; }});
}
format IntLogicOp {
@@ -219,7 +223,7 @@
CR = insertCRField(CR, BF, cr);
}});
-55: LoadIndexUpdateOp::lwzux({{ Rt = Mem; }});
+55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
60: IntLogicOp::andc({{ Ra = Rs & ~Rb; }});
87: LoadIndexOp::lbzx({{ Rt = Mem_ub; }});
119: LoadIndexUpdateOp::lbzux({{ Rt = Mem_ub; }});
@@ -228,7 +232,7 @@
format StoreIndexOp {
150: stwcx({{
bool store_performed = false;
-Mem = Rs;
+Mem_uw = Rs_uw;
if (Rsv) {
if (RsvLen == 4) {
if (RsvAddr == EA) {
@@ -243,7 +247,7 @@
Rsv = 0;
}});
-151: stwx({{ Mem = Rs; }});
+151: stwx({{ Mem_uw = Rs_uw; }});
}
183: StoreIndexUpdateOp::stwux({{ Mem = Rs; }});
@@ -515,12 +519,12 @@
}
}
-32: LoadDispOp::lwz({{ Rt = Mem; }});
-33: LoadDispUpdateOp::lwzu({{ Rt = Mem; }});
+32: LoadDispOp::lwz({{ Rt = Mem_uw; }});
+33: LoadDispUpdateOp::lwzu({{ Rt = Mem_uw; }});
34: LoadDispOp::lbz({{ Rt = Mem_ub; }});
35: LoadDispUpdateOp::lbzu({{ Rt = Mem_ub; }});
-36: StoreDispOp::stw({{ Mem = Rs; }});
-37: StoreDispUpdateOp::stwu({{ Mem = Rs; }});
+36: StoreDispOp::stw({{ Mem_uw = Rs_uw; }});
+37: StoreDispUpdateOp::stwu({{ Mem_uw = Rs_uw; }});
38: StoreDispOp::stb({{ Mem_ub = Rs_ub; }});
39: StoreDispUpdateOp::stbu({{ Mem_ub = Rs_ub; }});
40: LoadDispOp::lhz({{ Rt = Mem_uh; }});
diff --git a/src/arch/power/isa/formats/mem.isa
b/src/arch/power/isa/formats/mem.isa
index 8e6567d..d2b3ab7 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -263,6 +263,7 @@
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
base_class = 'MemIndexOp',
+ decode_template = CheckRaRtDecode,
exec_template_base = 'Load')
}};
@@ -277,6 +278,7 @@
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
base_class = 'MemIndexOp',
+ decode_template = CheckRaZeroDecode,
exec_template_base = 'Store')
}};
@@ -319,6 +321,7 @@
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
base_class = 'MemDispOp',
+ decode_template = CheckRaRtDecode,
exec_template_base = 'Load')
}};
@@ -333,5 +336,6 @@
(header_output, decoder_output, decode_block, exec_output) = \
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add byte-reversed load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40896 )
Change subject: arch-power: Add byte-reversed load-store instructions
..
arch-power: Add byte-reversed load-store instructions
This adds the following instructions.
* Load Halfword Byte-Reverse Indexed (lhbrx)
* Load Word Byte-Reverse Indexed (lwbrx)
* Load Doubleword Byte-Reverse Indexed (ldbrx)
* Store Halfword Byte-Reverse Indexed (sthbrx)
* Store Word Byte-Reverse Indexed (stwbrx)
* Store Doubleword Byte-Reverse Indexed (stdbrx)
Change-Id: Id7aae44c370d6376410ab8c82839b908ea6ca196
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40896
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
1 file changed, 14 insertions(+), 2 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e00ce3b..0cf6201 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -285,7 +285,11 @@
}});
}
-535: LoadIndexOp::lfsx({{ Ft_sf = Mem_sf; }});
+format LoadIndexOp {
+532: ldbrx({{ Rt = swap_byte(Mem); }});
+534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
+535: lfsx({{ Ft_sf = Mem_sf; }});
+}
536: IntLogicOp::srw({{
if (Rb & 0x20) {
@@ -299,10 +303,17 @@
598: MiscOp::sync({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
599: LoadIndexOp::lfdx({{ Ft = Mem_df; }});
631: LoadIndexUpdateOp::lfdux({{ Ft = Mem_df; }});
-663: StoreIndexOp::stfsx({{ Mem_sf = Fs_sf; }});
+
+format StoreIndexOp {
+660: stdbrx({{ Mem = swap_byte(Rs); }});
+662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
+663: stfsx({{ Mem_sf = Fs_sf; }});
+}
+
695: StoreIndexUpdateOp::stfsux({{ Mem_sf = Fs_sf; }});
727: StoreIndexOp::stfdx({{ Mem_df = Fs; }});
759: StoreIndexUpdateOp::stfdux({{ Mem_df = Fs; }});
+790: LoadIndexOp::lhbrx({{ Rt = swap_byte(Mem_uh); }});
792: IntLogicOp::sraw({{
bool shiftSetCA = false;
@@ -364,6 +375,7 @@
854: MiscOp::eieio({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
855: LoadIndexOp::lfiwax({{ Ft_uw = Mem; }});
+918: StoreIndexOp::sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
format IntLogicOp {
922: extsh({{ Ra = sext<16>(Rs); }});
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40896
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id7aae44c370d6376410ab8c82839b908ea6ca196
Gerrit-Change-Number: 40896
Gerrit-PatchSet: 7
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: Gabe Black
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40892 )
Change subject: arch-power: Refactor load-store instructions
..
arch-power: Refactor load-store instructions
This changes the base classes for load-store instructions
and introduces two new classes for DS form instructions
which use a shifted signed immediate field as the offset
from the base address and for X form instructions which
use registers for both the offset and the base address.
The formats have also been updated to make use of the new
base classes.
Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40892
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/insts/mem.cc
M src/arch/power/insts/mem.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
4 files changed, 57 insertions(+), 16 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
index 596d78d..4c2688c 100644
--- a/src/arch/power/insts/mem.cc
+++ b/src/arch/power/insts/mem.cc
@@ -63,7 +63,7 @@
}
// Print the displacement
-ss << ", " << (int32_t)disp;
+ss << ", " << d;
// Print the address register
ss << "(";
diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index de9b46c..e982515 100644
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -63,11 +63,12 @@
{
protected:
-int16_t disp;
+int64_t d;
/// Constructor
MemDispOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : MemOp(mnem, _machInst, __opClass), disp(machInst.d)
+ : MemOp(mnem, _machInst, __opClass),
+d(sext<16>(machInst.d))
{
}
@@ -75,6 +76,38 @@
Addr pc, const Loader::SymbolTable *symtab) const override;
};
+/**
+ * Class for memory operations with shifted displacement.
+ */
+class MemDispShiftOp : public MemOp
+{
+ protected:
+
+int64_t ds;
+
+/// Constructor
+MemDispShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : MemOp(mnem, _machInst, __opClass),
+ds(sext<14>(machInst.ds))
+{
+}
+};
+
+
+/**
+ * Class for memory operations with register indexed addressing.
+ */
+class MemIndexOp : public MemOp
+{
+ protected:
+
+/// Constructor
+MemIndexOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : MemOp(mnem, _machInst, __opClass)
+{
+}
+};
+
} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_MEM_HH__
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index ac52ab3..e00ce3b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -527,9 +527,7 @@
55: StoreDispUpdateOp::stfdu({{ Mem_df = Fs; }});
58: decode DS_XO {
-2: LoadDispOp::lwa({{ Rt = Mem_sw; }},
- {{ EA = Ra + (disp & 0xfffc); }},
- {{ EA = disp & 0xfffc; }});
+2: LoadDispShiftOp::lwa({{ Rt = Mem_sw; }});
}
format FloatArithOp {
diff --git a/src/arch/power/isa/formats/mem.isa
b/src/arch/power/isa/formats/mem.isa
index c7be2b1..1b2500c 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -240,7 +240,7 @@
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
- 'MemOp', 'Load', mem_flags, inst_flags)
+ 'MemIndexOp', 'Load', mem_flags, inst_flags)
}};
@@ -249,7 +249,7 @@
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
- 'MemOp', 'Store', mem_flags, inst_flags)
+ 'MemIndexOp', 'Store', mem_flags, inst_flags)
}};
@@ -262,7 +262,7 @@
# Generate the class
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
- base_class = 'MemOp',
+ base_class = 'MemIndexOp',
exec_template_base = 'Load')
}};
@@ -276,13 +276,13 @@
# Generate the class
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
- base_class = 'MemOp',
+ base_class = 'MemIndexOp',
exec_template_base = 'Store')
}};
-def format LoadDispOp(memacc_code, ea_code = {{ EA = Ra + disp;
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add fields for DS form instructions
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40891 ) Change subject: arch-power: Add fields for DS form instructions .. arch-power: Add fields for DS form instructions This introduces the DS field used by DS form instructions which specifies a signed integer immediate operand. Change-Id: I0e7a77e7a63fce4e50b7941850c277f556e65724 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40891 Reviewed-by: Boris Shingarov Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- M src/arch/power/types.hh 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index 72dcd1e..1e896e4 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -52,6 +52,7 @@ // Immediate fields Bitfield<15, 0> si; Bitfield<15, 0> d; +Bitfield<15, 2> ds; // Special purpose register identifier Bitfield<20, 11> spr; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40891 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I0e7a77e7a63fce4e50b7941850c277f556e65724 Gerrit-Change-Number: 40891 Gerrit-PatchSet: 6 Gerrit-Owner: Sandipan Das Gerrit-Reviewer: Boris Shingarov Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix precedence of register operands
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40890 )
Change subject: arch-power: Fix precedence of register operands
..
arch-power: Fix precedence of register operands
When RS and RA are both used as operands by an instruction,
RS takes precedence over RA. In such cases, either both the
register operands are used as sources or RS is a source and
RA is a destination.
This changes the order by giving RS the highest precedence
and will be useful for proper disassembly generation.
Change-Id: If351a03a814653f2f371afa936ec7a5cd4377b3a
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40890
Reviewed-by: Boris Shingarov
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/isa/operands.isa
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index 23cf50b..8cb39eb 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -41,9 +41,9 @@
def operands {{
# General Purpose Integer Reg Operands
-'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 1),
-'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 2),
-'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 3),
+'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
+'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
+'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
# General Purpose Floating Point Reg Operands
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40890
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If351a03a814653f2f371afa936ec7a5cd4377b3a
Gerrit-Change-Number: 40890
Gerrit-PatchSet: 6
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add TAR and associated instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40889 )
Change subject: arch-power: Add TAR and associated instructions
..
arch-power: Add TAR and associated instructions
This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it.
* Move To Target Address Register (mttar)
* Move From Target Address Register (mftar)
* Branch Conditional to Branch Target Address Register (bctar[l])
Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40889
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/insts/integer.cc
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/operands.isa
M src/arch/power/regs/int.hh
4 files changed, 15 insertions(+), 5 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index fdf3b51..c10abe6 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -49,12 +49,14 @@
myMnemonic == "mtxer" ||
myMnemonic == "mtlr" ||
myMnemonic == "mtctr" ||
+ myMnemonic == "mttar" ||
myMnemonic == "cmpi") {
printDest = false;
} else if (myMnemonic == "mfcr" ||
myMnemonic == "mfxer" ||
myMnemonic == "mflr" ||
- myMnemonic == "mfctr") {
+ myMnemonic == "mfctr" ||
+ myMnemonic == "mftar") {
printSrcs = false;
}
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e4f57ca..ac52ab3 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -152,8 +152,12 @@
}});
}
-// Conditionally branch to address in CTR based on CR.
-528: BranchRegCondOp::bcctr({{ NIA = CTR & -4ULL; }});
+// Conditionally branch to an address in a register based on
+// either CR only or both CR and CTR.
+format BranchRegCondOp {
+528: bcctr({{ NIA = CTR & -4ULL; }});
+560: bctar({{ NIA = TAR & -4ULL; }}, true);
+}
}
format IntRotateOp {
@@ -480,12 +484,14 @@
0x20: mfxer({{ Rt = XER; }});
0x100: mflr({{ Rt = LR; }});
0x120: mfctr({{ Rt = CTR; }});
+0x1f9: mftar({{ Rt = TAR; }});
}
467: decode SPR {
0x20: mtxer({{ XER = Rs; }});
0x100: mtlr({{ LR = Rs; }});
0x120: mtctr({{ CTR = Rs; }});
+0x1f9: mttar({{ TAR = Rs; }});
}
512: mcrxr({{
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index 07415ba..23cf50b 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -64,6 +64,7 @@
'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
+'TAR': ('IntReg', 'ud', 'INTREG_TAR', 'IsInteger', 9),
'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
# Setting as IntReg so things are stored as an integer, not double
diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
index 7d63f79..2d6a16b 100644
--- a/src/arch/power/regs/int.hh
+++ b/src/arch/power/regs/int.hh
@@ -35,9 +35,9 @@
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
-// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
+// CR, XER, LR, CTR, TAR, FPSCR, RSV, RSV-LEN, RSV-ADDR
// and zero register, which doesn't actually exist but needs a number
-const int NumIntSpecialRegs = 9;
+const int NumIntSpecialRegs = 10;
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
@@ -51,6 +51,7 @@
INTREG_XER,
INTREG_LR,
INTREG_CTR,
+INTREG_TAR,
INTREG_FPSCR,
INTREG_RSV,
INTREG_RSV_LEN,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40889
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Gerrit-Change-Number: 40889
Gerrit-PatchSet: 6
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix disassembly for branch instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40888 )
Change subject: arch-power: Fix disassembly for branch instructions
..
arch-power: Fix disassembly for branch instructions
This fixes disassembly generated for branch instructions
based on the AA and LK bits which determine how the target
address is calculated and whether a return address needs
to be set implicitly or not.
Change-Id: I1acba72c360a1fcb4691de17fbae1a012a752dbe
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40888
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/insts/branch.cc
1 file changed, 30 insertions(+), 5 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 1077f33..1789734 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -67,7 +67,16 @@
std::stringstream ss;
Addr target;
-ccprintf(ss, "%-10s ", mnemonic);
+// Generate correct mnemonic
+std::string myMnemonic(mnemonic);
+std::string suffix;
+
+// Additional characters depending on isa bits being set
+if (lk)
+suffix += "l";
+if (aa)
+suffix += "a";
+ccprintf(ss, "%-10s ", myMnemonic + suffix);
if (aa)
target = li;
@@ -102,10 +111,19 @@
std::stringstream ss;
Addr target;
-ccprintf(ss, "%-10s ", mnemonic);
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+std::string suffix;
+
+// Additional characters depending on isa bits being set
+if (lk)
+suffix += "l";
+if (aa)
+suffix += "a";
+ccprintf(ss, "%-10s ", myMnemonic + suffix);
// Print BI and BO fields
-ss << bi << ", " << bo << ", ";
+ss << (int) bi << ", " << (int) bo << ", ";
if (aa)
target = bd;
@@ -136,10 +154,17 @@
{
std::stringstream ss;
-ccprintf(ss, "%-10s ", mnemonic);
+// Generate the correct mnemonic
+std::string myMnemonic(mnemonic);
+std::string suffix;
+
+// Additional characters depending on isa bits being set
+if (lk)
+suffix += "l";
+ccprintf(ss, "%-10s ", myMnemonic + suffix);
// Print the BI and BO fields
-ss << bi << ", " << bo;
+ss << (int) bi << ", " << (int) bo;
return ss.str();
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40888
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1acba72c360a1fcb4691de17fbae1a012a752dbe
Gerrit-Change-Number: 40888
Gerrit-PatchSet: 6
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix branch conditional instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40887 )
Change subject: arch-power: Fix branch conditional instructions
..
arch-power: Fix branch conditional instructions
Among the register-based conditional branch instructions,
the ones using CTR should not decrement CTR when the bit
corresponding to this action is set in the BO field of
the instruction. In this case, the instruction should be
considered invalid. This fixes the following instructions.
* Branch Conditional to Count Register (bcctr[l])
Change-Id: Ib2dbf2bc36fced580b4b7f7b76783f68361f6bbf
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40887
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/util.isa
3 files changed, 17 insertions(+), 2 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/bitfields.isa
b/src/arch/power/isa/bitfields.isa
index 3ea6d8c..771a822 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -69,6 +69,7 @@
def bitfield FXM <19:12>;
// Branch fields
+def bitfield BO<25:21>;
def bitfield LK<0>;
def bitfield AA<1>;
diff --git a/src/arch/power/isa/formats/branch.isa
b/src/arch/power/isa/formats/branch.isa
index 2f50627..b970bc0 100644
--- a/src/arch/power/isa/formats/branch.isa
+++ b/src/arch/power/isa/formats/branch.isa
@@ -156,8 +156,10 @@
# Setup the 2 code versions and add code to update LR if necessary
if checkCTR:
code = GetCtrCondCode(code)
+decode_template = CheckLkDecode
else:
code = GetCondCode(code)
+decode_template = CheckBoLkDecode
code_lk1 = code + updateLrCode
inst_flags_lk1 = inst_flags + [ 'IsCall' ]
@@ -168,10 +170,10 @@
# Generate the classes
(header_output, decoder_output, decode_block, exec_output) = \
GenAluOp(name, Name, 'BranchRegCondOp', code, inst_flags,
- CheckLkDecode, BasicConstructor)
+ decode_template, BasicConstructor)
(header_output_lk1, decoder_output_lk1, _, exec_output_lk1) = \
GenAluOp(name, Name + 'LkSet', 'BranchRegCondOp', code_lk1,
- inst_flags_lk1, CheckLkDecode, BasicConstructor)
+ inst_flags_lk1, decode_template, BasicConstructor)
# Finally, add to the other outputs
header_output += header_output_lk1
diff --git a/src/arch/power/isa/formats/util.isa
b/src/arch/power/isa/formats/util.isa
index 34bebb0..529d07b 100644
--- a/src/arch/power/isa/formats/util.isa
+++ b/src/arch/power/isa/formats/util.isa
@@ -111,6 +111,18 @@
}
}};
+def template CheckBoLkDecode {{
+ {
+ if (!bits(BO, 2)) {
+ return new Unknown(machInst);
+ } else if (LK == 0) {
+ return new %(class_name)s(machInst);
+ } else {
+ return new %(class_name)sLkSet(machInst);
+ }
+ }
+}};
+
let {{
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40887
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib2dbf2bc36fced580b4b7f7b76783f68361f6bbf
Gerrit-Change-Number: 40887
Gerrit-PatchSet: 6
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-CC: lkcl
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor branch instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40886 )
Change subject: arch-power: Refactor branch instructions
..
arch-power: Refactor branch instructions
This changes the base classes for branch instructions and
switches to two high-level classes for unconditional and
conditional branches. The conditional branches are further
classified based on whether they use an immediate field or
a register for determining the target address.
Decoding has also been consolidated using formats that can
generate code after determining if an instruction branches
to an absolute address or a PC-relative address, or if it
implicitly sets the return address by looking at the AA and
LK bits.
Change-Id: I5fa7db7b6693586b4ea3c71e5cad8a60753de29c
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40886
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/insts/branch.cc
M src/arch/power/insts/branch.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/branch.isa
M src/arch/power/isa/formats/util.isa
M src/arch/power/types.hh
6 files changed, 224 insertions(+), 330 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 84834f1..1077f33 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -49,21 +49,30 @@
return *cachedDisassembly;
}
+
PowerISA::PCState
-BranchPCRel::branchTarget(const PowerISA::PCState ) const
+BranchOp::branchTarget(const PowerISA::PCState ) const
{
-return (uint32_t)(pc.pc() + disp);
+if (aa)
+return li;
+else
+return pc.pc() + li;
}
+
std::string
-BranchPCRel::generateDisassembly(
+BranchOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
+Addr target;
ccprintf(ss, "%-10s ", mnemonic);
-Addr target = pc + disp;
+if (aa)
+target = li;
+else
+target = pc + li;
Loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(target)) != symtab->end())
@@ -74,46 +83,34 @@
return ss.str();
}
+
PowerISA::PCState
-BranchNonPCRel::branchTarget(const PowerISA::PCState ) const
+BranchDispCondOp::branchTarget(const PowerISA::PCState ) const
{
-return targetAddr;
+if (aa) {
+return bd;
+} else {
+return pc.pc() + bd;
+}
}
+
std::string
-BranchNonPCRel::generateDisassembly(
+BranchDispCondOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
+Addr target;
ccprintf(ss, "%-10s ", mnemonic);
-Loader::SymbolTable::const_iterator it;
-if (symtab && (it = symtab->find(targetAddr)) != symtab->end())
-ss << it->name;
+// Print BI and BO fields
+ss << bi << ", " << bo << ", ";
+
+if (aa)
+target = bd;
else
-ccprintf(ss, "%#x", targetAddr);
-
-return ss.str();
-}
-
-PowerISA::PCState
-BranchPCRelCond::branchTarget(const PowerISA::PCState ) const
-{
-return (uint32_t)(pc.pc() + disp);
-}
-
-std::string
-BranchPCRelCond::generateDisassembly(
-Addr pc, const Loader::SymbolTable *symtab) const
-{
-std::stringstream ss;
-
-ccprintf(ss, "%-10s ", mnemonic);
-
-ss << bo << ", " << bi << ", ";
-
-Addr target = pc + disp;
+target = pc + bd;
Loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(target)) != symtab->end())
@@ -124,47 +121,25 @@
return ss.str();
}
+
PowerISA::PCState
-BranchNonPCRelCond::branchTarget(const PowerISA::PCState ) const
+BranchRegCondOp::branchTarget(ThreadContext *tc) const
{
-return targetAddr;
+Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
+return addr & -4ULL;
}
+
std::string
-BranchNonPCRelCond::generateDisassembly(
+BranchRegCondOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s ", mnemonic);
-ss << bo << ", " << bi << ", ";
-
-Loader::SymbolTable::const_iterator it;
-if (symtab && (it = symtab->find(targetAddr)) != symtab->end())
-ss << it->name;
-else
-ccprintf(ss, "%#x", targetAddr);
-
-return ss.str();
-}
-
-PowerISA::PCState
-BranchRegCond::branchTarget(ThreadContext *tc) const
-{
-uint32_t regVal = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index());
-return regVal & 0xfffc;
-}
-
-std::string
-BranchRegCond::generateDisassembly(
-Addr pc, const Loader::SymbolTable *symtab) const
-{
-std::stringstream ss;
-
-ccprintf(ss, "%-10s ", mnemonic);
-
-ss << bo << ", " << bi << ", ";
+// Print the BI and BO
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix extended opcode based decoding
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40885 )
Change subject: arch-power: Fix extended opcode based decoding
..
arch-power: Fix extended opcode based decoding
When multiple instructions share the same primary opcode,
the decoder can distinguish between them by looking at the
extended opcode field. However, the length and position of
the extended opcode field can slightly vary depending on
the instruction form.
This ensures that the correct extended opcode fields are
used for decoding such instructions.
Change-Id: I8207568ac975587377abba8a9b221ca3097b8488
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40885
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
1 file changed, 170 insertions(+), 162 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 1a8b375..8ffe007 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -97,7 +97,7 @@
1: BranchNonPCRel::ba({{ NIA = targetAddr; }});
}
-19: decode XO_XO {
+19: decode XL_XO {
0: CondMoveOp::mcrf({{
uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
@@ -181,12 +181,18 @@
29: andis_({{ Ra = Rs & (uimm << 16); }}, true);
}
-// Some instructions use bits 21 - 30, others 22 - 30. We have to use
-// the larger size to account for all opcodes. For those that use the
-// smaller value, the OE bit is bit 21. Therefore, we have two versions
-// of each instruction: 1 with OE set, the other without. For an
-// example see 'add' and 'addo'.
-31: decode XO_XO {
+// There are a large number of instructions that have the same primary
+// opcode (PO) of 31. In this case, the instructions are of different
+// forms. For every form, the XO fields may vary in position and width.
+// The X, XFL, XFX and XL form instructions use bits 21 - 30 and the
+// XO form instructions use bits 22 - 30 as extended opcode (XO). To
+// avoid conflicts, instructions of each form have to be defined under
+// separate decode blocks. However, only a single decode block can be
+// associated with a particular PO and it will recognize only one type
+// of XO field. A solution for associating decode blocks for the other
+// types of XO fields with the same PO is to have the other blocks as
+// nested default cases.
+31: decode X_XO {
0: IntOp::cmp({{
Xer xer = XER;
@@ -194,16 +200,6 @@
CR = insertCRField(CR, BF, cr);
}});
-8: IntSumOp::subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }}, true);
-10: IntSumOp::addc({{ Ra }}, {{ Rb }}, computeCA = true);
-
-11: IntArithOp::mulhwu({{
-uint64_t prod = Ra_ud * Rb_ud;
-Rt = prod >> 32;
-}});
-
-19: IntOp::mfcr({{ Rt = CR; }});
-
format LoadIndexOp {
20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
23: lwzx({{ Rt = Mem; }});
@@ -228,35 +224,12 @@
CR = insertCRField(CR, BF, cr);
}});
-40: IntSumOp::subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
55: LoadIndexUpdateOp::lwzux({{ Rt = Mem; }});
60: IntLogicOp::andc({{ Ra = Rs & ~Rb; }});
-
-75: IntArithOp::mulhw({{
-int64_t prod = Ra_sd * Rb_sd;
-Rt = prod >> 32;
-}});
-
87: LoadIndexOp::lbzx({{ Rt = Mem_ub; }});
-104: IntSumOp::neg({{ ~Ra }}, {{ 1 }});
119: LoadIndexUpdateOp::lbzux({{ Rt = Mem_ub; }});
124: IntLogicOp::nor({{ Ra = ~(Rs | Rb); }});
-format IntSumOp {
-136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }}, true);
-138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }}, true);
-}
-
-144: IntOp::mtcrf({{
-uint32_t mask = 0;
-for (int i = 0; i < 8; ++i) {
-if (((FXM >> i) & 0x1) == 0x1) {
-mask |= 0xf << (4 * i);
-}
-}
-CR = (Rs & mask) | (CR & ~mask);
-}});
-
format StoreIndexOp {
150: stwcx({{
bool store_performed = false;
@@ -279,51 +252,15 @@
}
183: StoreIndexUpdateOp::stwux({{ Mem = Rs; }});
-
-format IntSumOp {
-200: subfze({{ ~Ra }}, {{ xer.ca }}, computeCA = true);
-202: addze({{ Ra }}, {{ xer.ca }}, computeCA = true);
-}
-
215: StoreIndexOp::stbx({{ Mem_ub = Rs_ub; }});
-
-format IntSumOp {
-232: subfme({{ ~Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }}, true);
-234: addme({{ Ra }}, {{ (uint32_t)-1 }}, {{
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix disassembly for SPR move instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40882 )
Change subject: arch-power: Fix disassembly for SPR move instructions
..
arch-power: Fix disassembly for SPR move instructions
This fixes disassembly generated for move-to and move-from
Special Purpose Register (SPR) instructions.
Change-Id: I03f10e3a44a8437beec453dfae2207d71ce43c1e
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40882
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/insts/integer.cc
1 file changed, 10 insertions(+), 3 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index febd469..fdf3b51 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -42,12 +42,19 @@
std::string myMnemonic(mnemonic);
// Special cases
-if (!myMnemonic.compare("or") && srcRegIdx(0) == srcRegIdx(1)) {
+if (myMnemonic == "or" && srcRegIdx(0) == srcRegIdx(1)) {
myMnemonic = "mr";
printSecondSrc = false;
-} else if (!myMnemonic.compare("mtlr") || !myMnemonic.compare("cmpi"))
{
+} else if (myMnemonic == "mtcrf" ||
+ myMnemonic == "mtxer" ||
+ myMnemonic == "mtlr" ||
+ myMnemonic == "mtctr" ||
+ myMnemonic == "cmpi") {
printDest = false;
-} else if (!myMnemonic.compare("mflr")) {
+} else if (myMnemonic == "mfcr" ||
+ myMnemonic == "mfxer" ||
+ myMnemonic == "mflr" ||
+ myMnemonic == "mfctr") {
printSrcs = false;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40882
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I03f10e3a44a8437beec453dfae2207d71ce43c1e
Gerrit-Change-Number: 40882
Gerrit-PatchSet: 7
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests, arch-power: Add 64-bit hello binaries
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40951 ) Change subject: tests, arch-power: Add 64-bit hello binaries .. tests, arch-power: Add 64-bit hello binaries This adds 64-bit statically linked big and little endian binaries for the hello test program. It should be noted that all possible combinations of ABI version and endianness are possible for 64-bit binaries. However, standard toolchains always use ELF ABI v1 for big endian and ELF ABI v2 for little endian binaries. Change-Id: I2dca7eaa2b04a7b68b117ada799d4c3bb69368be Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40951 Reviewed-by: Boris Shingarov Reviewed-by: Bobby R. Bruce Tested-by: kokoro Maintainer: Bobby R. Bruce --- A tests/test-progs/hello/bin/power/linux/hello64be A tests/test-progs/hello/bin/power/linux/hello64le 2 files changed, 0 insertions(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/tests/test-progs/hello/bin/power/linux/hello64be b/tests/test-progs/hello/bin/power/linux/hello64be new file mode 100644 index 000..53604fb --- /dev/null +++ b/tests/test-progs/hello/bin/power/linux/hello64be Binary files differ diff --git a/tests/test-progs/hello/bin/power/linux/hello64le b/tests/test-progs/hello/bin/power/linux/hello64le new file mode 100644 index 000..b442d9a --- /dev/null +++ b/tests/test-progs/hello/bin/power/linux/hello64le Binary files differ 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40951 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2dca7eaa2b04a7b68b117ada799d4c3bb69368be Gerrit-Change-Number: 40951 Gerrit-PatchSet: 6 Gerrit-Owner: Sandipan Das Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Boris Shingarov Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests, arch-power: Move 32-bit hello binary
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40950 ) Change subject: tests, arch-power: Move 32-bit hello binary .. tests, arch-power: Move 32-bit hello binary This moves the 32-bit hello binary for Power under the linux subdirectory like it was originally before being removed and reintroduced. Change-Id: I5f3da38f9abdda90b31755ce7e7c955838cc7289 Signed-off-by: Sandipan Das Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40950 Reviewed-by: Boris Shingarov Reviewed-by: Bobby R. Bruce Tested-by: kokoro Maintainer: Bobby R. Bruce --- R tests/test-progs/hello/bin/power/linux/hello32 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: Boris Shingarov: Looks good to me, approved Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/tests/test-progs/hello/bin/power/hello32 b/tests/test-progs/hello/bin/power/linux/hello32 similarity index 100% rename from tests/test-progs/hello/bin/power/hello32 rename to tests/test-progs/hello/bin/power/linux/hello32 Binary files differ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40950 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I5f3da38f9abdda90b31755ce7e7c955838cc7289 Gerrit-Change-Number: 40950 Gerrit-PatchSet: 6 Gerrit-Owner: Sandipan Das Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Boris Shingarov Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests, arch-power: Add support for building hello
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40949 )
Change subject: tests, arch-power: Add support for building hello
..
tests, arch-power: Add support for building hello
Commit a440108cc ("tests: Add Makefiles for hello")
introduced Makefiles for building the hello test binary
for ARM and x86 using dockcross. Since dockcross also
provides an image with a 64-bit little endian toolchain
for Power, this adds a Makefile for building the hello
binary.
As of this moment, 64-bit little endian (ppc64le) is the
prevalent variant supported by most distributions. Hence,
we are currently limited to only building the binary for
this variant.
Change-Id: Ic20322ca33c69634d9f17d30b29e522cc35742fb
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40949
Tested-by: kokoro
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
---
A tests/test-progs/hello/src/Makefile.power
1 file changed, 11 insertions(+), 0 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/test-progs/hello/src/Makefile.power
b/tests/test-progs/hello/src/Makefile.power
new file mode 100644
index 000..6fb280a
--- /dev/null
+++ b/tests/test-progs/hello/src/Makefile.power
@@ -0,0 +1,11 @@
+all: hello64le-static
+
+hello64le-static: hello.c dockcross-ppc64le
+ ./dockcross-ppc64le bash -c '$$CC hello.c -o hello64le-static -static'
+
+dockcross-ppc64le:
+ docker run --rm dockcross/linux-ppc64le > ./dockcross-ppc64le
+ chmod +x ./dockcross-ppc64le
+
+clean:
+ rm -f dockcross* hello64le-static
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40949
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic20322ca33c69634d9f17d30b29e522cc35742fb
Gerrit-Change-Number: 40949
Gerrit-PatchSet: 6
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add and rename some opcode fields
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40884 )
Change subject: arch-power: Add and rename some opcode fields
..
arch-power: Add and rename some opcode fields
This introduces separate extended opcode (XO) fields for DS,
X, XFL, XFX, XL and XO form instructions and renames the
primary opcode field to PO based on the convention used in
the Power ISA manual.
Change-Id: I82598efe74c02960f38fe4ed5e22599340f7e15c
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40884
Tested-by: kokoro
Reviewed-by: Boris Shingarov
Reviewed-by: Gabe Black
Maintainer: Bobby R. Bruce
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/unimp.isa
M src/arch/power/isa/formats/unknown.isa
4 files changed, 11 insertions(+), 7 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/bitfields.isa
b/src/arch/power/isa/bitfields.isa
index 6cc67dd..3ea6d8c 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -34,10 +34,14 @@
// are reversed sometimes. Not sure of a fix to this though...
// Opcode fields
-def bitfield OPCODE<31:26>;
-def bitfield X_XO <10:0>;
-def bitfield XO_XO <10:1>;
+def bitfield PO<31:26>;
def bitfield A_XO <5:1>;
+def bitfield DS_XO <1:0>;
+def bitfield X_XO <10:1>;
+def bitfield XFL_XO<10:1>;
+def bitfield XFX_XO<10:1>;
+def bitfield XL_XO <10:1>;
+def bitfield XO_XO <9:1>;
// Register fields
def bitfield RA<20:16>;
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index a42861b..1a8b375 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -34,7 +34,7 @@
// Power ISA v3.0B has been used for instruction formats, opcode numbers,
// opcode field names, register names, etc.
//
-decode OPCODE default Unknown::unknown() {
+decode PO default Unknown::unknown() {
format IntImmArithOp {
7: mulli({{
diff --git a/src/arch/power/isa/formats/unimp.isa
b/src/arch/power/isa/formats/unimp.isa
index fef28ce..a3f4692 100644
--- a/src/arch/power/isa/formats/unimp.isa
+++ b/src/arch/power/isa/formats/unimp.isa
@@ -112,7 +112,7 @@
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
- "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst,
OPCODE,
+ "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst,
PO,
inst2string(machInst));
return std::make_shared();
}
diff --git a/src/arch/power/isa/formats/unknown.isa
b/src/arch/power/isa/formats/unknown.isa
index d0f81f1..d83f79c 100644
--- a/src/arch/power/isa/formats/unknown.isa
+++ b/src/arch/power/isa/formats/unknown.isa
@@ -63,7 +63,7 @@
Addr pc, const Loader::SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
-"unknown", machInst, OPCODE,
inst2string(machInst));
+"unknown", machInst, PO, inst2string(machInst));
}
}};
@@ -73,7 +73,7 @@
{
panic("attempt to execute unknown instruction at %#x"
"(inst 0x%08x, opcode 0x%x, binary: %s)",
- xc->pcState().pc(), machInst, OPCODE, inst2string(machInst));
+ xc->pcState().pc(), machInst, PO, inst2string(machInst));
return std::make_shared();
}
}};
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40884
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I82598efe74c02960f38fe4ed5e22599340f7e15c
Gerrit-Change-Number: 40884
Gerrit-PatchSet: 5
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-CC: lkcl
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor instruction decoding
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40883 )
Change subject: arch-power: Refactor instruction decoding
..
arch-power: Refactor instruction decoding
This reorders the decoding logic based on the values of
the opcode fields. The first level ordering is based on
the primary opcode (PO) and the second level ordering is
based on the extended opcode (XO).
Change-Id: Ia2d457967bfebb7b20163b56db1cbbe03ac17ceb
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40883
Tested-by: kokoro
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
---
M src/arch/power/isa/decoder.isa
1 file changed, 460 insertions(+), 446 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 71f8b3e..a42861b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -31,22 +31,154 @@
// The actual Power ISA decoder
// --
//
-// I've used the Power ISA Book I v2.06 for instruction formats,
-// opcode numbers, register names, etc.
+// Power ISA v3.0B has been used for instruction formats, opcode numbers,
+// opcode field names, register names, etc.
//
decode OPCODE default Unknown::unknown() {
+format IntImmArithOp {
+7: mulli({{
+int32_t src = Ra_sw;
+int64_t prod = src * imm;
+Rt = (uint32_t)prod;
+}});
+
+8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }},
+ [computeCA]);
+}
+
format IntImmOp {
10: cmpli({{
Xer xer = XER;
uint32_t cr = makeCRFieldUnsigned(Ra_uw, uimm, xer.so);
CR = insertCRField(CR, BF, cr);
-}});
+}});
+
11: cmpi({{
Xer xer = XER;
uint32_t cr = makeCRFieldSigned(Ra_sw, imm, xer.so);
CR = insertCRField(CR, BF, cr);
+}});
+}
+
+format IntImmArithOp {
+12: addic({{ uint32_t src = Ra; Rt = src + imm; }},
+ [computeCA]);
+
+13: addic_({{ uint32_t src = Ra; Rt = src + imm; }},
+ [computeCA, computeCR0]);
+}
+
+format IntImmArithCheckRaOp {
+14: addi({{ Rt = Ra + imm; }},
+ {{ Rt = imm }});
+
+15: addis({{ Rt = Ra + (imm << 16); }},
+ {{ Rt = imm << 16; }});
+}
+
+16: decode AA {
+
+// Conditionally branch relative to PC based on CR and CTR.
+0: BranchPCRelCondCtr::bc({{ NIA = (uint32_t)(CIA + disp); }});
+
+// Conditionally branch to fixed address based on CR and CTR.
+1: BranchNonPCRelCondCtr::bca({{ NIA = targetAddr; }});
+}
+
+17: IntOp::sc({{ return std::make_shared(); }});
+
+18: decode AA {
+
+// Unconditionally branch relative to PC.
+0: BranchPCRel::b({{ NIA = (uint32_t)(CIA + disp); }});
+
+// Unconditionally branch to fixed address.
+1: BranchNonPCRel::ba({{ NIA = targetAddr; }});
+}
+
+19: decode XO_XO {
+
+0: CondMoveOp::mcrf({{
+uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
+CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
+}});
+
+// Conditionally branch to address in LR based on CR and CTR.
+16: BranchLrCondCtr::bclr({{ NIA = LR & 0xfffc; }});
+
+format CondLogicOp {
+33: crnor({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, !(crBa | crBb));
}});
+
+129: crandc({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, crBa & !crBb);
+}});
+}
+
+150: MiscOp::isync({{ }}, [ IsSerializeAfter ]);
+
+format CondLogicOp {
+193: crxor({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, crBa ^ crBb);
+}});
+
+255: crnand({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, !(crBa & crBb));
+}});
+
+257: crand({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, crBa & crBb);
+}});
+
+289: creqv({{
+uint32_t crBa = bits(CR, 31 - ba);
+uint32_t crBb = bits(CR, 31 - bb);
+CR = insertBits(CR, 31 - bt, crBa == crBb);
+}});
+
+
[gem5-dev] Change in gem5/gem5[develop]: sim: Trap into GDB instead of panicking on SEGV
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44685 )
Change subject: sim: Trap into GDB instead of panicking on SEGV
..
sim: Trap into GDB instead of panicking on SEGV
When a segfault happens in the guest, report a SEGV trap to GDB (if
there is one attached) instead of bailing out immediately.
The obvious use-case for this, is the ability to debug guest crashes
in GDB in the standard manner.
The less-trivial use-case is for development of software in an
incomplete software stack (cf. Aarno-Engblom's "Virtual Platforms"
pp.105 et seq.) One particular example is Ingalls-Miranda simulation of
JIT compilers, where the VM's address space may be split between the
simulated and the real machine: in this case, GDB traps facilitate the
transparent illusion of an unbroken address space.
Change-Id: I9072ed5f6474e05e9a99dc42ae5754be28121355
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44685
Reviewed-by: Gabe Black
Reviewed-by: Andreas Sandberg
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/null/remote_gdb.hh
M src/sim/faults.cc
M src/sim/system.cc
M src/sim/system.hh
4 files changed, 21 insertions(+), 4 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved
Gabe Black: Looks good to me, but someone else must approve; Looks good
to me, approved
kokoro: Regressions pass
diff --git a/src/arch/null/remote_gdb.hh b/src/arch/null/remote_gdb.hh
index 4df9cc8..c47ca9b 100644
--- a/src/arch/null/remote_gdb.hh
+++ b/src/arch/null/remote_gdb.hh
@@ -47,6 +47,7 @@
bool breakpoint() { return false; }
void replaceThreadContext(ThreadContext *tc) {}
+bool trap(int type) { return true; }
virtual ~BaseRemoteGDB() {}
};
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 501b5d1..e4f4ae1 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -40,6 +40,8 @@
#include "sim/faults.hh"
+#include
+
#include "arch/decoder.hh"
#include "arch/locked_mem.hh"
#include "base/logging.hh"
@@ -94,15 +96,16 @@
Process *p = tc->getProcessPtr();
handled = p->fixupFault(vaddr);
}
-panic_if(!handled, "Page table fault when accessing virtual
address %#x",
- vaddr);
-
+panic_if(!handled &&
+ !tc->getSystemPtr()->trapToGdb(SIGSEGV, tc->contextId()),
+ "Page table fault when accessing virtual address %#x\n",
vaddr);
}
void
GenericAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr )
{
-panic("Alignment fault when accessing virtual address %#x\n", vaddr);
+panic_if(!tc->getSystemPtr()->trapToGdb(SIGSEGV, tc->contextId()),
+ "Alignment fault when accessing virtual address %#x\n",
vaddr);
}
void GenericHtmFailureFault::invoke(ThreadContext *tc,
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 9fd312c..8b23f90 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -495,6 +495,16 @@
lastWorkItemStarted.erase(p);
}
+bool
+System::trapToGdb(int signal, ContextID ctx_id) const
+{
+auto *gdb = threads.thread(ctx_id).gdb;
+if (!gdb)
+return false;
+gdb->trap(signal);
+return true;
+}
+
void
System::printSystems()
{
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 6613217..acdb316 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -561,6 +561,9 @@
void workItemEnd(uint32_t tid, uint32_t workid);
+/* Returns whether we successfully trapped into GDB. */
+bool trapToGdb(int signal, ContextID ctx_id) const;
+
protected:
/**
* Range for memory-mapped m5 pseudo ops. The range will be
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44685
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9072ed5f6474e05e9a99dc42ae5754be28121355
Gerrit-Change-Number: 44685
Gerrit-PatchSet: 4
Gerrit-Owner: Boris Shingarov
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Trap into GDB instead of panicking on SEGV
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44685 )
Change subject: sim: Trap into GDB instead of panicking on SEGV
..
sim: Trap into GDB instead of panicking on SEGV
When a segfault happens in the guest, report a SEGV trap to GDB (if
there is one attached) instead of bailing out immediately.
The obvious use-case for this, is the ability to debug guest crashes
in GDB in the standard manner.
The less-trivial use-case is for development of software in an
incomplete software stack (cf. Aarno-Engblom's "Virtual Platforms"
pp.105 et seq.) One particular example is Ingalls-Miranda simulation of
JIT compilers, where the VM's address space may be split between the
simulated and the real machine: in this case, GDB traps facilitate the
transparent illusion of an unbroken address space.
Change-Id: I9072ed5f6474e05e9a99dc42ae5754be28121355
---
M src/sim/faults.cc
M src/sim/system.cc
M src/sim/system.hh
3 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 501b5d1..13de0fc 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -40,6 +40,8 @@
#include "sim/faults.hh"
+#include
+
#include "arch/decoder.hh"
#include "arch/locked_mem.hh"
#include "base/logging.hh"
@@ -94,15 +96,16 @@
Process *p = tc->getProcessPtr();
handled = p->fixupFault(vaddr);
}
-panic_if(!handled, "Page table fault when accessing virtual
address %#x",
- vaddr);
-
+if (handled) return;
+panic_if(tc->getSystemPtr()->trap_to_gdb(SIGSEGV),
+ "Page table fault when accessing virtual address %#x\n",
vaddr);
}
void
GenericAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr )
{
-panic("Alignment fault when accessing virtual address %#x\n", vaddr);
+panic_if(tc->getSystemPtr()->trap_to_gdb(SIGSEGV),
+ "Alignment fault when accessing virtual address %#x\n",
vaddr);
}
void GenericHtmFailureFault::invoke(ThreadContext *tc,
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 9fd312c..e8f881a 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -495,6 +495,18 @@
lastWorkItemStarted.erase(p);
}
+bool
+System::trap_to_gdb(int signal) const
+{
+if (!threads.size())
+return true; /* true if we failed, so caller needs to panic */
+auto *gdb = threads.thread(0).gdb;
+if (!gdb)
+return true;
+gdb->trap(signal);
+return false;
+}
+
void
System::printSystems()
{
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 6613217..fe02349 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -561,6 +561,8 @@
void workItemEnd(uint32_t tid, uint32_t workid);
+bool trap_to_gdb(int signal) const;
+
protected:
/**
* Range for memory-mapped m5 pseudo ops. The range will be
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44685
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9072ed5f6474e05e9a99dc42ae5754be28121355
Gerrit-Change-Number: 44685
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Use 64-bit registers and operands
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40881 )
Change subject: arch-power: Use 64-bit registers and operands
..
arch-power: Use 64-bit registers and operands
This increases the width of the general-purpose registers
and some of the special purpose registers to 64 bits in
accordance with recent versions of the Power ISA. This
allows the registers to be used for both 32-bit and 64-bit
execution modes.
It should be noted that in 32-bit mode, the use of upper
word is dependent on the instruction being executed and in
some cases, this may be undefined.
Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40881
Tested-by: kokoro
Reviewed-by: Gabe Black
Reviewed-by: Boris Shingarov
Maintainer: Bobby R. Bruce
---
M src/arch/power/isa/operands.isa
1 file changed, 10 insertions(+), 10 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index e77fde2..07415ba 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -41,10 +41,10 @@
def operands {{
# General Purpose Integer Reg Operands
-'Ra': ('IntReg', 'uw', 'RA', 'IsInteger', 1),
-'Rb': ('IntReg', 'uw', 'RB', 'IsInteger', 2),
-'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
-'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 4),
+'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 1),
+'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 2),
+'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 3),
+'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
# General Purpose Floating Point Reg Operands
'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
@@ -54,16 +54,16 @@
'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
# Memory Operand
-'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 8),
+'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 8),
# Program counter and next
-'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
-'NIA': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
+'CIA': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 9),
+'NIA': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 9),
# Control registers
'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
-'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
-'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9),
+'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
+'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
# Setting as IntReg so things are stored as an integer, not double
@@ -72,5 +72,5 @@
# Registers for linked loads and stores
'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
-'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9),
+'RsvAddr': ('IntReg', 'ud', 'INTREG_RSV_ADDR', 'IsInteger', 9),
}};
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40881
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Gerrit-Change-Number: 40881
Gerrit-PatchSet: 5
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-CC: lkcl
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor CR field generation
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42943 )
Change subject: arch-power: Refactor CR field generation
..
arch-power: Refactor CR field generation
This splits the existing makeCRField utility into signed
and unsigned variants to help callers avoid confusion.
The CR bit union is also used to clean up the underlying
bit setting logic.
Change-Id: I2aa6ec0666d2bc5096eb6c775cc47f2a5a0621ee
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42943
Tested-by: kokoro
Reviewed-by: Gabe Black
Maintainer: Bobby R. Bruce
---
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
3 files changed, 21 insertions(+), 19 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 1c9b1cc..1771fea 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -65,28 +65,30 @@
/* Compute the CR (condition register) field using signed comparison */
inline uint32_t
-makeCRField(int32_t a, int32_t b, uint32_t xerSO) const
+makeCRFieldSigned(int64_t a, int64_t b, bool so) const
{
-uint32_t c = xerSO;
+Cr cr = 0;
-/* We've pre-shifted the immediate values here */
-if (a < b) { c += 0x8; }
-else if (a > b) { c += 0x4; }
-else{ c += 0x2; }
-return c;
+if (a < b) { cr.cr0.lt = 1; }
+else if (a > b) { cr.cr0.gt = 1; }
+else{ cr.cr0.eq = 1; }
+if (so) { cr.cr0.so = 1; }
+
+return cr.cr0;
}
/* Compute the CR (condition register) field using unsigned comparison
*/
inline uint32_t
-makeCRField(uint32_t a, uint32_t b, uint32_t xerSO) const
+makeCRFieldUnsigned(uint64_t a, uint64_t b, bool so) const
{
-uint32_t c = xerSO;
+Cr cr = 0;
-/* We've pre-shifted the immediate values here */
-if (a < b) { c += 0x8; }
-else if (a > b) { c += 0x4; }
-else{ c += 0x2; }
-return c;
+if (a < b) { cr.cr0.lt = 1; }
+else if (a > b) { cr.cr0.gt = 1; }
+else{ cr.cr0.eq = 1; }
+if (so) { cr.cr0.so = 1; }
+
+return cr.cr0;
}
std::string generateDisassembly(
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index f32861b..7f22d8c 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -39,12 +39,12 @@
format IntImmOp {
10: cmpli({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
+uint32_t cr = makeCRFieldUnsigned(Ra_uw, uimm, xer.so);
CR = insertCRField(CR, BF, cr);
}});
11: cmpi({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
+uint32_t cr = makeCRFieldSigned(Ra_sw, imm, xer.so);
CR = insertCRField(CR, BF, cr);
}});
}
@@ -250,12 +250,12 @@
format IntOp {
0: cmp({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
+uint32_t cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so);
CR = insertCRField(CR, BF, cr);
}});
32: cmpl({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra, Rb, xer.so);
+uint32_t cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so);
CR = insertCRField(CR, BF, cr);
}});
144: mtcrf({{
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 50badce..0ed0bf02 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -77,7 +77,7 @@
computeCR0Code = '''
Cr cr = CR;
-cr.cr0 = makeCRField((int32_t)%(result)s, (int32_t)0, xer.so);
+cr.cr0 = makeCRFieldSigned(%(result)s, 0, xer.so);
CR = cr;
'''
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42943
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2aa6ec0666d2bc5096eb6c775cc47f2a5a0621ee
Gerrit-Change-Number: 42943
Gerrit-PatchSet: 5
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Restore consistency with other platforms
Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40635 ) Change subject: arch-power: Restore consistency with other platforms .. arch-power: Restore consistency with other platforms The 32-bit POWER reference test binary was removed in c1ebdf66f (as a nasty surprise for POWER users). The remaining platforms split between two approaches: MIPS rebuilds "hello" from source. This fails for two reasons: 1) The trivial reason is that on POWER make abends due to no makefile. 2) The more fundamental reason is that gem5 is not completely bug-free (especially the Decoder on POWER in this case), therefore regression testing is only possible if we have not just some hello program, but a very particular bit sequence to serve as an immutable reference. ARM and X86 follow the reference-bit-sequence approach. POWER will be consistent with same. Including the sha1 for hello32, 77b27b67393311546e768b5ff35202490bad71aa, as a simple immutability assurance. I have also renamed hello to hello32 in anticipation to merge Sandipan's e52dbcb. Change-Id: I77ef31349c9e50b987c6f58bb23324844527366d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40635 Reviewed-by: Jason Lowe-Power Reviewed-by: Sandipan Das Reviewed-by: Pratik Sampat Maintainer: Jason Lowe-Power Tested-by: kokoro --- A tests/test-progs/hello/bin/power/hello32 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Sandipan Das: Looks good to me, approved Pratik Sampat: Looks good to me, approved kokoro: Regressions pass diff --git a/tests/test-progs/hello/bin/power/hello32 b/tests/test-progs/hello/bin/power/hello32 new file mode 100755 index 000..6619ae3 --- /dev/null +++ b/tests/test-progs/hello/bin/power/hello32 Binary files differ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40635 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I77ef31349c9e50b987c6f58bb23324844527366d Gerrit-Change-Number: 40635 Gerrit-PatchSet: 2 Gerrit-Owner: Boris Shingarov Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Boris Shingarov Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Pratik Sampat Gerrit-Reviewer: Sandipan Das Gerrit-Reviewer: kokoro Gerrit-CC: Gabe Black Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: util,python: Ignore ELF binary blobs in pre-commit
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40636 )
Change subject: util,python: Ignore ELF binary blobs in pre-commit
..
util,python: Ignore ELF binary blobs in pre-commit
Change-Id: I60554b2ae7536687a6c0a883a7678f793c3c77d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40636
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M util/style/style.py
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/style/style.py b/util/style/style.py
index 1a5e94b..d8afd09 100644
--- a/util/style/style.py
+++ b/util/style/style.py
@@ -106,6 +106,7 @@
_re_ignore("^ext/"),
# Ignore test data, as they are not code
_re_ignore("^tests/(?:quick|long)/"),
+_re_ignore("^tests/test-progs/hello/bin/"),
# Only include Scons files and those with extensions that suggest
source
# code
_re_only("^((.*\/)?(SConscript|SConstruct)|"
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40636
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I60554b2ae7536687a6c0a883a7678f793c3c77d4
Gerrit-Change-Number: 40636
Gerrit-PatchSet: 2
Gerrit-Owner: Boris Shingarov
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: util,python: Ignore ELF binary blobs in pre-commit
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40636 )
Change subject: util,python: Ignore ELF binary blobs in pre-commit
..
util,python: Ignore ELF binary blobs in pre-commit
Change-Id: I60554b2ae7536687a6c0a883a7678f793c3c77d4
---
M util/style/style.py
1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/util/style/style.py b/util/style/style.py
index 1a5e94b..d8afd09 100644
--- a/util/style/style.py
+++ b/util/style/style.py
@@ -106,6 +106,7 @@
_re_ignore("^ext/"),
# Ignore test data, as they are not code
_re_ignore("^tests/(?:quick|long)/"),
+_re_ignore("^tests/test-progs/hello/bin/"),
# Only include Scons files and those with extensions that suggest
source
# code
_re_only("^((.*\/)?(SConscript|SConstruct)|"
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40636
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I60554b2ae7536687a6c0a883a7678f793c3c77d4
Gerrit-Change-Number: 40636
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Restore consistency with other platforms
Boris Shingarov has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/40635 ) Change subject: arch-power: Restore consistency with other platforms .. arch-power: Restore consistency with other platforms The 32-bit POWER reference test binary was removed in c1ebdf66f (as a nasty surprise for POWER users). The remaining platforms split between two approaches: MIPS rebuilds "hello" from source. This fails for two reasons: 1) The trivial reason is that on POWER make abends due to no makefile. 2) The more fundamental reason is that gem5 is not completely bug-free (especially the Decoder on POWER in this case), therefore regression testing is only possible if we have not just some hello program, but a very particular bit sequence to serve as an immutable reference. ARM and X86 follow the reference-bit-sequence approach. POWER will be consistent with same. Including the sha1 for hello32, 77b27b67393311546e768b5ff35202490bad71aa, as a simple immutability assurance. I have also renamed hello to hello32 in anticipation to merge Sandipan's e52dbcb. Change-Id: I77ef31349c9e50b987c6f58bb23324844527366d --- A tests/test-progs/hello/bin/power/hello32 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/tests/test-progs/hello/bin/power/hello32 b/tests/test-progs/hello/bin/power/hello32 new file mode 100755 index 000..6619ae3 --- /dev/null +++ b/tests/test-progs/hello/bin/power/hello32 Binary files differ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40635 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I77ef31349c9e50b987c6f58bb23324844527366d Gerrit-Change-Number: 40635 Gerrit-PatchSet: 1 Gerrit-Owner: Boris Shingarov Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Implement mcrxr
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37295 )
Change subject: arch-power: Implement mcrxr
..
arch-power: Implement mcrxr
Implement the mcrxr instruction (Move to Condition Register from XER
X-form) as defined on p.132 of the green-cloth book:
The contents of XER<0:3> are copied into the Condition Register field
designated by BF. XER<0:3> are set to zero.
Change-Id: I82ae3d98e1eaf9182e90c0c86afe0f13d4a052e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37295
Reviewed-by: Gabe Black
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 475ddcc..f32861b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -278,6 +278,10 @@
0x100: mtlr({{ LR = Rs; }});
0x120: mtctr({{ CTR = Rs; }});
}
+512: mcrxr({{
+CR = insertCRField(CR, BF, XER<31:28>);
+XER = XER<27:0>;
+}});
}
// All loads with an index register. The non-update versions
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37295
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I82ae3d98e1eaf9182e90c0c86afe0f13d4a052e4
Gerrit-Change-Number: 37295
Gerrit-PatchSet: 4
Gerrit-Owner: Boris Shingarov
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Implement GDB XML target description for PowerPC
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31114 )
Change subject: arch-power: Implement GDB XML target description for PowerPC
..
arch-power: Implement GDB XML target description for PowerPC
Change-Id: I2610626a7e1464316ebaa770291d4bdcb59e8856
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31114
Reviewed-by: Ciro Santilli
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
A ext/gdb-xml/power.xml
M src/arch/power/SConscript
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
4 files changed, 118 insertions(+), 0 deletions(-)
Approvals:
Gabe Black: Looks good to me, but someone else must approve
Ciro Santilli: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/gdb-xml/power.xml b/ext/gdb-xml/power.xml
new file mode 100644
index 000..da5a07c
--- /dev/null
+++ b/ext/gdb-xml/power.xml
@@ -0,0 +1,92 @@
+
+
+
+
+
+ powerpc
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index a91b5d9..1187acf 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -1,6 +1,7 @@
# -*- mode:python -*-
# Copyright (c) 2009 The University of Edinburgh
+# Copyright (c) 2020 LabWare
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -56,3 +57,5 @@
DebugFlag('Power')
ISADesc('isa/main.isa')
+
+GdbXml('power.xml', 'gdb_xml_power')
diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index ccee0b1..661c431 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -136,6 +136,7 @@
#include
+#include "blobs/gdb_xml_power.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
@@ -213,3 +214,19 @@
return
}
+bool
+RemoteGDB::getXferFeaturesRead(const std::string , std::string
)
+{
+#define GDB_XML(x, s) \
+{ x, std::string(reinterpret_cast(Blobs::s), \
+Blobs::s ## _len) }
+static const std::map annexMap {
+GDB_XML("target.xml", gdb_xml_power),
+};
+#undef GDB_XML
+auto it = annexMap.find(annex);
+if (it == annexMap.end())
+return false;
+output = it->second;
+return true;
+}
diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh
index 1b673bb..3bb726e 100644
--- a/src/arch/power/remote_gdb.hh
+++ b/src/arch/power/remote_gdb.hh
@@ -76,6 +76,12 @@
public:
RemoteGDB(System *_system, ThreadContext *tc, int _port);
BaseGdbRegCache *gdbRegs();
+std::vector
+availableFeatures() const
+{
+return {"qXfer:features:read+"};
+};
+bool getXferFeaturesRead(const std::string , std::string
);
};
} // namespace PowerISA
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31114
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2610626a7e1464316ebaa770291d4bdcb59e8856
Gerrit-Change-Number: 31114
Gerrit-PatchSet: 4
Gerrit-Owner: Boris Shingarov
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Implement GDB XML target description for MIPS
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31574 )
Change subject: arch-mips: Implement GDB XML target description for MIPS
..
arch-mips: Implement GDB XML target description for MIPS
Change-Id: Icff3b2c3e60d5989978de854247232afbb3b0dae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31574
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Gabe Black
Reviewed-by: Jason Lowe-Power
---
A ext/gdb-xml/mips.xml
M src/arch/mips/SConscript
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
4 files changed, 123 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/ext/gdb-xml/mips.xml b/ext/gdb-xml/mips.xml
new file mode 100644
index 000..23133d7
--- /dev/null
+++ b/ext/gdb-xml/mips.xml
@@ -0,0 +1,94 @@
+
+
+
+
+
+ mips
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index cac589f..d8771de 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -1,6 +1,7 @@
# -*- mode:python -*-
# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# Copyright (c) 2020 LabWare
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -50,3 +51,5 @@
DebugFlag('MipsPRA')
ISADesc('isa/main.isa')
+
+GdbXml('mips.xml', 'gdb_xml_mips')
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 48138ee..bd9a40f 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 LabWare
+ * Copyright 2015-2020 LabWare
* Copyright 2014 Google, Inc.
* Copyright (c) 2010 ARM Limited
* All rights reserved
@@ -136,6 +136,7 @@
#include
#include "arch/mips/decoder.hh"
+#include "blobs/gdb_xml_mips.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
@@ -201,3 +202,20 @@
{
return
}
+
+bool
+RemoteGDB::getXferFeaturesRead(const std::string , std::string
)
+{
+#define GDB_XML(x, s) \
+{ x, std::string(reinterpret_cast(Blobs::s), \
+Blobs::s ## _len) }
+static const std::map annexMap {
+GDB_XML("target.xml", gdb_xml_mips),
+};
+#undef GDB_XML
+auto it = annexMap.find(annex);
+if (it == annexMap.end())
+return false;
+output = it->second;
+return true;
+}
diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
index 407a557..2119d8e 100644
--- a/src/arch/mips/remote_gdb.hh
+++ b/src/arch/mips/remote_gdb.hh
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 LabWare
+ * Copyright 2015-2020 LabWare
* Copyright 2014 Google, Inc.
* Copyright (c) 2007 The Regents of The University of Michigan
* All rights reserved.
@@ -79,6 +79,12 @@
public:
RemoteGDB(System *_system, ThreadContext *tc, int _port);
BaseGdbRegCache *gdbRegs();
+std::vector
+availableFeatures() const
+{
+return {"qXfer:features:read+"};
+};
+bool getXferFeaturesRead(const std::string , std::string
);
};
} // namespace MipsISA
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31574
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icff3b2c3e60d5989978de854247232afbb3b0dae
Gerrit-Change-Number: 31574
Gerrit-PatchSet: 2
Gerrit-Owner: Boris Shingarov
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Implement GDB XML target description for MIPS
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31574 )
Change subject: arch-mips: Implement GDB XML target description for MIPS
..
arch-mips: Implement GDB XML target description for MIPS
Change-Id: Icff3b2c3e60d5989978de854247232afbb3b0dae
---
A ext/gdb-xml/mips.xml
M src/arch/mips/SConscript
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
4 files changed, 123 insertions(+), 2 deletions(-)
diff --git a/ext/gdb-xml/mips.xml b/ext/gdb-xml/mips.xml
new file mode 100644
index 000..23133d7
--- /dev/null
+++ b/ext/gdb-xml/mips.xml
@@ -0,0 +1,94 @@
+
+
+
+
+
+ mips
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index cac589f..d8771de 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -1,6 +1,7 @@
# -*- mode:python -*-
# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# Copyright (c) 2020 LabWare
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -50,3 +51,5 @@
DebugFlag('MipsPRA')
ISADesc('isa/main.isa')
+
+GdbXml('mips.xml', 'gdb_xml_mips')
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 48138ee..bd9a40f 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 LabWare
+ * Copyright 2015-2020 LabWare
* Copyright 2014 Google, Inc.
* Copyright (c) 2010 ARM Limited
* All rights reserved
@@ -136,6 +136,7 @@
#include
#include "arch/mips/decoder.hh"
+#include "blobs/gdb_xml_mips.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
@@ -201,3 +202,20 @@
{
return
}
+
+bool
+RemoteGDB::getXferFeaturesRead(const std::string , std::string
)
+{
+#define GDB_XML(x, s) \
+{ x, std::string(reinterpret_cast(Blobs::s), \
+Blobs::s ## _len) }
+static const std::map annexMap {
+GDB_XML("target.xml", gdb_xml_mips),
+};
+#undef GDB_XML
+auto it = annexMap.find(annex);
+if (it == annexMap.end())
+return false;
+output = it->second;
+return true;
+}
diff --git a/src/arch/mips/remote_gdb.hh b/src/arch/mips/remote_gdb.hh
index 407a557..2119d8e 100644
--- a/src/arch/mips/remote_gdb.hh
+++ b/src/arch/mips/remote_gdb.hh
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 LabWare
+ * Copyright 2015-2020 LabWare
* Copyright 2014 Google, Inc.
* Copyright (c) 2007 The Regents of The University of Michigan
* All rights reserved.
@@ -79,6 +79,12 @@
public:
RemoteGDB(System *_system, ThreadContext *tc, int _port);
BaseGdbRegCache *gdbRegs();
+std::vector
+availableFeatures() const
+{
+return {"qXfer:features:read+"};
+};
+bool getXferFeaturesRead(const std::string , std::string
);
};
} // namespace MipsISA
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31574
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icff3b2c3e60d5989978de854247232afbb3b0dae
Gerrit-Change-Number: 31574
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Implement GDB XML target description for PowerPC
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31114 )
Change subject: arch-power: Implement GDB XML target description for PowerPC
..
arch-power: Implement GDB XML target description for PowerPC
Change-Id: I2610626a7e1464316ebaa770291d4bdcb59e8856
---
A ext/gdb-xml/power.xml
M src/arch/power/SConscript
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
4 files changed, 118 insertions(+), 0 deletions(-)
diff --git a/ext/gdb-xml/power.xml b/ext/gdb-xml/power.xml
new file mode 100644
index 000..da5a07c
--- /dev/null
+++ b/ext/gdb-xml/power.xml
@@ -0,0 +1,92 @@
+
+
+
+
+
+ powerpc
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 93be38c..607236a 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -1,6 +1,7 @@
# -*- mode:python -*-
# Copyright (c) 2009 The University of Edinburgh
+# Copyright (c) 2020 LabWare
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -57,3 +58,5 @@
DebugFlag('Power')
ISADesc('isa/main.isa')
+
+GdbXml('power.xml', 'gdb_xml_power')
diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index ccee0b1..661c431 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -136,6 +136,7 @@
#include
+#include "blobs/gdb_xml_power.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
@@ -213,3 +214,19 @@
return
}
+bool
+RemoteGDB::getXferFeaturesRead(const std::string , std::string
)
+{
+#define GDB_XML(x, s) \
+{ x, std::string(reinterpret_cast(Blobs::s), \
+Blobs::s ## _len) }
+static const std::map annexMap {
+GDB_XML("target.xml", gdb_xml_power),
+};
+#undef GDB_XML
+auto it = annexMap.find(annex);
+if (it == annexMap.end())
+return false;
+output = it->second;
+return true;
+}
diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh
index 1b673bb..3bb726e 100644
--- a/src/arch/power/remote_gdb.hh
+++ b/src/arch/power/remote_gdb.hh
@@ -76,6 +76,12 @@
public:
RemoteGDB(System *_system, ThreadContext *tc, int _port);
BaseGdbRegCache *gdbRegs();
+std::vector
+availableFeatures() const
+{
+return {"qXfer:features:read+"};
+};
+bool getXferFeaturesRead(const std::string , std::string
);
};
} // namespace PowerISA
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31114
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2610626a7e1464316ebaa770291d4bdcb59e8856
Gerrit-Change-Number: 31114
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem: Optionally share the backing store
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30994 )
Change subject: mem: Optionally share the backing store
..
mem: Optionally share the backing store
This patch adds the ability for a host-OS process external to gem5
to access the backing store via POSIX shared memory.
The new param shared_backstore of the System object is the filename
of the shared memory (i.e., the first argument to shm_open()).
Change-Id: I98c948a32a15049a4515e6c02a14595fb5fe379f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30994
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/physical.cc
M src/mem/physical.hh
M src/sim/System.py
M src/sim/system.cc
4 files changed, 32 insertions(+), 6 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 4bd812c..a03f200 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -71,8 +71,10 @@
PhysicalMemory::PhysicalMemory(const string& _name,
const vector& _memories,
- bool mmap_using_noreserve) :
-_name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve)
+ bool mmap_using_noreserve,
+ const std::string& shared_backstore) :
+_name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve),
+sharedBackstore(shared_backstore)
{
if (mmap_using_noreserve)
warn("Not reserving swap space. May cause SIGSEGV on actual
usage\n");
@@ -192,7 +194,23 @@
// perform the actual mmap
DPRINTF(AddrRanges, "Creating backing store for range %s with
size %d\n",
range.to_string(), range.size());
-int map_flags = MAP_ANON | MAP_PRIVATE;
+
+int shm_fd;
+int map_flags;
+
+if (sharedBackstore.empty()) {
+shm_fd = -1;
+map_flags = MAP_ANON | MAP_PRIVATE;
+} else {
+DPRINTF(AddrRanges, "Sharing backing store as %s\n",
+sharedBackstore.c_str());
+shm_fd = shm_open(sharedBackstore.c_str(), O_CREAT | O_RDWR, 0666);
+if (shm_fd == -1)
+ panic("Shared memory failed");
+if (ftruncate(shm_fd, range.size()))
+ panic("Setting size of shared memory failed");
+map_flags = MAP_SHARED;
+}
// to be able to simulate very large memories, the user can opt to
// pass noreserve to mmap
@@ -202,7 +220,7 @@
uint8_t* pmem = (uint8_t*) mmap(NULL, range.size(),
PROT_READ | PROT_WRITE,
-map_flags, -1, 0);
+map_flags, shm_fd, 0);
if (pmem == (uint8_t*) MAP_FAILED) {
perror("mmap");
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 88a5cda..9d4ff9a 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -127,6 +127,8 @@
// Let the user choose if we reserve swap space when calling mmap
const bool mmapUsingNoReserve;
+const std::string sharedBackstore;
+
// The physical memory used to provide the memory in the simulated
// system
std::vector backingStore;
@@ -158,7 +160,8 @@
*/
PhysicalMemory(const std::string& _name,
const std::vector& _memories,
- bool mmap_using_noreserve);
+ bool mmap_using_noreserve,
+ const std::string& shared_backstore);
/**
* Unmap all the backing store we have used.
diff --git a/src/sim/System.py b/src/sim/System.py
index 61fbe0e..e028f48 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -78,6 +78,10 @@
# I/O bridge or cache
mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main
memory")
+shared_backstore = Param.String("", "backstore's shmem segment
filename, "
+"use to directly address the backstore from another host-OS
process. "
+"Leave this empty to unset the MAP_SHARED flag.")
+
cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
redirect_paths = VectorParam.RedirectPath([], "Path redirections")
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 7841ec0..4e3416e 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -213,7 +213,8 @@
#else
kvmVM(nullptr),
#endif
- physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve),
+ physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve,
+ p->shared_backstore),
memoryMode(p->mem_mode),
_cacheLineSize(p->cache_line_size),
workItemsBegin(0),
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30994
To unsubscribe, or for help writing mail filters, visit
[gem5-dev] Change in gem5/gem5[develop]: mem: Clarify the meaning of shared_backstore param
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31034 )
Change subject: mem: Clarify the meaning of shared_backstore param
..
mem: Clarify the meaning of shared_backstore param
Change-Id: I36bb2b0633aed4e00db2f213a84a172279c10c78
---
M src/sim/System.py
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/sim/System.py b/src/sim/System.py
index 36b7e3f..e028f48 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -78,7 +78,9 @@
# I/O bridge or cache
mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main
memory")
-shared_backstore = Param.String("", "backstore's shmem segment
filename")
+shared_backstore = Param.String("", "backstore's shmem segment
filename, "
+"use to directly address the backstore from another host-OS
process. "
+"Leave this empty to unset the MAP_SHARED flag.")
cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31034
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I36bb2b0633aed4e00db2f213a84a172279c10c78
Gerrit-Change-Number: 31034
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem: Optionally share the backing store
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30994 )
Change subject: mem: Optionally share the backing store
..
mem: Optionally share the backing store
This patch adds the ability for a host-OS process external to gem5
to access the backing store via POSIX shared memory.
The new param shared_backstore of the System object is the filename
of the shared memory (i.e., the first argument to shm_open()).
Change-Id: I98c948a32a15049a4515e6c02a14595fb5fe379f
---
M src/mem/physical.cc
M src/mem/physical.hh
M src/sim/System.py
M src/sim/system.cc
4 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 4bd812c..80632ce 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -71,8 +71,10 @@
PhysicalMemory::PhysicalMemory(const string& _name,
const vector& _memories,
- bool mmap_using_noreserve) :
-_name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve)
+ bool mmap_using_noreserve,
+ const std::string& shared_backstore) :
+_name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve),
+sharedBackstore(shared_backstore)
{
if (mmap_using_noreserve)
warn("Not reserving swap space. May cause SIGSEGV on actual
usage\n");
@@ -192,7 +194,22 @@
// perform the actual mmap
DPRINTF(AddrRanges, "Creating backing store for range %s with
size %d\n",
range.to_string(), range.size());
-int map_flags = MAP_ANON | MAP_PRIVATE;
+
+int shm_fd;
+int map_flags;
+
+if (sharedBackstore.empty()) {
+shm_fd = -1;
+map_flags = MAP_ANON | MAP_PRIVATE;
+} else {
+DPRINTF(AddrRanges, "Sharing backing store as %s\n",
+sharedBackstore.c_str());
+shm_fd = shm_open(sharedBackstore.c_str(), O_CREAT | O_RDWR, 0666);
+if (shm_fd == -1)
+ panic("Shared memory failed");
+ftruncate(shm_fd, range.size());
+map_flags = MAP_SHARED;
+}
// to be able to simulate very large memories, the user can opt to
// pass noreserve to mmap
@@ -202,7 +219,7 @@
uint8_t* pmem = (uint8_t*) mmap(NULL, range.size(),
PROT_READ | PROT_WRITE,
-map_flags, -1, 0);
+map_flags, shm_fd, 0);
if (pmem == (uint8_t*) MAP_FAILED) {
perror("mmap");
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 88a5cda..9d4ff9a 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -127,6 +127,8 @@
// Let the user choose if we reserve swap space when calling mmap
const bool mmapUsingNoReserve;
+const std::string sharedBackstore;
+
// The physical memory used to provide the memory in the simulated
// system
std::vector backingStore;
@@ -158,7 +160,8 @@
*/
PhysicalMemory(const std::string& _name,
const std::vector& _memories,
- bool mmap_using_noreserve);
+ bool mmap_using_noreserve,
+ const std::string& shared_backstore);
/**
* Unmap all the backing store we have used.
diff --git a/src/sim/System.py b/src/sim/System.py
index 61fbe0e..36b7e3f 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -78,6 +78,8 @@
# I/O bridge or cache
mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main
memory")
+shared_backstore = Param.String("", "backstore's shmem segment
filename")
+
cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
redirect_paths = VectorParam.RedirectPath([], "Path redirections")
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 7057a97..5f5ab54 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -213,7 +213,8 @@
#else
kvmVM(nullptr),
#endif
- physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve),
+ physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve,
+ p->shared_backstore),
memoryMode(p->mem_mode),
_cacheLineSize(p->cache_line_size),
workItemsBegin(0),
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30994
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I98c948a32a15049a4515e6c02a14595fb5fe379f
Gerrit-Change-Number: 30994
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base: DPRINTF which XML we are sending to GDB
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30897 )
Change subject: base: DPRINTF which XML we are sending to GDB
..
base: DPRINTF which XML we are sending to GDB
For some reason which I am still puzzled over, this function can return
the wrong XML descriptor (i.e. aarch64 in a 32-bit context); to aid in
tracing what's going on, I have added DPRINTFs to easily see which XML
we are returning. Surprisingly, lifting the ternary to if, seems to
also result in returning the correct value.
Change-Id: I9d5e8df7c4e04759866f2abadfebdae814a94896
---
M src/arch/arm/remote_gdb.cc
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index b2977e5..d026e1d 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -343,7 +343,14 @@
GDB_XML("aarch64-fpu.xml", gdb_xml_aarch64_fpu),
};
#undef GDB_XML
-auto& annexMap = inAArch64(context()) ? annexMap64 : annexMap32;
+std::map annexMap;
+if (inAArch64(context())) {
+DPRINTF(GDBAcc, "GDB XML: aarch64\n");
+annexMap = annexMap64;
+} else {
+DPRINTF(GDBAcc, "GDB XML: arm32\n");
+annexMap = annexMap32;
+}
auto it = annexMap.find(annex);
if (it == annexMap.end())
return false;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30897
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d5e8df7c4e04759866f2abadfebdae814a94896
Gerrit-Change-Number: 30897
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
