date:20101108

[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick

2010-11-08 Thread Cron Daemon

* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing 
passed.
* build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby 
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing 
passed.
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp 
passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 passed.
* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
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* 
build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
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* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 passed.
* 
build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 passed.
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby 
passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 passed.
* 
build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing 
passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic 
passed.
* 
build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby 
passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing passed.
* build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic passed.
* build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed.
* 
build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 passed.
* 
build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 passed.
* build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing passed.
* 
build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 passed.
* build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic 
passed.
* build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby 
passed.
*

[m5-dev] changeset in m5: sim: Use forward declarations for ports.

2010-11-08 Thread Ali Saidi

changeset ee4ac00d0774 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ee4ac00d0774
description:
sim: Use forward declarations for ports.

Virtual ports need TLB data which means anything touching a file in the 
arch
directory rebuilds any file that includes system.hh which in everything.

diffstat:

 src/arch/alpha/freebsd/system.cc |   5 +++--
 src/arch/alpha/linux/system.cc   |   6 +++---
 src/arch/alpha/stacktrace.cc |   1 +
 src/arch/alpha/system.cc |  17 +
 src/arch/alpha/tru64/system.cc   |   3 ++-
 src/arch/arm/linux/system.cc |   4 +++-
 src/arch/arm/stacktrace.cc   |   1 +
 src/arch/arm/system.cc   |   1 -
 src/arch/mips/system.cc  |  10 +-
 src/base/remote_gdb.cc   |   1 +
 src/cpu/simple_thread.cc |   1 +
 src/dev/simple_disk.cc   |   2 +-
 src/dev/sparc/iob.cc |   1 +
 src/sim/system.cc|  15 ---
 src/sim/system.hh|   7 ---
 15 files changed, 43 insertions(+), 32 deletions(-)

diffs (truncated from 358 to 300 lines):

diff -r c10bc8ad3f97 -r ee4ac00d0774 src/arch/alpha/freebsd/system.cc
--- a/src/arch/alpha/freebsd/system.cc  Sat Nov 06 17:48:58 2010 -0700
+++ b/src/arch/alpha/freebsd/system.cc  Mon Nov 08 13:58:22 2010 -0600
@@ -43,6 +43,7 @@
 #include cpu/thread_context.hh
 #include mem/physical.hh
 #include mem/port.hh
+#include mem/vport.hh
 #include sim/byteswap.hh
 
 #define TIMER_FREQUENCY 1193180
@@ -77,8 +78,8 @@
 ppc_vaddr = (Addr)tc-readIntReg(17);
 timer_vaddr = (Addr)tc-readIntReg(18);
 
-virtPort.write(ppc_vaddr, (uint32_t)SimClock::Frequency);
-virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
+virtPort-write(ppc_vaddr, (uint32_t)SimClock::Frequency);
+virtPort-write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
 }
 
 void
diff -r c10bc8ad3f97 -r ee4ac00d0774 src/arch/alpha/linux/system.cc
--- a/src/arch/alpha/linux/system.ccSat Nov 06 17:48:58 2010 -0700
+++ b/src/arch/alpha/linux/system.ccMon Nov 08 13:58:22 2010 -0600
@@ -77,7 +77,7 @@
  * Since we aren't using a bootloader, we have to copy the
  * kernel arguments directly into the kernel's memory.
  */
-virtPort.writeBlob(CommandLine(), (uint8_t*)params()-boot_osflags.c_str(),
+virtPort-writeBlob(CommandLine(), 
(uint8_t*)params()-boot_osflags.c_str(),
 params()-boot_osflags.length()+1);
 
 /**
@@ -86,7 +86,7 @@
  * calculated it by using the PIT, RTC, etc.
  */
 if (kernelSymtab-findAddress(est_cycle_freq, addr))
-virtPort.write(addr, (uint64_t)(SimClock::Frequency /
+virtPort-write(addr, (uint64_t)(SimClock::Frequency /
 p-boot_cpu_frequency));
 
 
@@ -97,7 +97,7 @@
  * 255 ASNs.
  */
 if (kernelSymtab-findAddress(dp264_mv, addr))
-virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
+virtPort-write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
 else
 panic(could not find dp264_mv\n);
 
diff -r c10bc8ad3f97 -r ee4ac00d0774 src/arch/alpha/stacktrace.cc
--- a/src/arch/alpha/stacktrace.cc  Sat Nov 06 17:48:58 2010 -0700
+++ b/src/arch/alpha/stacktrace.cc  Mon Nov 08 13:58:22 2010 -0600
@@ -37,6 +37,7 @@
 #include base/trace.hh
 #include cpu/base.hh
 #include cpu/thread_context.hh
+#include mem/vport.hh
 #include sim/system.hh
 
 using namespace std;
diff -r c10bc8ad3f97 -r ee4ac00d0774 src/arch/alpha/system.cc
--- a/src/arch/alpha/system.cc  Sat Nov 06 17:48:58 2010 -0700
+++ b/src/arch/alpha/system.cc  Mon Nov 08 13:58:22 2010 -0600
@@ -38,6 +38,7 @@
 #include base/loader/symtab.hh
 #include base/trace.hh
 #include mem/physical.hh
+#include mem/vport.hh
 #include params/AlphaSystem.hh
 #include sim/byteswap.hh
 
@@ -65,8 +66,8 @@
 
 
 // Load program sections into memory
-pal-loadSections(functionalPort, loadAddrMask);
-console-loadSections(functionalPort, loadAddrMask);
+pal-loadSections(functionalPort, loadAddrMask);
+console-loadSections(functionalPort, loadAddrMask);
 
 // load symbols
 if (!console-loadGlobalSymbols(consoleSymtab))
@@ -99,7 +100,7 @@
  * others do.)
  */
 if (consoleSymtab-findAddress(env_booted_osflags, addr)) {
-virtPort.writeBlob(addr, (uint8_t*)params()-boot_osflags.c_str(),
+virtPort-writeBlob(addr, (uint8_t*)params()-boot_osflags.c_str(),
 strlen(params()-boot_osflags.c_str()));
 }
 
@@ -110,9 +111,9 @@
 if (consoleSymtab-findAddress(m5_rpb, addr)) {
 uint64_t data;
 data = htog(params()-system_type);
-virtPort.write(addr+0x50, data);
+virtPort-write(addr+0x50, data);
 data = htog(params()-system_rev);
-virtPort.write(addr+0x58, data);
+virtPort-write(addr+0x58, data);
 } else
 panic(could not find hwrpb\n);
 }
@@ -168,8 +169,8 @@
 // lda  gp,Y(gp): opcode 8, Ra = 29, rb =

[m5-dev] changeset in m5: ARM/Alpha/Cpu: Change prefetchs to be more like...

2010-11-08 Thread Ali Saidi

changeset 00ea9430643b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=00ea9430643b
description:
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.

This change modifies the way prefetches work. They are now like normal 
loads
that don't writeback a register. Previously prefetches were supposed to 
call
prefetch() on the exection context, so they executed with execute() 
methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all 
the CPUs
are blank, meaning that they get executed, but don't actually do 
anything.

On Alpha dead cache copy code was removed and prefetches are now normal 
ops.
They count as executed operations, but still don't do anything and 
IsMemRef is
not longer set on them.

On ARM IsDataPrefetch or IsInstructionPreftech is now set on all 
prefetch
instructions. The timing simple CPU doesn't try to do anything special 
for
prefetches now and they execute with the normal memory code path.

diffstat:

 src/arch/alpha/isa/decoder.isa  |   16 +
 src/arch/alpha/isa/mem.isa  |9 +-
 src/arch/arm/isa/insts/ldr.isa  |   27 ---
 src/arch/mips/isa/formats/mem.isa   |7 +-
 src/cpu/base_dyn_inst.hh|5 -
 src/cpu/base_dyn_inst_impl.hh   |   67 ---
 src/cpu/checker/cpu.cc  |   12 ---
 src/cpu/checker/cpu.hh  |   14 
 src/cpu/exec_context.hh |9 --
 src/cpu/inorder/cpu.cc  |   15 
 src/cpu/inorder/cpu.hh  |   10 --
 src/cpu/inorder/inorder_dyn_inst.cc |   32 -
 src/cpu/inorder/inorder_dyn_inst.hh |4 -
 src/cpu/inorder/resource.hh |6 -
 src/cpu/inorder/resources/cache_unit.cc |   37 --
 src/cpu/inorder/resources/cache_unit.hh |4 -
 src/cpu/ozone/cpu.hh|   14 
 src/cpu/ozone/cpu_impl.hh   |   89 -
 src/cpu/simple/base.cc  |  112 
 src/cpu/simple/base.hh  |7 --
 src/cpu/simple/timing.cc|   15 +++-
 src/cpu/static_inst.hh  |2 +
 22 files changed, 41 insertions(+), 472 deletions(-)

diffs (truncated from 807 to 300 lines):

diff -r ba11187e2582 -r 00ea9430643b src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isaMon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/alpha/isa/decoder.isaMon Nov 08 13:58:22 2010 -0600
@@ -47,11 +47,6 @@
 0x23: ldt({{ Fa = Mem.df; }});
 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
-#ifdef USE_COPY
-0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
-  {{ fault = xc-copySrcTranslate(EA); }},
-  inst_flags = [IsMemRef, IsLoad, IsCopy]);
-#endif
 }
 
 format LoadOrPrefetch {
@@ -71,11 +66,6 @@
 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp)  ~7; }});
 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
 0x27: stt({{ Mem.df = Fa; }});
-#ifdef USE_COPY
-0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
-   {{ fault = xc-copy(EA); }},
-   inst_flags = [IsMemRef, IsStore, 
IsCopy]);
-#endif
 }
 
 format StoreCond {
@@ -788,10 +778,8 @@
 
 format MiscPrefetch {
 0xf800: wh64({{ EA = Rb  ~ULL(63); }},
- {{ xc-writeHint(EA, 64, memAccessFlags); }},
- mem_flags = PREFETCH,
- inst_flags = [IsMemRef, IsDataPrefetch,
-   IsStore, MemWriteOp]);
+ {{ ; }},
+ mem_flags = PREFETCH);
 }
 
 format BasicOperate {
diff -r ba11187e2582 -r 00ea9430643b src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isaMon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/alpha/isa/mem.isaMon Nov 08 13:58:22 2010 -0600
@@ -396,6 +396,7 @@
 %(op_rd)s;
 %(ea_code)s;
 
+warn_once(Prefetch instrutions is Alpha do not do anything\n);
 if (fault == NoFault) {
 %(memacc_code)s;
 }
@@ -404,6 +405,8 @@
 }
 }};
 
+// Prefetches in Alpha don't actually do anything
+// They just build an effective address and complete
 def template MiscInitiateAcc {{
 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
   Trace::InstRecord *traceData) const
@@ -530,12 +533,10 @@
 inst_flags = makeList(inst_flags)
 
 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
-pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
-  'IsDataPrefetch', 'MemReadOp']
+pf_inst_flags =

[m5-dev] changeset in m5: ARM: Make all ARM uops delayed commit.

2010-11-08 Thread Ali Saidi

changeset ba11187e2582 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ba11187e2582
description:
ARM: Make all ARM uops delayed commit.

diffstat:

 src/arch/arm/insts/macromem.hh |   6 --
 src/arch/arm/isa/templates/mem.isa |  19 +++
 src/cpu/static_inst.hh |   2 ++
 3 files changed, 21 insertions(+), 6 deletions(-)

diffs (154 lines):

diff -r ee4ac00d0774 -r ba11187e2582 src/arch/arm/insts/macromem.hh
--- a/src/arch/arm/insts/macromem.hhMon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/arm/insts/macromem.hhMon Nov 08 13:58:22 2010 -0600
@@ -73,12 +73,6 @@
 
   public:
 void
-setDelayedCommit()
-{
-flags[IsDelayedCommit] = true;
-}
-
-void
 advancePC(PCState pcState) const
 {
 if (flags[IsLastMicroop]) {
diff -r ee4ac00d0774 -r ba11187e2582 src/arch/arm/isa/templates/mem.isa
--- a/src/arch/arm/isa/templates/mem.isaMon Nov 08 13:58:22 2010 -0600
+++ b/src/arch/arm/isa/templates/mem.isaMon Nov 08 13:58:22 2010 -0600
@@ -917,6 +917,7 @@
 assert(numMicroops = 2);
 uops = new StaticInstPtr[numMicroops];
 uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
 uops[1]-setLastMicroop();
 #endif
@@ -934,6 +935,7 @@
 assert(numMicroops = 2);
 uops = new StaticInstPtr[numMicroops];
 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
 uops[1]-setLastMicroop();
 #endif
@@ -963,6 +965,7 @@
 assert(numMicroops = 2);
 uops = new StaticInstPtr[numMicroops];
 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
 uops[1]-setLastMicroop();
 #endif
@@ -984,6 +987,7 @@
 uops = new StaticInstPtr[numMicroops];
 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
_base, _add, _imm);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
 uops[1]-setLastMicroop();
 #endif
@@ -1001,6 +1005,7 @@
 assert(numMicroops = 2);
 uops = new StaticInstPtr[numMicroops];
 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
 uops[1]-setLastMicroop();
 #endif
@@ -1021,6 +1026,7 @@
 uops = new StaticInstPtr[numMicroops];
 uops[0] = new %(acc_name)s(machInst, _result, _dest,
_base, _add, _imm);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
 uops[1]-setLastMicroop();
 #endif
@@ -1043,6 +1049,7 @@
 uops = new StaticInstPtr[numMicroops];
 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
 uops[1]-setLastMicroop();
 #endif
@@ -1064,6 +1071,7 @@
 uops = new StaticInstPtr[numMicroops];
 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
_shiftAmt, _shiftType, _index);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
 uops[1]-setLastMicroop();
 #endif
@@ -1087,14 +1095,17 @@
 if ((_dest == _index) || (_dest2 == _index)) {
 IntRegIndex wbIndexReg = INTREG_UREG0;
 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
+uops[0]-setDelayedCommit();
 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
+uops[1]-setDelayedCommit();
 uops[2] = new %(wb_decl)s;
 uops[2]-setLastMicroop();
 } else {
 IntRegIndex wbIndexReg = index;
 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
 uops[1]-setLastMicroop();
 }
@@ -1119,20 +1130,25 @@
 IntRegIndex wbIndexReg = index;
 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_shiftAmt, _shiftType, _index);
+uops[0]-setDelayedCommit();
 uops[1] = new %(wb_decl)s;
+uops[1]-setDelayedCommit();
 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
 uops[2]-setLastMicroop();
 } else if(_dest == _index) {
 IntRegIndex wbIndexReg = INTREG_UREG0;
 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
+

[m5-dev] changeset in m5: ARM/Alpha/Cpu: Stats change for prefetchs to be...

2010-11-08 Thread Ali Saidi

changeset 0d9de7394e38 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0d9de7394e38
description:
ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.

diffstat:

 tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
  | 4 +-
 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
  |14 +-
 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt 
  |   642 +-
 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
  | 2 +-
 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
  | 3 +
 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
  |11 +-
 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt 
  |10 +-
 tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
  | 4 +-
 tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
  |12 +-
 tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt 
  |10 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
  |12 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
  |17 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt 
  |  1782 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini 
  |12 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout 
  |17 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt  
  |   979 ++--
 tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini 
  | 4 +-
 tests/long/30.eon/ref/alpha/tru64/o3-timing/simout 
  |14 +-
 tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt  
  |   590 +-
 tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini 
  | 2 +-
 tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr 
  | 3 +
 tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout 
  |11 +-
 tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt  
  |10 +-
 tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini 
  | 4 +-
 tests/long/30.eon/ref/alpha/tru64/simple-timing/simout 
  |12 +-
 tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt  
  |10 +-
 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini 
  | 4 +-
 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout 
  |14 +-
 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt  
  |   616 +-
 tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini 
  | 2 +-
 tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr 
  | 3 +
 tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout 
  |11 +-
 tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt  
  |10 +-
 tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini 
  | 4 +-
 tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout 
  |12 +-
 tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt  
  |10 +-
 tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini 
  | 4 +-
 tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr 
  | 4 -
 tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout 
  |12 +-
 tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt  
  |24 +-
 tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini  
  | 4 +-
 tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout  
  |14 +-
 tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt   
  |   636 +-
 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini  
  | 2 +-
 tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr  
  | 3 +

[m5-dev] changeset in m5: scons: add a parameter to configure SCons' buil...

2010-11-08 Thread Ali Saidi

changeset e40fbbe1ed4f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e40fbbe1ed4f
description:
scons: add a parameter to configure SCons' build cache

diffstat:

 SConstruct |  7 +++
 1 files changed, 7 insertions(+), 0 deletions(-)

diffs (24 lines):

diff -r 0d9de7394e38 -r e40fbbe1ed4f SConstruct
--- a/SConstructMon Nov 08 13:58:24 2010 -0600
+++ b/SConstructMon Nov 08 13:58:24 2010 -0600
@@ -312,6 +312,7 @@
 ('CXX', 'C++ compiler', environ.get('CXX', main['CXX'])),
 ('BATCH', 'Use batch pool for build and tests', False),
 ('BATCH_CMD', 'Batch pool submission command name', 'qdo'),
+('M5_BUILD_CACHE', 'Cache built objects in this directory', False),
 ('EXTRAS', 'Add Extra directories to the compilation', '',
  PathListAllExist, PathListMakeAbsolute),
 )
@@ -549,6 +550,12 @@
 main.Append(CPPPATH=py_includes)
 main.Append(LIBPATH=py_lib_path)
 
+# Cache build files in the supplied directory.
+if main['M5_BUILD_CACHE']:
+print 'Using build cache located at', main['M5_BUILD_CACHE']
+CacheDir(main['M5_BUILD_CACHE'])
+
+
 # verify that this stuff works
 if not conf.CheckHeader('Python.h', ''):
 print Error: can't find Python.h header in, py_includes
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[m5-dev] changeset in m5: ARM: Don't return the result of a table walk th...

2010-11-08 Thread Ali Saidi

changeset cf9db1c47a77 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cf9db1c47a77
description:
ARM: Don't return the result of a table walk the same cycle it's 
completed.

The L1 cache may have been accessed to provide this data, which confuses
it, if it ends up being accesses twice in one cycle. Instead wait 1 tick
which will force the timing simple CPU to forward to its next clock 
cycle
when the translation completes.

Also prevent multiple outstanding table walks from occuring at once.

diffstat:

 src/arch/arm/table_walker.cc |  71 +++
 src/arch/arm/table_walker.hh |  12 +++
 2 files changed, 75 insertions(+), 8 deletions(-)

diffs (192 lines):

diff -r e40fbbe1ed4f -r cf9db1c47a77 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc  Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/table_walker.cc  Mon Nov 08 13:58:24 2010 -0600
@@ -41,13 +41,14 @@
 #include arch/arm/table_walker.hh
 #include arch/arm/tlb.hh
 #include dev/io_device.hh
+#include cpu/base.hh
 #include cpu/thread_context.hh
 
 using namespace ArmISA;
 
 TableWalker::TableWalker(const Params *p)
-: MemObject(p), port(NULL), tlb(NULL),
-  currState(NULL), doL1DescEvent(this), doL2DescEvent(this)
+: MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false),
+  doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
 {
 sctlr = 0;
 }
@@ -115,6 +116,35 @@
 currState-isFetch = (currState-mode == TLB::Execute);
 currState-isWrite = (currState-mode == TLB::Write);
 
+
+if (!currState-timing)
+return processWalk();
+
+if (pending) {
+pendingQueue.push_back(currState);
+currState = NULL;
+} else {
+pending = true;
+processWalk();
+}
+
+return NoFault;
+}
+
+void
+TableWalker::processWalkWrapper()
+{
+assert(!currState);
+assert(pendingQueue.size());
+currState = pendingQueue.front();
+pendingQueue.pop_front();
+pending = true;
+processWalk();
+}
+
+Fault
+TableWalker::processWalk()
+{
 Addr ttbr = 0;
 
 // If translation isn't enabled, we shouldn't be here
@@ -146,6 +176,9 @@
 if (currState-timing) {
 currState-transState-finish(f, currState-req,
   currState-tc, currState-mode);
+
+pending = false;
+nextWalk(currState-tc);
 currState = NULL;
 } else {
 currState-tc = NULL;
@@ -156,7 +189,8 @@
 
 if (currState-timing) {
 port-dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
-doL1DescEvent, (uint8_t*)currState-l1Desc.data, (Tick)0);
+doL1DescEvent, (uint8_t*)currState-l1Desc.data,
+currState-tc-getCpuPtr()-ticks(1));
 DPRINTF(TLBVerbose, Adding to walker fifo: queue size before adding: 
%d\n,
 stateQueueL1.size());
 stateQueueL1.push_back(currState);
@@ -167,7 +201,8 @@
flag = Request::UNCACHEABLE;
 }
 port-dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
-NULL, (uint8_t*)currState-l1Desc.data, (Tick)0, flag);
+NULL, (uint8_t*)currState-l1Desc.data,
+currState-tc-getCpuPtr()-ticks(1), flag);
 doL1Descriptor();
 f = currState-fault;
 }
@@ -498,10 +533,12 @@
 if (currState-timing) {
 currState-delayed = true;
 port-dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
-doL2DescEvent, (uint8_t*)currState-l2Desc.data, 0);
+doL2DescEvent, (uint8_t*)currState-l2Desc.data,
+currState-tc-getCpuPtr()-ticks(1));
 } else {
 port-dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
-NULL, (uint8_t*)currState-l2Desc.data, 0);
+NULL, (uint8_t*)currState-l2Desc.data,
+currState-tc-getCpuPtr()-ticks(1));
 doL2Descriptor();
 }
 return;
@@ -589,6 +626,9 @@
 currState-transState-finish(currState-fault, currState-req,
   currState-tc, currState-mode);
 
+pending = false;
+nextWalk(currState-tc);
+
 currState-req = NULL;
 currState-tc = NULL;
 currState-delayed = false;
@@ -600,10 +640,12 @@
 currState-fault = tlb-translateTiming(currState-req, currState-tc,
currState-transState, currState-mode);
 
+pending = false;
+nextWalk(currState-tc);
+
 currState-req = NULL;
 currState-tc = NULL;
 currState-delayed = false;
-
 delete currState;
 } else {
 // need to do L2 descriptor
@@ -633,15 +675,28 @@
   currState-transState, currState-mode);
 }
 
+
+

[m5-dev] changeset in m5: Bus: Have the I/O devices that return address r...

2010-11-08 Thread Ali Saidi

changeset d3c006ecccd3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d3c006ecccd3
description:
Bus: Have the I/O devices that return address ranges print them out.

This way we actually get device names associated with the devices.

diffstat:

 src/dev/io_device.cc |  3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diffs (20 lines):

diff -r cf9db1c47a77 -r d3c006ecccd3 src/dev/io_device.cc
--- a/src/dev/io_device.cc  Mon Nov 08 13:58:24 2010 -0600
+++ b/src/dev/io_device.cc  Mon Nov 08 13:58:24 2010 -0600
@@ -51,6 +51,8 @@
 {
 snoop = false;
 device-addressRanges(resp);
+for (AddrRangeIter i = resp.begin(); i != resp.end(); i++)
+ DPRINTF(BusAddrRanges, Adding Range %#x-%#x\n, i-start, i-end);
 }
 
 
@@ -95,6 +97,7 @@
 {
 assert(pioSize != 0);
 range_list.clear();
+DPRINTF(BusAddrRanges, registering range: %#x-%#x\n, pioAddr, pioSize);
 range_list.push_back(RangeSize(pioAddr, pioSize));
 }
 
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[m5-dev] changeset in m5: Mem: Finish half-baked support for mmaping file...

2010-11-08 Thread Ali Saidi

changeset 982b4c6c1470 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=982b4c6c1470
description:
Mem: Finish half-baked support for mmaping file in physmem.

Physmem has a parameter to be able to mem map a file, however
it isn't actually used. This changeset utilizes the parameter
so a file can be mmapped.

diffstat:

 configs/common/FSConfig.py |   8 ++-
 src/mem/physical.cc|  48 +++--
 src/mem/physical.hh|   8 +++---
 3 files changed, 44 insertions(+), 20 deletions(-)

diffs (176 lines):

diff -r d3c006ecccd3 -r 982b4c6c1470 configs/common/FSConfig.py
--- a/configs/common/FSConfig.pyMon Nov 08 13:58:24 2010 -0600
+++ b/configs/common/FSConfig.pyMon Nov 08 13:58:24 2010 -0600
@@ -200,9 +200,12 @@
 self.membus.badaddr_responder.warn_access = warn
 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
+self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = 
'128MB'),
+  file = disk('ael-arm.ext2'))
 self.bridge.side_a = self.iobus.port
 self.bridge.side_b = self.membus.port
 self.physmem.port = self.membus.port
+self.diskmem.port = self.membus.port
 
 self.mem_mode = mem_mode
 
@@ -224,7 +227,10 @@
 
 self.intrctrl = IntrControl()
 self.terminal = Terminal()
-self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 
norandmaps'
+self.kernel = binary('vmlinux.arm')
+self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + 
\
+' norandmaps slram=slram0,0x800,+0x800' +  
\
+' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
 
 return self
 
diff -r d3c006ecccd3 -r 982b4c6c1470 src/mem/physical.cc
--- a/src/mem/physical.cc   Mon Nov 08 13:58:24 2010 -0600
+++ b/src/mem/physical.cc   Mon Nov 08 13:58:24 2010 -0600
@@ -31,6 +31,7 @@
 
 #include sys/types.h
 #include sys/mman.h
+#include sys/user.h
 #include errno.h
 #include fcntl.h
 #include unistd.h
@@ -41,6 +42,7 @@
 #include string
 
 #include arch/registers.hh
+#include base/intmath.hh
 #include base/misc.hh
 #include base/random.hh
 #include base/types.hh
@@ -56,26 +58,39 @@
 PhysicalMemory::PhysicalMemory(const Params *p)
 : MemObject(p), pmemAddr(NULL), pagePtr(0),
   lat(p-latency), lat_var(p-latency_var),
-  cachedSize(params()-range.size()), cachedStart(params()-range.start)
+  _size(params()-range.size()), _start(params()-range.start)
 {
-if (params()-range.size() % TheISA::PageBytes != 0)
+if (size() % TheISA::PageBytes != 0)
 panic(Memory Size not divisible by page size\n);
 
 if (params()-null)
 return;
 
-int map_flags = MAP_ANON | MAP_PRIVATE;
-pmemAddr = (uint8_t *)mmap(NULL, params()-range.size(),
-   PROT_READ | PROT_WRITE, map_flags, -1, 0);
+
+if (params()-file == ) {
+int map_flags = MAP_ANON | MAP_PRIVATE;
+pmemAddr = (uint8_t *)mmap(NULL, size(),
+   PROT_READ | PROT_WRITE, map_flags, -1, 0);
+} else {
+int map_flags = MAP_PRIVATE;
+int fd = open(params()-file.c_str(), O_RDONLY);
+_size = lseek(fd, 0, SEEK_END);
+lseek(fd, 0, SEEK_SET);
+pmemAddr = (uint8_t *)mmap(NULL, roundUp(size(), PAGE_SIZE),
+   PROT_READ | PROT_WRITE, map_flags, fd, 0);
+}
 
 if (pmemAddr == (void *)MAP_FAILED) {
 perror(mmap);
-fatal(Could not mmap!\n);
+if (params()-file == )
+fatal(Could not mmap!\n);
+else
+fatal(Could not find file: %s\n, params()-file);
 }
 
 //If requested, initialize all the memory to 0
 if (p-zero)
-memset(pmemAddr, 0, p-range.size());
+memset(pmemAddr, 0, size());
 }
 
 void
@@ -94,8 +109,7 @@
 PhysicalMemory::~PhysicalMemory()
 {
 if (pmemAddr)
-munmap((char*)pmemAddr, params()-range.size());
-//Remove memPorts?
+munmap((char*)pmemAddr, size());
 }
 
 Addr
@@ -408,7 +422,7 @@
 {
 snoop = false;
 resp.clear();
-resp.push_back(RangeSize(start(), params()-range.size()));
+resp.push_back(RangeSize(start(), size()));
 }
 
 unsigned
@@ -463,6 +477,7 @@
 string filename = name() + .physmem;
 
 SERIALIZE_SCALAR(filename);
+SERIALIZE_SCALAR(_size);
 
 // write memory file
 string thefile = Checkpoint::dir() + / + filename.c_str();
@@ -477,8 +492,7 @@
 fatal(Insufficient memory to allocate compression state for %s\n,
 filename);
 
-if (gzwrite(compressedMem, pmemAddr, params()-range.size()) !=
-(int)params()-range.size()) {
+if (gzwrite(compressedMem, pmemAddr, size()) != (int)size()) {
 fatal(Write failed on physical memory checkpoint file

[m5-dev] changeset in m5: ARM: Keep the warnings to a minimum.

2010-11-08 Thread Ali Saidi

changeset e1eace3a118a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e1eace3a118a
description:
ARM: Keep the warnings to a minimum.

These warnings still need to be addresses, but pages of them is
counterproductive.

diffstat:

 src/arch/arm/isa.cc |  14 +++---
 src/dev/arm/RealView.py |   2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diffs (71 lines):

diff -r 982b4c6c1470 -r e1eace3a118a src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc   Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa.cc   Mon Nov 08 13:58:24 2010 -0600
@@ -180,10 +180,10 @@
 }
 switch (misc_reg) {
   case MISCREG_CLIDR:
-warn(The clidr register always reports 0 caches.\n);
+warn_once(The clidr register always reports 0 caches.\n);
 break;
   case MISCREG_CCSIDR:
-warn(The ccsidr register isn't implemented and 
+warn_once(The ccsidr register isn't implemented and 
 always reads as 0.\n);
 break;
   case MISCREG_ID_PFR0:
@@ -268,7 +268,7 @@
 }
 break;
   case MISCREG_CSSELR:
-warn(The csselr register isn't implemented.\n);
+warn_once(The csselr register isn't implemented.\n);
 break;
   case MISCREG_FPSCR:
 {
@@ -319,7 +319,7 @@
 return;
   case MISCREG_TLBIALLIS:
   case MISCREG_TLBIALL:
-warn(Need to flush all TLBs in MP\n);
+warn_once(Need to flush all TLBs in MP\n);
 tc-getITBPtr()-flushAll();
 tc-getDTBPtr()-flushAll();
 return;
@@ -331,7 +331,7 @@
 return;
   case MISCREG_TLBIMVAIS:
   case MISCREG_TLBIMVA:
-warn(Need to flush all TLBs in MP\n);
+warn_once(Need to flush all TLBs in MP\n);
 tc-getITBPtr()-flushMvaAsid(mbits(newVal, 31, 12),
 bits(newVal, 7,0));
 tc-getDTBPtr()-flushMvaAsid(mbits(newVal, 31, 12),
@@ -339,13 +339,13 @@
 return;
   case MISCREG_TLBIASIDIS:
   case MISCREG_TLBIASID:
-warn(Need to flush all TLBs in MP\n);
+warn_once(Need to flush all TLBs in MP\n);
 tc-getITBPtr()-flushAsid(bits(newVal, 7,0));
 tc-getDTBPtr()-flushAsid(bits(newVal, 7,0));
 return;
   case MISCREG_TLBIMVAAIS:
   case MISCREG_TLBIMVAA:
-warn(Need to flush all TLBs in MP\n);
+warn_once(Need to flush all TLBs in MP\n);
 tc-getITBPtr()-flushMva(mbits(newVal, 31,12));
 tc-getDTBPtr()-flushMva(mbits(newVal, 31,12));
 return;
diff -r 982b4c6c1470 -r e1eace3a118a src/dev/arm/RealView.py
--- a/src/dev/arm/RealView.py   Mon Nov 08 13:58:24 2010 -0600
+++ b/src/dev/arm/RealView.py   Mon Nov 08 13:58:24 2010 -0600
@@ -100,7 +100,7 @@
 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
 
-l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, 
warn_access=1)
+l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
 flash_fake= IsaFake(pio_addr=0x4000, pio_size=0x400)
 dmac_fake = AmbaFake(pio_addr=0x1003)
 uart1_fake= AmbaFake(pio_addr=0x1000a000)
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[m5-dev] changeset in m5: ARM: Add support for M5 ops in the ARM ISA

2010-11-08 Thread Ali Saidi

changeset a2c660de7787 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a2c660de7787
description:
ARM: Add support for M5 ops in the ARM ISA

diffstat:

 src/arch/arm/isa/decoder/arm.isa |8 +-
 src/arch/arm/isa/decoder/thumb.isa   |3 +-
 src/arch/arm/isa/formats/formats.isa |3 +
 src/arch/arm/isa/formats/m5ops.isa   |   78 +
 src/arch/arm/isa/includes.isa|1 +
 src/arch/arm/isa/insts/insts.isa |3 +
 src/arch/arm/isa/insts/m5ops.isa |  275 +++
 src/arch/arm/isa/operands.isa|3 +
 src/arch/arm/types.hh|2 +-
 util/m5/Makefile.arm |   65 
 util/m5/Makefile.thumb   |   67 
 util/m5/m5op_arm.S   |  143 ++
 12 files changed, 648 insertions(+), 3 deletions(-)

diffs (truncated from 756 to 300 lines):

diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/decoder/arm.isa
--- a/src/arch/arm/isa/decoder/arm.isa  Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa/decoder/arm.isa  Mon Nov 08 13:58:24 2010 -0600
@@ -90,7 +90,12 @@
 0x0: ArmParallelAddSubtract::armParallelAddSubtract();
 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
 0x2: ArmSignedMultiplies::armSignedMultiplies();
-0x3: ArmMiscMedia::armMiscMedia();
+0x3: decode MEDIA_OPCODE {
+ 0x1F: decode OPC2 {
+ default: ArmMiscMedia::armMiscMedia();
+ }
+ default: ArmMiscMedia::armMiscMedia();
+ }
 }
 }
 0x4: ArmMacroMem::armMacroMem();
@@ -107,6 +112,7 @@
 0xa, 0xb: VfpData::vfpData();
 } // CPNUM
 1: decode CPNUM { // 27-24=1110,4 ==1
+0x1: M5ops::m5ops();
 0xa, 0xb: ShortFpTransfer::shortFpTransfer();
 0xf: McrMrc15::mcrMrc15();
 } // CPNUM  (OP4 == 1)
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/decoder/thumb.isa
--- a/src/arch/arm/isa/decoder/thumb.isaMon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa/decoder/thumb.isaMon Nov 08 13:58:24 2010 -0600
@@ -84,6 +84,7 @@
 default: WarnUnimpl::cdp(); // cdp2
 }
 0x1: decode LTCOPROC {
+0x1: M5ops::m5ops();
 0xa, 0xb: ShortFpTransfer::shortFpTransfer();
 0xf: McrMrc15::mcrMrc15();
 }
@@ -125,7 +126,6 @@
 0x0: LoadByteMemoryHints::loadByteMemoryHints();
 0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints();
 0x2: Thumb32LoadWord::thumb32LoadWord();
-0x3: Unknown::undefined();
 }
 }
 0x1: decode HTOPCODE_8_7 {
@@ -140,6 +140,7 @@
 default: WarnUnimpl::cdp(); // cdp2
 }
 0x1: decode LTCOPROC {
+0x1: M5ops::m5ops();
 0xa, 0xb: ShortFpTransfer::shortFpTransfer();
 0xf: McrMrc15::mcrMrc15();
 }
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/formats/formats.isa
--- a/src/arch/arm/isa/formats/formats.isa  Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa/formats/formats.isa  Mon Nov 08 13:58:24 2010 -0600
@@ -79,3 +79,6 @@
 
 //Unconditional instructions
 ##include uncond.isa
+
+//M5 Psuedo-ops
+##include m5ops.isa
diff -r e1eace3a118a -r a2c660de7787 src/arch/arm/isa/formats/m5ops.isa
--- /dev/null   Thu Jan 01 00:00:00 1970 +
+++ b/src/arch/arm/isa/formats/m5ops.isaMon Nov 08 13:58:24 2010 -0600
@@ -0,0 +1,78 @@
+//
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the

[m5-dev] changeset in m5: ARM: Add checkpointing support

2010-11-08 Thread Ali Saidi

changeset 08d6a773d1b6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=08d6a773d1b6
description:
ARM: Add checkpointing support

diffstat:

 src/arch/arm/isa.hh  |  12 +-
 src/arch/arm/linux/system.cc |   5 +-
 src/arch/arm/linux/system.hh |   4 +-
 src/arch/arm/pagetable.hh|  87 +++
 src/arch/arm/table_walker.cc |  16 ++-
 src/arch/arm/table_walker.hh |   2 +-
 src/arch/arm/tlb.cc  |  14 ++-
 src/arch/arm/tlb.hh  |   2 -
 src/dev/arm/gic.cc   |  44 +-
 src/dev/arm/pl011.cc |  42 -
 src/dev/arm/rv_ctrl.cc   |   2 -
 src/dev/arm/timer_sp804.cc   |  59 -
 src/dev/arm/timer_sp804.hh   |   4 ++
 src/mem/physical.cc  |  30 +++
 src/mem/physical.hh  |   5 ++
 src/sim/SConscript   |   1 +
 src/sim/system.cc|   2 +-
 src/sim/system.hh|   2 +-
 18 files changed, 268 insertions(+), 65 deletions(-)

diffs (truncated from 587 to 300 lines):

diff -r a2c660de7787 -r 08d6a773d1b6 src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh   Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/isa.hh   Mon Nov 08 13:58:25 2010 -0600
@@ -178,10 +178,18 @@
 }
 
 void serialize(EventManager *em, std::ostream os)
-{}
+{
+DPRINTF(Checkpoint, Serializing Arm Misc Registers\n);
+SERIALIZE_ARRAY(miscRegs, NumMiscRegs);
+}
 void unserialize(EventManager *em, Checkpoint *cp,
 const std::string section)
-{}
+{
+DPRINTF(Checkpoint, Unserializing Arm Misc Registers\n);
+UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs);
+CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
+updateRegMap(tmp_cpsr);
+}
 
 ISA()
 {
diff -r a2c660de7787 -r 08d6a773d1b6 src/arch/arm/linux/system.cc
--- a/src/arch/arm/linux/system.cc  Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/linux/system.cc  Mon Nov 08 13:58:25 2010 -0600
@@ -99,9 +99,9 @@
 }
 
 void
-LinuxArmSystem::startup()
+LinuxArmSystem::initState()
 {
-ArmSystem::startup();
+ArmSystem::initState();
 ThreadContext *tc = threadContexts[0];
 
 // Set the initial PC to be at start of the kernel code
@@ -117,7 +117,6 @@
 {
 }
 
-
 LinuxArmSystem *
 LinuxArmSystemParams::create()
 {
diff -r a2c660de7787 -r 08d6a773d1b6 src/arch/arm/linux/system.hh
--- a/src/arch/arm/linux/system.hh  Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/linux/system.hh  Mon Nov 08 13:58:25 2010 -0600
@@ -67,8 +67,8 @@
 LinuxArmSystem(Params *p);
 ~LinuxArmSystem();
 
-/** Initialize the CPU for booting */
-void startup();
+void initState();
+
   private:
 #ifndef NDEBUG
 /** Event to halt the simulator if the kernel calls panic()  */
diff -r a2c660de7787 -r 08d6a773d1b6 src/arch/arm/pagetable.hh
--- a/src/arch/arm/pagetable.hh Mon Nov 08 13:58:24 2010 -0600
+++ b/src/arch/arm/pagetable.hh Mon Nov 08 13:58:25 2010 -0600
@@ -48,6 +48,8 @@
 #include arch/arm/vtophys.hh
 #include config/full_system.hh
 
+#include sim/serialize.hh
+
 namespace ArmISA {
 
 struct VAddr
@@ -71,39 +73,6 @@
 
 };
 
-struct TlbRange
-{
-Addr va;
-Addr size;
-int contextId;
-bool global;
-
-inline bool
-operator(const TlbRange r2) const
-{
-if (!(global || r2.global)) {
-if (contextId  r2.contextId)
-return true;
-else if (contextId  r2.contextId)
-return false;
-}
-
-if (va  r2.va)
-return true;
-return false;
-}
-
-inline bool
-operator==(const TlbRange r2) const
-{
-return va == r2.va 
-   size == r2.size 
-   contextId == r2.contextId 
-   global == r2.global;
-}
-};
-
-
 // ITB/DTB table entry
 struct TlbEntry
 {
@@ -143,10 +112,8 @@
 
 // Access permissions
 bool xn;// Execute Never
-uint8_t ap:3;   // Access permissions bits
-uint8_t domain:4;   // Access Domain
-
-TlbRange range; // For fast TLB searching
+uint8_t ap;   // Access permissions bits
+uint8_t domain;   // Access Domain
 
 //Construct an entry that maps to physical address addr for SE mode
 TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
@@ -196,9 +163,49 @@
 return (pfn  N) | (va  size);
 }
 
-void serialize(std::ostream os) { panic(Need to Implement\n); }
-void unserialize(Checkpoint *cp, const std::string section)
-   { panic(Need to Implement\n);}
+void
+serialize(std::ostream os)
+{
+SERIALIZE_SCALAR(pfn);
+SERIALIZE_SCALAR(size);
+SERIALIZE_SCALAR(vpn);
+SERIALIZE_SCALAR(asid);
+SERIALIZE_SCALAR(N);
+SERIALIZE_SCALAR(global);
+SERIALIZE_SCALAR(valid);

[m5-dev] changeset in m5: ARM: Add some TLB statistics for ARM

2010-11-08 Thread Ali Saidi

changeset 85a8198aa2ff in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=85a8198aa2ff
description:
ARM: Add some TLB statistics for ARM

diffstat:

 src/arch/arm/tlb.cc |  117 ++-
 src/arch/arm/tlb.hh |   28 ---
 2 files changed, 125 insertions(+), 20 deletions(-)

diffs (284 lines):

diff -r 08d6a773d1b6 -r 85a8198aa2ff src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc   Mon Nov 08 13:58:25 2010 -0600
+++ b/src/arch/arm/tlb.cc   Mon Nov 08 13:58:25 2010 -0600
@@ -152,6 +152,8 @@
 for(int i = size-1; i  0; i--)
   table[i] = table[i-1];
 table[0] = entry;
+
+inserts++;
 }
 
 void
@@ -178,13 +180,17 @@
 TlbEntry *te;
 while (x  size) {
te = table[x];
-   if (te-valid)
+   if (te-valid) {
DPRINTF(TLB,  -  %#x, asn %d ppn %#x size: %#x ap:%d\n,
 te-vpn  te-N, te-asid, te-pfn  te-N, te-size, 
te-ap);
+   flushedEntries++;
+   }
x++;
 }
 
 memset(table, 0, sizeof(TlbEntry[size]));
+
+flushTlb++;
 }
 
 
@@ -199,8 +205,10 @@
  DPRINTF(TLB,  -  %#x, asn %d ppn %#x size: %#x ap:%d\n,
 te-vpn  te-N, te-asid, te-pfn  te-N, te-size, te-ap);
 te-valid = false;
+flushedEntries++;
 te = lookup(mva,asn);
 }
+flushTlbMvaAsid++;
 }
 
 void
@@ -217,9 +225,11 @@
 te-valid = false;
 DPRINTF(TLB,  -  %#x, asn %d ppn %#x size: %#x ap:%d\n,
 te-vpn  te-N, te-asid, te-pfn  te-N, te-size, 
te-ap);
+flushedEntries++;
 }
 x++;
 }
+flushTlbAsid++;
 }
 
 void
@@ -237,9 +247,11 @@
 te-valid = false;
 DPRINTF(TLB,  -  %#x, asn %d ppn %#x size: %#x ap:%d\n,
 te-vpn  te-N, te-asid, te-pfn  te-N, te-size, 
te-ap);
+flushedEntries++;
 }
 x++;
 }
+flushTlbMva++;
 }
 
 void
@@ -268,34 +280,47 @@
 void
 TLB::regStats()
 {
-read_hits
+instHits
+.name(name() + .inst_hits)
+.desc(ITB inst hits)
+;
+
+instMisses
+.name(name() + .inst_misses)
+.desc(ITB inst misses)
+;
+
+instAccesses
+.name(name() + .inst_accesses)
+.desc(ITB inst accesses)
+;
+
+readHits
 .name(name() + .read_hits)
 .desc(DTB read hits)
 ;
 
-read_misses
+readMisses
 .name(name() + .read_misses)
 .desc(DTB read misses)
 ;
 
-
-read_accesses
+readAccesses
 .name(name() + .read_accesses)
 .desc(DTB read accesses)
 ;
 
-write_hits
+writeHits
 .name(name() + .write_hits)
 .desc(DTB write hits)
 ;
 
-write_misses
+writeMisses
 .name(name() + .write_misses)
 .desc(DTB write misses)
 ;
 
-
-write_accesses
+writeAccesses
 .name(name() + .write_accesses)
 .desc(DTB write accesses)
 ;
@@ -315,9 +340,57 @@
 .desc(DTB accesses)
 ;
 
-hits = read_hits + write_hits;
-misses = read_misses + write_misses;
-accesses = read_accesses + write_accesses;
+flushTlb
+.name(name() + .flush_tlb)
+.desc(Number of times complete TLB was flushed)
+;
+
+flushTlbMva
+.name(name() + .flush_tlb_mva)
+.desc(Number of times TLB was flushed by MVA)
+;
+
+flushTlbMvaAsid
+.name(name() + .flush_tlb_mva_asid)
+.desc(Number of times TLB was flushed by MVA  ASID)
+;
+
+flushTlbAsid
+.name(name() + .flush_tlb_asid)
+.desc(Number of times TLB was flushed by ASID)
+;
+
+flushedEntries
+.name(name() + .flush_entries)
+.desc(Number of entries that have been flushed from TLB)
+;
+
+alignFaults
+.name(name() + .align_faults)
+.desc(Number of TLB faults due to alignment restrictions)
+;
+
+prefetchFaults
+.name(name() + .prefetch_faults)
+.desc(Number of TLB faults due to prefetch)
+;
+
+domainFaults
+.name(name() + .domain_faults)
+.desc(Number of TLB faults due to domain restrictions)
+;
+
+permsFaults
+.name(name() + .perms_faults)
+.desc(Number of TLB faults due to permissions restrictions)
+;
+
+instAccesses = instHits + instMisses;
+readAccesses = readHits + readMisses;
+writeAccesses = writeHits + writeMisses;
+hits = readHits + writeHits + instHits;
+misses = readMisses + writeMisses + instMisses;
+accesses = readAccesses + writeAccesses + instAccesses;
 }
 
 #if !FULL_SYSTEM
@@ -400,6 +473,7 @@
 assert(flags  MustBeOne);
 if (sctlr.a || !(flags  AllowUnaligned)) {
 if (vaddr  flags  AlignmentMask) {
+alignFaults++;
 return new DataAbort(vaddr, 0, is_write, 
ArmFault::AlignmentFault);
 }
 }
@@

[m5-dev] changeset in m5: ARM: Add full-system regressions

2010-11-08 Thread Ali Saidi

changeset a1a85250e897 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a1a85250e897
description:
ARM: Add full-system regressions

diffstat:

 tests/SConscript   
|   21 +-
 tests/configs/realview-simple-atomic.py
|   96 +
 tests/configs/realview-simple-timing.py
|   98 +
 tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini  
|2 +-
 tests/long/00.gzip/ref/arm/linux/simple-atomic/simout  
|8 +-
 tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt   
|   32 +-
 tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini   
|4 +-
 tests/long/10.mcf/ref/arm/linux/simple-atomic/simout   
|8 +-
 tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
|   32 +-
 tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini   
|6 +-
 tests/long/10.mcf/ref/arm/linux/simple-timing/simout   
|   10 +-
 tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
|   32 +-
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini  
|  578 ++
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr  
|   39 +
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout  
|   16 +
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt   
|  399 ++
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status  
|1 +
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal 
|0 
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini  
|  575 +
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr  
|   39 +
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout  
|   16 +
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt   
|  483 
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status  
|1 +
 tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal 
|0 
 util/regress   
|2 +-
 25 files changed, 2464 insertions(+), 34 deletions(-)

diffs (truncated from 2739 to 300 lines):

diff -r 85a8198aa2ff -r a1a85250e897 tests/SConscript
--- a/tests/SConscript  Mon Nov 08 13:58:25 2010 -0600
+++ b/tests/SConscript  Mon Nov 08 13:58:25 2010 -0600
@@ -30,7 +30,7 @@
 #  Kevin Lim
 
 import os, signal
-import sys
+import sys, time
 import glob
 from SCons.Script.SConscript import SConsEnvironment
 
@@ -102,11 +102,26 @@
 if env['BATCH']:
 cmd = '%s -t %d %s' % (env['BATCH_CMD'], timeout, cmd)
 
+pre_exec_time = time.time()
 status = env.Execute(env.subst(cmd, target=target, source=source))
 if status == 0:
 # M5 terminated normally.
 # Run diff on output  ref directories to find differences.
 # Exclude the stats file since we will use diff-out on that.
+
+# NFS file systems can be annoying and not have updated yet
+# wait until we see the file modified
+statsdiff = os.path.join(tgt_dir, 'statsdiff')
+m_time = 0
+nap = 0
+while m_time  pre_exec_time and nap  10:
+try:
+m_time = os.stat(statsdiff).st_mtime
+except OSError:
+pass
+time.sleep(1)
+nap += 1
+
 outdiff = os.path.join(tgt_dir, 'outdiff')
 diffcmd = 'diff -ubrs %s ${SOURCES[2].dir} %s  %s' \
   % (output_ignore_args, tgt_dir, outdiff)
@@ -114,7 +129,6 @@
 print = Output differences =
 print contents(outdiff)
 # Run diff-out on stats.txt file
-statsdiff = os.path.join(tgt_dir, 'statsdiff')
 diffcmd = '$DIFFOUT ${SOURCES[2]} %s  %s' \
   % (os.path.join(tgt_dir, 'stats.txt'), statsdiff)
 diffcmd = env.subst(diffcmd, target=target, source=source)
@@ -260,6 +274,9 @@
 if env['TARGET_ISA'] == 'sparc':
 configs += ['t1000-simple-atomic',
 't1000-simple-timing']
+if env['TARGET_ISA'] == 'arm':
+configs += ['realview-simple-atomic',
+'realview-simple-timing']
 
 else:
 configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
diff -r 85a8198aa2ff -r a1a85250e897 tests/configs/realview-simple-atomic.py
--- /dev/null   Thu Jan 01 00:00:00 1970 +
+++ b/tests/configs/realview-simple-atomic.py   Mon Nov 08 13:58:25 2010 -0600
@@ -0,0 +1,96 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source

[m5-dev] changeset in m5: ARM: Update SE stats for TLB stats additions

2010-11-08 Thread Ali Saidi

changeset f61e079ad05e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f61e079ad05e
description:
ARM: Update SE stats for TLB stats additions

diffstat:

 tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini|   2 +-
 tests/long/00.gzip/ref/arm/linux/simple-atomic/simout|  10 +-
 tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt |   8 +-
 tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini|   2 +-
 tests/long/00.gzip/ref/arm/linux/simple-timing/simout|   8 +-
 tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt |  32 ++-
 tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini |   2 +-
 tests/long/10.mcf/ref/arm/linux/simple-atomic/simout |  10 +-
 tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt  |   8 +-
 tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini |   2 +-
 tests/long/10.mcf/ref/arm/linux/simple-timing/simout |  10 +-
 tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt  |   8 +-
 tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini  |   6 +-
 tests/long/20.parser/ref/arm/linux/simple-atomic/simout  |  10 +-
 tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt   |  32 ++-
 tests/long/20.parser/ref/arm/linux/simple-timing/config.ini  |   4 +-
 tests/long/20.parser/ref/arm/linux/simple-timing/simout  |   8 +-
 tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt   |  32 ++-
 tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini |   4 +-
 tests/long/30.eon/ref/arm/linux/simple-atomic/simout |  10 +-
 tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt  |  32 ++-
 tests/long/30.eon/ref/arm/linux/simple-timing/config.ini |   2 +-
 tests/long/30.eon/ref/arm/linux/simple-timing/simout |   8 +-
 tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt  |  32 ++-
 tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini |   4 +-
 tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout |  10 +-
 tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt  |  32 ++-
 tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini |   2 +-
 tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout |   8 +-
 tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt  |  32 ++-
 tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini  |   4 +-
 tests/long/50.vortex/ref/arm/linux/simple-atomic/simout  |  10 +-
 tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt   |  32 ++-
 tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini  |   2 +-
 tests/long/50.vortex/ref/arm/linux/simple-timing/simout  |   8 +-
 tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt   |  32 ++-
 tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini   |   4 +-
 tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout   |  10 +-
 tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt|  32 ++-
 tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini   |   2 +-
 tests/long/60.bzip2/ref/arm/linux/simple-timing/simout   |   8 +-
 tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt|  32 ++-
 tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini   |   4 +-
 tests/long/70.twolf/ref/arm/linux/simple-atomic/simout   |  14 ++--
 tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt|  32 ++-
 tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini   |   2 +-
 tests/long/70.twolf/ref/arm/linux/simple-timing/simout   |  10 ++-
 tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt|  32 ++-
 tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini  |   2 +-
 tests/quick/00.hello/ref/arm/linux/simple-atomic/simout  |  10 +-
 tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt   |  32 ++-
 51 files changed, 511 insertions(+), 173 deletions(-)

diffs (truncated from 1442 to 300 lines):

diff -r a1a85250e897 -r f61e079ad05e 
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini Mon Nov 08 
13:58:25 2010 -0600
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini Mon Nov 08 
13:59:35 2010 -0600
@@ -52,7 +52,7 @@
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
diff -r a1a85250e897 -r f61e079ad05e 
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
--- a/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout Mon Nov 08 
13:58:25 2010 -0600
+++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout Mon Nov 08 
13:59:35 2010 -0600
@@ -5,11 +5,11 @@
 All Rights Reserved
 
 
-M5 compiled Oct  5 2010 14:46:04
-M5 revision 878ec5a6f4d1+ 7707+ default qtip tip ext/fs_regressions.patch
-M5

[m5-dev] changeset in m5: X86: Fix X86_FS compilation.

2010-11-08 Thread Gabe Black

changeset f4362ffd810f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f4362ffd810f
description:
X86: Fix X86_FS compilation.

diffstat:

 src/arch/x86/linux/system.cc |  2 ++
 src/arch/x86/stacktrace.cc   |  1 +
 2 files changed, 3 insertions(+), 0 deletions(-)

diffs (30 lines):

diff -r f61e079ad05e -r f4362ffd810f src/arch/x86/linux/system.cc
--- a/src/arch/x86/linux/system.cc  Mon Nov 08 13:59:35 2010 -0600
+++ b/src/arch/x86/linux/system.cc  Mon Nov 08 12:43:38 2010 -0800
@@ -37,6 +37,7 @@
  * Authors: Gabe Black
  */
 
+#include arch/x86/isa_traits.hh
 #include arch/x86/linux/system.hh
 #include arch/x86/regs/int.hh
 #include arch/vtophys.hh
@@ -44,6 +45,7 @@
 #include cpu/thread_context.hh
 #include mem/physical.hh
 #include params/LinuxX86System.hh
+#include sim/byteswap.hh
 
 
 using namespace LittleEndianGuest;
diff -r f61e079ad05e -r f4362ffd810f src/arch/x86/stacktrace.cc
--- a/src/arch/x86/stacktrace.ccMon Nov 08 13:59:35 2010 -0600
+++ b/src/arch/x86/stacktrace.ccMon Nov 08 12:43:38 2010 -0800
@@ -37,6 +37,7 @@
 #include base/trace.hh
 #include cpu/base.hh
 #include cpu/thread_context.hh
+#include mem/vport.hh
 #include sim/system.hh
 
 using namespace std;
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Re: [m5-dev] changeset in m5: X86: Fix X86_FS compilation.

2010-11-08 Thread Gabe Black

 It's apparent an X86_FS regression is still really needed to keep that
code working like it should. Please make sure it builds before pushing
code, but I'm sure a regression would be harder to miss. This will be my
second highest generic M5 priority, possibly getting taken care of this
week or this coming weekend.

Could somebody give me a quick rundown on how the linux boot regressions
are structured? I assume specifying an external init script needs to
work. How does that hook in? Would I need to hack the kernel for that,
or replace the init on the image to load the user script, or what? I
think there may be one or two people out there that have done some of
this on their own already (I'm thinking of Joel specifically) and their
insight would also be helpful.

Gabe

On 11/08/10 12:43, Gabe Black wrote:
 changeset f4362ffd810f in /z/repo/m5
 details: http://repo.m5sim.org/m5?cmd=changeset;node=f4362ffd810f
 description:
   X86: Fix X86_FS compilation.

 diffstat:

  src/arch/x86/linux/system.cc |  2 ++
  src/arch/x86/stacktrace.cc   |  1 +
  2 files changed, 3 insertions(+), 0 deletions(-)

 diffs (30 lines):

 diff -r f61e079ad05e -r f4362ffd810f src/arch/x86/linux/system.cc
 --- a/src/arch/x86/linux/system.ccMon Nov 08 13:59:35 2010 -0600
 +++ b/src/arch/x86/linux/system.ccMon Nov 08 12:43:38 2010 -0800
 @@ -37,6 +37,7 @@
   * Authors: Gabe Black
   */
  
 +#include arch/x86/isa_traits.hh
  #include arch/x86/linux/system.hh
  #include arch/x86/regs/int.hh
  #include arch/vtophys.hh
 @@ -44,6 +45,7 @@
  #include cpu/thread_context.hh
  #include mem/physical.hh
  #include params/LinuxX86System.hh
 +#include sim/byteswap.hh
  
  
  using namespace LittleEndianGuest;
 diff -r f61e079ad05e -r f4362ffd810f src/arch/x86/stacktrace.cc
 --- a/src/arch/x86/stacktrace.cc  Mon Nov 08 13:59:35 2010 -0600
 +++ b/src/arch/x86/stacktrace.cc  Mon Nov 08 12:43:38 2010 -0800
 @@ -37,6 +37,7 @@
  #include base/trace.hh
  #include cpu/base.hh
  #include cpu/thread_context.hh
 +#include mem/vport.hh
  #include sim/system.hh
  
  using namespace std;
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Re: [m5-dev] changeset in m5: X86: Fix X86_FS compila tion.

2010-11-08 Thread Ali Saidi



Sorry Gabe,

To make a regression work you first need m5ops to work and the you can 
call m5 readfile, see if the file is non-zero and if it is execute it. 
The file is normally just a m5 exit call. I added a changeset that adds 
regressions for ARM_FS to reviewboard toady. You can checkout the change 
and look at the alpha image for what is required.


Ali



On Mon, 08 Nov 2010 12:49:25 -0800, Gabe Black gbl...@eecs.umich.edu 
wrote:
It's apparent an X86_FS regression is still really needed to keep 
that
code working like it should. Please make sure it builds before 
pushing
code, but I'm sure a regression would be harder to miss. This will be 
my
second highest generic M5 priority, possibly getting taken care of 
this

week or this coming weekend.

Could somebody give me a quick rundown on how the linux boot 
regressions

are structured? I assume specifying an external init script needs to
work. How does that hook in? Would I need to hack the kernel for 
that,

or replace the init on the image to load the user script, or what? I
think there may be one or two people out there that have done some of
this on their own already (I'm thinking of Joel specifically) and 
their

insight would also be helpful.

Gabe

On 11/08/10 12:43, Gabe Black wrote:

changeset f4362ffd810f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f4362ffd810f
description:
X86: Fix X86_FS compilation.

diffstat:

 src/arch/x86/linux/system.cc |  2 ++
 src/arch/x86/stacktrace.cc   |  1 +
 2 files changed, 3 insertions(+), 0 deletions(-)

diffs (30 lines):

diff -r f61e079ad05e -r f4362ffd810f src/arch/x86/linux/system.cc
--- a/src/arch/x86/linux/system.cc  Mon Nov 08 13:59:35 2010 -0600
+++ b/src/arch/x86/linux/system.cc  Mon Nov 08 12:43:38 2010 -0800
@@ -37,6 +37,7 @@
  * Authors: Gabe Black
  */

+#include arch/x86/isa_traits.hh
 #include arch/x86/linux/system.hh
 #include arch/x86/regs/int.hh
 #include arch/vtophys.hh
@@ -44,6 +45,7 @@
 #include cpu/thread_context.hh
 #include mem/physical.hh
 #include params/LinuxX86System.hh
+#include sim/byteswap.hh


 using namespace LittleEndianGuest;
diff -r f61e079ad05e -r f4362ffd810f src/arch/x86/stacktrace.cc
--- a/src/arch/x86/stacktrace.ccMon Nov 08 13:59:35 2010 -0600
+++ b/src/arch/x86/stacktrace.ccMon Nov 08 12:43:38 2010 -0800
@@ -37,6 +37,7 @@
 #include base/trace.hh
 #include cpu/base.hh
 #include cpu/thread_context.hh
+#include mem/vport.hh
 #include sim/system.hh

 using namespace std;
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[m5-dev] Review Request: ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.

2010-11-08 Thread Ali Saidi


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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/291/
---

Review request for Default.


Summary
---

ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.


Diffs
-

  src/arch/arm/isa.cc f61e079ad05e 
  src/arch/arm/tlb.hh f61e079ad05e 
  src/arch/arm/tlb.cc f61e079ad05e 
  src/arch/arm/utility.cc f61e079ad05e 

Diff: http://reviews.m5sim.org/r/291/diff


Testing
---


Thanks,

Ali

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[m5-dev] Review Request: ARM: Add support for a dumb IDE controller

2010-11-08 Thread Ali Saidi


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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/292/
---

Review request for Default.


Summary
---

ARM: Add support for a dumb IDE controller


Diffs
-

  configs/common/FSConfig.py f61e079ad05e 
  src/dev/Ide.py f61e079ad05e 
  src/dev/arm/realview.cc f61e079ad05e 
  src/dev/ide_ctrl.hh f61e079ad05e 
  src/dev/ide_ctrl.cc f61e079ad05e 
  src/dev/pcidev.cc f61e079ad05e 

Diff: http://reviews.m5sim.org/r/292/diff


Testing
---


Thanks,

Ali

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[m5-dev] Review Request: O3: prevent a squash when completeAcc() modifies misc reg through TC.

2010-11-08 Thread Ali Saidi


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http://reviews.m5sim.org/r/296/
---

Review request for Default.


Summary
---

O3: prevent a squash when completeAcc() modifies misc reg through TC.

This happens on ARM instructions when they update the IT state bits.
Code and associated comment was copied from execute() and initiateAcc() methods


Diffs
-

  src/cpu/o3/dyn_inst_impl.hh f61e079ad05e 

Diff: http://reviews.m5sim.org/r/296/diff


Testing
---


Thanks,

Ali

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[m5-dev] Review Request: imported patch ext/simd_opclasses.patch

2010-11-08 Thread Ali Saidi


---
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http://reviews.m5sim.org/r/297/
---

Review request for Default.


Summary
---

ARM/CPU: Add op classes for SIMD type instructions and use them in ARM ISA 
description.


Diffs
-

  src/arch/arm/isa/insts/div.isa f61e079ad05e 
  src/arch/arm/isa/insts/fp.isa f61e079ad05e 
  src/arch/arm/isa/insts/mult.isa f61e079ad05e 
  src/arch/arm/isa/insts/neon.isa f61e079ad05e 
  src/cpu/FuncUnit.py f61e079ad05e 
  src/cpu/o3/FUPool.py f61e079ad05e 
  src/cpu/o3/FuncUnitConfig.py f61e079ad05e 
  src/cpu/op_class.hh f61e079ad05e 

Diff: http://reviews.m5sim.org/r/297/diff


Testing
---


Thanks,

Ali

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[m5-dev] Review Request: ARM: Add a Keyboard Mouse Interface controller

2010-11-08 Thread Ali Saidi


---
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http://reviews.m5sim.org/r/295/
---

Review request for Default.


Summary
---

ARM: Add a Keyboard Mouse Interface controller


Diffs
-

  src/dev/arm/RealView.py f61e079ad05e 
  src/dev/arm/SConscript f61e079ad05e 
  src/dev/arm/kmi.hh PRE-CREATION 
  src/dev/arm/kmi.cc PRE-CREATION 

Diff: http://reviews.m5sim.org/r/295/diff


Testing
---


Thanks,

Ali

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[m5-dev] Review Request: ARM: Implement a CLCD Frame buffer

2010-11-08 Thread Ali Saidi


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---

Review request for Default.


Summary
---

ARM: Implement a CLCD Frame buffer


Diffs
-

  src/dev/arm/RealView.py f61e079ad05e 
  src/dev/arm/SConscript f61e079ad05e 
  src/dev/arm/amba_device.hh f61e079ad05e 
  src/dev/arm/amba_device.cc f61e079ad05e 
  src/dev/arm/pl111.hh PRE-CREATION 
  src/dev/arm/pl111.cc PRE-CREATION 

Diff: http://reviews.m5sim.org/r/294/diff


Testing
---


Thanks,

Ali

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[m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.

2010-11-08 Thread Ali Saidi


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http://reviews.m5sim.org/r/298/
---

Review request for Default.


Summary
---

O3: Make all instructions that write a misc register not perform the write 
until commit.

ARM Instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.

Added aliases for ARM FP exceptions and saturation flags in FPSCR.


Diffs
-

  src/arch/arm/isa.cc f61e079ad05e 
  src/arch/arm/isa/insts/fp.isa f61e079ad05e 
  src/arch/arm/isa/insts/neon.isa f61e079ad05e 
  src/arch/arm/isa/operands.isa f61e079ad05e 
  src/arch/arm/miscregs.hh f61e079ad05e 
  src/cpu/o3/commit_impl.hh f61e079ad05e 
  src/cpu/o3/dyn_inst.hh f61e079ad05e 
  src/cpu/o3/dyn_inst_impl.hh f61e079ad05e 

Diff: http://reviews.m5sim.org/r/298/diff


Testing
---


Thanks,

Ali

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[m5-dev] Review Request: imported patch ext/pretty_scons_output.patch

2010-11-08 Thread Ali Saidi


---
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http://reviews.m5sim.org/r/299/
---

Review request for Default.


Summary
---

Scons: Try to make SCons output prettier.

This change has scons print [ C], [CC], [LN], etc in front of normal commands 
instead of the entire command themselves and cleans up the build a good bit. 
Unfortunately, I couldn't figure out a way to get the same behavior from 
env.Command() calls so they're still verbose. 

Thoughts? Like it? Hate it?


Diffs
-

  SConstruct f61e079ad05e 

Diff: http://reviews.m5sim.org/r/299/diff


Testing
---


Thanks,

Ali

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Re: [m5-dev] Review Request: Scons: Try to make SCons output prettier.

2010-11-08 Thread Ali Saidi


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---

(Updated 2010-11-08 15:49:05.987230)


Review request for Default.


Summary (updated)
---

Scons: Try to make SCons output prettier.

This change has scons print [ C], [CC], [LN], etc in front of normal commands 
instead of the entire command themselves and cleans up the build a good bit. 
Unfortunately, I couldn't figure out a way to get the same behavior from 
env.Command() calls so they're still verbose. 

Thoughts? Like it? Hate it?


Diffs
-

  SConstruct f61e079ad05e 

Diff: http://reviews.m5sim.org/r/299/diff


Testing
---


Thanks,

Ali

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[m5-dev] Review Request: ARM: Add support for moving predicated false dest operands from sources.

2010-11-08 Thread Ali Saidi


---
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http://reviews.m5sim.org/r/300/
---

Review request for Default.


Summary
---

ARM: Add support for moving predicated false dest operands from sources.


Diffs
-

  src/arch/arm/isa/insts/misc.isa f61e079ad05e 
  src/arch/isa_parser.py f61e079ad05e 
  src/cpu/o3/dyn_inst.hh f61e079ad05e 
  src/cpu/o3/iew_impl.hh f61e079ad05e 
  src/cpu/o3/lsq_unit_impl.hh f61e079ad05e 

Diff: http://reviews.m5sim.org/r/300/diff


Testing
---


Thanks,

Ali

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Re: [m5-dev] Review Request: Scons: Try to make SCons output prettier.

2010-11-08 Thread Gabriel Michael Black


I've done this before, just a sec...

(some googling)

I think you have to use an Action object instead of a raw command in  
the Command builder. When building the Action object, the second  
parameter is the alternative text to output.


It might look like the following:

env.Command(target, source, Action(foo $TARGET $SOURCES, FOOING $SOURCES))

The []s are probably not necessary, but that's just my opinion.

It might be better to support a -v or --verbose option on the scons  
command line if we can. An environment variable is a little obscure,  
and it's likely you'll just want verbose output temporarily, not as a  
long term environment setting. I don't really remember whether adding  
command line options to the scons command line is feasible and/or  
advisable, so I'll defer to other people's opinions, but it seems a  
little more natural to me.


Gabe

Quoting Ali Saidi sa...@umich.edu:



---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/299/
---

(Updated 2010-11-08 15:49:05.987230)


Review request for Default.


Summary (updated)
---

Scons: Try to make SCons output prettier.

This change has scons print [ C], [CC], [LN], etc in front of normal  
commands instead of the entire command themselves and cleans up the  
build a good bit. Unfortunately, I couldn't figure out a way to get  
the same behavior from env.Command() calls so they're still verbose.


Thoughts? Like it? Hate it?


Diffs
-

  SConstruct f61e079ad05e

Diff: http://reviews.m5sim.org/r/299/diff


Testing
---


Thanks,

Ali

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Re: [m5-dev] Review Request: Scons: Try to make SCons output prettier.

2010-11-08 Thread Gabriel Michael Black

Oh wait, that's not an environment variable, that's a scons variable  
from the command line. My opinion still stands since it'd be sticky  
and it's not as nice as a -- option, but it's better than an  
environment variable.


Gabe

Quoting Gabriel Michael Black gbl...@eecs.umich.edu:


I've done this before, just a sec...

(some googling)

I think you have to use an Action object instead of a raw command in  
the Command builder. When building the Action object, the second  
parameter is the alternative text to output.


It might look like the following:

env.Command(target, source, Action(foo $TARGET $SOURCES, FOOING  
$SOURCES))


The []s are probably not necessary, but that's just my opinion.

It might be better to support a -v or --verbose option on the scons  
command line if we can. An environment variable is a little obscure,  
and it's likely you'll just want verbose output temporarily, not as  
a long term environment setting. I don't really remember whether  
adding command line options to the scons command line is feasible  
and/or advisable, so I'll defer to other people's opinions, but it  
seems a little more natural to me.


Gabe

Quoting Ali Saidi sa...@umich.edu:



---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/299/
---

(Updated 2010-11-08 15:49:05.987230)


Review request for Default.


Summary (updated)
---

Scons: Try to make SCons output prettier.

This change has scons print [ C], [CC], [LN], etc in front of  
normal commands instead of the entire command themselves and cleans  
up the build a good bit. Unfortunately, I couldn't figure out a way  
to get the same behavior from env.Command() calls so they're still  
verbose.


Thoughts? Like it? Hate it?


Diffs
-

 SConstruct f61e079ad05e

Diff: http://reviews.m5sim.org/r/299/diff


Testing
---


Thanks,

Ali

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Re: [m5-dev] Review Request: ARM: Add support for a dumb IDE controller

2010-11-08 Thread Nathan Binkert


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---



src/dev/ide_ctrl.cc
http://reviews.m5sim.org/r/292/#comment646

Is this something that we should deal with on a per device basis, or is 
this a more generic thing?  Also, is this something that should be configured 
by the user, or is this something that's either fixed or gleaned from the OS?


- Nathan


On 2010-11-08 15:34:45, Ali Saidi wrote:
 
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.m5sim.org/r/292/
 ---
 
 (Updated 2010-11-08 15:34:45)
 
 
 Review request for Default.
 
 
 Summary
 ---
 
 ARM: Add support for a dumb IDE controller
 
 
 Diffs
 -
 
   configs/common/FSConfig.py f61e079ad05e 
   src/dev/Ide.py f61e079ad05e 
   src/dev/arm/realview.cc f61e079ad05e 
   src/dev/ide_ctrl.hh f61e079ad05e 
   src/dev/ide_ctrl.cc f61e079ad05e 
   src/dev/pcidev.cc f61e079ad05e 
 
 Diff: http://reviews.m5sim.org/r/292/diff
 
 
 Testing
 ---
 
 
 Thanks,
 
 Ali
 


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Re: [m5-dev] Review Request: imported patch ext/arm_gdb.patch

2010-11-08 Thread Nathan Binkert


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---


Was the remote_gdb.cc file copied with hg cp  Be nice if it were.

- Nathan


On 2010-11-08 15:35:16, Ali Saidi wrote:
 
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.m5sim.org/r/293/
 ---
 
 (Updated 2010-11-08 15:35:16)
 
 
 Review request for Default.
 
 
 Summary
 ---
 
 imported patch ext/arm_gdb.patch
 
 
 Diffs
 -
 
   src/arch/arm/SConscript f61e079ad05e 
   src/arch/arm/remote_gdb.hh f61e079ad05e 
   src/arch/arm/remote_gdb.cc PRE-CREATION 
   src/arch/arm/utility.hh f61e079ad05e 
   src/arch/arm/utility.cc f61e079ad05e 
 
 Diff: http://reviews.m5sim.org/r/293/diff
 
 
 Testing
 ---
 
 
 Thanks,
 
 Ali
 


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Re: [m5-dev] Review Request: Scons: Try to make SCons output prettier.

2010-11-08 Thread nathan binkert

 I think you have to use an Action object instead of a raw command in the
 Command builder. When building the Action object, the second parameter is
 the alternative text to output.

 It might look like the following:

 env.Command(target, source, Action(foo $TARGET $SOURCES, FOOING
 $SOURCES))

 The []s are probably not necessary, but that's just my opinion.
If it's not too much work, it would be really nice to do this.

 It might be better to support a -v or --verbose option on the scons command
 line if we can. An environment variable is a little obscure, and it's likely
 you'll just want verbose output temporarily, not as a long term environment
 setting. I don't really remember whether adding command line options to the
 scons command line is feasible and/or advisable, so I'll defer to other
 people's opinions, but it seems a little more natural to me.
You can add a command line variable. I think that a verbose variable
would be nice though -v is already taken (we can repurpose it).

  Nate
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Re: [m5-dev] Review Request: Scons: Try to make SCons output prettier.

2010-11-08 Thread nathan binkert

 Thoughts? Like it? Hate it?
Love it.  What I'd really like would be to have the shorthand go to
stdout and have the verbose stuff go to some sort of scons.log in case
I want the command line.  That is probably too much work.  We could
also go the other way and add a -q/--quiet (though quiet already means
something quieter than we have).

  Nate
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Re: [m5-dev] Review Request: ARM: Add support for a dumb IDE controller

2010-11-08 Thread Ali Saidi



 On 2010-11-08 17:56:14, Nathan Binkert wrote:
  src/dev/ide_ctrl.cc, line 454
  http://reviews.m5sim.org/r/292/diff/1/?file=5058#file5058line454
 
  Is this something that we should deal with on a per device basis, or is 
  this a more generic thing?  Also, is this something that should be 
  configured by the user, or is this something that's either fixed or gleaned 
  from the OS?

It seems rather arbitrary, but the world of function pointers that sets this 
value in the OS is pretty deep. I think having the user configure it is fine, 
there isn't a really good way we could grab it from the OS since there isn't 
once place where there is a device struct that describes a ide controller. 
These values only seem to apply to the IDE device. 


- Ali


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---


On 2010-11-08 15:34:45, Ali Saidi wrote:
 
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.m5sim.org/r/292/
 ---
 
 (Updated 2010-11-08 15:34:45)
 
 
 Review request for Default.
 
 
 Summary
 ---
 
 ARM: Add support for a dumb IDE controller
 
 
 Diffs
 -
 
   configs/common/FSConfig.py f61e079ad05e 
   src/dev/Ide.py f61e079ad05e 
   src/dev/arm/realview.cc f61e079ad05e 
   src/dev/ide_ctrl.hh f61e079ad05e 
   src/dev/ide_ctrl.cc f61e079ad05e 
   src/dev/pcidev.cc f61e079ad05e 
 
 Diff: http://reviews.m5sim.org/r/292/diff
 
 
 Testing
 ---
 
 
 Thanks,
 
 Ali
 


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Re: [m5-dev] Review Request: imported patch ext/arm_gdb.patch

2010-11-08 Thread Ali Saidi



 On 2010-11-08 18:00:50, Nathan Binkert wrote:
  Was the remote_gdb.cc file copied with hg cp  Be nice if it were.

I'll make sure the committed code does that. Any other issues?


- Ali


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On 2010-11-08 15:35:16, Ali Saidi wrote:
 
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.m5sim.org/r/293/
 ---
 
 (Updated 2010-11-08 15:35:16)
 
 
 Review request for Default.
 
 
 Summary
 ---
 
 imported patch ext/arm_gdb.patch
 
 
 Diffs
 -
 
   src/arch/arm/SConscript f61e079ad05e 
   src/arch/arm/remote_gdb.hh f61e079ad05e 
   src/arch/arm/remote_gdb.cc PRE-CREATION 
   src/arch/arm/utility.hh f61e079ad05e 
   src/arch/arm/utility.cc f61e079ad05e 
 
 Diff: http://reviews.m5sim.org/r/293/diff
 
 
 Testing
 ---
 
 
 Thanks,
 
 Ali
 


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Re: [m5-dev] Review Request: Scons: Try to make SCons output prettier.

2010-11-08 Thread Ali Saidi

It's not sticky since it's not added to the sticky_vars below. Although it 
seems like our options are a bit adhoc and there is an arguments() class in 
scons that does some of this for us. RE your action command below, yes I saw 
that you can do it with an Action() however, according to the mailing list it's 
broken in SCons 2.0 or late 1.X so I'm not too excited about doing it. If we 
really wanted to we could detect the version and not do it in those cases, but 
that might be too much work.

Ali

On Nov 8, 2010, at 6:41 PM, Gabriel Michael Black wrote:

 Oh wait, that's not an environment variable, that's a scons variable from the 
 command line. My opinion still stands since it'd be sticky and it's not as 
 nice as a -- option, but it's better than an environment variable.
 
 Gabe
 
 Quoting Gabriel Michael Black gbl...@eecs.umich.edu:
 
 I've done this before, just a sec...
 
 (some googling)
 
 I think you have to use an Action object instead of a raw command in the 
 Command builder. When building the Action object, the second parameter is 
 the alternative text to output.
 
 It might look like the following:
 
 env.Command(target, source, Action(foo $TARGET $SOURCES, FOOING 
 $SOURCES))
 
 The []s are probably not necessary, but that's just my opinion.
 
 It might be better to support a -v or --verbose option on the scons command 
 line if we can. An environment variable is a little obscure, and it's likely 
 you'll just want verbose output temporarily, not as a long term environment 
 setting. I don't really remember whether adding command line options to the 
 scons command line is feasible and/or advisable, so I'll defer to other 
 people's opinions, but it seems a little more natural to me.
 
 Gabe
 
 Quoting Ali Saidi sa...@umich.edu:
 
 
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.m5sim.org/r/299/
 ---
 
 (Updated 2010-11-08 15:49:05.987230)
 
 
 Review request for Default.
 
 
 Summary (updated)
 ---
 
 Scons: Try to make SCons output prettier.
 
 This change has scons print [ C], [CC], [LN], etc in front of normal 
 commands instead of the entire command themselves and cleans up the build a 
 good bit. Unfortunately, I couldn't figure out a way to get the same 
 behavior from env.Command() calls so they're still verbose.
 
 Thoughts? Like it? Hate it?
 
 
 Diffs
 -
 
 SConstruct f61e079ad05e
 
 Diff: http://reviews.m5sim.org/r/299/diff
 
 
 Testing
 ---
 
 
 Thanks,
 
 Ali
 
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Re: [m5-dev] Review Request: Scons: Try to make SCons output prettier.

2010-11-08 Thread Ali Saidi

Check out scons -Q

Ali

On Nov 8, 2010, at 8:11 PM, Nathan Binkert wrote:

 Thoughts? Like it? Hate it?
 Love it.  What I'd really like would be to have the shorthand go to
 stdout and have the verbose stuff go to some sort of scons.log in case
 I want the command line.  That is probably too much work.  We could
 also go the other way and add a -q/--quiet (though quiet already means
 something quieter than we have).
 
  Nate
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Re: [m5-dev] Review Request: Scons: Try to make SCons output prettier.

2010-11-08 Thread Ali Saidi

Hmm. ok.. it seems like the issue only exists for builders. Which means we 
can do it although I don't know a way to make the non COMSTR ones produce 
output when VERBOSE=True. Thoughts?

Ali


pretty_scons.patch
Description: Binary data




On Nov 8, 2010, at 10:29 PM, Ali Saidi wrote:

 It's not sticky since it's not added to the sticky_vars below. Although it 
 seems like our options are a bit adhoc and there is an arguments() class in 
 scons that does some of this for us. RE your action command below, yes I saw 
 that you can do it with an Action() however, according to the mailing list 
 it's broken in SCons 2.0 or late 1.X so I'm not too excited about doing it. 
 If we really wanted to we could detect the version and not do it in those 
 cases, but that might be too much work.
 
 Ali
 
 On Nov 8, 2010, at 6:41 PM, Gabriel Michael Black wrote:
 
 Oh wait, that's not an environment variable, that's a scons variable from 
 the command line. My opinion still stands since it'd be sticky and it's not 
 as nice as a -- option, but it's better than an environment variable.
 
 Gabe
 
 Quoting Gabriel Michael Black gbl...@eecs.umich.edu:
 
 I've done this before, just a sec...
 
 (some googling)
 
 I think you have to use an Action object instead of a raw command in the 
 Command builder. When building the Action object, the second parameter is 
 the alternative text to output.
 
 It might look like the following:
 
 env.Command(target, source, Action(foo $TARGET $SOURCES, FOOING 
 $SOURCES))
 
 The []s are probably not necessary, but that's just my opinion.
 
 It might be better to support a -v or --verbose option on the scons command 
 line if we can. An environment variable is a little obscure, and it's 
 likely you'll just want verbose output temporarily, not as a long term 
 environment setting. I don't really remember whether adding command line 
 options to the scons command line is feasible and/or advisable, so I'll 
 defer to other people's opinions, but it seems a little more natural to me.
 
 Gabe
 
 Quoting Ali Saidi sa...@umich.edu:
 
 
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.m5sim.org/r/299/
 ---
 
 (Updated 2010-11-08 15:49:05.987230)
 
 
 Review request for Default.
 
 
 Summary (updated)
 ---
 
 Scons: Try to make SCons output prettier.
 
 This change has scons print [ C], [CC], [LN], etc in front of normal 
 commands instead of the entire command themselves and cleans up the build 
 a good bit. Unfortunately, I couldn't figure out a way to get the same 
 behavior from env.Command() calls so they're still verbose.
 
 Thoughts? Like it? Hate it?
 
 
 Diffs
 -
 
 SConstruct f61e079ad05e
 
 Diff: http://reviews.m5sim.org/r/299/diff
 
 
 Testing
 ---
 
 
 Thanks,
 
 Ali
 
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[m5-dev] Review Request: SimObject: Use self when calling the clear_child method.

2010-11-08 Thread Gabe Black


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Review request for Default.


Summary
---

SimObject: Use self when calling the clear_child method.


Diffs
-

  src/python/m5/SimObject.py f4362ffd810f 

Diff: http://reviews.m5sim.org/r/301/diff


Testing
---


Thanks,

Gabe

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Re: [m5-dev] Review Request: SimObject: Use self when calling the clear_child method.

2010-11-08 Thread Gabe Black

 This code was apparently never called before, and I think I landed on
it by accident. Could there be anything else like that? Maybe we should
put together a test configuration?

Gabe

On 11/08/10 23:37, Gabe Black wrote:
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.m5sim.org/r/301/
 ---

 Review request for Default.


 Summary
 ---

 SimObject: Use self when calling the clear_child method.


 Diffs
 -

   src/python/m5/SimObject.py f4362ffd810f 

 Diff: http://reviews.m5sim.org/r/301/diff


 Testing
 ---


 Thanks,

 Gabe

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