> warranty. (leave it on for the first 30 days!)
AT FULL CONTRAST with a lot of white on your screen. Burn in the flyback.
I bet the refurbished units probably had blown flybacks replaced.
_
Brian Guralnick
[EMAIL PROTECTED]
- Original Message -
From: "Tony Karavidas" <[EM
Hi Tony,
Leaving it on is being nice, let get hot and cold, every
day..
Darren Moore
> -Original Message-
> From: Tony Karavidas [mailto:[EMAIL PROTECTED]
>
>
> I've been buying a few things from this vendor, so now I'm on
> the sucker
> list. (they are legit, I opt-in on this one.
I've been buying a few things from this vendor, so now I'm on the sucker
list. (they are legit, I opt-in on this one. I recently purchased a NEW
160GB hard drive for my TIVO from them for $75!)
Since Protel s/w is so much more usable on a big screen, I thought I'd share
this current item. It's a r
At 05:34 PM 12/2/2003, you wrote:
Now, I have several throughhole pads that should connect to a
midlayer. They appear not to connect though. Beside the
4 90degree sectors, that form a heat resistance, also a
ring can bee seen, obviously isolating the hole.
The vias only have the sectors, not the ri
At 04:24 PM 27/11/2003 +0100, you wrote:
HELP!
I have been going over this for the better part of the day now, and cannot
find the solution.
On the processor schematic I have the busses [COL0..COL2] and
[R\O\W\0..R\O\W\7] with pullups on COL0..COL2. The COL bus is connected to
an input port, t
Thanks to all those that responded to the pervious post. It is no longer
necessary to reply if you haven't already done so. From the response it
appears that more than a few members were not receiving mail and that
resetting the ISP did resolve the problem.
Those that wish to catch up with miss
At 02:22 PM 2/12/2003 -0800, you wrote:
At 01:57 PM 12/2/2003, Tony Karavidas wrote:
Why are people asking DXP questions on the PEDA list? You'll probably get
more answers on the DXP list.
Tony, this list is intended for discussion of all EDA technical questions
including those of DXP.
Not all
Thanks Edi,
the split planes appear to have been accepted, at least halfway.
Now, I have several throughhole pads that should connect to a
midlayer. They appear not to connect though. Beside the
4 90degree sectors, that form a heat resistance, also a
ring can bee seen, obviously isolating the hole.
At 01:57 PM 12/2/2003, Tony Karavidas wrote:
Why are people asking DXP questions on the PEDA list? You'll probably get
more answers on the DXP list.
Tony, this list is intended for discussion of all EDA technical questions
including those of DXP.
Not all users of DXP are a member of the Protel
At 17:36 02.12.2003 +0100, you wrote:
I'm the first time trying to do a multilayer.
I've set up the middle two layers as GND and VCC.
Both layers are split. I therefore placed tracks
through them.
Use "Design|Split Planes..." and add the splits there. They're defined like
polygons.
Common tracks
For the first time I sent along the testpoint report.ipc. Even after carefully
re-generating my cam files, my boardhouse (Sierra Proto Express) claimed that my
gerbers didn't match.
What is up? How can I verify prior top sending my files? Is the testpoint report
useful?
Mike
PS what has ha
Hi All,
Is this conversion possible?. I think our version of Protel DOS
schematic is version 3.1...
Cheers,
Terry Creer
Printed Circuit Designer
Clipsal Integrated Systems Pty. Ltd.
Phone: (08) 8440 0500 (Ext. 448)
Fax: (08) 8346 0380
Email: [EMAIL PROTECTED]
Disclaimer: The informat
Happy Thanksgiving to all that observe it.
JaMi
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* To post a message: mailto:[EMAIL PROTECTED]
*
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*
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The violations detail is also included right on the Messages panel but it
doesn't show the specific highlight as does the PCB panel Jerry noted. That
would be a nice addition.
Why are people asking DXP questions on the PEDA list? You'll probably get
more answers on the DXP list.
-Original M
HELP!
I have been going over this for the better part of the day now, and cannot
find the solution.
On the processor schematic I have the busses [COL0..COL2] and
[R\O\W\0..R\O\W\7] with pullups on COL0..COL2. The COL bus is connected to
an input port, the ROW bus to an output port. All busses
I hate having power supply pins as part of schematic component symbols (especially
opamps and logic gate chips). I prefer to create an additional `component part' in the
chip purely for the power supply pins. This makes it easier to assign decoupling
components to the chip as well as reduce clut
If a double-sided pcb has a very large DIGITAL GND net and a small ANALOG GND net
would you connect the two GROUND planes created on the two layers to the DGND or AGND?
Connecting DGND would mean better current handling and thus presumably reduce digital
noise but would the large plane then act
Hello, all:
I've got to give a preliminary PCB placement to a customer. Of course PDF
can be made, but is there a free Protel viewer that he can use? If so, what
is it, and where do I get it?
Thanks, and happy Thanksgiving to you all.
Best regards,
Ivan Baggett
Bagotronix Inc.
website: www.ba
Hi, I am confused about these, if I have a multisheet schematic will net
names in one sheet connect to net names in another sheet without using ports
or offsheet connectors? To me a horizontal design is the same as flat
design, there is no hierarchy, which to me is the same as vertical, does
Pr
sorry, is there another list, room, forum, whatever for DXP? didn't realise
this was for 99
From: "Tony Karavidas" <[EMAIL PROTECTED]>
Reply-To: "Protel EDA Forum" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Subject: Re: [PEDA] component pin dialogue
Date: Sun, 23 Nov 2003 1
At 09:42 PM 11/20/2003, JaMi Smith wrote:
What I perceive from my original reading of the announcement is that
Protel / Altium is going to drop DXP and nVisage DXP (DXPnV), and
replace it with a new product, Protel 2004 (P04), which will be given to
all current DXP and DXPnV (collectively "DXP(nV)"
> -Original Message-
> From: Mike Ingle [mailto:[EMAIL PROTECTED]
> Sent: Friday, November 21, 2003 4:11 PM
> To: Protel EDA Forum
> Subject: [PEDA] pick and place report
>
> Hi all,
>
> This job will be my first where a pick and place machine is
> used. I have some confusion regarding
In DXP,
is there a way to open drill top (.gd1) (.gg1) outputs? when I double click
one it asks me what I want to open it with, or if it go to file-open it is
then opened as a text file, I want to view it just like the other gerber
file outputs
thank you
_
if you went through the rrouble of telling us you found the answer the least
you could have done is let us know the answer, I am a rookie DXP user and
would like to know how to do that too
how do you change multiple tracks?
From: "William Dager" <[EMAIL PROTECTED]>
Reply-To: "Protel EDA Forum"
Bagotronix Tech Support wrote:
Has anyone ever successfully used Protel's PLD/FPGA features with a vendor's
(Xilinx, Altera, Lattice, etc.) toolsuite and gotten usable results? Was it
worth the hassle? I ask because it is usually better to use the vendor's
fitting, place, and route software th
> Leave the lawyers out of it. They are the cause of 1/2 the world's
problems
> anyway. The only thing lawyers will do is drain money from Altium, and
we'll
> be paying for it with more expensive products.
Literally true. I have a saying:
"There are only 2 reasons you need a lawyer. #1 is if yo
I thought Protel 2.8 could convert this version. Can anyone verify?
-Original Message-
From: Christopher Rhomberg [mailto:[EMAIL PROTECTED]
Sent: Sunday, November 16, 2003 8:34 PM
To: Protel EDA Forum
Subject: [PEDA] Tango to Protel
Hi Everyone,
I got a design from someone else who s
William, Steve and others
I'm afraid that there was some confusion in this situation.
And that confusion was caused by original writer.
Because there was no other information in the original post specifying
the version of software, I assumed (and so did Steve, maybe others as well)
that the questi
...that is the question:
I'm making a footprint of a 128 pin qfp 0.4mm pitch. I have seen people use
a pad that is .070 x .010. Now with those numbers it would give me approx 2
mil's of LPI in between pads and approx 2 mil's guard from edge of pad to
start of LPI mask in the web between the pads
Ian,
I just knew that you could not speak to the issue.
You have only confirmed what was fairly obvious before, that you really are on the
Protel / Altium side of the fence.
You contribute greatly to the forum when there are small problems to be solved, but
you are nowhere to be found when an "i
In the PCB panel select rules from the drop down, select a rule class,
double click on a violation. A single click will highlight it the double
click opens the familiar details window.
Jerry Fisher C.I.D.
Assoc. Elec. Engineer
Pelco
10 corporate Dr.
Orangeburg N.Y. 10962
(845)398-8700
[EMAIL PR
Hey all,
Really silly question here, but how exactly do I go about highlighting
design rules violations in the PCB editor in DXP? This seems to function a
little differently than in 99SE...
I can generate the DRC okay, and see all of the violations display in the
MESSAGES window, and click
Sorry I sent that from the wrong E-Mail account.
[EMAIL PROTECTED] is the subscribed E-Mail
-Original Message-
From: Christopher Coley [mailto:[EMAIL PROTECTED]
Sent: Tuesday, December 02, 2003 10:52 AM
To: 'Protel EDA Forum'
Subject: RE: [PEDA] Possible Email Delivery Problem
I did no
We have had a couple reports of from members of this forum that they
stopped receiving forum mail last week. Although our systems seem to be
operating normally, the timing roughly coincides with a change we made to
the ISP for outgoing mail.
We've temporarily switched back to the old ISP to see
I'm the first time trying to do a multilayer.
I've set up the middle two layers as GND and VCC.
Both layers are split. I therefore placed tracks
through them. Common tracks on all layers were
placed as keepout.
Upon a printout, I found that middle layer don't
have keepouts.
Is it therefore true tha
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