Re: [PEDA] Process Identifiers
Andrew, you're not suggesting that the poor individual try to use or navigate the Protel help system are you? Good luck. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]] Sent: Friday, August 31, 2001 5:57 PM To: Protel EDA Forum Subject: Re: [PEDA] Process Identifiers On 04:15 PM 8/31/2001 -0700, Brad Velander wrote: Keith, the alternate approach that works is as follows. If you just want to look at a few processes. Go to your Down Arrow (Left side main toolbar). Select Customize. Or, alternatively, double-click on the menu bar within either the Schematic or PCB applications, just to the right of the last entry (Help). This will bring up the same dialog customization dialog. Then follow the steps that Brad outlined. regards, aj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Stop updating power plane connections
Does anyone know how to force Protel99SE SP6 to stop updating power plane connections. I am deleting components off of a PCB to make a mechanical template and have cleared all nets and removed all layers except the Top and Bottom in Layer Stack Manager but still get the stupid updating power plane connections pause. Any help appreciated, Thanks Cam Andruik Harding Instruments * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating/implementing IC socket PCB decals
You could try making, or editing a library component which has your custom socket decal. This component will be treated as 1 component. In the schematic, just change the IC's footprint to this new component decal. Brian Guralnick - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 04, 2001 12:14 PM Subject: [PEDA] Creating/implementing IC socket PCB decals | Hello Group, | | I'm new to protel, trying to figure out how to create and implement IC sockets decals/footprints on a PCB layout. | | Is it as simple as placing an IC and its socket on top of each other -or will that create a design rule violation? | | In pads, we created a dummy part (without a footprint)that acted as a placekeeper to get the socket part number on the BOM, I was hoping Protel might have a more elegant solution. | | Any suggestions? | | Thanks in advance! | | Charlie Rich | Lightwave Electronics | | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating/implementing IC socket PCB decals
Perhaps this is over simplistic, but... As long as the socket and component PCB footprints match, you can put the appropriate socket part number in a schematic symbol Part Field and include the field on the BOM report. You will also have to add a note on the BOM (or have an in-house convention) that the socket is to be used in addition to the component. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 12:15 PM To: Protel EDA Forum Subject: [PEDA] Creating/implementing IC socket PCB decals Hello Group, I'm new to protel, trying to figure out how to create and implement IC sockets decals/footprints on a PCB layout. Is it as simple as placing an IC and its socket on top of each other -or will that create a design rule violation? In pads, we created a dummy part (without a footprint)that acted as a placekeeper to get the socket part number on the BOM, I was hoping Protel might have a more elegant solution. Any suggestions? Thanks in advance! Charlie Rich Lightwave Electronics * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating/implementing IC socket PCB decals
SCRAP what I said earlier, need my morning coffee... :) Brian Guralnick - Original Message - From: Brian Guralnick [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 04, 2001 12:26 PM Subject: Re: [PEDA] Creating/implementing IC socket PCB decals | You could try making, or editing a library component which has your custom socket | decal. This component will be treated as 1 component. In the schematic, just change | the IC's footprint to this new component decal. | | | Brian Guralnick | | | - Original Message - | From: [EMAIL PROTECTED] | To: Protel EDA Forum [EMAIL PROTECTED] | Sent: Tuesday, September 04, 2001 12:14 PM | Subject: [PEDA] Creating/implementing IC socket PCB decals | | | | Hello Group, | | | | I'm new to protel, trying to figure out how to create and implement IC sockets | decals/footprints on a PCB layout. | | | | Is it as simple as placing an IC and its socket on top of each other -or will that | create a design rule violation? | | | | In pads, we created a dummy part (without a footprint)that acted as a placekeeper | to get the socket part number on the BOM, I was hoping Protel might have a more | elegant solution. | | | | Any suggestions? | | | | Thanks in advance! | | | | Charlie Rich | | Lightwave Electronics | | | | | | | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] P-CAD - Protel Translation
Warning Could not process message with given Content-Type: multipart/mixed; boundary=#DM25406312#
[PEDA] desgronte@web.de
Warning Could not process message with given Content-Type: multipart/mixed; boundary=#DM1079406#
Re: [PEDA] Orcad Net names off grid after translatation??
[PEDA] printing problem
Hello all All of a sudden the power print doesent show anything? It has worked quit perfekt earlier. All layer is selected, pressing Rebuild or Process PCB keep resulting in a blank paper. ( target pcb is selected ) Erase PPC file doesent help, getting same result. Any ideas?? Tommy * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P-CAD - Protel Translation
Mike, As best I understand, the currently-available (unless they've updated in the last couple of months) translation pack from Protel only works with P-CAD 2000 files, and DOES NOT work with P-CAD 2001. I had exactly the trouble you are having until I got a demo version of P-CAD 2000. Richard Bruer, P.E. Chief Engineer Instrument Division American Magnetics, Inc. 112 Flint Road Oak Ridge, TN 37830 Phone: (865) 482-1056 Fax: (865) 482-5472 mailto:[EMAIL PROTECTED] http://www.americanmagnetics.com -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Monday, September 03, 2001 7:54 PM To: proteledaforum Subject: [PEDA] P-CAD - Protel Translation Hi, I am trying to transpose a PCAD file into Protel (any version). I have tried the 'Pcad Translation pack' download from Protel, but only with limited success. All signal layer tracks and vias are imported into Protel, but no components and there pads. The Interal planes also seem to be ommitted. I have the PCAD 2001 30 day demo, and the original files, so have been able to try different angles. eg dxf, pdif. Can anyone shine any light? Cheers, Mike. [EMAIL PROTECTED] Posted from Association web site by: Mike Richardson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] printing problem
Tommy, here is my best guess at this moment. On the Browse PCB Print tab, click on the printer to highlight it, right click to bring up properties. Check the Print What area on the right mid way down the page. Is the Selected Objects Only checked? If it is checked, then the only items which will display or print are items within the PCB file which are selected. I would suggest that you try again with the Selected Objects Only unchecked. You will probably have to process the PCB again, possibly it will do it automatically when you have clicked OK after changing the setting. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: Tommy Åkesson [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 11:09 AM To: Protel EDA Forum Subject: [PEDA] printing problem Hello all All of a sudden the power print doesent show anything? It has worked quit perfekt earlier. All layer is selected, pressing Rebuild or Process PCB keep resulting in a blank paper. ( target pcb is selected ) Erase PPC file doesent help, getting same result. Any ideas?? Tommy * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Sv: Isolated Island on PCB
Abd ul-Rahman Lomax wrote: At 02:04 PM 9/1/01 -0400, Mike Reagan wrote: I doubt if you will find a decent board house that is willing to fabricate poygon pours on internal layers.notice I said decent Talk to some manufacturing engineers to find out why this is frowned upon I suspect that this is overstated. Fabricators may not want to produce copper-heavy layers that are asymmetrical in the stackup, because of potential warping. But using a copper pour in lieu of a negative plane (presumably balanced by another copper-heavy layer should not be any additional problem, especially if dead pad removal is used with the photoplot. By the way, I'd really like to know more about the warping allegedly produced by asymmetry. Has anyone actually seen this and verified that the asymmetry was the problem? I have a little trouble imagining a few mils of very ductile copper having enough strength to move the fiberglass around. I've had some 3-layer boards made by good fabricators, and they came out quite flat. I also have had conventional 4-layer boards with pretty well balanced power/ground inner planes that came out literally looking like Pringle's potato chips! Well, maybe I exaggerate just a little, but these boards were so severely warped that if you set them on a table, two edges would stick up about 2! later, we started having real problems with their boards, such that they would fail after soldering, or as much as 4 years later! We had to scrap pretty much everything they made! So, obviously not a high quality shop with tight control over their processes. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] BOM
I was wondering if there is any way to make changes in the .xls spreadsheet BOM and have the part fields updated on the schematic. Nick Cobb * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 2 P99 quirks
Greetings Jon, I have the missing dot syndrome also with the default font , but when I use the san serif font I get dots again. Another thing that may be happening if the text is small is that the plotter sees dots as a zero length draw and some board houses have their plotters or front end editor ignore these as they can clutter up a file with lots of unneeded data on jobs with polygon pours etc. As for the DXF I have not seen that, but you may want to scale the items to size and locate all in the positive quadrant so protel can draw it before creating the DXF. Also generating a DXF with only 4 or 5 place decimal seems better than autocad's default of 16 places (somewhere around a micron is overkill for PCB work). If you need someone to run the data through AutoCAD 2000 or Solidworks I can give it a try for you. Contact me off-line at [EMAIL PROTECTED] or [EMAIL PROTECTED] if I can help. Best regards - Evan Scarborough From: Jon Elson [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Subject: [PEDA] 2 P99 quirks Date: Tue, 04 Sep 2001 14:08:53 -0500 I found two small problems with P99 SP5 recently. 1. When generating Gerbers, the 'dot' on the small letter 'i' is missing, although it is clearly visible in the display. I went back and examined a few existing boards, and the dot is missing on all of them. This shows up clearly on the impoorted Gerber files, as well as on Gerber films produced through photoplotters. (I noteced it because I also use gerber files to produce artwork for instrument panel labels.) 2. I could not correctly import a DXF file created by other software to PCB. I noticed P99 said 'scaling document by 6.4E19' which seemed to be a rather extreme scaling factor! It then said something to the effect of 'document primitives outside workspace' and I got a blank document. (no surprise.) Does anyone know how it decides to do a rescaling, and where it gets the factor from? Thanks, Jon _ Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] None
Rather than putting down a regular keepout, put down a couple of layer-specific keepouts (on the outer layers). Richard Bruer, P.E. Chief Engineer Instrument Division American Magnetics, Inc. 112 Flint Road Oak Ridge, TN 37830 Phone: (865) 482-1056 Fax: (865) 482-5472 mailto:[EMAIL PROTECTED] http://www.americanmagnetics.com -Original Message- From: Evan Scarborough [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 3:55 PM To: Protel EDA Forum Subject: [PEDA] None Greetings all, Is there a way to set up a design rule so that the defined keepout areas only affect the outer layers (other than ignoring or turning off online DRC)? I am routing an 8 layer pcb and the surfaces have rather complicated keepout areas for a metal frame that mounts flush, but internally I have no need to stay out of these areas but I can't seem to convince the DRC that this is so (and I'm not sure I want to see what the autorouter does with this - it'll be bad enough with a 680 pin 1mm pitch BGA). Any help is appreciated! Thanks Best Regards - Evan Scarborough www.e-cadds.com _ Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] None
use the layer specific keepout tracks they work they look like tracks at first until you look at them closely they don't plot with the real tracks Dennis Saputelli Evan Scarborough wrote: Greetings all, Is there a way to set up a design rule so that the defined keepout areas only affect the outer layers (other than ignoring or turning off online DRC)? I am routing an 8 layer pcb and the surfaces have rather complicated keepout areas for a metal frame that mounts flush, but internally I have no need to stay out of these areas but I can't seem to convince the DRC that this is so (and I'm not sure I want to see what the autorouter does with this - it'll be bad enough with a 680 pin 1mm pitch BGA). Any help is appreciated! Thanks Best Regards - Evan Scarborough www.e-cadds.com -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Process Identifiers
Rob, you must have got lucky, go buy a lottery ticket, quick! I still get the stupid edit menu box popping up all the time with Sp6. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 1:30 PM To: Protel EDA Forum Subject: Re: [PEDA] Process Identifiers I noticed on Protel that if you clicked on the menu bar to bring Protel to the top when it was in the background it would bring up the menu edit dialog box. I just tried it on Protel 99SE Service pack 6 and it didn't do it, so I think it may have been fixed. Rob * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating/implementing IC socket PCB decals
What I did was simply have a Schematic Lib component for the socket with no pins, and a corresponding PCB Lib component (footprint) that had the silkscreen I wanted (but no pads, of course). The socket component is placed on the schematic, so it shows up in the BOM; when you synchronize, the footprint shows up on the PCB. I didn't have any DRC problem, although I may not have had component clearance design rules turned on -- seems like that would cause an error. If you use those, you'd probably need a footprint-specific rule for the socket. Dwight. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 9:15 AM Hello Group, I'm new to protel, trying to figure out how to create and implement IC sockets decals/footprints on a PCB layout. Is it as simple as placing an IC and its socket on top of each other -or will that create a design rule violation? In pads, we created a dummy part (without a footprint)that acted as a placekeeper to get the socket part number on the BOM, I was hoping Protel might have a more elegant solution. Any suggestions? Thanks in advance! Charlie Rich Lightwave Electronics * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Process Identifiers
is that nominally a right click type of thing? if so and it is popping up on a left click then you can clear it by holding the right shift key down and right clicking somewhere in space or maybe it's a left click, it hasn't happened lately Dennis Saputelli Brad Velander wrote: Rob, you must have got lucky, go buy a lottery ticket, quick! I still get the stupid edit menu box popping up all the time with Sp6. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 1:30 PM To: Protel EDA Forum Subject: Re: [PEDA] Process Identifiers I noticed on Protel that if you clicked on the menu bar to bring Protel to the top when it was in the background it would bring up the menu edit dialog box. I just tried it on Protel 99SE Service pack 6 and it didn't do it, so I think it may have been fixed. Rob -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] None
Evan Scarborough wrote: Greetings all, Is there a way to set up a design rule so that the defined keepout areas only affect the outer layers (other than ignoring or turning off online DRC)? I am routing an 8 layer pcb and the surfaces have rather complicated keepout areas for a metal frame that mounts flush, but internally I have no need to stay out of these areas but I can't seem to convince the DRC that this is so (and I'm not sure I want to see what the autorouter does with this - it'll be bad enough with a 680 pin 1mm pitch BGA). I think - I haven't done one like this - that you want to make an overall outline for the autorouter using lines that enclose the entire area. Then, you can draw fills in the areas to be kept clear on the outer layers, and set the flag when you double-click on the fills, to make them keep-outs. I'm not exactly sure what the autorouter will do with that info. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 2 P99 quirks
Evan Scarborough wrote: Greetings Jon, I have the missing dot syndrome also with the default font , but when I use the san serif font I get dots again. Ah, thanks. That is a useful workaround, as it might take Altium a while to get this fixed and in the next SP release. Another thing that may be happening if the text is small is that the plotter sees dots as a zero length draw and some board houses have their plotters or front end editor ignore these as they can clutter up a file with lots of unneeded data on jobs with polygon pours etc. No, because it doesn't even show up on the screen in Protel 99SE if you import the Gerber. The size of the characters does not seem to matter, either. As for the DXF I have not seen that, but you may want to scale the items to size and locate all in the positive quadrant so protel can draw it before creating the DXF. Also generating a DXF with only 4 or 5 place decimal seems better than autocad's default of 16 places (somewhere around a micron is overkill for PCB work). If you need someone to run the data through AutoCAD 2000 or Solidworks I can give it a try for you. Oh, I should have mentioned that Protel Adv PCB 2.8 read the same DXF file with no problems at all. So, I read it into 2.8 and saved as a PCB, then read in to Protel 99SE, and it was fine. Very strange! Thanks, Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Process Identifiers
Re: [PEDA] 2 P99 quirks
Jon, your DXF problem is not so strange at all. Because of the complexities of differing DXF versions and different tools generating the DXFs, reading them into Protel can be real hit and miss. For example, I have one DXF that reads perfectly into P98. Reading the same file into P99SE a bunch of features are jostled all around the area and the file makes no sense whatsoever. With DXF always try using ACAD version 12 or at least 13 DXF first. If it doesn't work you can try reading those into P98, doesn't work then you can try V2.8. If all of those fail then I usually try running it through Camtastic before importing into Protel. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: Jon Elson [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 3:10 PM To: Protel EDA Forum Subject: Re: [PEDA] 2 P99 quirks SNIP Oh, I should have mentioned that Protel Adv PCB 2.8 read the same DXF file with no problems at all. So, I read it into 2.8 and saved as a PCB, then read in to Protel 99SE, and it was fine. Very strange! Thanks, Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] BOM
I haven't had much joy in using the internal spreadsheet: it's far too limited and is restricted to the current session only. Instead, I export all part fields to a .dbf file, which I then open with Excel and edit. Finally, I reimport the database. Check out the processes Sch:ExportSchematicToDatabase and Sch:ImportSchematicFromDatabase Be warned, however, that the import function takes a _very_ long time to run, and there's absolutely no visual indication that it is running (Protel appears to hang for the duration). I make good use of my other PC while I'm waiting :-) John Haddy -Original Message- From: Nicholas Cobb [mailto:[EMAIL PROTECTED]] Sent: Wednesday, 5 September 2001 4:54 AM To: Protel EDA Forum Subject: [PEDA] BOM I was wondering if there is any way to make changes in the .xls spreadsheet BOM and have the part fields updated on the schematic. Nick Cobb * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] the letter i in gerber, was 2 P99 quirks
Indeed, with the default font, the dot on the i is missing in gerber. It also disappears in draft display mode. I looked directly at the gerber file; there is no attempt to draw the dot. It is not a case of a zero-length draw. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 3d Solids Modelling pkg
Don Ingram wrote: Hi All, We are looking for a 3D cad pkg for generating components enclosures etc for product design. $7K is a bit steep for us for Autocad or Solidworks given the frequency of use. ( at least for now ) Does anyone have any suggestions on a useful package that lives a bit further down the price scale, but is not a complete dog. I accept that you get what you pay for so we are attempting to locate a happy medium. Intellicad is a free (or cheap) AutoCad clone - available from http://www.cadopia.com, http://www.atlascomputers.ie and other places. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating/implementing IC socket PCB decals
On 04:26 PM 4/09/2001 -0700, Abd ul-Rahman Lomax said: ..snip.. Don't you hate it when you ask How do I ... and someone answers You shouldn't! You are trying to control the BOM from the PCB, but the BOM report from PCB is primitive compared to what can be done from the schematic. The BOM -- or the data from which a BOM is prepared, if one uses Excel or some other spreadsheet to make the actual BOM -- should be generated from the schematic. It is simple to place non-PCB parts on the schematic. I recommend considering the socket as the primary part. The IC, if you want it to be on the PCB, would have a padless footprint. It might have no primitives at all. Such a dummy footprint can be a tad odd in its behavior. I just created one, put a corresponding part on the schematic, and allowed Update to put this empty footprint on the PCB. It ended up outside the workspace. To get it into the workspace, I used the panel to edit it to a location in the workspace. The only things that displayed from this part were the reference designator and comment strings. Those could be hidden. The need to move this part around could have been avoided if I had manually placed it before running Update. Abd ul-Rahman, I agree with your comment that it can be depressing when you are told not to do something rather than how...but... We take the view that any socketed items are actually part of a higher level assembly than the PWA (printed wiring assembly). The PWA includes just the items that are run through the soldering process. Any extra things like ROMs or socketed protection components appear on the next higher level assy parts list. We use the Sch as the primary source for the PWA parts list but this has extra bits added, like the PCB. We usually do not try to include all PWA bits in the Sch, but I am aware that some people do. Doing this would certainly be easier if we had Sch symbol and PCB footprint attributes to prevent them being involved in synchronization and to be ignored during netlist import - as has been discussed recently. (There may need to be two attributes for a Sch symbol. One to prevent it being included in the netlist and internal netlist produced during synchronization. The other, included with the netlist, to prevent the part being included on the PCB if that netlist is imported to a PCB design.) As for the original question, what about: 1) Create socket footprint with all the pins/pads, but a minimum of overlay 2) Create IC footprint which is just overlay/silkscreen (no pins/pads) 3) Position together on PCB carefully 4) Create a union to ensure they move together 5) Pressure Protel to allow correct handling of negative component clearances to allow for overlapping components, I have an yone else want to add a voice Ian Wilson Considered Solutions Pty Ltd mailto:[EMAIL PROTECTED] ABN: 96 088 410 002 5 The Crescent CHATSWOOD 2067 Ph: +61 2 9411 4248 Fax: +61 2 9411 4249 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber clearance violations not found by Protel DRC
At 05:14 PM 9/4/01 -0500, Jon Elson wrote: Don't use measure primitives, use Report Measure Distance. You may have to set the snap grid to a small value, like .01 mil while you are doing the measuring. Reports/Measure Distance is not particularly good at accurately measuring the distance between two primitives because one must visually attempt to locate the edges of the primitives. If it falls on the snap grid, fine, but otherwise Reports/Measure Primitives directly measures the gap between any two primitives. It seems to be quite accurate. Yes, if you are going to use Reports/Measure Distance, you may need to be on a fine grid. Abd ul-Rahman Lomax LOMAX DESIGN ASSOCIATES PCB design, consulting, and training Protel EDA license resales Easthampton, Massachusetts, USA (413) 282-0013, efax (419) 730-4777 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 3d Solids Modelling pkg
acad is $3K SW is $4K at least here in usa i'm afraid that may be as far down the price scale as you can (or maybe should) go acad is pretty long in the tooth IMHO, all things 3D were glommed onto the core sw looks very cool and is inherently 3D and is much more touchy feeley, but either will take an upfront committent of time to get going Dennis Saputelli Don Ingram wrote: Hi All, We are looking for a 3D cad pkg for generating components enclosures etc for product design. $7K is a bit steep for us for Autocad or Solidworks given the frequency of use. ( at least for now ) Does anyone have any suggestions on a useful package that lives a bit further down the price scale, but is not a complete dog. I accept that you get what you pay for so we are attempting to locate a happy medium. Cheers Don P.S Nice to see that at least Chris Mackensen had his 'virtual sense of humour' with him when reading the post. ;-) - Original Message - From: Richard Bruer [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, September 05, 2001 6:11 AM Subject: Re: [PEDA] None Rather than putting down a regular keepout, put down a couple of layer-specific keepouts (on the outer layers). Richard Bruer, P.E. Chief Engineer Instrument Division American Magnetics, Inc. 112 Flint Road Oak Ridge, TN 37830 Phone: (865) 482-1056 Fax: (865) 482-5472 mailto:[EMAIL PROTECTED] http://www.americanmagnetics.com -Original Message- From: Evan Scarborough [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 3:55 PM To: Protel EDA Forum Subject: [PEDA] None Greetings all, Is there a way to set up a design rule so that the defined keepout areas only affect the outer layers (other than ignoring or turning off online DRC)? I am routing an 8 layer pcb and the surfaces have rather complicated keepout areas for a metal frame that mounts flush, but internally I have no need to stay out of these areas but I can't seem to convince the DRC that this is so (and I'm not sure I want to see what the autorouter does with this - it'll be bad enough with a 680 pin 1mm pitch BGA). Any help is appreciated! Thanks Best Regards - Evan Scarborough www.e-cadds.com _ Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 3d Solids Modelling pkg
Thanks for the help guys, I'll have a look at Intellicad. I had a peep at this back in the Visio days. That was AUD$7K. A fair few shekels for a small business. Cheers Don Ingram [EMAIL PROTECTED] Ph +61 7 4954 6074UTC+10hrs Fx +61 7 4954 6222 - Original Message - From: Peter Bennett [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 05, 2001 8:46 AM Subject: Re: [PEDA] 3d Solids Modelling pkg Don Ingram wrote: Hi All, We are looking for a 3D cad pkg for generating components enclosures etc for product design. $7K is a bit steep for us for Autocad or Solidworks given the frequency of use. ( at least for now ) Does anyone have any suggestions on a useful package that lives a bit further down the price scale, but is not a complete dog. I accept that you get what you pay for so we are attempting to locate a happy medium. Intellicad is a free (or cheap) AutoCad clone - available from http://www.cadopia.com, http://www.atlascomputers.ie and other places. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] gerber gen troubles
anyone noticed: when you hit F9 to make gerbers it makes ones that you have previsouly selected but have currently deselected very aggravating and a potential source of trouble scenario 1 (i dbl checked this) made a simple bd, plotted and reviewed in camtastic made some changes and decided not to make a top overlay unchecked top overlay, and there it was made anew anyway, checked file dates etc could not make it stop producing what it first produced yes saved and reopened the .cam file scenario 2 (worse) 4 layer bd w/ paste masks, extra assem note layers, pik place etc every time we replotted it made all new files of all the types including the drill and pik files which were specifically unchecked wiped the folder clean (external copy on hard drive, we never use the cam output in the DDB, what good is that anyway?) tried again with only gerbers checked, no drill, no pik it made them all again of course this has the effect of overwriting the pik files which had plotted differently at another iteration we renamed the PCB (the only PCB in the DDB) and ran the F9 it properly prompted for a target board since the former one no longer existed selected the board and it then made TWO sets of Gerbers with the both old name and the new name! 47 files in all, all made in one pass, all in the same folder more bush league behavoir IMHO Dennis Saputelli -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] gerber gen troubles
Dennis, I think that something is hooped in your Protel. I do the sort of thing that you are talking about but have not seen the issue you have. Oh, hold it,stop the presses. Dennis, I believe that you may find that it is not regenerating the all the Gerbers. Could it just be re-exporting with a new date and time stamp, the previous Gerbers when it exports the newly generated Gerbers? Are you looking at the date and time stamps only or have you viewed the Gerbers and noted changes? I bet the export facility, exports everything in the internal DDB directory, everytime it is run. Rename the old Gerber files within the DDB directory and then do a test again, I bet it exports the old DDB cam files with their new name when you generate a new set of cam files. I am thinking that the export function just blindly dumps all the files contained in the CAM directory out to the external directory and the OS puts a new date and timestamp on them. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 5:14 PM To: Protel EDA Forum Subject: Re: [PEDA] gerber gen troubles anyone noticed: when you hit F9 to make gerbers it makes ones that you have previsouly selected but have currently deselected very aggravating and a potential source of trouble scenario 1 (i dbl checked this) made a simple bd, plotted and reviewed in camtastic made some changes and decided not to make a top overlay unchecked top overlay, and there it was made anew anyway, checked file dates etc could not make it stop producing what it first produced yes saved and reopened the .cam file scenario 2 (worse) 4 layer bd w/ paste masks, extra assem note layers, pik place etc every time we replotted it made all new files of all the types including the drill and pik files which were specifically unchecked wiped the folder clean (external copy on hard drive, we never use the cam output in the DDB, what good is that anyway?) tried again with only gerbers checked, no drill, no pik it made them all again of course this has the effect of overwriting the pik files which had plotted differently at another iteration we renamed the PCB (the only PCB in the DDB) and ran the F9 it properly prompted for a target board since the former one no longer existed selected the board and it then made TWO sets of Gerbers with the both old name and the new name! 47 files in all, all made in one pass, all in the same folder more bush league behavoir IMHO Dennis Saputelli * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Creating/implementing IC socket PCB decals
Ian, I can see your points; but here's why I take the other approach of having the IC w/pins pads, and the socket having just an overlay: - Sometimes we only have the socket for prototype, then remove it; our method makes it a simple change to remove the socket. - We can have a single library component for a particular socket (e.g., DIP-8) and use it for any matching IC. - I'd rather not have multiple part-ids referring to the same manufacturer's part -- our rather simplistic parts-management system (Access and various macros/reports) wouldn't handle that nicely it'd probably confuse our parts purchaser (she's new at this -- we ALL are!). I think the choice of method in any particular instance may depend as much on existing BOM/parts management scheme as anything else; or on the specific situation (e.g., a 'temporary' socket vs. a permanent one). Good idea about creating the union -- something I usually forget to do. Dwight Harm Trax Softworks, Inc. -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 04, 2001 3:57 PM snip We take the view that any socketed items are actually part of a higher level assembly than the PWA (printed wiring assembly). The PWA includes just the items that are run through the soldering process. Any extra things like ROMs or socketed protection components appear on the next higher level assy parts list. We use the Sch as the primary source for the PWA parts list but this has extra bits added, like the PCB. We usually do not try to include all PWA bits in the Sch, but I am aware that some people do. Doing this would certainly be easier if we had Sch symbol and PCB footprint attributes to prevent them being involved in synchronization and to be ignored during netlist import - as has been discussed recently. (There may need to be two attributes for a Sch symbol. One to prevent it being included in the netlist and internal netlist produced during synchronization. The other, included with the netlist, to prevent the part being included on the PCB if that netlist is imported to a PCB design.) As for the original question, what about: 1) Create socket footprint with all the pins/pads, but a minimum of overlay 2) Create IC footprint which is just overlay/silkscreen (no pins/pads) 3) Position together on PCB carefully 4) Create a union to ensure they move together 5) Pressure Protel to allow correct handling of negative component clearances to allow for overlapping components, I have an yone else want to add a voice Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
