[PATCH v2 23/37] clk: rockchip: rk3576: Use correct clock register for CLK_SARADC

[Jonas Karlman]

Parent and divider fields for CLK_SARADC are located in CLKSEL_CON58 not
in CLKSEL_CON59. Change to use correct CLKSEL_CON for the CLK_SARADC
clock.

Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
Changes in v2:
- Split from "rk3576: Fix trivial clock configuration errors"
- Add fixes tag
---
 drivers/clk/rockchip/clk_rk3576.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3576.c 
b/drivers/clk/rockchip/clk_rk3576.c
index 04b0f6b13ed3..17f9b01ff0c8 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -691,7 +691,7 @@ static ulong rk3576_adc_set_clk(struct rk3576_clk_priv 
*priv,
                } else {
                        src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
                        assert(src_clk_div - 1 <= 255);
-                       rk_clrsetreg(&cru->clksel_con[59],
+                       rk_clrsetreg(&cru->clksel_con[58],
                                     CLK_SARADC_SEL_MASK |
                                     CLK_SARADC_DIV_MASK,
                                     (CLK_SARADC_SEL_GPLL <<
-- 
2.55.0