Setting rate of the VOP clocks never changes the clock parent and the
old divisor value is OR with new divisor value due to incorrect args
being passed to rk_clrsetreg() call.
Use selector and divisor masks and values correctly in rk_clrsetreg()
call to ensure VOP clocks are configured as expected.
Video is not supported for this SoC, so nothing is likely going to try
to change rate of VOP clocks until video support have been implemented.
Fixes: 5a7a856b132f ("clk: rockchip: Add support for RK3528")
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
---
Changes in v2:
- Split from "rk3528: Fix trivial clock configuration errors"
- Add fixes tag
- Collect r-b tag
---
drivers/clk/rockchip/clk_rk3528.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3528.c
b/drivers/clk/rockchip/clk_rk3528.c
index 812710872729..82a1b6e85b5b 100644
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -1097,7 +1097,7 @@ static ulong rk3528_dclk_vop_set_clk(struct
rk3528_clk_priv *priv,
}
div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask;
- rk_clrsetreg(&cru->clksel_con[id], sel, div);
+ rk_clrsetreg(&cru->clksel_con[id], sel_mask | div_mask, sel | div);
return rk3528_dclk_vop_get_clk(priv, clk_id);
}
--
2.55.0
