[gem5-users] DVFS in vanilla linux kernels
Hi all, I've been toying with the DVFS example in https://www.gem5.org/documentation/learning_gem5/part2/arm_dvfs_support/ with a v21 distro of GEM5. I got it working despite some small version variations... This is the command I use to launch the simulation: ./build/ARM/gem5.opt \ ./configs/example/arm/fs_bigLITTLE_DVFS.py \ --cpu-type=atomic \ --big-cpu-clock 2GHz 1GHz 500MHz \ --little-cpu-clock 1GHz 500MHz 250MHz \ --big-cpu-voltage 1.0V 0.5V 0.25V \ --little-cpu-voltage 1.0V 0.5V 0.25V \ --dvfs \ --bootloader=./common/boot.arm64 \ --kernel=./common/kernel_test/vmlinux \ --disk=./common/aarch64-ubuntu-trusty-headless.img \ --bootscript=./common/bash.rcS Where fs_bigLITTLE_DVFS.py was modified following the guide; boot.arm64 and aarch64-ubuntu-trusty-headless.img were obtained from the gem5 guest binaries repo ( https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries); bash.rcS is a simple command line application; and vmlinux was obtained from https://gem5.googlesource.com/arm/linux and compiled with make ARCH=arm64 CROSS_COMPILE=aarch64-none-elf- gem5_defconfigmake ARCH=arm64 CROSS_COMPILE=aarch64-none-elf- -j $(nproc) However, the latest linux version in googlesource is 4.15 and for different reasons I'm interested in the newer versions of the kernel. So, naturally I obtained the vanilla linux kernel from Linus' repository and compiled it with make ARCH=arm64 CROSS_COMPILE=aarch64-none-elf- defconfigmake ARCH=arm64 CROSS_COMPILE=aarch64-none-elf- -j $(nproc) I've tested the latest version (5.19) and even checked out the v4.14 and v4.15 branches; however, while the simulation works, the cpufreq driver is nowhere to be found. I've also tested using the pre-compiled kernel from the guest binaries (v4.15) and it also works. Finally, I tested building the kernel from the googlesource using different configurations (gem5_defconfig, oldconfig, defconfig) and only defconfig fails to generate the cpufreq drivers. Any ideas as to what I'm missing or some insights on what needs to be changed to defconfig in the vanilla kernels? Best, ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Dvfs-gem5
Hi,I'm working on gem5 .my question1) I could run mcpat but I didn't know how to compute power and performance from resultmy question2)I need to run DVFS on full-system-arm . I fount this site"http://www.m5sim.org/Running_gem5"and this paprer"Introducing DVFS-Management in a Full-SystemSimulator":1) I read that paper but didn't undrestand how run dvfs in according to site paper 2) I could run what that site said and I could set clock and voltage but couldn't set Frequency I confused how to run dvfs ( clock ,voltage and frequency).please help and guide me how to run DVFS on full-system-arm and recommend side ,document or a person worked on it.Best Regards.___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] DVFS-GEm5
Hi, I'm working on gem5 . my question1) I could run mcpat but I didn't know how to compute power and performance from result my question2) I need to run DVFS on full-system-arm . I fount this site" http://www.m5sim.org/Running_gem5"and this paprer"Introducing DVFS-Management in a Full-System Simulator": 1) I read that paper but didn't undrestand how run dvfs in according to site paper 2) I could run what that site said and I could set clock and voltage but couldn't set Frequency I confused how to run dvfs ( clock ,voltage and frequency). please help and guide me how to run DVFS on full-system-arm and recommend side ,document or a person worked on it. Best Regards. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
Re: [gem5-users] DVFS
Hi, > i m getting the output as clock = 1 1 3 4 i can't understand what it means? Those numbers represent "ticks". Ticks are the smallest time unit gem5 understands and 1 tick is equal to 1 picosecond [1]. As I understand from this config, you have 4 different clocks in your setup which are 1000GHz, 1000GHz, 333GHz and 250GHz. Cheers Serhat [1] http://gem5.org/Frequently_Asked_Questions#What_does_.22Global_frequency_set_at_1_ticks_per_second.22_refer_to.3F From: gem5-users [gem5-users-boun...@gem5.org] on behalf of nevethetha ganesan [nevethetha2...@gmail.com] Sent: 26 February 2019 05:36 To: gem5-users@gem5.org Subject: [gem5-users] DVFS Hello, I tried to enable dvfs in gem5 simulator. I defined four voltages for four clusters. In the config.ini file I am getting the output as dvfs enabled. But in the clockDomain attribute in the config.ini file i m getting the output as clock = 1 1 3 4 i can't understand what it means? Kindly help me!! ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] DVFS
Hello, I tried to enable dvfs in gem5 simulator. I defined four voltages for four clusters. In the config.ini file I am getting the output as dvfs enabled. But in the clockDomain attribute in the config.ini file i m getting the output as clock = 1 1 3 4 i can't understand what it means? Kindly help me!! ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] DVFS support in Garnet
Hello Gem5 Team, I need to implement DVFS support in Garnet. Can anyone suggest a possible way? Thanks, Monobrata ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS with self defined policies on gem5
Hi Andreas, I was looking into the option of probes. I wanted to first test the probes provided by SimpleTrace. Looking at the code it looks like if I run the gem5 command with --debug-flags=SimpleTrace, I should see the DPRINTFs given in the listener functions right. But I am not getting that. Do I need to do something else. It seems that SimpleTrace class is not instantiated anywhere, do I have to do that to make it run? Thanks for your help :) On Wed, Apr 15, 2015 at 6:28 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi all, The nice and clean option would be to use add an architecturally visible performance counter read from the DVFS governor (in software). The hackish option is to change the clock speed behind the back of the OS, by having the DVFSHandler object change the clocks based on e.g. a probe point or similar. Andreas From: Nimish Girdhar nimi...@tamu.edu Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Wednesday, 15 April 2015 20:04 To: gem5 users mailing list gem5-users@gem5.org Subject: Re: [gem5-users] DVFS with self defined policies on gem5 Okay.Actually I am making the decision of what frequency which core has to run, inside the cpu... So I guess I have to somehow communicate this to the dvfs handler which doesn't look so clean Is there any other way around or hack anybody has done?? On Apr 15, 2015 10:14 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, Setting the required frequency in /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed should not be in gem5 sources files. It can be done in a program (written in C, shell script or any other language) and running under Linux in FS mode. Regards Yahia 2015-04-15 16:55 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Thanks Yahia for sharing that. Can you explain a bit more as I don't have much experience with that. Let's say I have some algo to decide the cpu freq in gem5 SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that freq from here?? Thanks, On Apr 15, 2015 2:53 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, You have to enable userspace governor in your kernel then you can scale the CPU frequency by setting /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should work. Regards. Yahia 2015-04-15 4:00 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps, the kernel will be the one who decides the performance levels of the cores at different point of time. But in my case I want to decide the levels based on some counters as mentioned above. Has anybody tried anything similar to that? I want to know how can I access and update the dvfs handler registers from within the cpu src code. Any help will be appreciated. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS with self defined policies on gem5
Thanks for the solution AndreasI will try that. On Apr 15, 2015 6:29 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi all, The nice and clean option would be to use add an architecturally visible performance counter read from the DVFS governor (in software). The hackish option is to change the clock speed behind the back of the OS, by having the DVFSHandler object change the clocks based on e.g. a probe point or similar. Andreas From: Nimish Girdhar nimi...@tamu.edu Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Wednesday, 15 April 2015 20:04 To: gem5 users mailing list gem5-users@gem5.org Subject: Re: [gem5-users] DVFS with self defined policies on gem5 Okay.Actually I am making the decision of what frequency which core has to run, inside the cpu... So I guess I have to somehow communicate this to the dvfs handler which doesn't look so clean Is there any other way around or hack anybody has done?? On Apr 15, 2015 10:14 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, Setting the required frequency in /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed should not be in gem5 sources files. It can be done in a program (written in C, shell script or any other language) and running under Linux in FS mode. Regards Yahia 2015-04-15 16:55 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Thanks Yahia for sharing that. Can you explain a bit more as I don't have much experience with that. Let's say I have some algo to decide the cpu freq in gem5 SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that freq from here?? Thanks, On Apr 15, 2015 2:53 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, You have to enable userspace governor in your kernel then you can scale the CPU frequency by setting /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should work. Regards. Yahia 2015-04-15 4:00 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps, the kernel will be the one who decides the performance levels of the cores at different point of time. But in my case I want to decide the levels based on some counters as mentioned above. Has anybody tried anything similar to that? I want to know how can I access and update the dvfs handler registers from within the cpu src code. Any help will be appreciated. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS with self defined policies on gem5
Hi Andreas, The nice and clean option would be to use add an architecturally visible performance counter read from the DVFS governor (in software). Is there any example of any such counter which I can look at to get an idea how this will be done?? On Apr 16, 2015 10:43 AM, Nimish Girdhar nimi...@tamu.edu wrote: Thanks for the solution AndreasI will try that. On Apr 15, 2015 6:29 PM, Andreas Hansson andreas.hans...@arm.com wrote: Hi all, The nice and clean option would be to use add an architecturally visible performance counter read from the DVFS governor (in software). The hackish option is to change the clock speed behind the back of the OS, by having the DVFSHandler object change the clocks based on e.g. a probe point or similar. Andreas From: Nimish Girdhar nimi...@tamu.edu Reply-To: gem5 users mailing list gem5-users@gem5.org Date: Wednesday, 15 April 2015 20:04 To: gem5 users mailing list gem5-users@gem5.org Subject: Re: [gem5-users] DVFS with self defined policies on gem5 Okay.Actually I am making the decision of what frequency which core has to run, inside the cpu... So I guess I have to somehow communicate this to the dvfs handler which doesn't look so clean Is there any other way around or hack anybody has done?? On Apr 15, 2015 10:14 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, Setting the required frequency in /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed should not be in gem5 sources files. It can be done in a program (written in C, shell script or any other language) and running under Linux in FS mode. Regards Yahia 2015-04-15 16:55 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Thanks Yahia for sharing that. Can you explain a bit more as I don't have much experience with that. Let's say I have some algo to decide the cpu freq in gem5 SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that freq from here?? Thanks, On Apr 15, 2015 2:53 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, You have to enable userspace governor in your kernel then you can scale the CPU frequency by setting /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should work. Regards. Yahia 2015-04-15 4:00 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps, the kernel will be the one who decides the performance levels of the cores at different point of time. But in my case I want to decide the levels based on some counters as mentioned above. Has anybody tried anything similar to that? I want to know how can I access and update the dvfs handler registers from within the cpu src code. Any help will be appreciated. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS with self defined policies on gem5
Hi Nimish,
as Andreas pointed out, there are two possible ways for this.
If you want to simulate a smart *software* governor, then you can access
the PMU (see code in src/arch/arm/{pmu.cc,pmu.hh,ArmPMU.py}). The
interface to that should be through the normal PMU functions, and the
counters therefore should be available through the perf toolkit, PAPI,
and the respective ARM coprocessor interface (gory details here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Bcgddibf.html#
)
Directly evaluating the stats inside gem5 and then changing the
frequency of the right ClockDomain without OS / simulated system
involvement, can either be a quick approximation of such a thing, or
modelling a *hardware* DVFS controller.
Hope that helps.
--
Thanks,
Stephan
Stephan Diestelhorst
Staff Engineer
ARM Research - Systems
+44 (0)1223 405662
On Thursday 16 April 2015 16:49:03 Nimish Girdhar wrote:
Hi Andreas,
The nice and clean option would be to use add an architecturally visible
performance counter read from the DVFS governor (in software).
Is there any example of any such counter which I can look at to get an idea
how this will be done??
On Apr 16, 2015 10:43 AM, Nimish Girdhar
nimi...@tamu.edumailto:nimi...@tamu.edu wrote:
Thanks for the solution AndreasI will try that.
On Apr 15, 2015 6:29 PM, Andreas Hansson
andreas.hans...@arm.commailto:andreas.hans...@arm.com wrote:
Hi all,
The nice and clean option would be to use add an architecturally visible
performance counter read from the DVFS governor (in software).
The hackish option is to change the clock speed behind the back of the OS,
by having the DVFSHandler object change the clocks based on e.g. a probe
point or similar.
Andreas
From: Nimish Girdhar nimi...@tamu.edumailto:nimi...@tamu.edu
Reply-To: gem5 users mailing list
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Date: Wednesday, 15
April 2015 20:04
To: gem5 users mailing list
gem5-users@gem5.orgmailto:gem5-users@gem5.org
Subject: Re:
[gem5-users] DVFS with self defined policies on gem5
Okay.Actually I am making the decision of what frequency which core has
to run, inside the cpu...
So I guess I have to somehow communicate this to the dvfs handler which
doesn't look so clean
Is there any other way around or hack anybody has done??
On Apr 15, 2015 10:14 AM, Yahia Benmoussa
yahia.benmou...@gmail.commailto:yahia.benmou...@gmail.com wrote:
Hello,
Setting the required frequency in
/sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed should not be in gem5
sources files. It can be done in a program (written in C, shell script or
any other language)
and running under Linux in FS mode.
Regards
Yahia
2015-04-15 16:55 GMT+02:00 Nimish Girdhar
nimi...@tamu.edumailto:nimi...@tamu.edu:
Thanks Yahia for sharing that.
Can you explain a bit more as I don't have much experience with that.
Let's say I have some algo to decide the cpu freq in gem5
SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that
freq from here??
Thanks,
On Apr 15, 2015 2:53 AM, Yahia Benmoussa
yahia.benmou...@gmail.commailto:yahia.benmou...@gmail.com wrote:
Hello,
You have to enable userspace governor in your kernel then you can scale the
CPU frequency by setting
/sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should
work.
Regards.
Yahia
2015-04-15 4:00 GMT+02:00 Nimish Girdhar
nimi...@tamu.edumailto:nimi...@tamu.edu:
Hello all,
I am working on a project where I have to use DVFS to change the frequency
of cores based on my evaluation of some counters that I inserted in the
gem5 o3 cpu src code.
I followed the guidelines given on
http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS .
But with these
steps, the kernel will be the one who decides the performance levels of the
cores at different point of time. But in my case I want to decide the
levels based on some counters as mentioned above.
Has anybody tried anything similar to that? I want to know how can I access
and update the dvfs handler registers from within the cpu src code.
Any help will be appreciated.
Thanks,
--
Warm regards
Nimish Girdhar
Department of Electrical and Computer Engineering
Texas AM University
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Re: [gem5-users] DVFS with self defined policies on gem5
Thanks Yahia for sharing that. Can you explain a bit more as I don't have much experience with that. Let's say I have some algo to decide the cpu freq in gem5 SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that freq from here?? Thanks, On Apr 15, 2015 2:53 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, You have to enable userspace governor in your kernel then you can scale the CPU frequency by setting /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should work. Regards. Yahia 2015-04-15 4:00 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps, the kernel will be the one who decides the performance levels of the cores at different point of time. But in my case I want to decide the levels based on some counters as mentioned above. Has anybody tried anything similar to that? I want to know how can I access and update the dvfs handler registers from within the cpu src code. Any help will be appreciated. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS with self defined policies on gem5
Hello, Setting the required frequency in /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed should not be in gem5 sources files. It can be done in a program (written in C, shell script or any other language) and running under Linux in FS mode. Regards Yahia 2015-04-15 16:55 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Thanks Yahia for sharing that. Can you explain a bit more as I don't have much experience with that. Let's say I have some algo to decide the cpu freq in gem5 SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that freq from here?? Thanks, On Apr 15, 2015 2:53 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, You have to enable userspace governor in your kernel then you can scale the CPU frequency by setting /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should work. Regards. Yahia 2015-04-15 4:00 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps, the kernel will be the one who decides the performance levels of the cores at different point of time. But in my case I want to decide the levels based on some counters as mentioned above. Has anybody tried anything similar to that? I want to know how can I access and update the dvfs handler registers from within the cpu src code. Any help will be appreciated. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS with self defined policies on gem5
Okay.Actually I am making the decision of what frequency which core has to run, inside the cpu... So I guess I have to somehow communicate this to the dvfs handler which doesn't look so clean Is there any other way around or hack anybody has done?? On Apr 15, 2015 10:14 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, Setting the required frequency in /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed should not be in gem5 sources files. It can be done in a program (written in C, shell script or any other language) and running under Linux in FS mode. Regards Yahia 2015-04-15 16:55 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Thanks Yahia for sharing that. Can you explain a bit more as I don't have much experience with that. Let's say I have some algo to decide the cpu freq in gem5 SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that freq from here?? Thanks, On Apr 15, 2015 2:53 AM, Yahia Benmoussa yahia.benmou...@gmail.com wrote: Hello, You have to enable userspace governor in your kernel then you can scale the CPU frequency by setting /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should work. Regards. Yahia 2015-04-15 4:00 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps, the kernel will be the one who decides the performance levels of the cores at different point of time. But in my case I want to decide the levels based on some counters as mentioned above. Has anybody tried anything similar to that? I want to know how can I access and update the dvfs handler registers from within the cpu src code. Any help will be appreciated. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS with self defined policies on gem5
Hi all, The nice and clean option would be to use add an architecturally visible performance counter read from the DVFS governor (in software). The hackish option is to change the clock speed behind the back of the OS, by having the DVFSHandler object change the clocks based on e.g. a probe point or similar. Andreas From: Nimish Girdhar nimi...@tamu.edumailto:nimi...@tamu.edu Reply-To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Date: Wednesday, 15 April 2015 20:04 To: gem5 users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org Subject: Re: [gem5-users] DVFS with self defined policies on gem5 Okay.Actually I am making the decision of what frequency which core has to run, inside the cpu... So I guess I have to somehow communicate this to the dvfs handler which doesn't look so clean Is there any other way around or hack anybody has done?? On Apr 15, 2015 10:14 AM, Yahia Benmoussa yahia.benmou...@gmail.commailto:yahia.benmou...@gmail.com wrote: Hello, Setting the required frequency in /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed should not be in gem5 sources files. It can be done in a program (written in C, shell script or any other language) and running under Linux in FS mode. Regards Yahia 2015-04-15 16:55 GMT+02:00 Nimish Girdhar nimi...@tamu.edumailto:nimi...@tamu.edu: Thanks Yahia for sharing that. Can you explain a bit more as I don't have much experience with that. Let's say I have some algo to decide the cpu freq in gem5 SRC/CPU/O3/commit_impl.hh... How can I set the file you mentioned to that freq from here?? Thanks, On Apr 15, 2015 2:53 AM, Yahia Benmoussa yahia.benmou...@gmail.commailto:yahia.benmou...@gmail.com wrote: Hello, You have to enable userspace governor in your kernel then you can scale the CPU frequency by setting /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should work. Regards. Yahia 2015-04-15 4:00 GMT+02:00 Nimish Girdhar nimi...@tamu.edumailto:nimi...@tamu.edu: Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps, the kernel will be the one who decides the performance levels of the cores at different point of time. But in my case I want to decide the levels based on some counters as mentioned above. Has anybody tried anything similar to that? I want to know how can I access and update the dvfs handler registers from within the cpu src code. Any help will be appreciated. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.orgmailto:gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS with self defined policies on gem5
Hello, You have to enable userspace governor in your kernel then you can scale the CPU frequency by setting /sys/devices/system/cpu/cpu*/cpufreq/scaling_setspeed file. It should work. Regards. Yahia 2015-04-15 4:00 GMT+02:00 Nimish Girdhar nimi...@tamu.edu: Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps, the kernel will be the one who decides the performance levels of the cores at different point of time. But in my case I want to decide the levels based on some counters as mentioned above. Has anybody tried anything similar to that? I want to know how can I access and update the dvfs handler registers from within the cpu src code. Any help will be appreciated. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] DVFS with self defined policies on gem5
Hello all, I am working on a project where I have to use DVFS to change the frequency of cores based on my evaluation of some counters that I inserted in the gem5 o3 cpu src code. I followed the guidelines given on http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS . But with these steps, the kernel will be the one who decides the performance levels of the cores at different point of time. But in my case I want to decide the levels based on some counters as mentioned above. Has anybody tried anything similar to that? I want to know how can I access and update the dvfs handler registers from within the cpu src code. Any help will be appreciated. Thanks, -- Warm regards Nimish Girdhar Department of Electrical and Computer Engineering Texas AM University ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS enabled with ARM detailed CPU
Hi Giorgos, Am Samstag, 4. April 2015, 20:18:26 schrieb Giorgos Kopanas: I am trying to make Gem5 work with the DVFS as explained in the website. While running in Atomic Simple it is working as intended but when I change the cpu type to arm_detailed the simulation crushes during boot. The message that is shown is the following: gem5.opt: build/ARM/mem/cache/cache_impl.hh:633: bool CacheTagStore::recvTimingReq(PacketPtr) [with TagStore = LRU; PacketPtr = Packet*]: Assertion `!pkt-req-isUncacheable()' failed. Has anyone actually ever booted the DVFS enabled kernel that is proposed in the website with arm_detailed cpu type or is it not supported? This should work, we certainly use detailed mode together with DVFS. There has been quite a bit of work and flux on uncacheable things lately, are you running this with the most recent (non-stable) gem5? If yes, it might also be worthwhile to get try out some of the uncacheable patches on RB (search for uncacheable there), and / or produce some additional information to get this debugged. Thanks, Stephan -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS enabled with ARM detailed CPU
Hello, I was running through the developing branch. The stable version works. Thank you, Giorgos 2015-04-06 16:46 GMT+03:00 Stephan Diestelhorst stephan.diestelho...@arm.com: Hi Giorgos, Am Samstag, 4. April 2015, 20:18:26 schrieb Giorgos Kopanas: I am trying to make Gem5 work with the DVFS as explained in the website. While running in Atomic Simple it is working as intended but when I change the cpu type to arm_detailed the simulation crushes during boot. The message that is shown is the following: gem5.opt: build/ARM/mem/cache/cache_impl.hh:633: bool CacheTagStore::recvTimingReq(PacketPtr) [with TagStore = LRU; PacketPtr = Packet*]: Assertion `!pkt-req-isUncacheable()' failed. Has anyone actually ever booted the DVFS enabled kernel that is proposed in the website with arm_detailed cpu type or is it not supported? This should work, we certainly use detailed mode together with DVFS. There has been quite a bit of work and flux on uncacheable things lately, are you running this with the most recent (non-stable) gem5? If yes, it might also be worthwhile to get try out some of the uncacheable patches on RB (search for uncacheable there), and / or produce some additional information to get this debugged. Thanks, Stephan -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS enabled with ARM detailed CPU
Hi On Monday 06 April 2015 15:55:01 Giorgos Kopanas wrote: I was running through the developing branch. The stable version works. Great news; the volatility regarding uncacheable in the main branch should hopefully settle soon (with the patches mentioned). Thanks, Stephan -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] DVFS enabled with ARM detailed CPU
Dear All, I am trying to make Gem5 work with the DVFS as explained in the website. While running in Atomic Simple it is working as intended but when I change the cpu type to arm_detailed the simulation crushes during boot. The message that is shown is the following: gem5.opt: build/ARM/mem/cache/cache_impl.hh:633: bool CacheTagStore::recvTimingReq(PacketPtr) [with TagStore = LRU; PacketPtr = Packet*]: Assertion `!pkt-req-isUncacheable()' failed. Has anyone actually ever booted the DVFS enabled kernel that is proposed in the website with arm_detailed cpu type or is it not supported? Sincerely, Giorgos Kopanas ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] DVFS in SE mode
Dear users I am using SE mode to simulate my project. There are some reasons that I could not use FS simulation mode. Is there a way to run DVFS during the simulation time? I searched the mailing list, but I could not find any solution. Thanks, Hadi ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS does not seem to work on ARM full system simulation
Hi Rahul, I followed the instructions given here http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS, and was able to run and test DVFS. You may also want to read a similar question http://comments.gmane.org/gmane.comp.emulators.m5.users/17881 that I had posed earlier. Hope this helps. On Thu, Dec 25, 2014 at 2:31 AM, rahul shrivastava via gem5-users gem5-users@gem5.org wrote: Hi, I performing 4 core ARM full system simulation to test dvfs functionality. However, when I login through m5term and check for cpufreq governor, the directory doesn't exist. Here is the output for cpu3 *root@gem5sim:/sys/devices/system/cpu/cpu3# lsonline subsystem topology uevent* Ideally, there should be a cpufreq for every core which provides the interface to change the frequency of the core, which is missing Could you please let me know if there is some other way to change the frequency of the cores Regards Rahul ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] DVFS does not seem to work on ARM full system simulation
Hi, I performing 4 core ARM full system simulation to test dvfs functionality. However, when I login through m5term and check for cpufreq governor, the directory doesn't exist. Here is the output for cpu3 *root@gem5sim:/sys/devices/system/cpu/cpu3# lsonline subsystem topology uevent* Ideally, there should be a cpufreq for every core which provides the interface to change the frequency of the core, which is missing Could you please let me know if there is some other way to change the frequency of the cores Regards Rahul ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] DVFS and energy controllers
Hi, I followed the sample code provided in commit 6bbb7ae309 to set up DVFS. This got rid of the warning in Gem5 warn: Existing EnergyCtrl, but no enabled DVFSHandler found. However, the kernel still reports saying [0.366079] gem5_energy_ctrl_mc: gem5_mc_init: No energy controller found Is there any documentation available on how to get DVFS working and perhaps the cpufreq module working? Regards Guru ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS and energy controllers
Just to follow up, I modified config/example/fs.py to contain the following test_sys.cpu_clk_domain = SrcClockDomain() test_sys.cpu_clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz'] test_sys.cpu_clk_domain.domain_id = 0 test_sys.cpu_clk_domain.voltage_domain = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V']) test_sys.dvfs_handler.domains = [test_sys.cpu_clk_domain] test_sys.dvfs_handler.enable = True On Fri, Dec 5, 2014 at 11:42 AM, Guru Prasad gurup...@buffalo.edu wrote: Hi, I followed the sample code provided in commit 6bbb7ae309 to set up DVFS. This got rid of the warning in Gem5 warn: Existing EnergyCtrl, but no enabled DVFSHandler found. However, the kernel still reports saying [0.366079] gem5_energy_ctrl_mc: gem5_mc_init: No energy controller found Is there any documentation available on how to get DVFS working and perhaps the cpufreq module working? Regards Guru ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS and energy controllers
Hi Guru, On Friday 05 December 2014 16:42:52 Guru Prasad via gem5-users wrote: I followed the sample code provided in commit 6bbb7ae309 to set up DVFS. Great! This got rid of the warning in Gem5 warn: Existing EnergyCtrl, but no enabled DVFSHandler found. However, the kernel still reports saying [0.366079] gem5_energy_ctrl_mc: gem5_mc_init: No energy controller found Is there any documentation available on how to get DVFS working and perhaps the cpufreq module working? I have a quick write-up here: http://gem5.org/Running_gem5#Experimenting_with_DVFS Please let me / the list know if you have further questions, and also feel free to adapt the wiki. -- Thanks, Stephan Stephan Diestelhorst Staff Engineer ARM RD Systems -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS and energy controllers
Stephan, Thanks. It works perfectly. Apologize for missing it in the documentation. Regards Guru On Fri, Dec 5, 2014 at 11:55 AM, Stephan Diestelhorst via gem5-users gem5-users@gem5.org wrote: Hi Guru, On Friday 05 December 2014 16:42:52 Guru Prasad via gem5-users wrote: I followed the sample code provided in commit 6bbb7ae309 to set up DVFS. Great! This got rid of the warning in Gem5 warn: Existing EnergyCtrl, but no enabled DVFSHandler found. However, the kernel still reports saying [0.366079] gem5_energy_ctrl_mc: gem5_mc_init: No energy controller found Is there any documentation available on how to get DVFS working and perhaps the cpufreq module working? I have a quick write-up here: http://gem5.org/Running_gem5#Experimenting_with_DVFS Please let me / the list know if you have further questions, and also feel free to adapt the wiki. -- Thanks, Stephan Stephan Diestelhorst Staff Engineer ARM RD Systems -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS in x86 arch | A valid RSDP was not found
On 09/18/2014 12:02 PM, Lokesh Jindal wrote: RSDP PTR in x86 FS simulation : A valid RSDP was not found Hello, I am very new to gem5. I am trying to run x86 FS simulation with a linux kernel(v2.6.28.4)compiled with ACPI enabled. I am seeing the following error: /ACPI Error (tbxfroot-0219): A valid RSDP was not found [20080926]/ The kernel is not able to locate the RSD PTR signature. I can see some RSDP-related code in /src/arch/x86/bios directory in gem5, which I am guessing takes care of setting up ACPI desriptor tables. Could someone explain me some details here: 1. What does linux kernel expect from Gem5 related to ACPI set up and init? 2. What kind of ACPI related set up (including taking care of RSDP desriptor tables) is actually done by Gem5? 3. Most importantly, how to fix the above mentioned error? I have attached log files for reference and the .config file I used while compiling linux kernel. Pardon me if I have explained something unclearly/incorrectly. Thanks and Regards Lokesh Jindal. UW-Madison. Hey, Could anyone help me out here? My ultimate aim is to enable support for DVFS for linux kernel in x86 arch on gem5. And this is the first step. Kindly provide some insight. Thanks Lokesh Jindal Grad student, UW-Madison ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS in Quiesce states
Srini, kudos for making per-core DVFS work! A quick head¹s up: we are also working on (per-core) DVFS support and are just polishing those patches for consumption, should hopefully have them ready within a week or two. On the main question, I have no hard opinion, but wonder what the reasoning is for either. The OS should cope with the core being woken up spuriously, maybe check the run queues and go back to sleep if nothing has happened. Likewise, on the HW side, it depends. Some systems might do DVFS of a remote core, some need to run code on the core that is to be DVFS-ed (obviously requiring wakeup). HTH, Stephan On 23.03.2014 14:26, Srinivasan Narayanamoorthy narayanam...@wisc.edu wrote: Hi all, I have implemented a per-core DVFS in gem5, mimicking an on-demand governer. My question here is if the cpu is in quiesce state(TC is suspended) while DVFS routine is scheduled, should I wakeup() the suspended TC?. Similarly while doing a drain and switching to a different cpu model, should the suspended TC be explicitly woken up? I am doing both in my implementation and nothing has broken so far. But am wondering if it is actually done that way. Thanks Srini ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS in Quiesce states
Hi Stephan, Thanks for the response. I think I understand what you are saying about DVFS, but for switching cpu models, I thought it is a must to wake the cpu (from quiesce()) since a drain needs to be done. Please let me know if I am missing something here. Thanks Srini On 03/24/14, Stephan Diestelhorst wrote: Srini, kudos for making per-core DVFS work! A quick head¹s up: we are also working on (per-core) DVFS support and are just polishing those patches for consumption, should hopefully have them ready within a week or two. On the main question, I have no hard opinion, but wonder what the reasoning is for either. The OS should cope with the core being woken up spuriously, maybe check the run queues and go back to sleep if nothing has happened. Likewise, on the HW side, it depends. Some systems might do DVFS of a remote core, some need to run code on the core that is to be DVFS-ed (obviously requiring wakeup). HTH, Stephan On 23.03.2014 14:26, Srinivasan Narayanamoorthy narayanam...@wisc.edu wrote: Hi all, I have implemented a per-core DVFS in gem5, mimicking an on-demand governer. My question here is if the cpu is in quiesce state(TC is suspended) while DVFS routine is scheduled, should I wakeup() the suspended TC?. Similarly while doing a drain and switching to a different cpu model, should the suspended TC be explicitly woken up? I am doing both in my implementation and nothing has broken so far. But am wondering if it is actually done that way. Thanks Srini ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England Wales, Company No: 2548782 ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] DVFS in Quiesce states
Hi all, I have implemented a per-core DVFS in gem5, mimicking an on-demand governer. My question here is if the cpu is in quiesce state(TC is suspended) while DVFS routine is scheduled, should I wakeup() the suspended TC?. Similarly while doing a drain and switching to a different cpu model, should the suspended TC be explicitly woken up? I am doing both in my implementation and nothing has broken so far. But am wondering if it is actually done that way. Thanks Srini ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS on gem5
Hi, In my project I need to dump out the power profile (with time) for some benchmarks. In that case, I think I need to dump out the GEM5 statistics to McPAT for power calculation every a few cycles. As I'm very new to GEM5, could anybody let me know where to start for dumping GEM5 statistics for every 100 cycles? Thanks a lot. On Thu, Feb 16, 2012 at 3:21 AM, Simone Corbetta simone.corbe...@gmail.comwrote: As Patrick said, to enable DVFS with GEM5 simulation, you have to plug a power model. McPAT can be used to generate power estimates according to the statistics collected from a cycle-accurate simulation with GEM5 (you need also to translate GEM5 output statistics to XML format as required by McPAT). For Dynamic VFS you need to reiterate the loop and simulate changing DVFS after desired number of iterations; GEM5 allows you to stop simulation and then start back again, so you can for sure loop on it. Simone Corbetta On Wed, Feb 15, 2012 at 7:11 PM, Patrick plafr...@gmail.com wrote: Xiao, One of my colleagues at Notre Dame, Sheng Li, was working on a tool called McPAT for power analysis. I believe that it has been shown to work with gem5. This might be useful for you. Last I heard, Li and McPAT had moved to HP: http://www.hpl.hp.com/research/mcpat/. Patrick La Fratta On Fri, Feb 10, 2012 at 2:42 PM, Xiao Guo guox...@gmail.com wrote: Hi, Is there any DVFS support for gem5? Anybody has done this before? Any help would be appreciated! Thanks! Xiao ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Simone Corbetta, Ph.D. student Politecnico di Milano Dipartimento di Elettronica e Informazione Viale delle Rimembranze di Lambrate 14 20134 Milano, ITALY Office: +39.02.2399.9623 Home: http://home.dei.polimi.it/scorbetta Linkedin: http://www.linkedin.com/in/thelibrarian ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Best Regards, == Chun Zhang chun.zhang...@gmail.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS on gem5
I think you should make modifications to the Python script that makes GEM5 execute, such that every N cycles you dump statistics to a new file, reset statistics and get back to execution. Probably some hints can be found in the configs/example directory under GEM5, which contain execution scripts. On Fri, Feb 17, 2012 at 9:37 AM, Chun Zhang chun.zhang...@gmail.com wrote: Hi, In my project I need to dump out the power profile (with time) for some benchmarks. In that case, I think I need to dump out the GEM5 statistics to McPAT for power calculation every a few cycles. As I'm very new to GEM5, could anybody let me know where to start for dumping GEM5 statistics for every 100 cycles? Thanks a lot. On Thu, Feb 16, 2012 at 3:21 AM, Simone Corbetta simone.corbe...@gmail.com wrote: As Patrick said, to enable DVFS with GEM5 simulation, you have to plug a power model. McPAT can be used to generate power estimates according to the statistics collected from a cycle-accurate simulation with GEM5 (you need also to translate GEM5 output statistics to XML format as required by McPAT). For Dynamic VFS you need to reiterate the loop and simulate changing DVFS after desired number of iterations; GEM5 allows you to stop simulation and then start back again, so you can for sure loop on it. Simone Corbetta On Wed, Feb 15, 2012 at 7:11 PM, Patrick plafr...@gmail.com wrote: Xiao, One of my colleagues at Notre Dame, Sheng Li, was working on a tool called McPAT for power analysis. I believe that it has been shown to work with gem5. This might be useful for you. Last I heard, Li and McPAT had moved to HP: http://www.hpl.hp.com/research/mcpat/. Patrick La Fratta On Fri, Feb 10, 2012 at 2:42 PM, Xiao Guo guox...@gmail.com wrote: Hi, Is there any DVFS support for gem5? Anybody has done this before? Any help would be appreciated! Thanks! Xiao ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Simone Corbetta, Ph.D. student Politecnico di Milano Dipartimento di Elettronica e Informazione Viale delle Rimembranze di Lambrate 14 20134 Milano, ITALY Office: +39.02.2399.9623 Home: http://home.dei.polimi.it/scorbetta Linkedin: http://www.linkedin.com/in/thelibrarian ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Best Regards, == Chun Zhang chun.zhang...@gmail.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Simone Corbetta, Ph.D. student Politecnico di Milano Dipartimento di Elettronica e Informazione Viale delle Rimembranze di Lambrate 14 20134 Milano, ITALY Office: +39.02.2399.9623 Home: http://home.dei.polimi.it/scorbetta Linkedin: http://www.linkedin.com/in/thelibrarian ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS on gem5
Hi all, I've checked the scripts under configs/example and configs/common. However, I didn't find the option or related functions to dump the statistics every N cycles. I do try the checkpoints option, but the output is not the same as in m5out/stats.txt. Could anybody let me know how I can dump the statistics for every N cycles? For example, any option I can try or the part of code I need to change? Thanks a lot. On Fri, Feb 17, 2012 at 4:40 PM, Simone Corbetta simone.corbe...@gmail.comwrote: I think you should make modifications to the Python script that makes GEM5 execute, such that every N cycles you dump statistics to a new file, reset statistics and get back to execution. Probably some hints can be found in the configs/example directory under GEM5, which contain execution scripts. On Fri, Feb 17, 2012 at 9:37 AM, Chun Zhang chun.zhang...@gmail.com wrote: Hi, In my project I need to dump out the power profile (with time) for some benchmarks. In that case, I think I need to dump out the GEM5 statistics to McPAT for power calculation every a few cycles. As I'm very new to GEM5, could anybody let me know where to start for dumping GEM5 statistics for every 100 cycles? Thanks a lot. On Thu, Feb 16, 2012 at 3:21 AM, Simone Corbetta simone.corbe...@gmail.com wrote: As Patrick said, to enable DVFS with GEM5 simulation, you have to plug a power model. McPAT can be used to generate power estimates according to the statistics collected from a cycle-accurate simulation with GEM5 (you need also to translate GEM5 output statistics to XML format as required by McPAT). For Dynamic VFS you need to reiterate the loop and simulate changing DVFS after desired number of iterations; GEM5 allows you to stop simulation and then start back again, so you can for sure loop on it. Simone Corbetta On Wed, Feb 15, 2012 at 7:11 PM, Patrick plafr...@gmail.com wrote: Xiao, One of my colleagues at Notre Dame, Sheng Li, was working on a tool called McPAT for power analysis. I believe that it has been shown to work with gem5. This might be useful for you. Last I heard, Li and McPAT had moved to HP: http://www.hpl.hp.com/research/mcpat/. Patrick La Fratta On Fri, Feb 10, 2012 at 2:42 PM, Xiao Guo guox...@gmail.com wrote: Hi, Is there any DVFS support for gem5? Anybody has done this before? Any help would be appreciated! Thanks! Xiao ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Simone Corbetta, Ph.D. student Politecnico di Milano Dipartimento di Elettronica e Informazione Viale delle Rimembranze di Lambrate 14 20134 Milano, ITALY Office: +39.02.2399.9623 Home: http://home.dei.polimi.it/scorbetta Linkedin: http://www.linkedin.com/in/thelibrarian ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Best Regards, == Chun Zhang chun.zhang...@gmail.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Simone Corbetta, Ph.D. student Politecnico di Milano Dipartimento di Elettronica e Informazione Viale delle Rimembranze di Lambrate 14 20134 Milano, ITALY Office: +39.02.2399.9623 Home: http://home.dei.polimi.it/scorbetta Linkedin: http://www.linkedin.com/in/thelibrarian ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Best Regards, == Chun Zhang chun.zhang...@gmail.com ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS on gem5
Xiao, One of my colleagues at Notre Dame, Sheng Li, was working on a tool called McPAT for power analysis. I believe that it has been shown to work with gem5. This might be useful for you. Last I heard, Li and McPAT had moved to HP: http://www.hpl.hp.com/research/mcpat/. Patrick La Fratta On Fri, Feb 10, 2012 at 2:42 PM, Xiao Guo guox...@gmail.com wrote: Hi, Is there any DVFS support for gem5? Anybody has done this before? Any help would be appreciated! Thanks! Xiao ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] DVFS on gem5
As Patrick said, to enable DVFS with GEM5 simulation, you have to plug a power model. McPAT can be used to generate power estimates according to the statistics collected from a cycle-accurate simulation with GEM5 (you need also to translate GEM5 output statistics to XML format as required by McPAT). For Dynamic VFS you need to reiterate the loop and simulate changing DVFS after desired number of iterations; GEM5 allows you to stop simulation and then start back again, so you can for sure loop on it. Simone Corbetta On Wed, Feb 15, 2012 at 7:11 PM, Patrick plafr...@gmail.com wrote: Xiao, One of my colleagues at Notre Dame, Sheng Li, was working on a tool called McPAT for power analysis. I believe that it has been shown to work with gem5. This might be useful for you. Last I heard, Li and McPAT had moved to HP: http://www.hpl.hp.com/research/mcpat/. Patrick La Fratta On Fri, Feb 10, 2012 at 2:42 PM, Xiao Guo guox...@gmail.com wrote: Hi, Is there any DVFS support for gem5? Anybody has done this before? Any help would be appreciated! Thanks! Xiao ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Simone Corbetta, Ph.D. student Politecnico di Milano Dipartimento di Elettronica e Informazione Viale delle Rimembranze di Lambrate 14 20134 Milano, ITALY Office: +39.02.2399.9623 Home: http://home.dei.polimi.it/scorbetta Linkedin: http://www.linkedin.com/in/thelibrarian ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
