[PEDA] Old patch files

2001-11-09 Thread intellasys




[PEDA] Possible enhancement for polygon display!

2001-11-09 Thread Brian Guralnick

I was thinking,

I was thinking of a possible means of accelerating design work with multiple
polygons all over the place.  During design, as an option, what if Protel just
generated quick & dirty raster type polygon planes with regard to the area where you
are working on the PCB?  Moving traces & components would relocate everything in a
snap.  When you do a final DRC, or prepare to print, or make the Gerbers, Protel then
would generate the final polygon planes.


Brian Guralnick


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Re: [PEDA] Polygon problems!

2001-11-09 Thread Ian Wilson

On 04:34 PM 9/11/2001 +, Coleman, Tim said:
>Hi folks
>
>I have a problem with polygons! I can't select the propertise to change
>them. I can't adjust the vertices, I can't delet them, I can't move them.
>It's as though they weren't there. I can see them but I can't touch them!
>I've never had this problem before. What do I have to do to regain control
>of my design?  Any clues?
>
>TC


As the others have said, it is possible that the outline for the polygon 
can be separated from the tracks that make up the polygon.  This can happen 
when you don't lock the polygon tracks and then do selections and moves.  I 
have a feeling I have looked at someone else's file and found a problem the 
associations between a polygon and the tracks that make up that poly.  I 
worked through this issue using the ASCII format.  But I can't recall all 
the detail, was that a file you sent Brad V? Or was that some other issue? 
Can you recall the details?

To gain control you can use the re-pour all polygons server that Jason 
Morgan wrote. It is available on the Protel User yahoo goups:

http://groups.yahoo.com/group/protel-users/files/CitelTools%28RePourAllPolys 
%29.zip

I think you will need to be a member of yahoo to get it.

This server will re-pour all the polys on the design.

You can also do this by turning all layer on and then SA (Select All) and 
then do a dummy move (M-S) and click a reference point and then click back 
to the same location.  You should be prompted to re-pour x polygons.

Ian Wilson

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Re: [PEDA] Pricing

2001-11-09 Thread Ian Wilson

On 04:29 PM 9/11/2001 -0500, Abd ul-Rahman Lomax said:
<..PCAD stuff snipped..>
>Now, to ATS for Protel. Today, you can buy from Accel Technologies (the 
>U.S. Protel rep, we've gone full circle) the upgrade from Protel 98 to 
>Protel 99SE for $1995. Essentially, a Protel 98 user can buy ATS for that 
>price, and since ATS includes automatic upgrades, *the next version will 
>be included.*
>
>This is, if anything, a price *reduction.* Since July 1, the Protel 98 to 
>Protel 99SE upgrade has been that same price, it was $1495 before that. 
>Now, since October 1, it includes ATS for a year!
>
>Protel has not announced ATS or upgrade pricing for current Protel 99SE 
>users. But if it was more than about $995, Protel would be *penalizing* 
>users for upgrading to 99SE sooner than October 1. I don't think they are 
>going to do that. From previous indications and history, I'm going to 
>guess that upgrade from Protel 99SE to the next release is going to be 
>about $995 and it will include one year of ATS. The ongoing ATS price, I 
>was told, has not really been established, or if it has, it has not been 
>announced to sales.


I too have spoken to people in Altium on ATS (in fact they rang me in 
response to a long, hopefully carefully crafted email, direct email that I 
had sent).  My understanding is that the information in the press release 
is correct.  I repeat:
"Altium Total Support is annually renewable and is priced at US$1995. for 
P-CAD and Protel full suites. Prices of other product configurations are 
available on request."

This press release information is consistent with my discussions with 
Altium.  So we seem to have conflicting advice.  There is no mention in the 
press release that the price information is related to upgrade pricing for P98.

My *guess* is that the currently targeted upgrade price, for existing P99SE 
license holders is the ATS price.  This price, annually, is, it seems to me 
roughly doubling our current effective maintenance costs for maintaining a 
Protel license at the latest and greatest.

I did look to see if there had been an announcement on the ASX (Austr. 
Stock Exch) about ATS as there are strict rules for such announcements, and 
the need for accuracy.  Unfortunately, I could not find anything about 
ATS.  Nor is there any mention of ATS in the financial report (at least the 
searching for ATS in the pdf finds).

So we seem to be in FUD mode at the moment.  It would seem sensible that 
Protel CSC should provide public detailed clarification to our questions 
and possible incorrect statements.

Ian Wilson

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Re: [PEDA] Pricing

2001-11-09 Thread Abd ul-Rahman Lomax

At 05:39 PM 11/9/01 -0500, [EMAIL PROTECTED] wrote:
>and to add another question to the confusion
>
>What happens if you have two Protel Licenses and buy 1 ATS?
>
>It might be affordable then.

It might be illegal then

Sure, you'd get the CD for the upgrade, but if you really want to save some 
money, just get a friend to give you a copy. Illegal, but why not go 
two-for-one?

You can upgrade/maintain only one license, I am sure, but you would have 
only one license for the new version, not two.

It is looking like it *will* be affordable, my guess right now is that the 
upgrade from 99SE to the next version is going to be about what the upgrade 
was from 98 to 99, not much more.

Problem is, this is a guess, time will tell how educated it is. I have no 
special inside information. Because of my situation supporting second-hand 
license sales, I am going to be asking for some hints from my contacts in 
Altium. At that time I might know something I won't be able to announce, 
we'll see how far I get.

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] Pricing

2001-11-09 Thread Brad Velander

Rob,
try my quandry, 5 licenses and a bunch of rogue engineers who care
not about licenses, support or anything else as long as they can get a
design out the door. If they can't get the design out the door then they all
want to instantly buy some other program that minute.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
#300 - 4401 Still Creek Drive,
Burnaby, B.C., Canada, V5C 6G9.
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
Website: www.norsat.com


-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Friday, November 09, 2001 2:39 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Pricing




and to add another question to the confusion

What happens if you have two Protel Licenses and buy 1 ATS?


It might be affordable then.

Rob

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Re: [PEDA] Pricing

2001-11-09 Thread rlamoreaux



and to add another question to the confusion

What happens if you have two Protel Licenses and buy 1 ATS?


It might be affordable then.

Rob


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Re: [PEDA] Pricing

2001-11-09 Thread Abd ul-Rahman Lomax

At 04:36 PM 11/9/01 -0500, Bagotronix Tech Support wrote:
>What a huge mass of confusion this ATS nonsense has caused.

Yes, the announcement was *very* badly done. The Press Release was directly 
contradicted by USA Protel sales.

I'd suggest that Altium *communicate* -- this means back and forth -- with 
the users about plans *before* making a full public announcements. There 
would be no harm in making an announcement here on this list a couple of 
days before it goes out to everyone and his brother. Altium could say, "we 
are thinking of doing this" -- i.e., they have decided to do it but before 
it is 100% final they want to see what we think -- and then any misgivings 
or questions that we have could be *answered*, not only here, but then in 
the press release and major announcement. We *express* our displeasure, 
most users won't. They will just have one more reason to go somewhere else 
for CAD software. Too much of that, it could really hurt. It *has* hurt.

There is *still* chaos, the resale market for 99SE is in confusion; if 
someone buys a second-hand SE license now, will they have to pay another 
$2000 to get the next version? We had been thinking it would be about 
$1000. So suddenly, from the announcement, the resale price -- which Altium 
sales has been trying to increase, at least by asking me -- informally -- 
to work to that end -- drops $1000, from about $6000 to $5000.

We had all this discussion here, and not a peep from any Protel rep. Sure, 
we are used to relative silence from them, but generally when we go too far 
off into the ozone, Protel CSC has popped in with corrections. This time, 
nothing.

Sometimes I wonder if the Altium sales people are professionals They 
seem intelligent enough when I talk to them. But something is wacky about 
the situation.

[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] Pricing

2001-11-09 Thread Bagotronix Tech Support

What a huge mass of confusion this ATS nonsense has caused.  I now know
nothing about the future of Protel or its products,  whereas before all this
I *thought* I knew there was a PCB software provider that provided free
services packs and tech support, and I could choose whether or not and when
to upgrade.

There is no understanding where there was understanding before.  We have
gone from light into darkness.  The FUD is engulfing me...

Best regards,
Ivan Baggett
Bagotronix Inc.
website:  www.bagotronix.com


- Original Message -
From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, November 09, 2001 4:29 PM
Subject: Re: [PEDA] Pricing


> At 02:48 PM 11/9/01 -0500, Sean James wrote:
> >Well everybody, Accel/PCAD did the same exact thing by changing their
> >pricing. Who owns Accel/PCAD and Protel?
>
> Yes, Altium, nee Protel, owns both. BUT the Accel pricing boost was while
> Accel Technologies was independent. It was my impression that Protel
> wrapped up the whole bundle of PCAD products, which used to sell for about
> $20K, and reduced the price to $9995. Bit I had not seen PCAD pricing
recently.
>
> So I called 'em up. First I talked to Protel sales, and I found out some
> *very* interesting information. It seems we may have been reading the
> announcement incorrectly. I should have called sooner. More about that
below.
>
> Then I asked about PCAD pricing. Yes, PCAD 2001 is still $9995. The
> original separate prices of all the units now included was $27K not
> including simulation. Protel tossed in CAMtastic and the simulation
package
> that used to sell for another $10K. So Accel under Protel/Altium ownership
> has drastically reduced prices. They also got rid of the dongle. I'm sure
> PCAD users were heartbroken over that :-)
>
> Now, to ATS for Protel. Today, you can buy from Accel Technologies (the
> U.S. Protel rep, we've gone full circle) the upgrade from Protel 98 to
> Protel 99SE for $1995. Essentially, a Protel 98 user can buy ATS for that
> price, and since ATS includes automatic upgrades, *the next version will
be
> included.*
>
> This is, if anything, a price *reduction.* Since July 1, the Protel 98 to
> Protel 99SE upgrade has been that same price, it was $1495 before that.
> Now, since October 1, it includes ATS for a year!
>
> Protel has not announced ATS or upgrade pricing for current Protel 99SE
> users. But if it was more than about $995, Protel would be *penalizing*
> users for upgrading to 99SE sooner than October 1. I don't think they are
> going to do that. From previous indications and history, I'm going to
guess
> that upgrade from Protel 99SE to the next release is going to be about
$995
> and it will include one year of ATS. The ongoing ATS price, I was told,
has
> not really been established, or if it has, it has not been announced to
sales.
>
>
>
>
>
> [EMAIL PROTECTED]
> Abdulrahman Lomax
> Easthampton, Massachusetts USA


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Re: [PEDA] keepoutlayer and planes ??

2001-11-09 Thread Frank Gilley

My experience with planes-to-the-edge has been this... to date, no one
has ever sent me a board that has both power and ground all the way out
to the edge whether I pulled the planes back in the gerbers or not. 
It appears to be pretty much SOP.  However, I have received almost
all the boards that have multiple ground planes only- no power plane at
all- that came back with the planes out to the edge.  I actually
wanted them that way, but I didn't specify other than not pulling the
planes back on the gerbers.  I never really thought about it too
much, but that is quite a decision on the board house's
part.  Luckily for me, they seem to be able to determine which
designs are RF and which are Digital and such.
One pet peeve of mine- I've had it happen twice on high-current designs-
a board house adding thermal reliefs to all the through-hole
components.  A near disaster.  Needless to say, we don't use
those houses any more.  Funny thing is, they acted very baffled as
to why we would be angry about that.
As for plating edges, I have had this done several times.  I don't
believe it's all that uncommon.  In a case with RF components near
an edge, and the board mounting surface being a chunk of aluminum that
follows the perimeter underneath the board, the RF can flow right off the
edge of the board and down to the aluminum case "ground plane"
with very little inductance.  This is especially effective with
thicker boards, where proper GND via diameters can get pretty
large.  I have seen a few cases where edge plating seemed to really
make a difference.  A well placed set of stitching holes appears to
be almost equally effective though in the majority of situations, and I
generally get by with that.  
Funny you should mention this right now, I was kicking around the idea of
plating an edge of our new receiver board and see if it accidentally had
any effect.
-Frank

At 03:21 PM 11/9/2001 -0500, Abdulrahman Lomax wrote:
At 09:44 AM 11/9/01 -0700, Bob
Fearon wrote:
Abdul-Rahman
    Yes I have seen an inner plane layer come all the way
out to an edge.
    The design was supposed to be "better for
RF", but made no difference
    in board performance. The two outside layers were
plated aound the edge
    and shorted ( on purpose ) to the inner layer. This
was a nightmare to
    build and cost "extra".
    The same performance was achieved by placing a row of
vias 100 mils
    from the edge on a "regular" board, at a
much lower cost.
This is not an example of what I asked for. Instead, this was a board
deliberately fabricated without edge clearance. Yes, it was not a great
idea from the start, as anyone who knows HF design would have
anticipated, unless -- maybe -- one was trying to squeeze the last
percent out of noise emissions *and* board space was very limited. I
could see doing this with very small PCBs, where the via ring would take
up an appreciable percentage of the board space.
It should not have been much more expensive. In fact, as I recall,
depending on the process, panel edges plate if you don't do something to
prevent it!  (The same electroless copper used to plate the inside
of holes also plates the panel edge, I'd think, I don't remember actually
seeing this; however, that edge is normally routed away when all the
processing is done, leaving the unplated edges that we normally see. So
to accomplish this relatively inexpensively, one would route the boards
as one routes a breakaway board *before* going to the electroless copper;
this would leave some unplated tabs but one might hide the unplated tabs
behind mounting holes)
Edge effect with regard to radiated noise is a controversial subject, but
actually plating the board edge I have never before seen suggested.
[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

Frank Gilley
Dell-Star Technologies
(918) 838-1973 Phone
(918) 838-8814 Fax
[EMAIL PROTECTED]
http://www.dellstar.com

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Re: [PEDA] Chip & Wire

2001-11-09 Thread Watnoski, Michael




Re: [PEDA] Pricing

2001-11-09 Thread Abd ul-Rahman Lomax

At 02:48 PM 11/9/01 -0500, Sean James wrote:
>Well everybody, Accel/PCAD did the same exact thing by changing their 
>pricing. Who owns Accel/PCAD and Protel?

Yes, Altium, nee Protel, owns both. BUT the Accel pricing boost was while 
Accel Technologies was independent. It was my impression that Protel 
wrapped up the whole bundle of PCAD products, which used to sell for about 
$20K, and reduced the price to $9995. Bit I had not seen PCAD pricing recently.

So I called 'em up. First I talked to Protel sales, and I found out some 
*very* interesting information. It seems we may have been reading the 
announcement incorrectly. I should have called sooner. More about that below.

Then I asked about PCAD pricing. Yes, PCAD 2001 is still $9995. The 
original separate prices of all the units now included was $27K not 
including simulation. Protel tossed in CAMtastic and the simulation package 
that used to sell for another $10K. So Accel under Protel/Altium ownership 
has drastically reduced prices. They also got rid of the dongle. I'm sure 
PCAD users were heartbroken over that :-)

Now, to ATS for Protel. Today, you can buy from Accel Technologies (the 
U.S. Protel rep, we've gone full circle) the upgrade from Protel 98 to 
Protel 99SE for $1995. Essentially, a Protel 98 user can buy ATS for that 
price, and since ATS includes automatic upgrades, *the next version will be 
included.*

This is, if anything, a price *reduction.* Since July 1, the Protel 98 to 
Protel 99SE upgrade has been that same price, it was $1495 before that. 
Now, since October 1, it includes ATS for a year!

Protel has not announced ATS or upgrade pricing for current Protel 99SE 
users. But if it was more than about $995, Protel would be *penalizing* 
users for upgrading to 99SE sooner than October 1. I don't think they are 
going to do that. From previous indications and history, I'm going to guess 
that upgrade from Protel 99SE to the next release is going to be about $995 
and it will include one year of ATS. The ongoing ATS price, I was told, has 
not really been established, or if it has, it has not been announced to sales.





[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] keepoutlayer and planes ??

2001-11-09 Thread Brad Velander

My 2 cents worth, since we do this regularily.

The edge plating will make a significant difference in board
emmisions with GHz frequency signals depending on the board material used.
It gets worse the higher your frequencies go. The problem is that the board
material is a dielectric and thus will conduct high freq. signals between
the copper of the other outer layers. It is essentially a waveguide. The
vias will block some of the signal but the higher the frequency the closer
you have to space the vias until you are almost hole to hole and your board
has no structural strength along the line of vias.
The additional cost for the edge plating should be minimal. The only
operation or labor is to route the board edges before doing the intitial
electoless plating, instead of doing it after the board is processed. There
is no additional work or effort unless there is also still unplated routing
to do after the board is processed.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
#300 - 4401 Still Creek Drive,
Burnaby, B.C., Canada, V5C 6G9.
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
Website: www.norsat.com


-Original Message-
From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
Sent: Friday, November 09, 2001 12:22 PM
To: Protel EDA Forum
Subject: Re: [PEDA] keepoutlayer and planes ??


At 09:44 AM 11/9/01 -0700, Bob Fearon wrote:
>Abdul-Rahman
> Yes I have seen an inner plane layer come all the way out to an edge.
> The design was supposed to be "better for RF", but made no difference
> in board performance. The two outside layers were plated aound the
edge
> and shorted ( on purpose ) to the inner layer. This was a nightmare to
> build and cost "extra".
> The same performance was achieved by placing a row of vias 100 mils
> from the edge on a "regular" board, at a much lower cost.

This is not an example of what I asked for. Instead, this was a board 
deliberately fabricated without edge clearance. Yes, it was not a great 
idea from the start, as anyone who knows HF design would have anticipated, 
unless -- maybe -- one was trying to squeeze the last percent out of noise 
emissions *and* board space was very limited. I could see doing this with 
very small PCBs, where the via ring would take up an appreciable percentage 
of the board space.

It should not have been much more expensive. In fact, as I recall, 
depending on the process, panel edges plate if you don't do something to 
prevent it!  (The same electroless copper used to plate the inside of holes 
also plates the panel edge, I'd think, I don't remember actually seeing 
this; however, that edge is normally routed away when all the processing is 
done, leaving the unplated edges that we normally see. So to accomplish 
this relatively inexpensively, one would route the boards as one routes a 
breakaway board *before* going to the electroless copper; this would leave 
some unplated tabs but one might hide the unplated tabs behind mounting 
holes)

Edge effect with regard to radiated noise is a controversial subject, but 
actually plating the board edge I have never before seen suggested.
[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] keepoutlayer and planes ??

2001-11-09 Thread Abd ul-Rahman Lomax

At 09:44 AM 11/9/01 -0700, Bob Fearon wrote:
>Abdul-Rahman
> Yes I have seen an inner plane layer come all the way out to an edge.
> The design was supposed to be "better for RF", but made no difference
> in board performance. The two outside layers were plated aound the edge
> and shorted ( on purpose ) to the inner layer. This was a nightmare to
> build and cost "extra".
> The same performance was achieved by placing a row of vias 100 mils
> from the edge on a "regular" board, at a much lower cost.

This is not an example of what I asked for. Instead, this was a board 
deliberately fabricated without edge clearance. Yes, it was not a great 
idea from the start, as anyone who knows HF design would have anticipated, 
unless -- maybe -- one was trying to squeeze the last percent out of noise 
emissions *and* board space was very limited. I could see doing this with 
very small PCBs, where the via ring would take up an appreciable percentage 
of the board space.

It should not have been much more expensive. In fact, as I recall, 
depending on the process, panel edges plate if you don't do something to 
prevent it!  (The same electroless copper used to plate the inside of holes 
also plates the panel edge, I'd think, I don't remember actually seeing 
this; however, that edge is normally routed away when all the processing is 
done, leaving the unplated edges that we normally see. So to accomplish 
this relatively inexpensively, one would route the boards as one routes a 
breakaway board *before* going to the electroless copper; this would leave 
some unplated tabs but one might hide the unplated tabs behind mounting 
holes)

Edge effect with regard to radiated noise is a controversial subject, but 
actually plating the board edge I have never before seen suggested.
[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA

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Re: [PEDA] Chip & Wire

2001-11-09 Thread Sean James

Any help or information would be greatly appreciated. My only other option
is to by a 3rd party add-on for AutoCAD (I used to do chip & wire in ACAD
without any intelligence; not easy and a big PITA).

Sean James
PCB Designer
Telecast Fiber Systems, Inc.
102 Grove Street
Worcester, MA 01605
(TEL) 508.754.4858 x33
(FAX) 413.541.6170
- Original Message -
From: "Bob Fearon" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, November 09, 2001 11:59 AM
Subject: Re: [PEDA] Chip & Wire


> Sean
> I have used Protel for "Chip and Wire", but it was Ver 2.8.
> If you can use that out date info, contact me off-forum.
> Bob Fearon
>
>
> Sean James wrote:
>
> > Has anybody attempted to do chip & wire (hybrid layouts) with Protel?
> >
> > Sean James
> > PCB Designer
> > Telecast Fiber Systems, Inc.
> > 102 Grove Street
> > Worcester, MA 01605
> > (TEL) 508.754.4858 x33
> > (FAX) 413.541.6170

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[PEDA] Pricing

2001-11-09 Thread Sean James




Re: [PEDA] Chip & Wire

2001-11-09 Thread Michael Reagan

Sean,
I have designed both  MCMs and Hybrids with both Protel and PCAD.  You can
give me a call Monday  301 620 0080 and maybe I can guide you thru.  I am
not in my office today.


Mike Reagan
EDSI
Frederick Md

> -Original Message-
> From: Bob Fearon [mailto:[EMAIL PROTECTED]]
> Sent: Friday, November 09, 2001 12:00 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] Chip & Wire
>
>
> Sean
> I have used Protel for "Chip and Wire", but it was Ver 2.8.
> If you can use that out date info, contact me off-forum.
> Bob Fearon
>
>
> Sean James wrote:
>
> > Has anybody attempted to do chip & wire (hybrid layouts) with Protel?
> >
> > Sean James
> > PCB Designer
> > Telecast Fiber Systems, Inc.
> > 102 Grove Street
> > Worcester, MA 01605
> > (TEL) 508.754.4858 x33
> > (FAX) 413.541.6170
>

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Re: [PEDA] ATS Specifications

2001-11-09 Thread Frank Gilley

Brad isn't the only one to return from vacation to hear this most 
disappointing news.

I'm a little shocked...from what I can tell, we are basically going to have 
to pay for our technical support and service packs from now on.  A whopping 
$2K a year.  Apparantly with penalty if you don't maintain a continuous 
subscription as well.

All this fun starts upon our next upgrade...we get one year of *what we had 
before* then its payola after that.
What are we getting for all this extra money?  As far as I can tell, only 
*what we had before*.  What about that giant Protel 99se price increase to 
boot??
Without some tangible promise of...something... for all this extra money, 
this looks like clear gouging from our standpoint.  I have seen no promise 
of anything different than what we currently get.  I can't believe that 
Protel isn't offering even token promises of improvement in the area that 
we are now going to be charged for... now that's arrogance.

Protel is throwing away one if its most important market 
advantages.  Especially since free support and service packs go a long way 
to help smooth over so many of their other problems.  I'll bet there are 
quite a few within the company itself that strongly disagree with this 
course change, this kind of thing could divide many who work there.

Guess vacation is over...

Frank

At 07:32 AM 11/9/2001 +1100, Ian Wilson wrote:
>On 09:00 AM 8/11/2001 -0800, Brad Velander said:
>>Hi all,
>> seems in reading this message that I may have missed something
>>significant while I was away on vacation. I did not receive any email about
>>this "ATS", does anybody still have a copy of the email that they can
>>forward to me? Was this email posted to the EDA forum or was it sent via
>>personal email?
>>Sounds like Protel is changing their upgrade and support policies and I
>>should be aware of these changes.
>>
>>Sincerely,
>>Brad Velander.
>
>Personal email. (Copy sent direct)
>
>But you can get all the guff from the Protel www site.
>
>By my calculations it appears Protel support cost have about doubled - 
>assuming the current roughly 2 year upgrade cycle. What's more the support 
>costs are now the same as PCAD.  For Protel this equates to about 25% per 
>annum.
>
>What should be remembered though is that there is about a year (from the 
>next upgrade) before existing P99SE users are affected.  But I am yet to 
>be convinced, and will be lobbying for a *very* significant reduction in 
>the annual maintenance cost.
>
>I do not like yearly maintenance as I can't see how it encourages good, 
>responsive-to-the-market software.  But I would probably go along with it 
>if it reflected roughly the current upgrade cost.
>
>Ian Wilson



Frank Gilley
Dell-Star Technologies
(918) 838-1973 Phone
(918) 838-8814 Fax
[EMAIL PROTECTED]
http://www.dellstar.com

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Re: [PEDA] Polygon problems!

2001-11-09 Thread Jim McGrath

Tim,

Just as a precaution I create my polygons with a trackwidth other than
any already used on the board. If they lose their "inteligence" for some
reason I can always select the culprits for easy identification/deletion and
rebuild. Its a holdover from earlier versions of Protel that I have used.

Regards,

Jim McGrath
CAD Connections, Inc.

"Coleman, Tim" wrote:

> Hi folks
>
> I have a problem with polygons! I can't select the propertise to change
> them. I can't adjust the vertices, I can't delet them, I can't move them.
> It's as though they weren't there. I can see them but I can't touch them!
> I've never had this problem before. What do I have to do to regain control
> of my design?  Any clues?
>
> TC

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Re: [PEDA] Chip & Wire

2001-11-09 Thread Bob Fearon

Sean
I have used Protel for "Chip and Wire", but it was Ver 2.8.
If you can use that out date info, contact me off-forum.
Bob Fearon


Sean James wrote:

> Has anybody attempted to do chip & wire (hybrid layouts) with Protel?
>
> Sean James
> PCB Designer
> Telecast Fiber Systems, Inc.
> 102 Grove Street
> Worcester, MA 01605
> (TEL) 508.754.4858 x33
> (FAX) 413.541.6170

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Re: [PEDA] Polygon problems!

2001-11-09 Thread Brad Velander

Tim,
I have experienced similar difficulties from time to time, typically
I can click around a little bit and finally get the vertices to highlight
using the Move Polygon vertices command. Remember that the vertices may
actually be in an area where there is no polygon pour because it was removed
as dead copper. I have always found that trying to select the vertices only
works when you are quite close to the actual outline location, not just
inside the polygon.
Other issues which have plagued people before, did you move the
polygons in a group selection or from one layer to another? Sometimes people
have moved the polygon fill tracks without actually moving the polygon
outline. The polygon outline does not then reside where one expects it to
reside.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
#300 - 4401 Still Creek Drive,
Burnaby, B.C., Canada, V5C 6G9.
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
Website: www.norsat.com


-Original Message-
From: Coleman, Tim [mailto:[EMAIL PROTECTED]]
Sent: Friday, November 09, 2001 8:34 AM
To: Protel EDA user group Forum (E-mail)
Subject: [PEDA] Polygon problems!


Hi folks

I have a problem with polygons! I can't select the propertise to change
them. I can't adjust the vertices, I can't delet them, I can't move them.
It's as though they weren't there. I can see them but I can't touch them!
I've never had this problem before. What do I have to do to regain control
of my design?  Any clues?

TC

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Re: [PEDA] keepoutlayer and planes ??

2001-11-09 Thread Bob Fearon

Abdul-Rahman
Yes I have seen an inner plane layer come all the way out to an edge.
The design was supposed to be "better for RF", but made no difference
in board performance. The two outside layers were plated aound the edge
and shorted ( on purpose ) to the inner layer. This was a nightmare to
build and cost "extra".
The same performance was achieved by placing a row of vias 100 mils
from the edge on a "regular" board, at a much lower cost.

Bob Fearon


Abd ul-Rahman Lomax wrote:

> At 05:32 PM 11/8/01 -0500, Mike Reagan wrote:
>
> >you scare me man   thinking that you are design aircraft components and dont
> >know how to use the progam I think you better fligt test it
>
> Knowing how to use the program is a convenience, not a necessity. The
> necessity is to know how to inspect the gerbers or films and the board itself.
>
> Let me put it this way. If I want reliability of a pcb, I will prefer it to
> be designed by someone who knows electronics and reliability issues, but
> who is a beginner with a piece of software he uses, than by one for whom
> the reverse is true.
>
> (I don't think Mr. Robison is designing "aircraft components." Last we
> spoke, he was designing equipment that might fly *on* a plane, but it does
> not *fly* the plane. If one of his boards fails, if I am correct, it will
> be a nuisance, not a disaster.)
>
> In my experience, boards for hi-rel usage (for me, it has been space
> flight) are reviewed through several different stages, at least. While it
> is obviously best and safest to get the board right in the first place
> (after all, there is a statistical possibility that the later safeguards
> could all fail), the knowledge that negative planes should not go to the
> board edge is widespread. As I mentioned previously, most board houses,
> perhaps all, will already create an edge clearance if you don't put one
> there and you don't clearly specify that you *don't* want one. They have
> been dealing with gerbers with no edge clearance for years, but they have
> probably never encountered a request for planes to go to the edge.
>
> Has anyone reading this received fabricated boards with no inner plane
> clearance? Was it from an established fabricator? (I'd be surprised if it
> *never* happened, but I would also be surprised if it was at all common.)
>
> [EMAIL PROTECTED]
> Abdulrahman Lomax
> Easthampton, Massachusetts USA

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[PEDA] Polygon problems!

2001-11-09 Thread Coleman, Tim

Hi folks

I have a problem with polygons! I can't select the propertise to change
them. I can't adjust the vertices, I can't delet them, I can't move them.
It's as though they weren't there. I can see them but I can't touch them!
I've never had this problem before. What do I have to do to regain control
of my design?  Any clues?

TC

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[PEDA] Chip & Wire

2001-11-09 Thread Sean James




Re: [PEDA] keepoutlayer and planes ??

2001-11-09 Thread Ian Wilson

On 10:37 AM 9/11/2001 +, Stephen Casey said:
> > Has anyone reading this received fabricated boards with no inner plane
> > clearance? Was it from an established fabricator? (I'd be surprised if it
> > *never* happened, but I would also be surprised if it was at all common.)
>
>Abd,
>
>Yes, I have received boards with no clearance. My mistake on my first Protel
>job, but the board house didn't spot/query it. We stopped using them for
>another reason, and the new fabricator is (so far) superb. In fact, I posted
>a question to this list about board edge clearances a while back. I did add
>the clearances to the job this time, but they queried and fixed another
>issue that the first company would almost certainly have ignored. It would
>be very nice if Protel could add some DRC features to trap this.
>
>Steve.


I am giggling over this - not because it is a bad idea but more that Protel 
added a warning that there were entities on internal planes layers in lieu 
of full DRC for the planes.  So now we get a warning that we have tracks on 
the internal planes and then along comes Steve and wants them to add a 
warning if we *don't* have tracks on the internal layers!  Damed if we do, 
damed if we don't.

Actually I think it would be a good idea - since we have poor plane DRC 
adding a warning that there does not appear to be a plane backoff would be 
a worthwhile addition.

Ian

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[PEDA] Multi-Layer (Ex: minor display refresh bug)

2001-11-09 Thread Ian Wilson

On 10:25 PM 8/11/2001 -0500, Abd ul-Rahman Lomax said:
><..snip..>
>>Abd ul-Rahman Lomax has also recently mentioned that "blind" and "buried"
>>vias are sometimes inappropriately displayed.
>
>Actually, they are *always* inappropriately displayed. Either you have 
>multilayer turned off, in which case no vias are displayed at all, or you 
>have it turned on, in which case vias are displayed unconditionally, 
>whether or not they exist on the enabled layers. This is really a major 
>shortcoming at the point, actually one of the worst of which I know.
>
>>  I concur that this could be
>>regarded as a bug, but apart from that, I personally don't regard the
>>MultiLayer layer as being "bad" in nature. It is a "special" layer, like the
>>Drill Draw, Drill Guide and Keep Out layers, but PCB applications differ
>>from general purpose CAD applications (such as Autocad) in that there is a
>>good case for "special" layers to be provided.
>
>I have not heard, yet, any good argument for the maintenance of this layer 
>as a "layer." It is a "concept" more than it is a layer. A button that, in 
>Display setup, turns on all copper layers would be useful. But a via is a 
>via, it does not need a special layer!

This email is a little long - don't bother reading it if you are not 
interested in discussing future features. Here is a tip vaguely realted to 
some of the discussion below:
Tip:  On a PCB that does not use any mid signal layers, you can display the 
padstack of a multilayer pad correctly if you make the   MID layer size 0,0.

No on to the discussion:

I have no problem with the "special" layers that Geoff discusses. We are 
not using a generic CAD package.  But, I think the multi-layer layer as 
currently implemented is no longer a useful concept, apart from that 
dreaded curse, backwards compatibility.

As I see it there is one basic issue, that is, ** entities on multi-layer 
do not also belong on the signal layers **.  Even though they do in 
reality.  This breaks a number of useful constructs in the design rule 
system and has left a legacy of display artefacts.  For example, if 
multi-layer pads and vias *also* existed on the bottom layer then we could 
apply different solder mask expansion top and bottom in a sensible fashion. 
Both major issues could be fixed by special case programming, but I think 
there may be a better method...

I have a concept for layer groupings that could integrate nicely with the 
desired layer pairings that we have discussed and been after for some 
time.  If we were able to create named layer groups, consisting of one or 
more of the "base" layers, we could easily have facilities like:
1) Enabling/disabling of groups of layers in single "layer" mode.  So 
single layer mode may cause more than one "base" layer to be displayed if 
the current layer was actually a layer group. This would integrate directly 
into the existing behavior of the '+' & '-' keys, no change required.  A 
corollary would be that an item on a named layer would show just that 
particular layer, and no other, correctly in single layer mode.
2) Design rules could be scoped by named layer groups
3) The entities in the named layer still exist on all the relevant base 
layers and so the base layer-scoped design rules apply to them in the usual 
manner.  This is what I want mostly.
4) It should make a ready fix for many of the display artefacts and 
problems we have observed with blind and buried vias, and at other times. 
Multi-layer would simply be a (pre) defined collection of all signal 
layers.  As a new layer is added by the stack manager signal layers are 
added to the pre-defined multi-layer group automatically. *see note
5) It ought to be able to integrate into our desires for better padstacks.
6) Shouldn't cause any issue with flexible layer pairings feature that a 
number of us have been asking for (where the user can set up the layer 
pairing used when a component is flipped from the bottom to the top of the 
board and visa-versa.
7) In a fashion it can be used to create multi-coloured mech layers.

I can see some issues, mainly what to do when a library component is 
carrying a named group layer and there is already a named goup layer with 
different base layer members in the PCB.  Warn the user?  Create a new 
unique name? Offer to merge the two layer groups into the union of the 
sets?  This situation may arise if we get elaborate padstacks as a number 
of us have been requesting, and the component pads were placed on a named 
group layer.

An alternative solution would be to prevent library components from 
carrying named group layers, and implement padstacks using the database 
entity association techniques already used for things like polygons and, in 
fact, PCB components themselves (so a component becomes a hierarchy of 
associated entities rather than the current one-layer of association.  In 
this manner complex pads could be built up from surface pads on a number of 
layers, along with a n

Re: [PEDA] Routed trace length

2001-11-09 Thread Florian Finsterbusch

Hello Richards,

you can get a detailed list to control all netlengths.
To create this list press "Reports / Netlist Status" in the PCB editor.


Best regards, 

Florian Finsterbusch


> -Original Message-
> From: Mark Richards [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, November 08, 2001 12:11 AM
> To: Protel EDA Forum
> Subject: [PEDA] Routed trace length
> 
> 
> Hello,
> When manually routing traces (Protel 99SE), I often need to do some
> length matching. I have searched all the menu's and the help files, but
> I have been unable to find anything that will tell me the physical
> length of a routed net. Am I missing something (besides most of my brain
> cells)? Is there anything within the PCB editor that provides this
> information? I have tried several times to just use the "Equalize Net
> Lengths" feature with very disappointing results. Any suggestions would
> be greatly appreciated.
> 
> Regards,
> 
> --
> Mark Richards
> ON Semiconductor
> 5005 E. McDowell Road
> Phoenix, Arizona 85008
> Phone: 602.244.7267
> Pager: 866-208-9913
> 
> 
> 

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Re: [PEDA] keepoutlayer and planes ??

2001-11-09 Thread Stephen Casey

> Has anyone reading this received fabricated boards with no inner plane
> clearance? Was it from an established fabricator? (I'd be surprised if it
> *never* happened, but I would also be surprised if it was at all common.)

Abd,

Yes, I have received boards with no clearance. My mistake on my first Protel
job, but the board house didn't spot/query it. We stopped using them for
another reason, and the new fabricator is (so far) superb. In fact, I posted
a question to this list about board edge clearances a while back. I did add
the clearances to the job this time, but they queried and fixed another
issue that the first company would almost certainly have ignored. It would
be very nice if Protel could add some DRC features to trap this.

Steve.


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