[PEDA] Signal integrity analysis
Hi all, I am a signal integrity analysis virgin until today. However, it occurred to me that the software must generate a spice netlist which represents the PCB area of interest. Our IC designers could really do with this, so they can add it to their simulations. Does anyone know how I can get this spice netlist information out of Protel? Perhaps there is something I could access through writing a macro...? Any ideas? Dave Watling * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] signal integrity
It always says that there are warnings about my PCB, however it seems to work fine when I let it continue. I assume that these are undefined integrity (IBIS or similar) libraries. Actually they are probably loops in the tracks. These loops may be under pads and thus hard to find. I ran into this on a board I was doing in P99SE and found that after it complained most signals would work but a few would not simulate. I later brought the board into DXP and DXP comlained that the signals had loops in them and thus could not be simulated. One loop was obvious, but others were under pads so hard to find without DXP pointing out the location. Protel explained that this was due to the agorithm using the tracks not the copper. I fixed the loops and SI worked great. How do you define the IBIS (or protel library file) to use for each component?? Once you take over a net you can double click on a pin in the net and change the model and stimulus for that pin. How does protel store the simulation(signal integrity) libraries? I don't know and as long as it works I don't care. ;-} I'm usually too busy to look into things like this, and as I get older time goes faster so I don't have the extra time I did when I was young. Why does it not import so many IBIS files, it always complains the the file I have imported a few different IBIS files, but I can't remember why some wouldn't import. I do remember looking at the files to try to figure it out, but not what the resolution was. Hope this helps, Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] signal integrity
- Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, October 11, 2002 4:29 AM Subject: Re: [PEDA] signal integrity It always says that there are warnings about my PCB, however it seems to work fine when I let it continue. I assume that these are undefined integrity (IBIS or similar) libraries. Actually they are probably loops in the tracks. These loops may be under pads and thus hard to find. I ran into this on a board I was doing in P99SE and found that after it complained most signals would work but a few would not simulate. I later brought the board into DXP and DXP comlained that the signals had loops in them and thus could not be simulated. One loop was obvious, but others were under pads so hard to find without DXP pointing out the location. Protel explained that this was due to the agorithm using the tracks not the copper. I fixed the loops and SI worked great. So I should probably get DXP back to find these kind of errors... How do you define the IBIS (or protel library file) to use for each component?? Once you take over a net you can double click on a pin in the net and change the model and stimulus for that pin. Is there a way to assign a component a whole IBIS file (ie the IBIS file for that component includign pins etc) as opposed to just each individual pin?? I was thinking in terms of a component properties entry or similar. ie In the PCB or Schematic workflow... * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] signal integrity
the copper. I fixed the loops and SI worked great. So I should probably get DXP back to find these kind of errors... Well it does do a bit better job at it, and from the sounds of it the first Service pack will fix almost all the issues and requests for improvements. Once you take over a net you can double click on a pin in the net and change the model and stimulus for that pin. Is there a way to assign a component a whole IBIS file (ie the IBIS file for that component includign pins etc) as opposed to just each individual pin?? I was thinking in terms of a component properties entry or similar. ie In the PCB or Schematic workflow... This is another area where DXP improved things. It is much easier to assign models to a component and they stay with it since you assign them while creating an integrated library. I have noticed with 99SE that once you assign a model to one pin the other pins of that type get most of the fields from that one. Unfortunately not all the fields carry over. Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] signal integrity
Once you take over a net you can double click on a pin in the net and change the model and stimulus for that pin. Is there a way to assign a component a whole IBIS file (ie the IBIS file for that component includign pins etc) as opposed to just each individual pin?? I was thinking in terms of a component properties entry or similar. ie In the PCB or Schematic workflow... This is another area where DXP improved things. It is much easier to assign models to a component and they stay with it since you assign them while creating an integrated library. I have noticed with 99SE that once you assign a model to one pin the other pins of that type get most of the fields from that one. Unfortunately not all the fields carry over. In 99SE if you just go to Reports - Signal Integrity, then it shows lots of info, including two sections... One of the sections is labelled: ICs with valid models the other is called: ICs With No Valid Model From this, I thought that maybe somewhere you could specify (per component) what IBIS file to use to obtain the component characteristics. I can't seem to find anything on this in any of the help files however... :( * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] signal integrity
: [PEDA] signal integrity the copper. I fixed the loops and SI worked great. So I should probably get DXP back to find these kind of errors... Well it does do a bit better job at it, and from the sounds of it the first Service pack will fix almost all the issues and requests for improvements. Once you take over a net you can double click on a pin in the net and change the model and stimulus for that pin. Is there a way to assign a component a whole IBIS file (ie the IBIS file for that component includign pins etc) as opposed to just each individual pin?? I was thinking in terms of a component properties entry or similar. ie In the PCB or Schematic workflow... This is another area where DXP improved things. It is much easier to assign models to a component and they stay with it since you assign them while creating an integrated library. I have noticed with 99SE that once you assign a model to one pin the other pins of that type get most of the fields from that one. Unfortunately not all the fields carry over. Robert D. LaMoreaux * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] signal integrity
It's very easy to use, you just set up what the output device is, what the input device is (in terms of pins) on a particular net. You set up the output and input device family Then you can transmit a waveform (rising edge, falling edge, clock) down the line. And get the waveform at each node. I wouldn't expect the voltage levels to be good for anything analog based, however if dealing with a digital system (at the lower speeds where an error in the calculations won't be catastrophic) it is very handy for a quick idea of the min/max voltages on the line and whether you are borerline on the threshold voltages for whatever signalling you're using. I assume that if you used actual manufacturer's IBIS files (as opposed to simple logic family buffers) then the accuracy would increase slightly. I'm not too sure whether it takes into account such things as varying plane spacing and other oddities such as via-via capacitence etc (ad nauseam). You could test this yourself of course. I will probably test it a little later. - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Friday, October 11, 2002 9:12 AM Subject: Re: [PEDA] signal integrity Robert and Bevan, While I have not done any playing around with Protels Signal Integrity capability, primarily because I haven't had the time and I know it will take some study time to understand it's implementation and proper usage, and secondarily because I know that models are somehow involved which means you have to have a model for everything involved, which usually means that you have to build some, and to do that properly, and make sure the ones you have are good, you have to fully understand the models. Anyway, even though I do not know anything about Protels implementation, I have been following your posts on this thread here in the forum, and one thing that was stated here kind of reached out and hit me over the head with a club sized question mark. If I understand what you have said regarding loops under pads, it appears that you are actually saying that Protel (in either the 99 SE or DXP incarnation) cannot distinguish that the continuity of the trace merged with (as it were) the continuity of the pad, or possibly a better way to put it might be that the signal trace transitioned into a different, shall we say conductor. This is a little scary to me, in that it appears that it would therefore be making improper calculations, especially if the calculations consider that portion of the trace that extends under the pad as an extension or continuation of the same trace for that specific length (whether it be in addition to or in place of the characteristics of the pad itself). It would appear that it may be ignoring the change in conductor characteristics, and that from the perspective of capacitance (being certainly more with respect to adjacent planes) and inductance (being probably less), which both will effect impedance at least to the point of being a discontinuity, and more importantly from the perspective cross talk due to the change in environment to adjacent conductors, etc., etc.. All of this prompts me to wonder and question whether or not Protel takes things that may drastically affect the characteristics of the signal conductor into account, such as changes in conductor width, vias, and transitions to different layers (with different relationships to planes (read distances)). Quite possibly I am worrying about things that appear to be trivial to most, and quite possibly I am thinking of Protels SI capability far beyond its intended design, but I am thinking of its usability and accuracy in terms of a recent design which used two 16 bit LVDS controlled impedance differential data busses operating at 500 MHz between 3 large BGA's, with BGA termination packs in the middle of the whole thing. One of the very unfortunate side effects if using high density BGA's is the fact that you are sometimes forced to use vias to get into or out of the connection array, which forces you to use these vias on a signal conductor that you otherwise would never dream of using a via on. At these speeds, and especially in a controlled impedance environment, these kinds of things, and things like recognizing a loop under a pad that in reality is not even there from the electrical perspective, make me wonder just what the Protel (99SE/DXP) Signal Integrity capabilities really are, and whether or not it is even realistically usable, and therefore worth the time to learn how to use. In my recent designs I have dealt with one RF Engineer who really is worried about the size and shape of the pads on the components of a 1 GHz synthesizer, down to the point of the direction that the trace has to enter the pad, and with another RF Engineer who wants to use 20 mil controlled impedance traces which go directly into the pads
Re: [PEDA] signal integrity
I did play round with it a while ago, actually testing some of our design centres IBIS models to see if they converted correctly. The engineer involved in writing the models was quite interested and the results I got when running waveforms around 150MHz seemed to give the sort of ringing and results as would be expected from our test boards. The prop delays of the traces however never seem to be exactly as calculated and if you really need accurate results you have to measure using a correctly deskewed scope. Bevan Weiss [EMAIL PROTECTED] on 11/10/2002 07:50:21 AM Please respond to Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] cc:(bcc: Clive Broome/sdc) Subject: Re: [PEDA] signal integrity It's very easy to use, you just set up what the output device is, what the input device is (in terms of pins) on a particular net. You set up the output and input device family Then you can transmit a waveform (rising edge, falling edge, clock) down the line. And get the waveform at each node. I wouldn't expect the voltage levels to be good for anything analog based, however if dealing with a digital system (at the lower speeds where an error in the calculations won't be catastrophic) it is very handy for a quick idea of the min/max voltages on the line and whether you are borerline on the threshold voltages for whatever signalling you're using. I assume that if you used actual manufacturer's IBIS files (as opposed to simple logic family buffers) then the accuracy would increase slightly. I'm not too sure whether it takes into account such things as varying plane spacing and other oddities such as via-via capacitence etc (ad nauseam). You could test this yourself of course. I will probably test it a little later. - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Friday, October 11, 2002 9:12 AM Subject: Re: [PEDA] signal integrity Robert and Bevan, While I have not done any playing around with Protels Signal Integrity capability, primarily because I haven't had the time and I know it will take some study time to understand it's implementation and proper usage, and secondarily because I know that models are somehow involved which means you have to have a model for everything involved, which usually means that you have to build some, and to do that properly, and make sure the ones you have are good, you have to fully understand the models. Anyway, even though I do not know anything about Protels implementation, I have been following your posts on this thread here in the forum, and one thing that was stated here kind of reached out and hit me over the head with a club sized question mark. If I understand what you have said regarding loops under pads, it appears that you are actually saying that Protel (in either the 99 SE or DXP incarnation) cannot distinguish that the continuity of the trace merged with (as it were) the continuity of the pad, or possibly a better way to put it might be that the signal trace transitioned into a different, shall we say conductor. This is a little scary to me, in that it appears that it would therefore be making improper calculations, especially if the calculations consider that portion of the trace that extends under the pad as an extension or continuation of the same trace for that specific length (whether it be in addition to or in place of the characteristics of the pad itself). It would appear that it may be ignoring the change in conductor characteristics, and that from the perspective of capacitance (being certainly more with respect to adjacent planes) and inductance (being probably less), which both will effect impedance at least to the point of being a discontinuity, and more importantly from the perspective cross talk due to the change in environment to adjacent conductors, etc., etc.. All of this prompts me to wonder and question whether or not Protel takes things that may drastically affect the characteristics of the signal conductor into account, such as changes in conductor width, vias, and transitions to different layers (with different relationships to planes (read distances)). Quite possibly I am worrying about things that appear to be trivial to most, and quite possibly I am thinking of Protels SI capability far beyond its intended design, but I am thinking of its usability and accuracy in terms of a recent design which used two 16 bit LVDS controlled impedance differential data busses operating at 500 MHz between 3 large BGA's, with BGA termination packs in the middle of the whole thing. One of the very unfortunate side effects if using high density BGA's is the fact that you are sometimes forced to use vias to get into or out of the connection array, which forces you to use these vias on a signal conductor that you otherwise would never dream of using a via
[PEDA] signal integrity
I've just started playing around with the signal integrity aspect of Protel99SE and am quite pleased with it... It always says that there are warnings about my PCB, however it seems to work fine when I let it continue. I assume that these are undefined integrity (IBIS or similar) libraries. How do you define the IBIS (or protel library file) to use for each component?? How does protel store the simulation(signal integrity) libraries? Why does it not import so many IBIS files, it always complains the the file load failed. I've only managed to get a single one working, that's the CY22393FC IBIS file. Any suggestions as to how to rememdy this, or will I have to dig around in the IBIS specifications and insure that the files I wish to import are all correctly defined? Thanks, Bevan Weiss * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Re: [PEDA] Signal Integrity dialog locks up.
hmmm it's been years since I've played with programming under MS-Win~1 for multi-proc systems I think the OS will obviously take advantage of the multi-proc (and the OS scheduler may schedule separate processes of apps on different processors), but I think (if I recall) the applications have to sense and use (and set ProcessorAffinity) for its respective *threads*, with those types of system calls to the kernel in order for the threads to take advantage of the multi-proc (Winnt and Win2k of course). I do not know if Protaltium implements that or not And there is probably some extra shared memory management and perhaps marshalling of resources that would need to be written (which is fodder for bugs and crashing! so hey, maybe they did ;-) just kidding)... Does anyone else know off the top of their heads about the Processor_Affinity stuff? I think this is correct... (It's been a while) I know for example, my multitrack recording software does purposefully implement this stuff by hook or by crook for the threads and plug-in effects running on different processors. The multitrack recording software boasts about only a ** 35% ** increase in performance with a dual processor system versus the single processor system, pound for pound (or dyne for dyne or slug for slug.. ;-). But a dual processor system is better for multitrack type software to keep those separate threads on different processors in pseudo/apparent in-process dll attachment type configuration (without having to enter/exit from the host CPU to another machine to process things at high data rates)... I think 2 computers might be better (but more costly???) as a second computer at the same speed would be 100%... but then you have file integrity, revision control, possible merge-ification issues and multiple copies of things but you may gain some crash safe redundancy... I wonder how this would behave on the new Dell's dual 1.7GHz processor 400MHz memory bussed RDRAM machines? (which I suppose in theory brings the bus speed to 200 MHz for each processor in theory... which is not much more than 133MHz) I'd wait for 800MHz busses -chris shoe shine boy assistant bottle washer -Original Message- From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 7:49 PM To: Protel EDA Forum Subject: Re: [PEDA] Signal Integrity dialog locks up. On 01:20 PM 8/7/2001 -0700, Brad Velander wrote: Daryl, welcome to the Protel(ooops, Altium) club. We all meet here regularly to lick our wounds, share war stories and generally commiserate about our problems. You will make a suitably good initiate candidate, you seem to have passed all the tests. 8^ Seriously, I would warn you against looking for wonderful performance increases from going to dual processors. There are things to be said for dual processors but it doesn't necessarily make Protel that much better. I will not respond...I will not...I will notArghh. The point about dual-proc systems is that they do not experience the latencies single-proc computers do experience, routinely, btw, NOT that they do the same job quicker (at least for programs that aren't written to take advantage of the second proc.) What they DO offer is a way out of sitting around while the computer is locked up tight, at least allowing the user to fire up Eudora and write a quick rant against Protel, do a net search for component data, write a proposal (or that damned monthly report), open a second instance of Protel, (not generally recommended, but I've done it to my advantage in the past.) or otherwise utilize the PC whilst the resource hog blindly grinds away at its task, happy in not knowing that it hasn't succeeded in stopping all other work. I say it again. Brad, you have to try personally running under a dual-proc before judging this subject. Admittedly, IFf you can afford dual computers, that's one way to go. But it won't solve the latency problems. 100% is 100%, regardless. Ever auto-routed two boards simultaneously on a single computer? It CAN be done. Two instances. Isolate 1st to Proc 1, second to Proc 2. respectfully, aj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Signal Integrity dialog locks up.
Choosing Tools | Signal Integrity... locks up the Protel session, requiring process kill using Win2000 TaskMgr. There is no GP fault, in fact TM says it's running, however Protel does not respond to keyboard or mouse input or system redraw messages. Any clues on where to begin looking for the problem? Darryl Newberry Hardware Engineer Blazie, a division of Freedom Scientific, Inc 2850 SE Market Pl #3 Stuart, FL 34997 (561) 223 6443 x2015 tel (561) 223 6413 fax http://www.freedomscientific.com/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Daryl, Mike's comment is very valid, Protel has many typical processes which show no outward signs of actually executing while they are running. For all intent and purposes you think the machine has locked but that is simply not the case. Other good examples of this are database linking, printing or gerbering large panelized designs, sometimes the software reports 99% completion in the first 10 seconds of running a particular process. It can take 20 minutes or more to complete the last 1%. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: Michael Reagan [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 9:35 AM To: Protel EDA Forum Subject: Re: [PEDA] Signal Integrity dialog locks up. . Choosing Tools | Signal Integrity... locks up the Protel session, requiring process kill using Win2000 TaskMgr. There is no GP fault, in fact TM says it's running, however Protel does not respond to keyboard or mouse input or system redraw messages. Any clues on where to begin looking for the problem? Darryl, You didn't say how long you saw it locked up. Let it run, Some of my tasks take several hours. It comes back about 99 % of the time with the right answer. Just another bug Altimatum can fix Mike Reagan EDSI Frederick Md * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
If I may pose the question another way: Has anybody on the list _actually_used_ the Protel SI package to evaluate waveforms? What was your experience, was it useful in isolating problems? Did you have any issues with configuration or operation? Darryl Newberry Hardware Engineer Blazie, a division of Freedom Scientific, Inc 2850 SE Market Pl #3 Stuart, FL 34997 (561) 223 6443 x2015 tel (561) 223 6413 fax http://www.freedomscientific.com/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Re: [PEDA] Signal Integrity dialog locks up.
Re: [PEDA] Signal Integrity dialog locks up.
I used the old version 3 simulator for some simple stuff, but I had some problems. It has been so long, I don't remember the details, but I do remember that the program did not give any useful indication of what was wrong. It made debugging a simulation pretty painful. We ended up buying a seperate piece of software for simulations. It is better to simplify the circuits as much as possible and bring the simulation up in small pieces. This makes it a lot easier to figure out whats wrong when the simulation blows up. Since our simulation schematics are always quite different than the boards schematics, there is no benefit to using Protel over our other software. Because of this, I haven't tried any simulations in Protel SE99, so I can't comment on any improvements over Version 3. Just my $0.02... ~~ Cliff Gerhard, P.E. Director - EE Group E-M Designs, Inc. 32122 Camino Capistrano Suite 200 San Juan Capistrano, CA 92675 PH 949.661.3016 x 501 FX 949.661.3017 www.GerhardEng.com www.emdesigns.com -Original Message- From: Darryl Newberry [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 10:13 AM To: Protel EDA Forum Subject: Re: [PEDA] Signal Integrity dialog locks up. If I may pose the question another way: Has anybody on the list _actually_used_ the Protel SI package to evaluate waveforms? What was your experience, was it useful in isolating problems? Did you have any issues with configuration or operation? Darryl Newberry Hardware Engineer Blazie, a division of Freedom Scientific, Inc 2850 SE Market Pl #3 Stuart, FL 34997 (561) 223 6443 x2015 tel (561) 223 6413 fax http://www.freedomscientific.com/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Andrew J Jenkins wrote: Hmm...here's one for my guru friends to think about. Can one preset process prioritization for tasks called to the NT/2k task manager, and are SI and other Protel processes transparent enough to avail themselves to such manipulation? If so, one might admittedly lose a bit of execution speed for the affected task, but gain in still being able to use their PC, at least those who are hampered by a single-proc system and have to experience these difficulties... The NT/2K task manager lets you view and manipulate the CPU allocation and task priority at the process level. An application is typically a single process. If you look at the task manager while running Protel, you will see an entry called Client99SE.exe. If you right click on this you can set the process priority and CPU affinity (in systems with more than one CPU). The Protel application is a single process. Within each process, there may be more than one executable thread. On systems with more than one CPU, the OS can assign different threads from a single process to different CPU's. An application must be explicitly written to use multiple threads in order to benefit from multiple CPU's. It appears that launching Protel 99SE creates about twelve different threads but all but one of them (the main thread) are normally in the stopped state. I do not know what these particular threads are intended for but additional threads are created, executed and destroyed when various Protel processes are executed. As far as I know, there is no way for a user to change the priority or CPU affinity for individual process threads using the standard OS user interface. These parameters can certainly be altered programatically when each thread is created but this would have to be explicitly added by Protel programmers. John Williams * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
OK, thanks everybody for your input on this issue. The list is a really great resource. The reality is I have about 6 board designs that have to go out for fast turn proto this week and hopefully go into a commercial UL/FCC/CE/USB ready product by September. I don't know what all YOU people do all day long, but my boss doesn't want me to sit on my fat hairy ass for hours waiting for $8000 bloatware to complete basic signal analysis. (No offense to those whose bosses do--and please tell me where to send my resume! ;-) ) In summary, after using Protel for about 4 weeks to TRY to get a lot of real work done, I have formed the opinion that it just basically sucks--lots of cutesy trees, tabs, windows, icons and menus, lots of feature-itis, but not much real engineering guts or ease of use. THE EMPEROR HAS NO CLOTHES!!! And yes I CAN talk because I've spent the last 10 years designing various commercial products with P-Cad, PADS, Accel/Tango EDA, and now Protel. About the only positive thing I can say about Protel right now is that I am glad that I wasn't the engineer who recommended purchasing two seats. Unfortunately I am more or less forced to use it. OK, it _is_ better than Xacto knife, Bishop Graphics, and a light table. ;-) My apologies to those who have an irrational emotional attachment to Protel. When I commit , I want results. I know it's not an apples-apples comparison, but Specctra V10 routed the entire board 100%, in 5 passes over 2 layers, with more or less fab-ready results, in about 20 seconds, using the default configuration. This gave me a warm fuzzy feeling, even when considering we blew almost $11K on it with all the bells and whistles. Now for another couple of questions: 1) Can anybody recommend a professional level SI/EMI simulator add-in/on that integrates with either Protel or Specctra--one that actually works? 2) Since I have to keep on using Protel, should I get a dual CPU workstation? What specs for W2K? Darryl Newberry Hardware Engineer Freedom Scientific, Inc 2850 SE Market Pl Stuart FL 34997 (561) 223-6443 http://www.freedomscientific.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Hyperlynx sells a signal integrity/emi tool that is supposed to be great. I Use it before layout only, to set trace widths and look at signals vs diferent termination schemes. I have yet to successfully use the signal integrity tools in Protel. They don't seem, to be its shining star. The basic layout, and auto-router are OK, but certainly not up to Specctra standards. In summary, I think that the schamtic entry and board layout functionality of Protel is as good as anything I have seen, and by reading the correspondence on this list would say that the more expensive packages are not better in this respect. On the other hand, the addition of Specctra is wise for auto-routing. Do any other basic layout packages do a better auto-routing job? Just as a place to say this, I wish that there was a way that good FPGA tools were integrated w/ the schematic capture, package (w/ good footprints avail for layout). I spend most of my time enterering 200+ pin symbols into the schematic library, just to have to change them manually when I rev the part. mike -Original Message- From: Darryl Newberry [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 12:49 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Signal Integrity dialog locks up. OK, thanks everybody for your input on this issue. The list is a really great resource. The reality is I have about 6 board designs that have to go out for fast turn proto this week and hopefully go into a commercial UL/FCC/CE/USB ready product by September. I don't know what all YOU people do all day long, but my boss doesn't want me to sit on my fat hairy ass for hours waiting for $8000 bloatware to complete basic signal analysis. (No offense to those whose bosses do--and please tell me where to send my resume! ;-) ) In summary, after using Protel for about 4 weeks to TRY to get a lot of real work done, I have formed the opinion that it just basically sucks--lots of cutesy trees, tabs, windows, icons and menus, lots of feature-itis, but not much real engineering guts or ease of use. THE EMPEROR HAS NO CLOTHES!!! And yes I CAN talk because I've spent the last 10 years designing various commercial products with P-Cad, PADS, Accel/Tango EDA, and now Protel. About the only positive thing I can say about Protel right now is that I am glad that I wasn't the engineer who recommended purchasing two seats. Unfortunately I am more or less forced to use it. OK, it _is_ better than Xacto knife, Bishop Graphics, and a light table. ;-) My apologies to those who have an irrational emotional attachment to Protel. When I commit , I want results. I know it's not an apples-apples comparison, but Specctra V10 routed the entire board 100%, in 5 passes over 2 layers, with more or less fab-ready results, in about 20 seconds, using the default configuration. This gave me a warm fuzzy feeling, even when considering we blew almost $11K on it with all the bells and whistles. Now for another couple of questions: 1) Can anybody recommend a professional level SI/EMI simulator add-in/on that integrates with either Protel or Specctra--one that actually works? 2) Since I have to keep on using Protel, should I get a dual CPU workstation? What specs for W2K? Darryl Newberry Hardware Engineer Freedom Scientific, Inc 2850 SE Market Pl Stuart FL 34997 (561) 223-6443 http://www.freedomscientific.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Daryl, welcome to the Protel(ooops, Altium) club. We all meet here regularly to lick our wounds, share war stories and generally commiserate about our problems. You will make a suitably good initiate candidate, you seem to have passed all the tests. 8^ Seriously, I would warn you against looking for wonderful performance increases from going to dual processors. There are things to be said for dual processors but it doesn't necessarily make Protel that much better. Some of the problems that I have experienced which seem performance based have also been experienced by others using much faster CPUs or even dual CPUs if my memory serves me correctly. It seems that Protel has discovered ways to thwart nearly all performance increase attempts. There is nothing but the eventual event timeout which will bring the sleeping/looping processes back to life, and it seems to be timer related rather then performance speed related. That's my feeling anyway, some other more knowledgeable people may disagree but others experience my same issues and problems with much beefier machines. They have saved me from stamping my feet up and down and yelling for a better machine only to find the problems may not disappear. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: Darryl Newberry [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 12:49 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Signal Integrity dialog locks up. OK, thanks everybody for your input on this issue. The list is a really great resource. SNIP My apologies to those who have an irrational emotional attachment to Protel. When I commit , I want results. I know it's not an apples-apples comparison, but Specctra V10 routed the entire board 100%, in 5 passes over 2 layers, with more or less fab-ready results, in about 20 seconds, using the default configuration. This gave me a warm fuzzy feeling, even when considering we blew almost $11K on it with all the bells and whistles. Now for another couple of questions: 1) Can anybody recommend a professional level SI/EMI simulator add-in/on that integrates with either Protel or Specctra--one that actually works? 2) Since I have to keep on using Protel, should I get a dual CPU workstation? What specs for W2K? Darryl Newberry Hardware Engineer Freedom Scientific, Inc 2850 SE Market Pl Stuart FL 34997 (561) 223-6443 http://www.freedomscientific.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
works? 2) Since I have to keep on using Protel, should I get a dual CPU workstation? What specs for W2K? Darryl, Get two computers. One to do Sim and routing and one for layout. I started with a dual CPU and it never helped. But two computers work great , the second one can be a low end system but get tons of memory. Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Correct me if I am wrong but Protel just started using IBIS models SPK6 for there signal simulation. Ted -Original Message- From: Mike Ingle [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 3:27 PM To: Protel EDA Forum Subject: Re: [PEDA] Signal Integrity dialog locks up. Hyperlynx sells a signal integrity/emi tool that is supposed to be great. I Use it before layout only, to set trace widths and look at signals vs diferent termination schemes. I have yet to successfully use the signal integrity tools in Protel. They don't seem, to be its shining star. The basic layout, and auto-router are OK, but certainly not up to Specctra standards. In summary, I think that the schamtic entry and board layout functionality of Protel is as good as anything I have seen, and by reading the correspondence on this list would say that the more expensive packages are not better in this respect. On the other hand, the addition of Specctra is wise for auto-routing. Do any other basic layout packages do a better auto-routing job? Just as a place to say this, I wish that there was a way that good FPGA tools were integrated w/ the schematic capture, package (w/ good footprints avail for layout). I spend most of my time enterering 200+ pin symbols into the schematic library, just to have to change them manually when I rev the part. mike -Original Message- From: Darryl Newberry [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 12:49 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Signal Integrity dialog locks up. OK, thanks everybody for your input on this issue. The list is a really great resource. The reality is I have about 6 board designs that have to go out for fast turn proto this week and hopefully go into a commercial UL/FCC/CE/USB ready product by September. I don't know what all YOU people do all day long, but my boss doesn't want me to sit on my fat hairy ass for hours waiting for $8000 bloatware to complete basic signal analysis. (No offense to those whose bosses do--and please tell me where to send my resume! ;-) ) In summary, after using Protel for about 4 weeks to TRY to get a lot of real work done, I have formed the opinion that it just basically sucks--lots of cutesy trees, tabs, windows, icons and menus, lots of feature-itis, but not much real engineering guts or ease of use. THE EMPEROR HAS NO CLOTHES!!! And yes I CAN talk because I've spent the last 10 years designing various commercial products with P-Cad, PADS, Accel/Tango EDA, and now Protel. About the only positive thing I can say about Protel right now is that I am glad that I wasn't the engineer who recommended purchasing two seats. Unfortunately I am more or less forced to use it. OK, it _is_ better than Xacto knife, Bishop Graphics, and a light table. ;-) My apologies to those who have an irrational emotional attachment to Protel. When I commit , I want results. I know it's not an apples-apples comparison, but Specctra V10 routed the entire board 100%, in 5 passes over 2 layers, with more or less fab-ready results, in about 20 seconds, using the default configuration. This gave me a warm fuzzy feeling, even when considering we blew almost $11K on it with all the bells and whistles. Now for another couple of questions: 1) Can anybody recommend a professional level SI/EMI simulator add-in/on that integrates with either Protel or Specctra--one that actually works? 2) Since I have to keep on using Protel, should I get a dual CPU workstation? What specs for W2K? Darryl Newberry Hardware Engineer Freedom Scientific, Inc 2850 SE Market Pl Stuart FL 34997 (561) 223-6443 http://www.freedomscientific.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
I use Protel's SI tools for controlled impedance calculations. My results have been within +/- 5 % of any of the same analysis we have performed by TYCO, KCA, or other board houses using top of the line Polar Instruments tools.I have a great degree of confidence with the tools, you just have to set it up and walk away from it for a few hours. Thats the only drawback . We have finally obtained some actual measured data for crosstalk on our backplanes which I am attempting to verify against Protels crosstalk tools. It is taking a while to verify due to my lack of time for this side project. Mike Reagan EDSI * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
I've used the Signal intergrity utility and it was helpful and matched what I was seeing on the problem design I inherited. I wish the problem I currently have (1 buffer and 8 or 64 memory chips) could be run in it, but it would be difficult with two boards and a connector involved not to mention the design being done in an old version of PCAD. I have not had Protel hang in quite a while, and the last time I found was due to improper spice simulation values on parts in the schematic. I just pulled it up on a smaller design and nd ran some signals without any glitches or delays. I do wish it would just update the waveanalyzer everytime instead of opening a new window since I end up getting tons of windows. I have found that Protel is sensitive to DLL HELL, and I have had similar problems when using WIn9x with other programs written with Borland tools (delphi). At one point I found multiple versions of a Borland DLL were causing problems. I also had a plug in install go screwy and I ended up unistalling Protel and reinstalling. Sorry you're having such troubles. Have your checked the rest of your Windows Systems' integrity? And no I am not in love with Protel. I do feel it is the best value currently for a company doing small quantities and thus not able to justify $40K+ for two seats. Rob * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Re: [PEDA] Signal Integrity dialog locks up.
I have used it a couple of times to check our companies IBIS modals and can say that it does produce waveforms that do appear to be what is expected. But a couple of points you have to watch out for: Any major complexity will seriously degrade the speed, I copy the trace of interest and the bare minimum components to a new board and then design the schematic and netlist etc. I use dual Pentium 300 Mhz comp so thats also an issue. The IBIS converter seems to work as expected (on our IBIS files at least) and these can then be imported into SI and the speed grade of the process selected. First waveforms may look nothing like what is expected as any load capacitance has not settled. Set longer times. Accuracy of the waveform with comparison to a real life PCB has not been thouroughly checked, but it seems to have all the right bumps and shape and reflections as expected for a particular test waveform. Mike Reagan did a comparison of the controlled impedance tools and posted the results on 26-9-2000. He found good accuracy between Protel and other tools with around +/- 10 % variation. ___ Clive Broome IDT Sydney Design CentrePh: +61 2 9763 3513 8 Bayswater Dr, HomebushFax:+61 2 9763 3409 Sydney, NSW, 2127 Email:[EMAIL PROTECTED] Australia Australia's Leading Semiconductor Designers --- Darryl Newberry [EMAIL PROTECTED] on 08/08/2001 03:12:35 AM Please respond to Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] cc:(bcc: Clive Broome/sdc) Subject: Re: [PEDA] Signal Integrity dialog locks up. If I may pose the question another way: Has anybody on the list _actually_used_ the Protel SI package to evaluate waveforms? What was your experience, was it useful in isolating problems? Did you have any issues with configuration or operation? Darryl Newberry Hardware Engineer Blazie, a division of Freedom Scientific, Inc 2850 SE Market Pl #3 Stuart, FL 34997 (561) 223 6443 x2015 tel (561) 223 6413 fax http://www.freedomscientific.com/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Andrew, I thought that I had covered my ass sufficiently on my post. I mentioned that there were things to be said for dual processors but that the same old problems would probably still plague Protel's performance. Wasn't that enough, or is there something wrong with that statement? I left the door wide open for you if you wanted to comment about the dual processors, I know you are an ardent fan of the dual processors. I only commented that the seemingly dead process problems with 'Protel' did not seem to improve significantly with the increased performance of dual processors and that it seemed time limited (some form of process timeout) rather then performance limited. The problem with public forums is that you can never cover your ass enough to everybody's liking. Andrew, I don't know if you think that I am one who has argued against you on this dual processor issue, I have not. However, I can't get my company to dish out for a single processor at even 1Ghz so a dual is out of the question. I do understand the layman's version of what a dual does for you and it matches well with your more detailed technical description. That is why I left the door open so wide, I figured that you might step up to the plate and take a crack at the ball. Have a good one buddy, however please try just a little bit harder to recognize friend from foe. I hate friendly fire incidents, they are so tragic. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com -Original Message- From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 4:49 PM To: Protel EDA Forum Subject: Re: [PEDA] Signal Integrity dialog locks up. SNIP I say it again. Brad, you have to try personally running under a dual-proc before judging this subject. Admittedly, IFf you can afford dual computers, that's one way to go. But it won't solve the latency problems. 100% is 100%, regardless. Ever auto-routed two boards simultaneously on a single computer? It CAN be done. Two instances. Isolate 1st to Proc 1, second to Proc 2. respectfully, aj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Excellent advice, thanks. I looked at a dual 750 at one point a few months back, but I.T. gave me a vanilla Dell Optiplex GX110. I am already using 2 systems , W2K for P99, MS Orifice, etc, and W98 for certain embedded dev tools that require it, legacy Tango designs, DOS things, blah blah. I guess I'll upgrade to 3 boxes?!? But hey it's cool, I already have a 4-port KVM switch! ;-) Now if I could just make several boxes run distributed now THAT would be cool. Any linux gurus out there? -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 5:08 PM To: Protel EDA Forum Subject: Re: [PEDA] Signal Integrity dialog locks up. works? 2) Since I have to keep on using Protel, should I get a dual CPU workstation? What specs for W2K? Darryl, Get two computers. One to do Sim and routing and one for layout. I started with a dual CPU and it never helped. But two computers work great , the second one can be a low end system but get tons of memory. Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity Designator Mapping
At 09:25 PM 3/20/01 -0800, Jim Mcgrath wrote: I don't know if this helps but connectors are typically J designators. I use CN for cap networks. I hope I didn't miss the point as Mr. Lomax catches me on from time to time. I hope that Mr. Mcgrath and others are not shy to respond to this list because of my presence here. Anyway, I'll be at PCB Design Conference West for the next two days. As to the matter at hand, I thought of writing about this but did not have time. Changing the CN designators to J or P would not only be more standard, but it would also probably solve the signal integrity analzyer problem. As to which is to be used, J or P, that is a whole other can of worms. Some people just use J. But that standard I know has J indicating a stationary connector and P a mobile connector, relatively speaking. Generally a P plugs into a J. If both are mobile, then the male (with pins) is P, the female (with sockets) is J. The signal integrity analyzer we presently have is only a taste of the future; it is not a mature tool. I'd expect it to have user-definable models in the future, just as the 3-D board display will, I expect, have user-definable models. (I'm not panning the signal-integrity analyzer. I haven't used it; some users have reported good results with it. But I don't think we can alter the models.) [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Signal Integrity and Long (Ringing) Traces
Anyone had any meaningful results when trying to run SI on long traces. Im attempting to characterise some of our boards and chips to check Protel against the real thing. I can load in the ibis model of the chip OK. I am running the board using a 250 MHz square wave and 100 mm unterminated trace length between the IC and an SMB socket. But Im getting a nice looking square wave with no ringing. A funny thing is that SI thinks the connector is an IC even though it is defined as a connector. ___ Clive Broome IDT Sydney Design CentrePh: +61 2 9763 3513 8 Bayswater Dr, HomebushFax:+61 2 9763 3409 Sydney, NSW, 2127 Email:[EMAIL PROTECTED] Australia Australia's Leading Semiconductor Designers --- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
