Re: [gem5-users] Question about Multitasking in Full System mode Single CPU

Hi Taeklim, On Wed, Nov 28, 2018 at 4:04 PM Taeklim Kim wrote: > Hi all, > > I'm using the Full system mode to run 2 benchmarks(SPEC) in single core, > and I tried to check is there any context switch happens. > > But I think Gem5 fs mode doesn't support multiple workload in single core, > becau

Re: [gem5-users] Simulation time profiling for Gem5 with Garnet2.0

Hi Sumit, You should be able to get this information using gprof. You can run gem5 with gprof by compiling the profiling version (gem5.prof). If you prefer to use the google perf tools ( https://gperftools.github.io/gperftools/cpuprofile.html), then you can compile gem5.perf and use those. Cheers

Re: [gem5-users] [gem5-dev] How to Perform Regression Test

Please see https://gem5.googlesource.com/public/gem5/+/master/TESTING.md for details on how to use the new regression tests. We will be migrating to this interface as soon as we have ported the old tests (hopefully soon). Jason On Wed, Nov 14, 2018 at 5:13 AM Ciro Santilli wrote: > Hi Liang, >

Re: [gem5-users] Cache Trace Debugging

Hi Tassneem, There are a number of cache debug flags. See https://gem5.googlesource.com/public/gem5/+/master/src/mem/cache/SConscript#44 or use gem5.opt --debug-help to see a list. There are likely more relevant debug flags in src/mem/cache/tags, too. Cheers, Jason On Fri, Nov 16, 2018 at 12:02

Re: [gem5-users] Issue with the simulator and image booting

Just to quickly chime in here... I haven't yet automated an Ubuntu setup that just works yet, but I might > do that at some point. The only reasonable reason IMHO to use Ubuntu > is if you need a very difficult to compile package that Buildroot does > not have. Yeah, automating Ubuntu is a major

Re: [gem5-users] installation of gem5 on OS X

Hey Brandon, Does this look like another place in syscall_emul where we need to have a ifdef guard for linux? It looks like this was recently committed by you. https://gem5-review.googlesource.com/c/public/gem5/+/12112 Thanks, Jason On Wed, Sep 26, 2018 at 12:26 PM aditya pendyala wrote: > Hi

Re: [gem5-users] serial8250: too much work for irq4

Hi Ashok, This isn't an error, just information. It's coming from the serial emulator saying there may be issues with the output from the serial port (e.g., into m5out/system_terminal_whatever). Jason On Tue, Aug 21, 2018 at 7:54 AM Ashok Sathyan wrote: > Dear all, > > While running FS mode fo

[gem5-users] Update on new testing infrastructure

Hey all, I'm excited to announce that we've finally merged the new testing infrastructure into the mainline! Big thanks to Sean Wilson for all of the effort he put in to building it from scratch! Now, to test to make sure your changes don't break anything unexpectedly, you can simply run: cd tes

Re: [gem5-users] Duplicated execution of m5ops

://gem5-users.gem5.narkive.com/bQ8pOq6I/arm64-pseudo-instructions > This was an unanswered mail(?) 3 years ago. The setup is the same: same > disk image and executing a script… > > > > Could I forward this problem to the dev mailing list, or do you want me to > run more tests? >

Re: [gem5-users] Duplicated execution of m5ops

o m5 exit is > called). Do you know where m5 readfile is called (where the rcS is parsed > in FS mode?) > > > > > > > > Best regards > > Kon > > > > > > *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of *Jason > Lowe-Power >

Re: [gem5-users] Duplicated execution of m5ops

Hi Kon, The PARSEC patch file modifies the parsec ROI library so when you run an application like blackscholes, at the beginning of the ROI and at the end of the ROI the stats will be dumped/reset *in the execution of the benchmark!* You are adding in extra dump/reset stats by calling `m5 dumpres

Re: [gem5-users] dumpresetstats in python file?

Hi Jimmy, Yes. The python code is almost exactly what you have. You can use `m5.stats.reset()` and `m5.stats.dump()` from python. See https://gem5.googlesource.com/public/gem5/+/master/src/python/m5/stats/__init__.py#192 . Cheers, Jason On Mon, Aug 13, 2018 at 8:31 AM Jimmy Situ wrote: > Hi, A

Re: [gem5-users] Is it possible to make gem5 exit with status 1 on Linux kernel panic?

Hi Ciro, As far as I know, it's not desired behavior for the exit status to be 0 when a panic happens. It's probably just something that has never come up. Feel free to submit a patch to change this! It looks like something would need to change in `raiseFatalSignal()` in src/sim/init_signals.cc.

Re: [gem5-users] --topology no such option

I believe you need to enable Ruby (--ruby). BTW, I strongly encourage you to understand the runscripts you are using. learning.gem5.org is a good place to start. Jason On Fri, Aug 10, 2018 at 5:37 AM Parmida Vahdatnia < parmida.vahdat...@gmail.com> wrote: > I also tried the flag > > --garnet-ne

Re: [gem5-users] EmulatedDriver in SE mode: initialize the driver

Hi Joao, I'm not sure exactly what the problem is because I haven't used this code in quite some time. However, I would start by making sure the code here ( https://gem5.googlesource.com/public/gem5/+/master/src/sim/syscall_emul.hh#691) is executing. That's what's going to call your emulated drive

Re: [gem5-users] Gem5 build error

const T&) [with T > = unsigned char; std::ostream = std::basic_ostream]': > build/ARM/base/bitunion.hh:446:35: ERROR: type qualifiers ignored on > cast result type [-Werror=ignored-qualifiers] > os << (const unsigned int)t; > > > Is it also because of gcc8?

Re: [gem5-users] Gem5 build error

Hi Thawra, It looks like this pybind11 commit fixes the issue. https://github.com/pybind/pybind11/pull/1396. Last time you sent the email no one had posted a fix to pybind, yet :). I just posted a patch on gerrit. Please download it, test it, and review it on gerrit. If it works for you we'll pus

Re: [gem5-users] 回复： gem5 fails with Assertion `cmdBytesLeft <=MAX_DMA_SIZE' failed

Hi Jimmy, Interesting. I wouldn't be surprised if there was a bug in that code. In fact, the banked L3 doesn't really work as expected. The interleaving bits are the same as the index bits so the effective capacity is actually lower than the parameters since only a subset of the sets can be used.

Re: [gem5-users] 回复： fatal: Number of ISAs (0) assigned to the CPU does notequal number of threads (1)

Hi Jimmy, Oops. I thought I sent this yesterday... sorry :). It looks like you figured it out in the meantime. That branch is a little old. You also need to call createThreads() on the timingCpus. See https://github.com/darchr/gem5/blob/feature/simplefs/configs/myconfigs/system/system.py#L140 cr

Re: [gem5-users] dacapo (java) benchmark suite encounters "SIGSEGV" and "null exception" during timing mode (fs mode) after restarting from a checkpoint

ply that > unimplemented instructions don't cause the problem? Any clues or > suggestions to debug these problems? > > best, > Da Zhang > > > > On Mon, Jul 16, 2018 at 1:32 PM Jason Lowe-Power > wrote: > >> Hello, >> >> Are you seeing any wa

Re: [gem5-users] dacapo (java) benchmark suite encounters "SIGSEGV" and "null exception" during timing mode (fs mode) after restarting from a checkpoint

Hello, Are you seeing any warnings like "warn: Instruction XXX not implemented"? There are many X86 SIMD instructions that are currently unimplemented. I would bet that your application is using some of those instructions and getting 0's as the output instead of the correct value. The "right" wa

Re: [gem5-users] Error when building gem5

Hi Tariq, Thanks for letting us know about this issue. Nikos just merged a change that fixes it: https://gem5-review.googlesource.com/c/public/gem5/+/11429 Cheers, Jason On Tue, Jun 19, 2018 at 11:01 AM Jason Lowe-Power wrote: > HI Tariq, > > You can fix it and submit a patch

Re: [gem5-users] gem5 killed when booting linux

Hello, It looks like your host OS killed the gem5 process "Program terminated with signal SIGKILL, Killed. The program no longer exists." Could you have run out of memory on the host? Jason On Tue, Jun 19, 2018 at 7:54 PM web wrote: > Hi, All > > I am trying to boot my ubuntu with gem5 under

Re: [gem5-users] Running Parsec 3.0 in x86 FS mode with ruby memory

Hi Mayank, The information here: http://www.lowepower.com/jason/creating-disk-images-for-gem5.html and here: http://www.lowepower.com/jason/setting-up-gem5-full-system.html should work with minor changes with Ruby. The first post about creating a disk image should be exactly the same whether you'r

Re: [gem5-users] Error when building gem5

HI Tariq, You can fix it and submit a patch to gerrit :). Likely, you just need #include at the top of addr_range_map.hh. See https://gem5.googlesource.com/public/gem5/+/master/CONTRIBUTING.md for more details. Cheers, Jason On Tue, Jun 19, 2018 at 10:44 AM Tariq Azmy wrote: > Hi, > > I got

Re: [gem5-users] How to attach multiple disk images a simulation with gem5 fs.py?

Hi Ciro, I'm not sure if you can do it with fs.py (I bet not) :). When you set the ide controller up (e.g., pc.south_bridge.ide.disks) it takes a python list of length 2 of disk images. Cheers, Jason On Fri, Jun 15, 2018 at 6:43 AM Ciro Santilli wrote: > Thanks for confirming, > > Feel free t

Re: [gem5-users] Developing a new cpu model

Hi Amir, First, sorry for the late reply. Two answers/comments: 1) There is already a GPU model in gem5 (see src/gpu-compute), and there is also gem5-gpu (https://gem5-gpu.cs.wisc.edu/wiki/). Though, gem5-gpu isn't maintained actively anymore. Also, AMD is currently updating their GPU model. They

Re: [gem5-users] m5 pseudo instructions in KVM mode x86

Hi Mohammad, In KVM mode the magic instructions are mapped to MMIO accesses. (See the implementation of the user-mode side in util/m5/.) There is a specific part of physical memory that is mapped for the magic instructions. For x86 I believe it is somewhere between 3GB and 4GB. See https://github.

Re: [gem5-users] Has anyone ever produced an Spectre or Meltdown proof of concept running on gem5 or would that be feasible?

Ciro Santilli wrote: > Awesome... > > If I were you, I'd do that blog post quick now that the hype is large, > if well presented it could really hit Hacker News :-) > > On Wed, Apr 11, 2018 at 5:36 PM, Jason Lowe-Power > wrote: > > Hi Ciro, > > > > Yeah. In

Re: [gem5-users] Memory models possibilities

Hi Rich, Some answers inline below. Cheers, Jason On Tue, May 29, 2018 at 4:59 PM Richard Brown wrote: > Hello everyone, > > I have been reading several posts in this forum and the gem5 > documentation, I am new with gem5, I have to work with memory subsystem > and I have already changed char

Re: [gem5-users] Failed to find stat 'system.bigCluster.clk_domain.clock' and others

Hi Yara, I'm not very familiar with the power modeling in gem5, but this seems like you found and then fixed a bug! We would really appreciate it if you contributed this change to the mainline. You can find a description of how to do this in the CONTRIBUTING document ( https://gem5.googlesource.co

Re: [gem5-users] Issues in handling compressed data for L3 cache

Hi Srajan, Could you post this on our code review site so the patch creator (Daniel) can take a look? You can register on the site with a google account (e.g., your gmail). Then, you can post a reply on this page: https://gem5-review.googlesource.com/c/public/gem5/+/9741. One possible source of y

Re: [gem5-users] x86 floating point instruction

uncUnitConfig.py and seems like the op lats for > the SIMD functional units are not defined, so I assumed it takes value of 1 > by default. > > I am not really familiar with x86 SIMD extension, so maybe this question > is more related to x86 ISA in general. > > Thanks. > >

Re: [gem5-users] Response for WritebackDirty packets (learning.gem5)

sendReqRetry()" later. > > > > Muhammad Ali Akhtar > Principal Design Engineer > http://www.linkedin.com/in/muhammadakhtar > > On Tue, May 22, 2018 at 3:40 AM, Jason Lowe-Power > wrote: > >> Hello, >> >> No. You should not have a response for Writeba

Re: [gem5-users] Increasing TLB size not working for X86 with O3CPU

ers, Jason On Thu, May 24, 2018 at 9:11 AM Da Zhang wrote: > I am using FS mode. > > On Thu, May 24, 2018 at 12:00 PM, Jason Lowe-Power > wrote: > >> Hi Da, >> >> Are you using SE mode or FS mode? IIRC, the TLB size does nothing in SE >> mode (it doesn&#

Re: [gem5-users] How to run a dynamically linked executable syscall emulation mode se.py in gem5?

Hi Ciro, As you seemed to have figured out, running dynamically linked executables has only been tested for x86_64 native platforms. It *is supported* if your binary is x86 and your native machine is x86. I'm not sure what it would take to get this working for native ARM machines (e.g., simulating

Re: [gem5-users] RISCV ISA : "C" (compressed) extension supported?

e differences were much >>> more significant). >>> >>> I ran into this particular issue only today, though, so I can only say >>> it *seems* *to affect only binaries compíled with C extensions*. >>> >>> I'll run the tests suggested and reply h

Re: [gem5-users] RISCV ISA : "C" (compressed) extension supported?

Hi Marcelo, I'm not sure if RISC-V has been tested with the out of order CPU at all! I'm happy that at least it doesn't completely fail! For you problem of only fetching 1 instruction per cycle... I think it's going to take some digging. My first guess would be that it could be a problem with the

Re: [gem5-users] Increasing TLB size not working for X86 with O3CPU

Hi Da, Are you using SE mode or FS mode? IIRC, the TLB size does nothing in SE mode (it doesn't use a TLB). The TLB is only used in FS mode. Jason On Thu, May 24, 2018 at 8:45 AM Da Zhang wrote: > Hey guys, > > I tried to increase the dtb size (i.e., number of tlb entries) for our > research.

Re: [gem5-users] x86 floating point instruction

Hi Tariq, It wold be great if you could review Gabe's patch on gerrit. Since it works for you, giving it a +1 or a +2 would be appropriate. Cheers, Jason On Wed, May 23, 2018 at 5:56 PM Tariq Azmy wrote: > Thanks Gabe. Yeah it does not impact the program but it's just that the > statistic is i

Re: [gem5-users] Response for WritebackDirty packets (learning.gem5)

Hello, No. You should not have a response for WritebackDirty. In fact, most (all?) writes do not have responses. See src/mem/packet.cc. ( https://gem5.googlesource.com/public/gem5/+/master/src/mem/packet.cc#80) Some commands have the "NeedsResponse" flag set. If so, this request will be turned int

Re: [gem5-users] Issues in handling compressed data for L3 cache

Hi, While I'm not sure I can directly answer your question, I know there's been significant changes recently to the tag structure in the caches to support creating new compressed caches. See this set of changesets (some of which have been merged) in gerrit (our code review site). https://gem5-revi

Re: [gem5-users] Problems with clock() from time.h in x86 32 bit

p->tv_nsec = TheISA::htog(tp->tv_nsec); > > -tp.copyOut(tc->getMemProxy()); > +//tp.copyOut(tc->getMemProxy()); > > return 0; > } > > > On Tue, May 15, 2018 at 7:33 PM, Jason Lowe-Power > wrote: > >> You can try using debug flag

Re: [gem5-users] No checkpoint file generated

Hi Ryan, Checkpointing is controlled from the python run scripts. When you run "/sbin/m5 checkpoint" it creates a exit event that exits the simulator event loop. This kicks control back to the Python run script. I don't believe that fs/se.py correctly support this kind of exit. However, you could

Re: [gem5-users] Is classic memory system thread-safe?

st (issued from the > TraceCPU, or issued by a cache to another cache) according to the ticks and > thus guarantee the consistency? > > Regards, > > Chen > > On 05/14/2018 04:07 PM, Jason Lowe-Power wrote: > > Hi Chen, > > To answer your question simply: No. >

Re: [gem5-users] Memory writes pattern distribution analysis using gem5

Hi Muhammad, I would write a new probe and run your analysis online instead of trying to generate a trace and running it after the fact. See the examples in src/mem/probes. Jason --- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049

Re: [gem5-users] Problems with unsupported instructions

etter with a completely > simulated target, like ARM than x86... > > On Tue, May 15, 2018 at 7:38 PM, Jason Lowe-Power > wrote: > >> Hello, >> >> Yes. Those instructions are unimplemented, so you would have to implement >> them. There are some cases where

Re: [gem5-users] Problems with unsupported instructions

Hello, Yes. Those instructions are unimplemented, so you would have to implement them. There are some cases where unimplemented instructions can be ignored (e.g., hints to caches). However, if your application is using fdivr, it seems important. I wish I could give you a good pointer on how to imp

Re: [gem5-users] Problems with clock() from time.h in x86 32 bit

um/a.out' > warn: ignoring syscall access(...) > fatal: readBlob(0x4080ae651, ...) failed > Memory Usage: 97236700 KBytes > > > > > On Mon, May 14, 2018 at 6:25 PM, Jason Lowe-Power > wrote: > >> Hello, >> >> Have you compiled your binary statically? I b

Re: [gem5-users] Is classic memory system thread-safe?

g multiple simulated trace CPUs and using a different file for each trace CPU. Also, to answer your other question, no, the mailing list does not send an email to the original author by default. I think you can change this setting in mailman, though. Jason ------- Jason Lowe-Power Assistant

Re: [gem5-users] gem5 cc-NUMA with Ruby

aths from each CPU to the directories (which are the memory controllers). Specifically, as long as you're not using point-to-point or crossbar it should be NUMA. However, the built-in topologies are probably not the exact cache hierarchy/topology that you want to simulate. Jason --- Jason

Re: [gem5-users] Understanding how exit event is scheduled

're simply playing a trace from your new object, you could ignore the exit event by restarting simulation after the exit event from your python runscript. Hope this helps, Jason ------- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049 Ke

Re: [gem5-users] Classical vs ruby memory models

Hello, See inline answers below. On Mon, May 14, 2018 at 7:24 AM Sakshi Tiwari wrote: > Can anyone please help me with my queries in the previous mail? > > On Sat, May 12, 2018 at 6:34 PM, Sakshi Tiwari > wrote: > >> Hi, >> >> For my work, I had to implement three-levels of caches with LLC as

Re: [gem5-users] Problems with clock() from time.h in x86 32 bit

Hello, Have you compiled your binary statically? I believe dynamically linked executables will only work if the host and the guest are *exactly* the same (e.g., both x86-64 in this case). Jason On Mon, May 14, 2018 at 7:10 AM Øyvind Harboe wrote: > I'm getting a "bad_alloc" from the config/exa

Re: [gem5-users] Gem5 build error

Hi Thawra, My guess is that this is an issue with the version of pybind11 we're using and gcc 8+. We haven't tested on anything after gcc 7.X. I'll put testing gcc 8 on my to do list, but I don't know when I'll get to it. I would try downgrading gcc to 7 or possibly using clang. Jason On Tue, M

Re: [gem5-users] passing arguments to executable in SE mode.

The cmd parameter expects a python list. You need to have commas between the elements (https://developers.google.com/edu/python/lists). I would encourage you to read up on how to program in Python :). Jason --- Jason Lowe-Power Assistant Professor, Computer Science Department University

Re: [gem5-users] How to build gem5 out of tree?

Hi Ciro, You can specify any directory as the parameter to scons. I believe the convention is to have a directory named "build" as the second to last component of the path, but I don't think it's *required*. For instance you could do the following: $ scons /scratch/jlp/build/my_gem5/gem5.opt --d

Re: [gem5-users] Linux 4.x kernel

Hi Jochen, I've gotten up to the current mainline kernel working. On this page ( http://www.lowepower.com/jason/setting-up-gem5-full-system.html) is a link to the config file that I used for 4.8.13. If you want to use a more recent kernel you can start with that config file and run "make oldconfig

Re: [gem5-users] how to enable DPRINT statements

that you want to use a timing CPU and caches, if you're using se.py. Jason --- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049 Kemper Hall jlowepo...@ucdavis.edu On Thu, Apr 19, 2018 at 12:42 PM Mandrita wrote: > Hi all,

Re: [gem5-users] Connect CPU and accelerator through a bus

an example accelerator like you described: https://github.com/powerjg/gem5/tree/devel/accel/src/accel. That branch (devel/accel) has all of the necessary code. Cheers, Jason ------- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049 Kemper

Re: [gem5-users] Simulate 2 Processors

Hi Elena, If you want to simulate two processors in the same system, you must have a single gem5 instance (process) on the host. dist-gem5 is useful if you want to simulate two different systems communicating over ethernet. Jason --- Jason Lowe-Power Assistant Professor, Computer

Re: [gem5-users] Some questions regarding SE vs FS in GEM5 for multi-core applications

Hi Xin, In SE mode, there is no thread scheduling. *Processes* are assigned to cores in the python config file. Or, if there is a fork/clone, you can see the code in the syscall emulation file ( https://gem5.googlesource.com/public/gem5/+/master/src/sim/syscall_emul.hh#1242 ). All of the cores sh

Re: [gem5-users] Has anyone ever produced an Spectre or Meltdown proof of concept running on gem5 or would that be feasible?

Hi Ciro, Yeah. In fact, I think I've pointed to this before on the mailing list. See https://github.com/jlpresearch/gem5/tree/spectre-test for all of the necessary code and configs. There's also a brief explanation of how it works in spectre.rst. The visualization with the pipeline viewer (or Kona

Re: [gem5-users] Multithread with se.py

Hi Gagan, You need to set the same Process as the workload parameter on each CPU (and create the threads). The file configs/learning_gem5/part3/simple_ruby.py ( https://gem5.googlesource.com/public/gem5/+/master/configs/learning_gem5/part3/simple_ruby.py) shows an example of how to do this. Jason

Re: [gem5-users] cxx_class in the Python Class for SimObject

Hello, cxx_class is the C++ class name that will be created when ValuePredictorParams::create() is called (the return value of that function). Usually, it's exactly the same as the Python class name. Again, http://learning.gem5.org/book/part2/ explains many of these details. If you think somethin

Re: [gem5-users] Instantiate new SimObject

See http://learning.gem5.org/book/part2/helloobject.html. That chapter explains all of the details of creating a new SimObject and instantiating it. Jason On Sun, Apr 1, 2018 at 4:12 PM Pawan Joshi wrote: > Hello > I am adding this new Value predictor to the O3 pipeline, but I am unsure > where

Re: [gem5-users] How to use m5 readfile and m5 execfile?

There is a script parameter for the system object. That is the file that is read when you call m5 readfile. For execfile, you'll have to dig into the code in util/m5 and in the magic instruction code (src/sim?). Jason On Tue, Mar 27, 2018, 11:04 AM Ciro Santilli wrote: > https://stackoverflow.c

Re: [gem5-users] Full-system restoring from checkpoint with different runscript

Hi Timon, Good to hear. Rather than starting with a different disk, what I usually do is have two disk images. One for boot and one for the workloads. After I resume from the checkpoint, I then mount the second disk with the workloads on it. Jason On Fri, Mar 23, 2018 at 7:18 AM Timon Evenblij

Re: [gem5-users] Full-system restoring from checkpoint with different runscript

This is what the hack_back_ckpt.rcS is for: https://gem5.googlesource.com/public/gem5/+/master/configs/boot/hack_back_ckpt.rcS Jason On Wed, Mar 21, 2018 at 3:12 AM Timon Evenblij wrote: > Hi all, > > A quick question: Is it possible to restore from a checkpoint with a > different runscript the

Re: [gem5-users] How to set L1 Cache access latency and L2 Cache access latency in Ruby mode？

u can add a delay when enqueuing messages. This is what the parameters you listed in your email do. You should use this for the "cache" latencies. 2) You can also add delays to the network. Jason ------- Jason Lowe-Power Assistant Professor, Computer Science Department University of Ca

Re: [gem5-users] O3CPU DeriveO3CPUParams

the FullO3CPU. Is this ok to define > this way if they are not matched? I know that FullO3CPU is derived from > Base03CPU, which is also a child of BaseCPU class. > > Thanks > > On Fri, Mar 16, 2018 at 11:11 AM, Jason Lowe-Power > wrote: > >> Hi Tariq, >> >&

Re: [gem5-users] Restoring checkpoints with ruby?

Hi Haiyang, Checkpointing and Ruby hasn't been tested in a while, as far as I know. I guess what I mean by that is that I haven't used the feature in a long time, and I don't know of anyone that tracks mainline gem5 that does use Ruby and checkpointing :). When taking a checkpoint, you have to us

Re: [gem5-users] O3CPU DeriveO3CPUParams

Hi Tariq, The way SimObject parameters work is explained in Part 2 of Learning gem5 here: http://learning.gem5.org/book/part2/parameters.html. It's a little convoluted (you have to go through python to set parameters), but it is incredibly flexible. The *defaults* for

Re: [gem5-users] How to do port forwarding from guest to host and vice versa?

Hi Ciro, This doesn't work straightforwardly right now. For gdb, I believe there is a special case for debugging the guest application (see remote_gdb code). Otherwise, there is a special network device: "EtherTap" that allows gem5 to send network request to the host. See src/dev/net/Ethernet.py.

Re: [gem5-users] No Dirty Blocks in the system??

er any of the *questions raised*. > > [1]: "Die-Stacked DRAM Caches for Servers: Hit Ratio, Latency, or > Bandwidth? Have It All with Footprint Cache" > > Thank you > Varun > > On Wed, Feb 28, 2018 at 10:44 PM, Jason Lowe-Power > wrote: > >> Hi Varun, &

Re: [gem5-users] Gem5 execution stackttrace

e discussion above regarding ARM+ RUBY. I >> have been working with ARM +RUBY and I have simulated 2x2/ 4x4 Mesh_XY NoC >> with MESI_Two_Level protocol. This protocol works fine with ARM in full >> system mode. But originally MESI_Two_Level lacked the multiple DMA >> controlle

Re: [gem5-users] No Dirty Blocks in the system??

Hi Varun, I imagine there are other code paths that writeback dirty data. The cache code is pretty complicated so I can't tell you exactly where to look off the top of my head. One thing you could do is put an inform (or use debug flags) at the memory controller. Here, you can see when there are w

Re: [gem5-users] Errors building on Ubuntu 17.10

lly this provides some guidance. Cheers, Jason On Sat, Feb 24, 2018 at 1:33 AM Paul V. Gratz wrote: > Hi Jason, > Hmm, do you have a sense for which (just a small subset is fine) > combinations are a good idea to run and/or which aren't :-). > Paul > > On Fri, Feb 23, 2018

Re: [gem5-users] Errors building on Ubuntu 17.10

d have been > working through it, thanks for that site, its great! > Paul > > > On Thu, Feb 22, 2018 at 4:16 PM, Jason Lowe-Power > wrote: > >> Hi Paul, >> >> Thanks for letting us know. There's currently a patch on our review site >> that solves the

Re: [gem5-users] Errors building on Ubuntu 17.10

Hi Paul, Thanks for letting us know. There's currently a patch on our review site that solves the implicit fallthrough problem ( https://gem5-review.googlesource.com/c/public/gem5/+/8541). I haven't seen the uninitialized warning, though. Cheers, Jason ------- Jason Lowe-Power

Re: [gem5-users] running fs.py with X86KvmCPU failed

forward > (as with --fast-forward option)? So that we can avoid the long wait time > for things like initialization. > > best, > Da Zhang > > > > On Thu, Feb 15, 2018 at 12:17 PM, Jason Lowe-Power > wrote: > >> Hi Da, >> >> You likely need to enable g

Re: [gem5-users] panic: Possible Deadlock detected. Aborting! (Jason)

t; > Can you tell me about more debug flags other than ProtocolTrace that can > be used to trace the addresses in caches. > > regards, > > Muhammad > > > > > On 14 February 2018 at 22:05, Jason Lowe-Power > wrote: > >> Hi Muhammad, >> >> Unf

Re: [gem5-users] running fs.py with X86KvmCPU failed

> Now, I can run gem5 for linux kernel v4.8.13 and ubuntu 16.04.1 with >> kvm support. And the speedup is so amazing. It used to take me 20 ~ 30 >> minutes to boot up the system without the kvm cpu. Now, it takes only >> several seconds!!! >> >> Thanks so much! >&

Re: [gem5-users] panic: Possible Deadlock detected. Aborting! (Jason)

Hi Muhammad, Unfortunately, debugging these kinds of issues is *incredibly* difficult. Especially when they only occur during full system execution. I would try grepping for the address that is deadlocking and starting by tracing the address from where it originally issued through the cache hiera

Re: [gem5-users] Confusion about Memory Address in GEM5

Hi Muhammad, The addresses in your application are virtual addresses and the addresses in the cache are physical addresses. https://en.wikipedia.org/wiki/Virtual_address_space may help. Jason --- Jason Lowe-Power Assistant Professor, Computer Science Department University of California

Re: [gem5-users] Learning gem5 not working (Jason)

Hi Muhammad, It works fine for me. For instance, http://learning.gem5.org/book/index.html loads correctly. What is the error you are seeing? Jason On Mon, Feb 12, 2018 at 12:33 PM SHARJEEL KHILJI < sharjeelsaeedkhi...@gmail.com> wrote: > Hi Jason, > > Your website Learning gem5 is not working.

[gem5-users] Learning gem5 tutorial at ASPLOS

9, 2018 at 1:12 PM Jason Lowe-Power wrote: > Hi all, > > Apologies if you get more than one copy of this message. > > We are running another Learning gem5 tutorial at ASPLOS in Williamsburg VA > this year. The tutorial is on Saturday March 24th. More information can be >

Re: [gem5-users] Define Cache Address Ranges?

., if you use bit 6 for interleaving and bits 6-10 for indexing then you will never use any even sets in the first bank or any odd sets in the second bank.) This can also affect your actual associativity. Jason --- Jason Lowe-Power Assistant Professor, Computer Science Department University

Re: [gem5-users] Increasing cacheline size in gem5

Hi Varun, Some comments inline below. On Tue, Feb 6, 2018 at 11:33 PM Saivarun R wrote: > Hi Jason, > > As you pointed out, I went through the dram_ctrl.cc file and spent some > time designing the implementation. I want to know if what I understood is > correct regarding the implementation or n

Re: [gem5-users] running fs.py with X86KvmCPU failed

These patches "fix" the problem. However, they may not apply cleanly to HEAD and they definitely are not cleanly implemented. https://gem5-review.googlesource.com/c/public/gem5/+/7362 https://gem5-review.googlesource.com/c/public/gem5/+/7361 Cheers, Jason On Wed, Feb 7, 2018 at 8:49 PM Da Zhang

Re: [gem5-users] HBM model supported by GEM5

See src/mem/dram_ctrl.hh, dram_ctrl.cc, and DRAMCtrl.py. gem5 supports HBM out-of-the-box. Cheers, Jason On Mon, Feb 5, 2018 at 3:24 AM Vishwas Rao wrote: > > > Hi, > We would like to know whether GEM5 supports the HBM memory model and is it > open ? > We want to know, whether can we make any

Re: [gem5-users] fail to run fs mode with linux kernel v4.8.13 and ubuntu image 16.04.1

Hi Da, I'm aware of this problem and have submitted a patch. Unfortunately, I haven't had time to fix the problem in the correct way (as detailed by Gabe in the review). This patch will get linux to boot. If you have the inclination, feel free to fix it the correct way! https://gem5-review.google

Re: [gem5-users] Switching between Fastforwarding, Warmup, Detailed: Sampling long benchmarks

; I forgot to specify them. > Also, a final question: how useful is it to specify something like > new_cpu.system = system before swithcing to the new cpu? > I have seen it used sometimes, but in my experiments it does not change > anything. > > Cheers > Timon > > On F

Re: [gem5-users] Increasing cacheline size in gem5

ne would be a better option to go > ahead. > > Thank you > Varun > > On Tue, Jan 30, 2018 at 2:39 AM, Jason Lowe-Power > wrote: > >> Hi Vaurn, >> >> Three quick answers: >> 1. Currently, the cache line size in gem5 is global to the system. So you &

Re: [gem5-users] Increasing cacheline size in gem5

3. What I would do is *not* use the cache line size parameter for the DRAM cache, but make your own new parameter. Basically treat the the DRAM cache as a memory object that accepts 64 byte requests but stores data with a different line size. Hope this helps. Jason ------- Jason Lowe-

Re: [gem5-users] Switching between Fastforwarding, Warmup, Detailed: Sampling long benchmarks

Hi Timon, To answer your question: Yes. I have succeeded in writing scripts to switch between atomic and detailed mode. In fact, you can write scripts that do much more complicated things as well. For an example, you can check out my github repo: https://github.com/jlpresearch/gem5/tree/jason/kvm-

[gem5-users] Learning gem5 tutorial at ASPLOS

tart in just one day! If you have any questions, feel free to email Jason Lowe-Power at ja...@lowepower.com. Hope to see you in Williamsburg! Jason ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] New O3 Pipeline Viewer like Google Maps

hort writeup on this tool to post on a gem5 blog? Nothing is set in stone, yet, but I'm trying to build up some content before launch. Let me know if you want more information. I haven't quite gotten all of the details nailed down on these things, yet. Cheers, Jason --- J

Re: [gem5-users] Pseudo-instructions vs ISA Extension

izes. Cheers, Jason ------- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049 Kemper Hall https://faculty.engineering.ucdavis.edu/lowepower/ On Tue, Jan 2, 2018 at 11:28 AM Gus Smith wrote: > ​Appreciate the reply, Jason! That helps a lot! &

Re: [gem5-users] How to implement NUMA system in gem5

available here: https://youtu.be/8GsD5M2TKjk?t=5458. Cheers, Jason ------- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049 Kemper Hall jlowepo...@ucdavis.edu On Mon, Jan 1, 2018 at 11:17 PM narges akbari wrote: > Hello > > I

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