Re: [PEDA] WANTED: PCB Expert (Off Topic)
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Mark E Witherite wrote: > That's a bad assumption. This last year > I learned that a board house is only as good as it's production > employees. a company that was once a NASA's top ten list, sent me batch of > boards with two nets shorted. And yes they were ordered with bed of nails > testing. This seems to be an endemic problem in the industry. We have blackballed at least 4 PCB fabricators, in my memory, for failing to do electrical testing, while charging for it and stamping "ET" on the boards. The last one was Imagineering, which produced one 4- and one 6-layer board for us last year where they failed to do the testing. We had about 25% failure on one board and close to 50% on the 6-layer board! We don't have a tester, so we need to stuff the boards and then track down the defects. I had to dig down into the power-ground layers to break shorts between the two planes. So, we don't use them anymore, we went back to Advanced Circuits, who have never pulled this sort of stunt on us. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
got it! - Original Message - From: "Abd ulRahman Lomax" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Friday, April 12, 2002 1:30 PM Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > I've been having ISP problems. Verizon. Need I say more? Anyway, I think > they are fixed, courtesy of addr.com. > > At 05:52 PM 4/11/2002 +0100, Jason Morgan wrote: > >As for the latest on the actual problem - board warping to well within IPC > >recomendations but outside of what we'd like, it seems that the latest > >boards have even less of a problem. > > Since warpage is "well within IPC recommendations" [presumably for a > maximum warpage specification], the most significant problem here is the > design of the rack into which the boards fit; it was clearly not designed > to handle normal PC boards. > > One more comment: if one uses a single supplier for fabrication and > assembly, one can make any specification whatever for warp on the final > board (including residual changes in warp after soldering), and it will be > the responsibility of the fabricator/assembler to make it work. If they > can't do it, it would be, again, their responsibility to tell you that in > advance. To avoid getting into a major hassle, it would be wise to make the > warpage requirement, and that it is tighter than the IPC standard, obvious > and crystal clear in the purchase order/supplied specifications and files. > Of course, fabrication outside the norms can have a major impact on cost; > thus fixing the rack might well be the most economical procedure. Do the > racks meet their specification? If not, the manufacturer would be > presumably be responsible for replacing them > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
I've been having ISP problems. Verizon. Need I say more? Anyway, I think they are fixed, courtesy of addr.com. At 05:52 PM 4/11/2002 +0100, Jason Morgan wrote: >As for the latest on the actual problem - board warping to well within IPC >recomendations but outside of what we'd like, it seems that the latest >boards have even less of a problem. Since warpage is "well within IPC recommendations" [presumably for a maximum warpage specification], the most significant problem here is the design of the rack into which the boards fit; it was clearly not designed to handle normal PC boards. One more comment: if one uses a single supplier for fabrication and assembly, one can make any specification whatever for warp on the final board (including residual changes in warp after soldering), and it will be the responsibility of the fabricator/assembler to make it work. If they can't do it, it would be, again, their responsibility to tell you that in advance. To avoid getting into a major hassle, it would be wise to make the warpage requirement, and that it is tighter than the IPC standard, obvious and crystal clear in the purchase order/supplied specifications and files. Of course, fabrication outside the norms can have a major impact on cost; thus fixing the rack might well be the most economical procedure. Do the racks meet their specification? If not, the manufacturer would be presumably be responsible for replacing them * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Jason, please don't think that you are safe by the fact the board shops may comply with IPC or other specifications. IPC and other specifications allow for platings which would experience solder joint embrittlement during fabrication if the wrong solders/processes are used. Nothing ties the board plating and assembly procedures together in a singular uniquely compatible specification. Not to mention that the thickness of platings can effect circuit performance at high frequencies and boards from differing manufacturers can perform differently based upon different plating options. You are most certainly not IPC compliant if you don't specify your plating. It would be an IPC omission to leave undefined gaps in your board specification. Why specify even initial or plated Cu thickness, the boards you received last time seemed to work fine, they were manufactured by an IPC compliant shop? The next boards don't perform the same, well it must be the fab shops fault. Wrong! Just trying to help you in the long run, a lot of us have been where you are before. Some of us have paid for our former bliss with our sweat, tears and blood, some have survived through pure luck but learned what we did in the past was unacceptable. This is the last that I will say unless you request more information, can't force you to accept my advice. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21. > -Original Message- > From: Jason Morgan [mailto:[EMAIL PROTECTED]] > Sent: Thursday, April 11, 2002 9:52 AM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Brad, > > The boards are manufactured to BS and IPC recommendations by > a high volume > international supplier if there are any problems with the > plating, ( of > which there is no evidence and which I doubt there are), then > its not our > problem. > > Thanks for all your help, > > > Jason. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Brad, The boards are manufactured to BS and IPC recommendations by a high volume international supplier if there are any problems with the plating, ( of which there is no evidence and which I doubt there are), then its not our problem. As for the latest on the actual problem - board warping to well within IPC recomendations but outside of what we'd like, it seems that the latest boards have even less of a problem. Its not gone away, and we are still working on a better resolution, but for now we've decided to just run with them and see what the best and worst look like. Thanks for all your help, Jason. -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: 11 April 2002 16:41 To: 'Protel EDA Forum' Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) Jason, aside from your problems with warp and twist, there are other possible problems lurking if you do not know the actual thickness of your Nickel/Gold plating. There are a myriad of complicated electro/chemical/physics related problems which can occur with Nickel Gold plating, the most common of which is solder joint embrittlement. SN/PB/AU Solder joint embrittlement can cause solder joint failures in field units which are a devil to find because they will break connections during thermal or stress cycles and be fine other times. In conjunction with your warping, your design would be a prime candidate for these failures. In the extreme cases I have been told of boards having significant numbers of their components drop off the boards when the board is manually flexed. On a typical SMD land pattern design if your Gold is greater then approx. 25 - 30 microinches then you may have embrittlement problems if you do not use special solder compositions. I would suggest that you must find out what the nickel & gold plating thickness is for your board. Then you could discuss them here with us and we could give you some more detailed information. In the future you should specify the gold plating requirements and not rely on luck or a single fabricators judgement as to what plating thickness your require for your board. One of the best studies which I have found on this issue was performed by HP. The article was titled "Effect of AU on the Reliability of Fine Pitch Surface Mount Solder Joints" by Judith Glazer, HP, Palo Alto, California. It was published in "Proceedings, Surface Mount International Conference, Aug 25 - 29 (1991), San Jose, CA." It was republished in Circuit World 18, pg 41-46 1992 and Surface Mount Technology 4, pgs 15 - 28 (1992). Good luck Jason. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11. > -Original Message- > From: Jason Morgan [mailto:[EMAIL PROTECTED]] > Sent: Thursday, April 11, 2002 1:10 AM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Monitoring - sort of, bit busy for full followup. > > Anyway, I did post a full explanation that the plating would > be Cu+Ni+Au, no > idea on the proportions. > > J. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Jason, aside from your problems with warp and twist, there are other possible problems lurking if you do not know the actual thickness of your Nickel/Gold plating. There are a myriad of complicated electro/chemical/physics related problems which can occur with Nickel Gold plating, the most common of which is solder joint embrittlement. SN/PB/AU Solder joint embrittlement can cause solder joint failures in field units which are a devil to find because they will break connections during thermal or stress cycles and be fine other times. In conjunction with your warping, your design would be a prime candidate for these failures. In the extreme cases I have been told of boards having significant numbers of their components drop off the boards when the board is manually flexed. On a typical SMD land pattern design if your Gold is greater then approx. 25 - 30 microinches then you may have embrittlement problems if you do not use special solder compositions. I would suggest that you must find out what the nickel & gold plating thickness is for your board. Then you could discuss them here with us and we could give you some more detailed information. In the future you should specify the gold plating requirements and not rely on luck or a single fabricators judgement as to what plating thickness your require for your board. One of the best studies which I have found on this issue was performed by HP. The article was titled "Effect of AU on the Reliability of Fine Pitch Surface Mount Solder Joints" by Judith Glazer, HP, Palo Alto, California. It was published in "Proceedings, Surface Mount International Conference, Aug 25 - 29 (1991), San Jose, CA." It was republished in Circuit World 18, pg 41-46 1992 and Surface Mount Technology 4, pgs 15 - 28 (1992). Good luck Jason. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11. > -Original Message- > From: Jason Morgan [mailto:[EMAIL PROTECTED]] > Sent: Thursday, April 11, 2002 1:10 AM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Monitoring - sort of, bit busy for full followup. > > Anyway, I did post a full explanation that the plating would > be Cu+Ni+Au, no > idea on the proportions. > > J. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Monitoring - sort of, bit busy for full followup. Anyway, I did post a full explanation that the plating would be Cu+Ni+Au, no idea on the proportions. J. -Original Message- From: Mark E Witherite [mailto:[EMAIL PROTECTED]] Sent: 09 April 2002 15:34 To: Protel EDA Forum Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) Hi Igor, There were many other post to this subject. Have you examined the gerbers? The only reason I could think of to use such a thick nickel plating would be to provide some EMI shielding. If that were the case then I would suspect there would be polygons. Jason never verified that the nickel plating was 1.1 mils. I also assumed that all the most common problems have been investigated. That's a bad assumption. This last year I learned that a board house is only as good as it's production employees. a company that was once a NASA's top ten list, sent me batch of boards with two nets shorted. And yes they were ordered with bed of nails testing. Lastly I did the math on the expansion ( assuming low stress nickel). I only got a difference of about 4mils in the two metals. I would think that this would only cause a bow of less than 4 mils. Sorry for shooting off before I pick up the calculator. I would still like to know if the nickel plating thickness was really 1.1mil. How about it Jason ? Are you still monitoring this thread? Cheers Mark At 08:47 AM 4/9/02 +1000, you wrote: >Agree witht that. Also, there seem to be no polygons placed on the routing >layers, which might add to the problem. > >Igor > >-Original Message- >From: Mark E Witherite [mailto:[EMAIL PROTECTED]] >Sent: Thursday, 4 April 2002 4:56 AM >To: Protel EDA Forum >Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > >My Money is on the mismatch of thermal coefficient of expansion between the >copper and the nickle gold foil. > >At 04:52 PM 4/3/02 +0100, you wrote: > >Many thanks, > > > >Details are as follows: > > > >6 Layer 1.6 FR4 > >8" x 10" Board > > > >PCB support is a wasted rectangle 10mm wide along all edges, supporting PCB > >at 2 or 3 points along each edge. (First observation is that this should > >have copper layers) > > > >Layer stack up is two cores + two foils (sizes rounded to 1 decimal place) > > > >R/P Layer Typethou > >- - Resist 0.4 > >R 1 Ni/Au 0.5oz 1.1 > >R 1 Foil 0.5oz 0.7 > >- - Prepreg 76307.0 > >P 2 1oz Copper 1.4 > >- - Core15.0 > >R 3 1oz Copper 1.4 > >- - Prepreg 10805.0 > >- - Prepreg 10805.0 > >R 4 1oz Copper 1.4 > >- - Core15.0 > >P 5 1oz Copper 1.4 > >- - Prepreg 76307.0 > >R 6 Foil 0.5oz 0.7 > >R 6 Ni/Au 0.5oz 1.1 > >- - Resist 0.4 > >- > >Total 64 = 1.625mm > > > >Effects are: > >Boards are flat from production, but twist on heating in solder reflow or > >wave solder. > > > >An analysis of 5 board produced 1 that exceeded the IPC warpage > >specifications. > > > >Trouble is all but one was too twisted to fit into the rack without effort. > > > >We had the same problem with the alpha version, but here this was put down > >to an incomplete plane > >on the two plance layers, this has been changed to a full plane - no change > >to warp. > > > >Suggestions so far have been to: > >0: Add copper to waste (breakout) parts layers > >1: Change the breakout to a waste part scored along the two long >edges. > >2: Use a three core construction > >3: Add copper hash to layers 3 and 4, (other either side of the two > >cores) > >4: Change warp and weft of cores > >5: Increase core thickness and decrease 1080 prepreg thickness. > >6: Use 1.8 FR4 by increasing core thickness (undesireable) > > > >So far we've had no input from the manufacturer as to what (if any) of the > >above will be better, though > >they agree that all should have some affect (positive or negative) on bow > >and twist. > > > >We've also noticed that over a long period (weeks) the twist gets less. > > > >Regards > > > >Jason. > > > > > >-Original Message- > >From: Mike Reagan [mailt
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Agree witht that. Also, there seem to be no polygons placed on the routing layers, which might add to the problem. Igor -Original Message- From: Mark E Witherite [mailto:[EMAIL PROTECTED]] Sent: Thursday, 4 April 2002 4:56 AM To: Protel EDA Forum Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) My Money is on the mismatch of thermal coefficient of expansion between the copper and the nickle gold foil. At 04:52 PM 4/3/02 +0100, you wrote: >Many thanks, > >Details are as follows: > >6 Layer 1.6 FR4 >8" x 10" Board > >PCB support is a wasted rectangle 10mm wide along all edges, supporting PCB >at 2 or 3 points along each edge. (First observation is that this should >have copper layers) > >Layer stack up is two cores + two foils (sizes rounded to 1 decimal place) > >R/P Layer Typethou >- - Resist 0.4 >R 1 Ni/Au 0.5oz 1.1 >R 1 Foil 0.5oz 0.7 >- - Prepreg 76307.0 >P 2 1oz Copper 1.4 >- - Core15.0 >R 3 1oz Copper 1.4 >- - Prepreg 10805.0 >- - Prepreg 10805.0 >R 4 1oz Copper 1.4 >- - Core15.0 >P 5 1oz Copper 1.4 >- - Prepreg 76307.0 >R 6 Foil 0.5oz 0.7 >R 6 Ni/Au 0.5oz 1.1 >- - Resist 0.4 >- >Total 64 = 1.625mm > >Effects are: >Boards are flat from production, but twist on heating in solder reflow or >wave solder. > >An analysis of 5 board produced 1 that exceeded the IPC warpage >specifications. > >Trouble is all but one was too twisted to fit into the rack without effort. > >We had the same problem with the alpha version, but here this was put down >to an incomplete plane >on the two plance layers, this has been changed to a full plane - no change >to warp. > >Suggestions so far have been to: >0: Add copper to waste (breakout) parts layers >1: Change the breakout to a waste part scored along the two long edges. >2: Use a three core construction >3: Add copper hash to layers 3 and 4, (other either side of the two >cores) >4: Change warp and weft of cores >5: Increase core thickness and decrease 1080 prepreg thickness. >6: Use 1.8 FR4 by increasing core thickness (undesireable) > >So far we've had no input from the manufacturer as to what (if any) of the >above will be better, though >they agree that all should have some affect (positive or negative) on bow >and twist. > >We've also noticed that over a long period (weeks) the twist gets less. > >Regards > >Jason. > > >-Original Message- >From: Mike Reagan [mailto:[EMAIL PROTECTED]] >Sent: 03 April 2002 16:43 >To: Protel EDA Forum >Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > >Jason >Some of our advice is free >What process is warping the boards? Reflow or manufacturing? or upset >employee? > >Mike Reagan >EDSI > > > >- Original Message - >From: Jason Morgan <[EMAIL PROTECTED]> >To: 'Protel EDA Forum' <[EMAIL PROTECTED]> >Sent: Wednesday, April 03, 2002 9:03 AM >Subject: [PEDA] WANTED: PCB Expert (Off Topic) > > > > Hi, > > > > We have a board warping problem and are looking for a PCB expert to help > > resolve it. > > (Preferably located in the UK, but not important) > > > > When I say expert, I mean *EXPERT*. The problem is quite complex and >already > > has baffled two manufacturers. > > > > We will pay the going rate for any consultation. > > > > Regards, > > > > Jason Morgan > > Mark Witherite C.I.D. Assistant Research Engineer Astronomy & Astrophysics Penn State University 2565 Park Center Blvd Suite 200 State College, PA. 16801 email [EMAIL PROTECTED] telephone 814 865 9839 fax 814 865 9100 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
John Said: >Another test: if you run two bare boards through reflow, with one >"top" facing up and the other facing down, do both boards warp in >the same direction, or is it always toward the "top" (or "bottom", >as the case may be). The former would point to a reflow issue, while >the latter would be related to board fab/design. Good idea, I'll suggest that to the assembly house. J. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
I am not beting exact on the actual thickness of the Ni/Au as its not specified in the board report, only that the outer serfaces are plated to 1oz, part of that plating will be copper when the via and through hole connections are made. The manufacturers report only states the plate thickness, not the proportion of Ni/Au to Cu. j. -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: 04 April 2002 20:00 To: 'Protel EDA Forum' Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) But Harry, the query was only, why there was 1.1mils associated with the NI/Au? Normal standards would call for 150 - 200 uinches of NI and upto 50uinches of Au. Not 1.1mils! Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11. > -Original Message- > From: H. Selfridge [mailto:[EMAIL PROTECTED]] > Sent: Thursday, April 04, 2002 10:34 AM > To: Protel EDA Forum > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Copper on a printed circuit is subject to severe oxidation > unless coated. > Cu oxides are poor electrical conductors. > > Gold is a passive metal with excellent conductivity. > > If you plate gold directly on copper, Au/Cu intermetallics > are formed that > cause the bond to be brittle and subject to mechanical > failure under stress. > > Plating nickel over the copper forms a barrier that has desirable > intermetallic characteristics. However, Ni also oxidizes > readily. Ni > oxides are poor electrical conductors. > > Plating Au over the Ni gives the best overall metallic > structure for a pcb > (pwb). The Au is corrosion resistant, and has excellent > conductivity. The > Ni barrier under the Au prevents Cu migration into the Au. > Ni/Au and Ni/Cu > intermetallics at the bonds are both hard and relatively durable. > > That is half a semester in 5 lines that tells why nickel > plating is used > under gold on a pcb (pwb). * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
At 04:04 PM 4/3/2002 -0500, Lomax wrote: >This list is also not the prime place to find advice on this, I'd suggest >the IPC Designers Forum. Butyou never can tell... Well, I did leave a door open I strongly suspect that the solution is somewhere among all the suggestions made here; certainly many possible sources for the warping and fit problem were given that could be investigated, including one excellent suggestion from Mr. Haddy: >Another test: if you run two bare boards through reflow, with one >"top" facing up and the other facing down, do both boards warp in >the same direction, or is it always toward the "top" (or "bottom", >as the case may be). The former would point to a reflow issue, while >the latter would be related to board fab/design. I also suggested something that would be related: making a more thorough description of the warping, i.e., how much and in what way are the boards warped; what is the distribution, how consistent is it, etc. This information could help to interpret the results of the test Mr. Haddy suggested. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
I would suggest a closer look at the reflow profiling - despite the claims of "optimum" profile. What I would look at in particular is the soak time (or bottom side preheat if the oven supports this). At a distance, my guess would be that the top side of the board is getting to correct temperature, but the bottom side is staying too cool. I would run a thermal profile pass with thermocouples attached to both the top and bottom surfaces of the PCB. BTW, does the board contain numbers of large inflexible components like PLCCs? Another test: if you run two bare boards through reflow, with one "top" facing up and the other facing down, do both boards warp in the same direction, or is it always toward the "top" (or "bottom", as the case may be). The former would point to a reflow issue, while the latter would be related to board fab/design. John Haddy > -Original Message- > From: Jason Morgan [mailto:[EMAIL PROTECTED]] > Sent: Friday, 5 April 2002 1:40 AM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Thanks for all the advice and suggestions. > > Some more info that I missed from the first post: > > We've been trying to solve this for some time. We've tried boards supplied > from more than one house and populated at more than one house, > all with the > same sorts of results. > > We're not the fab, so we have no control on the process, its up > to their QA. > > The profile is optimum (according to fab) and any change would > result in bad > joints. > > We've tried reflow and wave with the same or similar results. > > We've tried with and without components with the same or similar results. > > So the component layout and thermal profile probably are not to blame. > > It must be the board design or the results of that combined with the > conventional layup for such a design. > > I can't say who designed the rack, but to our knowlege their own cards fit > into the rack OK - even though our samples are twisted to a small degree. > > We're prepared to try adding hashing to the inner layers - it > seems logical, > but as the PCB house seem not to be sure we don't want to spend > the money on > a run without all the available information (it costs 2k for each run). > > I'll keep you all informed of the solution and the outcome, thanks once > again for all the help. > > Jason > > > -Original Message- > From: Jon Elson [mailto:[EMAIL PROTECTED]] > Sent: 03 April 2002 21:53 > To: Protel EDA Forum > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Jason Morgan wrote: > > > Many thanks, > > > > Details are as follows: > > > > 6 Layer 1.6 FR4 > > 8" x 10" Board > > > > PCB support is a wasted rectangle 10mm wide along all edges, supporting > PCB > > at 2 or 3 points along each edge. (First observation is that > this should > > have copper layers) > > A number of different ways to even out copper coverage on layers on > opposing sides of board were mentioned, and these are probably aimed > at solving residual stresses left in the board. That sounds good, but may > be difficult to accomplish, dpending on board density, etc. > > One thing that comes to mind is that the boards come out of the laminating > press flat, go through all the additional steps in PCB fabrication OK, but > then warp when YOU process them to attach components. Are you sure > you have to heat the boards as hot, for as long as you are doing, to get > good soldering? That may have something to do with it. > > Finally, could you give the boards some mechanical support during > the reflow > soldering? Making some simple metal frames that hold the board edges > during the entire time it is heated might keep them flat as they cool. > > Jon > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Jason Morgan wrote: > We've tried with and without components with the same or similar results. Wow, this sure eliminates a number of possibilities! > I can't say who designed the rack, but to our knowlege their own cards fit > into the rack OK - even though our samples are twisted to a small degree. > > We're prepared to try adding hashing to the inner layers - it seems logical, > but as the PCB house seem not to be sure we don't want to spend the money on > a run without all the available information (it costs 2k for each run). I think this may be the only variable left to be manipulated. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Good question - too quickly read - too quick on reply - not answered. Still a good question. At 10:59 AM 4/4/02 -0800, you wrote: >But Harry, > the query was only, why there was 1.1mils associated with the NI/Au? >Normal standards would call for 150 - 200 uinches of NI and upto 50uinches >of Au. Not 1.1mils! snip * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
But Harry, the query was only, why there was 1.1mils associated with the NI/Au? Normal standards would call for 150 - 200 uinches of NI and upto 50uinches of Au. Not 1.1mils! Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11. > -Original Message- > From: H. Selfridge [mailto:[EMAIL PROTECTED]] > Sent: Thursday, April 04, 2002 10:34 AM > To: Protel EDA Forum > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Copper on a printed circuit is subject to severe oxidation > unless coated. > Cu oxides are poor electrical conductors. > > Gold is a passive metal with excellent conductivity. > > If you plate gold directly on copper, Au/Cu intermetallics > are formed that > cause the bond to be brittle and subject to mechanical > failure under stress. > > Plating nickel over the copper forms a barrier that has desirable > intermetallic characteristics. However, Ni also oxidizes > readily. Ni > oxides are poor electrical conductors. > > Plating Au over the Ni gives the best overall metallic > structure for a pcb > (pwb). The Au is corrosion resistant, and has excellent > conductivity. The > Ni barrier under the Au prevents Cu migration into the Au. > Ni/Au and Ni/Cu > intermetallics at the bonds are both hard and relatively durable. > > That is half a semester in 5 lines that tells why nickel > plating is used > under gold on a pcb (pwb). * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Copper on a printed circuit is subject to severe oxidation unless coated. Cu oxides are poor electrical conductors. Gold is a passive metal with excellent conductivity. If you plate gold directly on copper, Au/Cu intermetallics are formed that cause the bond to be brittle and subject to mechanical failure under stress. Plating nickel over the copper forms a barrier that has desirable intermetallic characteristics. However, Ni also oxidizes readily. Ni oxides are poor electrical conductors. Plating Au over the Ni gives the best overall metallic structure for a pcb (pwb). The Au is corrosion resistant, and has excellent conductivity. The Ni barrier under the Au prevents Cu migration into the Au. Ni/Au and Ni/Cu intermetallics at the bonds are both hard and relatively durable. That is half a semester in 5 lines that tells why nickel plating is used under gold on a pcb (pwb). At 08:38 AM 4/4/02 -0600, you wrote: snip >Anyone know why you would use such a think nickle plating? >Cheers >Mark snip * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Jason, You indicate the "Profile is Optimum" according to Fab. Which I conclude to be, that the layer stack up order is balanced around the center line of the board stack up.. As well , you indicated or implied the copper is equally distributed on each signal pair and internal plane pairs on either side of the center line of the layer stack up. Which means No odd numbered plane layers or signal layers..in the stack up.. etc.. No predominate copper pour areas in one section of the board vs. another.No split plane areas that are not balanced by a corresponding split plane area.. on the other side of the centerline of the layer stack up...etc. I have discovered that a balanced copper distribution is the number one requirement to control and or minimize warpage. If there is substantial difference in the percentage or density of copper on the signal layers, you will see differential expansions during reflow. That differential force will warp and twist the board and as it has been said in the past post a quick cool down will set the twist or warp. You indicated the component layout and thermal profile are probably not to blame. The question I ask, Is there a higher concentration of direct connection to the plane in one area vs.another?This will have a tremendous heat sinking differential and could cause a warpage as well. If all is well in the areas mention above.. Then that leaves Fab. shop with the lions share of the responsibility for warped boards if in fact the above conditions are met. Generally plating differentials are not enough to warp a board beyond 10% out of plane.. Fab. will need to review their process controls. Speed (time in the flow) and temperature here are the main parameters. I would look at the speed or the amount of time the board in the jig is sent through the Flow. If you can prove and or get fabrication to admit it is not in the design or layer stack up then it becomes their full responsibility and you should not have to pay for warped boards. Here, I assume you have in your fabrication drawings a specification that defines the acceptable percentage of warpage. That is my two cents.. Sam Cox. At 04:40 PM 4/4/2002 +0100, you wrote: >Thanks for all the advice and suggestions. > >Some more info that I missed from the first post: > >We've been trying to solve this for some time. We've tried boards supplied >from more than one house and populated at more than one house, all with the >same sorts of results. > >We're not the fab, so we have no control on the process, its up to their QA. > >The profile is optimum (according to fab) and any change would result in bad >joints. > >We've tried reflow and wave with the same or similar results. > >We've tried with and without components with the same or similar results. > >So the component layout and thermal profile probably are not to blame. > >It must be the board design or the results of that combined with the >conventional layup for such a design. > >I can't say who designed the rack, but to our knowlege their own cards fit >into the rack OK - even though our samples are twisted to a small degree. > >We're prepared to try adding hashing to the inner layers - it seems logical, >but as the PCB house seem not to be sure we don't want to spend the money on >a run without all the available information (it costs 2k for each run). > >I'll keep you all informed of the solution and the outcome, thanks once >again for all the help. > >Jason > > >-----Original Message- >From: Jon Elson [mailto:[EMAIL PROTECTED]] >Sent: 03 April 2002 21:53 >To: Protel EDA Forum >Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > >Jason Morgan wrote: > > > Many thanks, > > > > Details are as follows: > > > > 6 Layer 1.6 FR4 > > 8" x 10" Board > > > > PCB support is a wasted rectangle 10mm wide along all edges, supporting >PCB > > at 2 or 3 points along each edge. (First observation is that this should > > have copper layers) > >A number of different ways to even out copper coverage on layers on >opposing sides of board were mentioned, and these are probably aimed >at solving residual stresses left in the board. That sounds good, but may >be difficult to accomplish, dpending on board density, etc. > >One thing that comes to mind is that the boards come out of the laminating >press flat, go through all the additional steps in PCB fabrication OK, but >then warp when YOU process them to attach components. Are you sure >you have to heat the boards as hot, for as long as you are doing, to get >good soldering? That may have something to do with it. > >Finally, could you give the boards some mechanical support duri
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Hi Mark, on the Nickel/Gold I made a couple of assumptions. It is Nickel and Gold, not some fancy alloy and the thickness probably is in error. He is probably including his final copper plate in with the Nickel/Gold measurement as he doesn't list anything other then the initial 0.5oz foil for the external layer. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11. > -Original Message- > From: Mark E Witherite [mailto:[EMAIL PROTECTED]] > Sent: Thursday, April 04, 2002 6:38 AM > To: Protel EDA Forum > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Hi, > I did the math last night on the CTE differences. When I saw > the thick > nickel plating (5 times the mil STD 275 minimum (.2mils)), > it looked like > a bimetal element to me. But for a 10 inch length and a 100 degree C > change in temperature, the copper's final length was 10.017 > inches and the > nickel was 10.0133 inches. The 4 mill difference doesn't > appear to seem > to be a factor. I would have to dig out the text books to > determine how > much bow it would cause and I don't have time for that. > Anyone know why > you would use such a think nickle plating? > Cheers > Mark > > > -Original Message- > > > From: H. Selfridge [mailto:[EMAIL PROTECTED]] > > > Sent: Wednesday, April 03, 2002 13:24 > > > To: Protel EDA Forum > > > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > > > > <<>> > > > > > > At 04:52 PM 4/3/02 +0100, you wrote: > > > >Many thanks, > > > > > > > >Details are as follows: > > > > > > > >6 Layer 1.6 FR4 > > > >8" x 10" Board > > > > > > > >PCB support is a wasted rectangle 10mm wide along all edges, > > > supporting PCB > > > >at 2 or 3 points along each edge. (First observation is > > > that this should > > > >have copper layers) > > > > > > > >Layer stack up is two cores + two foils (sizes rounded to 1 > > > decimal place) > > > > > > > >R/P Layer Typethou > > > >- - Resist 0.4 > > > >R 1 Ni/Au 0.5oz 1.1 > > > >R 1 Foil 0.5oz 0.7 > > > >- - Prepreg 76307.0 > > > >P 2 1oz Copper 1.4 > > > >- - Core15.0 > > > >R 3 1oz Copper 1.4 > > > >- - Prepreg 10805.0 > > > >- - Prepreg 10805.0 > > > >R 4 1oz Copper 1.4 > > > >- - Core15.0 > > > >P 5 1oz Copper 1.4 > > > >- - Prepreg 76307.0 > > > >R 6 Foil 0.5oz 0.7 > > > >R 6 Ni/Au 0.5oz 1.1 > > > >- - Resist 0.4 > > > >- > > > >Total 64 = 1.625mm > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Thanks for all the advice and suggestions. Some more info that I missed from the first post: We've been trying to solve this for some time. We've tried boards supplied from more than one house and populated at more than one house, all with the same sorts of results. We're not the fab, so we have no control on the process, its up to their QA. The profile is optimum (according to fab) and any change would result in bad joints. We've tried reflow and wave with the same or similar results. We've tried with and without components with the same or similar results. So the component layout and thermal profile probably are not to blame. It must be the board design or the results of that combined with the conventional layup for such a design. I can't say who designed the rack, but to our knowlege their own cards fit into the rack OK - even though our samples are twisted to a small degree. We're prepared to try adding hashing to the inner layers - it seems logical, but as the PCB house seem not to be sure we don't want to spend the money on a run without all the available information (it costs 2k for each run). I'll keep you all informed of the solution and the outcome, thanks once again for all the help. Jason -Original Message- From: Jon Elson [mailto:[EMAIL PROTECTED]] Sent: 03 April 2002 21:53 To: Protel EDA Forum Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) Jason Morgan wrote: > Many thanks, > > Details are as follows: > > 6 Layer 1.6 FR4 > 8" x 10" Board > > PCB support is a wasted rectangle 10mm wide along all edges, supporting PCB > at 2 or 3 points along each edge. (First observation is that this should > have copper layers) A number of different ways to even out copper coverage on layers on opposing sides of board were mentioned, and these are probably aimed at solving residual stresses left in the board. That sounds good, but may be difficult to accomplish, dpending on board density, etc. One thing that comes to mind is that the boards come out of the laminating press flat, go through all the additional steps in PCB fabrication OK, but then warp when YOU process them to attach components. Are you sure you have to heat the boards as hot, for as long as you are doing, to get good soldering? That may have something to do with it. Finally, could you give the boards some mechanical support during the reflow soldering? Making some simple metal frames that hold the board edges during the entire time it is heated might keep them flat as they cool. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Since it seems to get better over time is it possible that there is a moisture or humidity related problem. I have seen surface mount chips explode if they absorb moisture then get soldered. If the laminate has moisture in it and it changes with the heating it may then relax as it reabsorbs moisture. Try baking a board at a lower temperature and see if you get the same warping. If this is the case it is a material problem. Larry At 04:04 PM 4/3/02 -0500, you wrote: >At 03:03 PM 4/3/2002 +0100, Jason Morgan wrote: > >>We have a board warping problem and are looking for a PCB expert to help >>resolve it. >>(Preferably located in the UK, but not important) > >Unless it involves looking at the fabbed board itself -- we haven't gone >far enough to know if that would be necessary -- location of the expert >should be irrelevant. > >>When I say expert, I mean *EXPERT*. The problem is quite complex and already >>has baffled two manufacturers. > >This is a tad discouraging. Usually manufacturers *are* the experts. But >the board is warping in reflow/wave solder, so a PCB fabricator might not >be the best source, I'd talk to assembly people. > >This list is also not the prime place to find advice on this, I'd suggest >the IPC Designers Forum. Butyou never can tell... > > From a subsequent post: > >>Details are as follows: >> >>6 Layer 1.6 FR4 >>8" x 10" Board > >Normal. > >>PCB support is a wasted rectangle 10mm wide along all edges, supporting PCB >>at 2 or 3 points along each edge. (First observation is that this should >>have copper layers) > >For the board to warp, especially if it is warping consistently, something >must be out of balance. Or the board material is bad or has been >improperly used, i.e., fabricator error. Fab error would mostly be another >version of "out of balance," such as some issue around warp and weft as >mentioned below. > >>Layer stack up is two cores + two foils (sizes rounded to 1 decimal place) >> >> >>R/P Layer Typethou >>- - Resist 0.4 >>R 1 Ni/Au 0.5oz 1.1 >>R 1 Foil 0.5oz 0.7 >>- - Prepreg 76307.0 >>P 2 1oz Copper 1.4 >>- - Core15.0 >>R 3 1oz Copper 1.4 >>- - Prepreg 10805.0 >>- - Prepreg 10805.0 >>R 4 1oz Copper 1.4 >>- - Core15.0 >>P 5 1oz Copper 1.4 >>- - Prepreg 76307.0 >>R 6 Foil 0.5oz 0.7 >>R 6 Ni/Au 0.5oz 1.1 >>- - Resist 0.4 >>- >>Total 64 = 1.625mm > >Unstated is the assignment of layers to trace and plane layers. That could >have a major effect on warp. > >What were the design considerations behind this stackup? > > >>Effects are: >>Boards are flat from production, but twist on heating in solder reflow or >>wave solder. > >The components being used could have some effect. Is it wave or reflow or >both? Who is doing the soldering? Are they experts? > >>An analysis of 5 board produced 1 that exceeded the IPC warpage >>specifications. >> >>Trouble is all but one was too twisted to fit into the rack without effort. > >Right off I wonder why boards that meet IPC spec for warpage are difficult >to insert into the rack. Who designed the rack? One would think a rack >would be designed to accommodate a certain level of warp, specifically >that which is within standard production specifications. > >>We had the same problem with the alpha version, but here this was put down >>to an incomplete plane >>on the two plance layers, this has been changed to a full plane - no change >>to warp. > >You don't have enough data to say that with certainty, I'd suggest. The >sample is too small. > >Some precise description of the amount of warp, and the variance over the >sample space, might be useful. > >>Suggestions so far have been to: >>0: Add copper to waste (breakout) parts layers >>1: Change the breakout to a waste part scored along the two long edges. >>2: Use a three core construction >>3: Add copper hash to layers 3 and 4, (other either side of the two >>cores) >>4: Change warp and weft of cores >>5: Increase core thickness and decrease 1080 prepreg thickness. >>6: Use 1.8 FR4 by increasing core thickness (undesireable) > >I'd think that 6 might be ruled out because it could make the board more >difficult to fit into a rack, plus stackup design might be necessarily >controlled by other crucial design considerations, such as impedance and >interplane capacitance. > >>So far we've had no input from the manufacturer as to what (if any) of the >>above will be better, though >>they agree that all should have some affect (positive or negative) on bow >>and twist. > >This is less than helpful! >
Re: [PEDA] WANTED: PCB Expert (Off Topic)
I have to backpedal on the CTE differences, I jumped on it because the pure CTEs are that much different, all other things being equal. I have no idea what Ni-Au alloy CTE is vs Cu. I think Mr. Selfridge enumerates the more likely culprits. I have experienced some of those, albeit on MUCH larger boards, e.g. 14" x 17" x 0.093 with a LOT of weight--many rows of small relays. 8 by 10 is pretty small, so I agree that you would look at the laminate process, copper distribution on matched layers, and the jig. > -Original Message- > From: H. Selfridge [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, April 03, 2002 13:24 > To: Protel EDA Forum > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Some things to consider: > > 1. FR4 resin transition temperature is between 115C and > 135C. Reflow > soldering temperatures are typically 215C to 255C. Any > internal stress in > the board will be relieved by warp and twist when the board > becomes plastic > at the reflow temperature. The board fab must use care when > pressing to > ensure that cooldown is controlled and uniform - otherwise > internal stress > is created which will try to relieve in the reflow process. > > 2. Since reflow temperature is typically above resin transition > temperature, the board must be properly supported during > reflow. If the > jigs are not properly set, the board will deform during reflow. > > 3. Component placement on thin boards is a factor because of > weight during > reflow, and because of component heat-sinking during reflow. > Again, the > jig placement, and cooldown control are critical. > > 4. Your details suggest you have tried to keep a balanced copper > distribution. If, however, there is substantial difference in the > percentage of copper on the signal layers, you will see differential > expansion during reflow. That differential force will warp > and twist the > board - quick cooldown will set the twist. > > From your comment that the board tends to flatten after a > period of time, > it seems likely that one of items 2 thru 4 above is at play. On the > limited information available, I would look especially > carefully at the > copper balance in opposing layers. > > > > > At 04:52 PM 4/3/02 +0100, you wrote: > >Many thanks, > > > >Details are as follows: > > > >6 Layer 1.6 FR4 > >8" x 10" Board > > > >PCB support is a wasted rectangle 10mm wide along all edges, > supporting PCB > >at 2 or 3 points along each edge. (First observation is > that this should > >have copper layers) > > > >Layer stack up is two cores + two foils (sizes rounded to 1 > decimal place) > > > >R/P Layer Typethou > >- - Resist 0.4 > >R 1 Ni/Au 0.5oz 1.1 > >R 1 Foil 0.5oz 0.7 > >- - Prepreg 76307.0 > >P 2 1oz Copper 1.4 > >- - Core15.0 > >R 3 1oz Copper 1.4 > >- - Prepreg 10805.0 > >- - Prepreg 10805.0 > >R 4 1oz Copper 1.4 > >- - Core15.0 > >P 5 1oz Copper 1.4 > >- - Prepreg 76307.0 > >R 6 Foil 0.5oz 0.7 > >R 6 Ni/Au 0.5oz 1.1 > >- - Resist 0.4 > >- > >Total 64 = 1.625mm > > > >Effects are: > >Boards are flat from production, but twist on heating in > solder reflow or > >wave solder. > > > >An analysis of 5 board produced 1 that exceeded the IPC warpage > >specifications. > > > >Trouble is all but one was too twisted to fit into the rack > without effort. > > > >We had the same problem with the alpha version, but here > this was put down > >to an incomplete plane > >on the two plance layers, this has been changed to a full > plane - no change > >to warp. > > > >Suggestions so far have been to: > >0: Add copper to waste (breakout) parts layers > >1: Change the breakout to a waste part scored along the > two long edges. > >2: Use a three core construction > >3: Add copper hash to layers 3 and 4, (other either > side of the two > >cores) > >4: Change warp and weft of cores > >5: Increase core thickness and decrease 1080 prepreg thickness. > >6: Use 1.8 FR4 by increasing core thick
Re: [PEDA] WANTED: PCB Expert (Off Topic)
At 03:03 PM 4/3/2002 +0100, Jason Morgan wrote: >We have a board warping problem and are looking for a PCB expert to help >resolve it. >(Preferably located in the UK, but not important) Unless it involves looking at the fabbed board itself -- we haven't gone far enough to know if that would be necessary -- location of the expert should be irrelevant. >When I say expert, I mean *EXPERT*. The problem is quite complex and already >has baffled two manufacturers. This is a tad discouraging. Usually manufacturers *are* the experts. But the board is warping in reflow/wave solder, so a PCB fabricator might not be the best source, I'd talk to assembly people. This list is also not the prime place to find advice on this, I'd suggest the IPC Designers Forum. Butyou never can tell... From a subsequent post: >Details are as follows: > >6 Layer 1.6 FR4 >8" x 10" Board Normal. >PCB support is a wasted rectangle 10mm wide along all edges, supporting PCB >at 2 or 3 points along each edge. (First observation is that this should >have copper layers) For the board to warp, especially if it is warping consistently, something must be out of balance. Or the board material is bad or has been improperly used, i.e., fabricator error. Fab error would mostly be another version of "out of balance," such as some issue around warp and weft as mentioned below. >Layer stack up is two cores + two foils (sizes rounded to 1 decimal place) > > >R/P Layer Typethou >- - Resist 0.4 >R 1 Ni/Au 0.5oz 1.1 >R 1 Foil 0.5oz 0.7 >- - Prepreg 76307.0 >P 2 1oz Copper 1.4 >- - Core15.0 >R 3 1oz Copper 1.4 >- - Prepreg 10805.0 >- - Prepreg 10805.0 >R 4 1oz Copper 1.4 >- - Core15.0 >P 5 1oz Copper 1.4 >- - Prepreg 76307.0 >R 6 Foil 0.5oz 0.7 >R 6 Ni/Au 0.5oz 1.1 >- - Resist 0.4 >- >Total 64 = 1.625mm Unstated is the assignment of layers to trace and plane layers. That could have a major effect on warp. What were the design considerations behind this stackup? >Effects are: >Boards are flat from production, but twist on heating in solder reflow or >wave solder. The components being used could have some effect. Is it wave or reflow or both? Who is doing the soldering? Are they experts? >An analysis of 5 board produced 1 that exceeded the IPC warpage >specifications. > >Trouble is all but one was too twisted to fit into the rack without effort. Right off I wonder why boards that meet IPC spec for warpage are difficult to insert into the rack. Who designed the rack? One would think a rack would be designed to accommodate a certain level of warp, specifically that which is within standard production specifications. >We had the same problem with the alpha version, but here this was put down >to an incomplete plane >on the two plance layers, this has been changed to a full plane - no change >to warp. You don't have enough data to say that with certainty, I'd suggest. The sample is too small. Some precise description of the amount of warp, and the variance over the sample space, might be useful. >Suggestions so far have been to: >0: Add copper to waste (breakout) parts layers >1: Change the breakout to a waste part scored along the two long edges. >2: Use a three core construction >3: Add copper hash to layers 3 and 4, (other either side of the two >cores) >4: Change warp and weft of cores >5: Increase core thickness and decrease 1080 prepreg thickness. >6: Use 1.8 FR4 by increasing core thickness (undesireable) I'd think that 6 might be ruled out because it could make the board more difficult to fit into a rack, plus stackup design might be necessarily controlled by other crucial design considerations, such as impedance and interplane capacitance. >So far we've had no input from the manufacturer as to what (if any) of the >above will be better, though >they agree that all should have some affect (positive or negative) on bow >and twist. This is less than helpful! The exact geometry of the warping could be interesting. For example, if the warping is aligned with the division between the waste area and the main board area, or with some other copper discontinuity, this could point to the cause. I'd make at least a rough contour map of the most warped board, and overlay this over the design on a mech layer to see what associations pop out. If I had to do something quickly with this board, I would add hatching to all empty spaces on the board, such that each layer had roughly the same copper density over its entire surface, and such that each lay
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Jason Morgan wrote: > Many thanks, > > Details are as follows: > > 6 Layer 1.6 FR4 > 8" x 10" Board > > PCB support is a wasted rectangle 10mm wide along all edges, supporting PCB > at 2 or 3 points along each edge. (First observation is that this should > have copper layers) A number of different ways to even out copper coverage on layers on opposing sides of board were mentioned, and these are probably aimed at solving residual stresses left in the board. That sounds good, but may be difficult to accomplish, dpending on board density, etc. One thing that comes to mind is that the boards come out of the laminating press flat, go through all the additional steps in PCB fabrication OK, but then warp when YOU process them to attach components. Are you sure you have to heat the boards as hot, for as long as you are doing, to get good soldering? That may have something to do with it. Finally, could you give the boards some mechanical support during the reflow soldering? Making some simple metal frames that hold the board edges during the entire time it is heated might keep them flat as they cool. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Re: [PEDA] WANTED: PCB Expert (Off Topic)
I agree with Brad Mike Reagan - Original Message - From: Brad Velander <[EMAIL PROTECTED]> To: 'Protel EDA Forum' <[EMAIL PROTECTED]> Sent: Wednesday, April 03, 2002 2:07 PM Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) Darryl, Henry, Mark, just as a point of discussion, I don't see the issue that you allude to. The nickel and copper are reasonably well matched. The nickel and copper are typically just either side of the laminate CTE. Nickel must be thicker then gold in any reasonable plating application and gold is so ductile, I can't see the gold effecting bow or twist. Please share any comments, possibly you know something that I have never seen nor heard of. If it's fine with you we can take this to OT the forum. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11. > -Original Message- > From: Darryl Newberry [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, April 03, 2002 10:45 AM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Ditto on CTE mismatch & profile. > Cu = 16.56 m/m* C > Au = 4.39 m/m* C > Ni = 12.96 m/m* C > > Ni-Au = ?? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Darryl, Henry, Mark, just as a point of discussion, I don't see the issue that you allude to. The nickel and copper are reasonably well matched. The nickel and copper are typically just either side of the laminate CTE. Nickel must be thicker then gold in any reasonable plating application and gold is so ductile, I can't see the gold effecting bow or twist. Please share any comments, possibly you know something that I have never seen nor heard of. If it's fine with you we can take this to OT the forum. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11. > -Original Message- > From: Darryl Newberry [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, April 03, 2002 10:45 AM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > Ditto on CTE mismatch & profile. > Cu = 16.56 µm/m*°C > Au = 4.39 µm/m*°C > Ni = 12.96 µm/m*°C > > Ni-Au = ?? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Ditto on CTE mismatch & profile. Cu = 16.56 µm/m*°C Au = 4.39 µm/m*°C Ni = 12.96 µm/m*°C Ni-Au = ?? > -Original Message- > From: Mark E Witherite [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, April 03, 2002 13:56 > To: Protel EDA Forum > Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > My Money is on the mismatch of thermal coefficient of > expansion between the > copper and the nickle gold foil. > > At 04:52 PM 4/3/02 +0100, you wrote: > >Many thanks, > > > >Details are as follows: > > > >6 Layer 1.6 FR4 > >8" x 10" Board > > > >PCB support is a wasted rectangle 10mm wide along all edges, > supporting PCB > >at 2 or 3 points along each edge. (First observation is > that this should > >have copper layers) > > > >Layer stack up is two cores + two foils (sizes rounded to 1 > decimal place) > > > >R/P Layer Typethou > >- - Resist 0.4 > >R 1 Ni/Au 0.5oz 1.1 > >R 1 Foil 0.5oz 0.7 > >- - Prepreg 76307.0 > >P 2 1oz Copper 1.4 > >- - Core15.0 > >R 3 1oz Copper 1.4 > >- - Prepreg 10805.0 > >- - Prepreg 10805.0 > >R 4 1oz Copper 1.4 > >- - Core15.0 > >P 5 1oz Copper 1.4 > >- - Prepreg 76307.0 > >R 6 Foil 0.5oz 0.7 > >R 6 Ni/Au 0.5oz 1.1 > >- - Resist 0.4 > >- > >Total 64 = 1.625mm > > > >Effects are: > >Boards are flat from production, but twist on heating in > solder reflow or > >wave solder. > > > >An analysis of 5 board produced 1 that exceeded the IPC warpage > >specifications. > > > >Trouble is all but one was too twisted to fit into the rack > without effort. > > > >We had the same problem with the alpha version, but here > this was put down > >to an incomplete plane > >on the two plance layers, this has been changed to a full > plane - no change > >to warp. > > > >Suggestions so far have been to: > >0: Add copper to waste (breakout) parts layers > >1: Change the breakout to a waste part scored along the > two long edges. > >2: Use a three core construction > >3: Add copper hash to layers 3 and 4, (other either > side of the two > >cores) > >4: Change warp and weft of cores > >5: Increase core thickness and decrease 1080 prepreg thickness. > >6: Use 1.8 FR4 by increasing core thickness (undesireable) > > > >So far we've had no input from the manufacturer as to what > (if any) of the > >above will be better, though > >they agree that all should have some affect (positive or > negative) on bow > >and twist. > > > >We've also noticed that over a long period (weeks) the twist > gets less. > > > >Regards > > > >Jason. > > > > > >-Original Message- > >From: Mike Reagan [mailto:[EMAIL PROTECTED]] > >Sent: 03 April 2002 16:43 > >To: Protel EDA Forum > >Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > > > > >Jason > >Some of our advice is free > >What process is warping the boards? Reflow or > manufacturing? or upset > >employee? > > > >Mike Reagan > >EDSI > > > > > > > >- Original Message - > >From: Jason Morgan <[EMAIL PROTECTED]> > >To: 'Protel EDA Forum' <[EMAIL PROTECTED]> > >Sent: Wednesday, April 03, 2002 9:03 AM > >Subject: [PEDA] WANTED: PCB Expert (Off Topic) > > > > > > > Hi, > > > > > > We have a board warping problem and are looking for a PCB > expert to help > > > resolve it. > > > (Preferably located in the UK, but not important) > > > > > > When I say expert, I mean *EXPERT*. The problem is quite > complex and > >already > > > has baffled two manufacturers. > > > > > > We will pay the going rate for any consultation. > > > > > > Regards, > > > > > > Jason Morgan > > > > > Mark Witherite C.I.D. > Assistant Research Engineer > Astronomy & Astrophysics > Penn State University > 2565 Park Center Blvd > Suite 200 > State College, PA. 16801 > email [EMAIL PROTECTED] > telephone 814 865 9839 > fax 814 865 9100 > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Some things to consider: 1. FR4 resin transition temperature is between 115C and 135C. Reflow soldering temperatures are typically 215C to 255C. Any internal stress in the board will be relieved by warp and twist when the board becomes plastic at the reflow temperature. The board fab must use care when pressing to ensure that cooldown is controlled and uniform - otherwise internal stress is created which will try to relieve in the reflow process. 2. Since reflow temperature is typically above resin transition temperature, the board must be properly supported during reflow. If the jigs are not properly set, the board will deform during reflow. 3. Component placement on thin boards is a factor because of weight during reflow, and because of component heat-sinking during reflow. Again, the jig placement, and cooldown control are critical. 4. Your details suggest you have tried to keep a balanced copper distribution. If, however, there is substantial difference in the percentage of copper on the signal layers, you will see differential expansion during reflow. That differential force will warp and twist the board - quick cooldown will set the twist. From your comment that the board tends to flatten after a period of time, it seems likely that one of items 2 thru 4 above is at play. On the limited information available, I would look especially carefully at the copper balance in opposing layers. At 04:52 PM 4/3/02 +0100, you wrote: >Many thanks, > >Details are as follows: > >6 Layer 1.6 FR4 >8" x 10" Board > >PCB support is a wasted rectangle 10mm wide along all edges, supporting PCB >at 2 or 3 points along each edge. (First observation is that this should >have copper layers) > >Layer stack up is two cores + two foils (sizes rounded to 1 decimal place) > >R/P Layer Typethou >- - Resist 0.4 >R 1 Ni/Au 0.5oz 1.1 >R 1 Foil 0.5oz 0.7 >- - Prepreg 76307.0 >P 2 1oz Copper 1.4 >- - Core15.0 >R 3 1oz Copper 1.4 >- - Prepreg 10805.0 >- - Prepreg 10805.0 >R 4 1oz Copper 1.4 >- - Core15.0 >P 5 1oz Copper 1.4 >- - Prepreg 76307.0 >R 6 Foil 0.5oz 0.7 >R 6 Ni/Au 0.5oz 1.1 >- - Resist 0.4 >- >Total 64 = 1.625mm > >Effects are: >Boards are flat from production, but twist on heating in solder reflow or >wave solder. > >An analysis of 5 board produced 1 that exceeded the IPC warpage >specifications. > >Trouble is all but one was too twisted to fit into the rack without effort. > >We had the same problem with the alpha version, but here this was put down >to an incomplete plane >on the two plance layers, this has been changed to a full plane - no change >to warp. > >Suggestions so far have been to: >0: Add copper to waste (breakout) parts layers >1: Change the breakout to a waste part scored along the two long edges. >2: Use a three core construction >3: Add copper hash to layers 3 and 4, (other either side of the two >cores) >4: Change warp and weft of cores >5: Increase core thickness and decrease 1080 prepreg thickness. >6: Use 1.8 FR4 by increasing core thickness (undesireable) > >So far we've had no input from the manufacturer as to what (if any) of the >above will be better, though >they agree that all should have some affect (positive or negative) on bow >and twist. > >We've also noticed that over a long period (weeks) the twist gets less. > >Regards > >Jason. > > >-Original Message- >From: Mike Reagan [mailto:[EMAIL PROTECTED]] >Sent: 03 April 2002 16:43 >To: Protel EDA Forum >Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) > > >Jason >Some of our advice is free >What process is warping the boards? Reflow or manufacturing? or upset >employee? > >Mike Reagan >EDSI > > > >- Original Message - >From: Jason Morgan <[EMAIL PROTECTED]> >To: 'Protel EDA Forum' <[EMAIL PROTECTED]> >Sent: Wednesday, April 03, 2002 9:03 AM >Subject: [PEDA] WANTED: PCB Expert (Off Topic) > > > > Hi, > > > > We have a board warping problem and are looking for a PCB expert to help > > resolve it. > > (Preferably located in the UK, but not important) > > > > When I say expert, I mean *EXPERT*. The problem is quite complex and >already > > has baffled t
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Have you tried running a blank board (no solder, no components) through the solder/reflow heating cycle? And possibly a board with solder, but no components? >> > Hi, >> > >> > We have a board warping problem and are looking for a PCB expert to help >> > resolve it. >> > (Preferably located in the UK, but not important) >> > >> > When I say expert, I mean *EXPERT*. The problem is quite complex and >>already >> > has baffled two manufacturers. >> > >> > We will pay the going rate for any consultation. >> > >> > Regards, >> > >> > Jason Morgan >> > > >Mark Witherite C.I.D. >Assistant Research Engineer >Astronomy & Astrophysics >Penn State University >2565 Park Center Blvd >Suite 200 >State College, PA. 16801 >email [EMAIL PROTECTED] >telephone 814 865 9839 >fax 814 865 9100 > > Cheesecote Mountain CAMAC, 24 Halley Drive; Pomona, NY 10970 voice: 845 364 0211, fax: 845 362 6947, www.cmcamac.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Jason, here is just one possible avenue to add to your enquiries, reflow/wave temp profile! Is the temp profile heating or cooling too quickly (particularly cooling). One other thing that you don't mention, how is the copper balance across the design and all layers? I don't necessarily have your answer but thought these two issues were not mentioned. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Many thanks, Details are as follows: 6 Layer 1.6 FR4 8" x 10" Board PCB support is a wasted rectangle 10mm wide along all edges, supporting PCB at 2 or 3 points along each edge. (First observation is that this should have copper layers) Layer stack up is two cores + two foils (sizes rounded to 1 decimal place) R/P Layer Typethou - - Resist 0.4 R 1 Ni/Au 0.5oz 1.1 R 1 Foil 0.5oz 0.7 - - Prepreg 76307.0 P 2 1oz Copper 1.4 - - Core15.0 R 3 1oz Copper 1.4 - - Prepreg 10805.0 - - Prepreg 10805.0 R 4 1oz Copper 1.4 - - Core15.0 P 5 1oz Copper 1.4 - - Prepreg 76307.0 R 6 Foil 0.5oz 0.7 R 6 Ni/Au 0.5oz 1.1 - - Resist 0.4 - Total 64 = 1.625mm Effects are: Boards are flat from production, but twist on heating in solder reflow or wave solder. An analysis of 5 board produced 1 that exceeded the IPC warpage specifications. Trouble is all but one was too twisted to fit into the rack without effort. We had the same problem with the alpha version, but here this was put down to an incomplete plane on the two plance layers, this has been changed to a full plane - no change to warp. Suggestions so far have been to: 0: Add copper to waste (breakout) parts layers 1: Change the breakout to a waste part scored along the two long edges. 2: Use a three core construction 3: Add copper hash to layers 3 and 4, (other either side of the two cores) 4: Change warp and weft of cores 5: Increase core thickness and decrease 1080 prepreg thickness. 6: Use 1.8 FR4 by increasing core thickness (undesireable) So far we've had no input from the manufacturer as to what (if any) of the above will be better, though they agree that all should have some affect (positive or negative) on bow and twist. We've also noticed that over a long period (weeks) the twist gets less. Regards Jason. -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED]] Sent: 03 April 2002 16:43 To: Protel EDA Forum Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic) Jason Some of our advice is free What process is warping the boards? Reflow or manufacturing? or upset employee? Mike Reagan EDSI - Original Message - From: Jason Morgan <[EMAIL PROTECTED]> To: 'Protel EDA Forum' <[EMAIL PROTECTED]> Sent: Wednesday, April 03, 2002 9:03 AM Subject: [PEDA] WANTED: PCB Expert (Off Topic) > Hi, > > We have a board warping problem and are looking for a PCB expert to help > resolve it. > (Preferably located in the UK, but not important) > > When I say expert, I mean *EXPERT*. The problem is quite complex and already > has baffled two manufacturers. > > We will pay the going rate for any consultation. > > Regards, > > Jason Morgan > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] WANTED: PCB Expert (Off Topic)
Jason Some of our advice is free What process is warping the boards? Reflow or manufacturing? or upset employee? Mike Reagan EDSI - Original Message - From: Jason Morgan <[EMAIL PROTECTED]> To: 'Protel EDA Forum' <[EMAIL PROTECTED]> Sent: Wednesday, April 03, 2002 9:03 AM Subject: [PEDA] WANTED: PCB Expert (Off Topic) > Hi, > > We have a board warping problem and are looking for a PCB expert to help > resolve it. > (Preferably located in the UK, but not important) > > When I say expert, I mean *EXPERT*. The problem is quite complex and already > has baffled two manufacturers. > > We will pay the going rate for any consultation. > > Regards, > > Jason Morgan > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
