Add missing break to prevent rate change of CLK_I2C8 to fall through
and also affect the CLK_I2C9 rate.
Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <[email protected]>
---
Changes in v2:
- Split from "rk3576: Fix trivial clock configuration errors"
- Add fixes tag
---
drivers/clk/rockchip/clk_rk3576.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk_rk3576.c
b/drivers/clk/rockchip/clk_rk3576.c
index 314a543895a3..04b0f6b13ed3 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -469,6 +469,7 @@ static ulong rk3576_i2c_set_clk(struct rk3576_clk_priv
*priv, ulong clk_id,
case CLK_I2C8:
rk_clrsetreg(&cru->clksel_con[57], CLK_I2C8_SEL_MASK,
src_clk << CLK_I2C8_SEL_SHIFT);
+ break;
case CLK_I2C9:
rk_clrsetreg(&cru->clksel_con[58], CLK_I2C9_SEL_MASK,
src_clk << CLK_I2C9_SEL_SHIFT);
--
2.55.0