Re: [PEDA] A little OT - PCB labelling
Maxim makes some silicon serial number chips. But they aren't human readable - you need to connect a computing/display device to read out the serial number. If human readable is what you must have, the only thing I can think of that will survive all your board treatments is engraving. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Stephen Casey [EMAIL PROTECTED] To: Protel forum [EMAIL PROTECTED] Sent: Thursday, June 05, 2003 8:17 AM Subject: [PEDA] A little OT - PCB labelling Hello all, What methods of labelling would you recommend for unique identification of PCBs. We have been using thermal printed labels for serial numbers etc, but these are destroyed if a board is reworked. The boards have an area for hand writing serial numbers, but this is removed when solvent cleaning! I need a simple method of labelling individual boards, that'll withstand high temperatures and solvents! Any ideas? Thanks a lot. Steve. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
Here are some I have tried; Metallic inks, solder resist - add a little thinner to make it runny enough to write with and apply with fine brush, engraving pen, paper label with polyimide tape (gold tape) over the top We used to life test at 220°C for 1000hrs and marking was indeed a pain. The first two methods need a brush for application so are a bit fiddly. The last two methods were overall winners with method four firm favourite for speed and convenience. Ordinary soft graphite pencil is best for marking the paper part of the label. I suppose reflow temperatures are higher but exposure is much shorter so you might be OK. Rob Stephen Casey [EMAIL PROTECTED]To: Protel forum [EMAIL PROTECTED] ee.co.ukcc: Subject: [PEDA] A little OT - PCB labelling 05-Jun-2003 01:17 PM Please respond to Protel EDA Forum Hello all, What methods of labelling would you recommend for unique identification of PCBs. We have been using thermal printed labels for serial numbers etc, but these are destroyed if a board is reworked. The boards have an area for hand writing serial numbers, but this is removed when solvent cleaning! I need a simple method of labelling individual boards, that'll withstand high temperatures and solvents! Any ideas? Thanks a lot. Steve. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
In a message dated 6/5/2003 9:07:39 AM Eastern Daylight Time, [EMAIL PROTECTED] writes: What methods of labelling would you recommend for unique identification of PCBs. We have been using thermal printed labels for serial numbers etc, but these are destroyed if a board is reworked. The boards have an area for hand writing serial numbers, but this is removed when solvent cleaning! I need a simple method of labelling individual boards, that'll withstand high temperatures and solvents! Any ideas? How about an area of bare copper (soldermask opening) in which you can scribe the serial number? Steve Hendrix * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
Hmm, that will withstand high temperatures and solvents!, and that is user-configurable, ie, is not executed by etching of each board with a unique s/n? An engraved plate that is riveted to the board (not screwed) is the first thing that comes to mind. You would, of course, need to assign an area to attach the nameplate, and it might be of some value to have the holes taken care of during the etch/drilling operation. aj From: Stephen Casey [mailto:[EMAIL PROTECTED] Hello all, What methods of labelling would you recommend for unique identification of PCBs. We have been using thermal printed labels for serial numbers etc, but these are destroyed if a board is reworked. The boards have an area for hand writing serial numbers, but this is removed when solvent cleaning! I need a simple method of labelling individual boards, that'll withstand high temperatures and solvents! Any ideas? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
Hi Steve, We have been using a kind of stamp marker that imprints the P/N or S/N onto the PCB. The result is much better if you have a solid area of copper (components side or solder side) where the imprint is made. Since it is mechanical it won't be affected by heat or solvent. The digit dials of our stamper had an auto-increment feature that was very useful for S/N. The digit size was about 0.1 Inch high if I remember correctly. 10~12 digits. I hope this helps. Nick * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
Thanks Ivan, We do have a Maxim device on the board (Superb little things - I try to put one on everything I design), but we also need some human readable labelling (don't ask me why - ISO900 (or whatever today's new quality initiative is called) nonsense!). I'll keep thinking. Steve. As an aside, and at the risk of causing offence, is it just me or is every QA inspector a failed Engineer? Every time I get audited they always say 'Hey, I used to be an Engineer'. Well, I am an Engineer, and can't fathom why anybody who wanted to do engineering, and was good at it, would want to move into QA inspection. I'll stop now - My blood pressure is on the rise! -Original Message- From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED] Sent: 05 June 2003 14:22 To: Protel EDA Forum Subject: Re: [PEDA] A little OT - PCB labelling Maxim makes some silicon serial number chips. But they aren't human readable - you need to connect a computing/display device to read out the serial number. If human readable is what you must have, the only thing I can think of that will survive all your board treatments is engraving. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Stephen Casey [EMAIL PROTECTED] To: Protel forum [EMAIL PROTECTED] Sent: Thursday, June 05, 2003 8:17 AM Subject: [PEDA] A little OT - PCB labelling Hello all, What methods of labelling would you recommend for unique identification of PCBs. We have been using thermal printed labels for serial numbers etc, but these are destroyed if a board is reworked. The boards have an area for hand writing serial numbers, but this is removed when solvent cleaning! I need a simple method of labelling individual boards, that'll withstand high temperatures and solvents! Any ideas? Thanks a lot. Steve. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] stackups - Capacitance - Book Recommendation Wanted
There are obviously a lot of analog things to worry about when designing a fast, dense digital board. I fought a large digital board I did through 3 iterations by simply trying different things without fully knowing what I was doing. It eventually worked but I don't know if my next design will! I would appreciate it if someone could recommend some books on high speed board design that cover topics such as stackups, capacitor resonances, trace thickness, and any other important issues. Of course, I would prefer a cookbook approach if possible since I don't want to get into the heavy math of it all if I can avoid it. Thanks, Ray Mitchell * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] how to control GND connections
Hello again. I've been tossing and turning this problem over and over and stil haven't a workable solution. I do not want every via or component pin that is in the GND net to connect to the GND plan, only certain ones; I want to control where the current enters the plane. Putting arcs around them works, but is not correctly handled by the DRC: on one board I ended up with too many arcs and no connection to GND.. Luckily the fab house made a comment on those arcs and I could save the otherwise useless boards by specifying what arc to remove. Is there a way to do this that at least generates a DRC warning? OKok I got the warning that there were primitives on the GND plane but that didn't help much: I usually have stackup and other texts/markers on every copper layer. The warning didn't specify any of them so I wrongly assumed it was moating about my texts and such. Maybe someone in the forum has figured this out, or has some otherwise useful comments. Any help is (as always) greatly appreciated. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance
Thanks for the in-depth story and link. Rene Ian Wilson wrote: The first resonance (at least) of a cap is series, so looks like a short circuit. By adding a number of different valued caps you can scatter a number of these nice AC shorts around your board and around your frequencies of interest. [ snip ] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
Hi, In a previous company we used a self adhesive pre-printed metallic label that could stand (2-3 passes) of reflow and was safe in the wash. It even withstood conformal coat removal. However I don't know the supplier, the fab house was Foundation Technologies (A division or Radstone) in Towchester, UK. Jason. -Original Message- From: Stephen Casey [mailto:[EMAIL PROTECTED] Sent: 05 June 2003 13:17 To: Protel forum Subject: [PEDA] A little OT - PCB labelling Hello all, What methods of labelling would you recommend for unique identification of PCBs. We have been using thermal printed labels for serial numbers etc, but these are destroyed if a board is reworked. The boards have an area for hand writing serial numbers, but this is removed when solvent cleaning! I need a simple method of labelling individual boards, that'll withstand high temperatures and solvents! Any ideas? Thanks a lot. Steve. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Dennis, Please see below. JaMi - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, June 04, 2003 4:30 PM Subject: Re: [PEDA] eight-layer stackup you just use a via and short track in the component footprint design and then run update free primitives (yes i know they are not 'free') it works no drc probs You are right, this does in fact work fine, and in fact is pretty close to what I do normally anyway. I normally use one separate component for the BGA pad pattern footprint, and then make a second component that contains all of the dogbone traces and vias and all of what I call the BGA escape routing, which is all of the inner routing on the different layers out to the edge of the BGA. I keep all of the escape routing intact in its own component, which is placed in the design directly on top of the BGA component footprint (with free primitives updated)until I have everything in the area of the BGA routed exactly the way I want it. This allows me to easily edit the routing internal to the perimeter of the BGA in the Component Editor, and use Update PCB and then as you point out, use the update free primitives. Once I get everything the way I like it, I then release all of the primitives of the second component into the design, and then all of the traces and vias become part of the design. Using your methodology, I would just keep the dogbone traces and the vias as part of my first component, rather then the second component which I release. For that matter, I could just keep everything from my normal first BGA component and my second routing component, all in one component, and never release any it, and just keep updating free primitives as I go along. I guess it is all a matter of personal preferences. I prefer to have a standard BGA pattern for a component, and have nothing attached to it in the end product, and have all of my vias and traces and routing as normal vias and traces in the end product of the board, where I can go in and change things such as width or layer or whatever one at a time just as a normal trace. This also allows me to do things like highlight a net all the way to the BGA pad, and get the full length of the net in the netlist report. Most importantly, this method allows me to end up with a PCB that does not have any non standard little hidden tricks in it that may not be seen by the next person down the line to work on the board, or even forgotten by me the next time I have to come back in a year or two and work on the design again. In this sense, I would prefer to have the DRC errors showing right out there in plain sight where they can be seen for what they are. My whole point in this post and the earlier post where I discussed this DRC error issue (see the thread on subject quick question on last Saturday (5/31/03)) is simply that sometimes Protel DRC errors really are not errors at all, and I would like a way to handle them. Certainly there are ways to do tricks to make the little iridescent glow go away, but in some cases I just learn to live with them. I personally would rather have a Protel DRC error glowing here and there (which I can simply reset so I do not have to look at them) in the design, than have to play tricks here and there and do some non standard thing to make the DRC happy. I would rather have the DRC error, which anyone could see was not a real error anyway, then have to jump thru the update free primitives hoop on the finished design that gets released to production and sent down the road to the next designer who may work on the design a few years from now after I am gone. There is just something that bugs me about having to play tricks in a design to make a screwed up piece of software happy, especially when the screwed up piece of software in wrong half the time when it comes to DRC errors anyway. am i on the same page as this discussion or maybe i have missed something? Yep. You are in fact on the exact same page. ds JaMi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] how to control GND connections
For products that are not highly cost sensitive we typically label different ground groups separately on the schematic-- DGND (digital ground), PGND (power ground), AGND (analog ground), SGND (sensor ground), etc., etc.-- which need to be kept separate to avoid errors due to high-currents along certain parts of the ground plane-- and then connect them together at critical points using zero ohm resistors or ferrite beads. A side benefit--this can be useful during circuit testing and debugging because one can more readily isolate sources of noise, shorts, and other faults. More of a workaround than a solution to your problembut one which we use increasingly because it not only avoids the CAD problem that you bring up, but also makes the product more serviceable. Best regards, Kerry Berland [EMAIL PROTECTED] Silicon Engines 2101 Oxford Road Des Plaines, IL 60018 USA 847-803-6860 Fax 847-803-6870 - Original Message - From: Leo Potjewijd [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Thursday, June 05, 2003 10:47 AM Subject: [PEDA] how to control GND connections Hello again. I've been tossing and turning this problem over and over and stil haven't a workable solution. I do not want every via or component pin that is in the GND net to connect to the GND plan, only certain ones; I want to control where the current enters the plane. Putting arcs around them works, but is not correctly handled by the DRC: on one board I ended up with too many arcs and no connection to GND.. Luckily the fab house made a comment on those arcs and I could save the otherwise useless boards by specifying what arc to remove. Is there a way to do this that at least generates a DRC warning? OKok I got the warning that there were primitives on the GND plane but that didn't help much: I usually have stackup and other texts/markers on every copper layer. The warning didn't specify any of them so I wrongly assumed it was moating about my texts and such. Maybe someone in the forum has figured this out, or has some otherwise useful comments. Any help is (as always) greatly appreciated. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
Julian, Please see below, JaMi - Original Message - From: Julian Higginson [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, June 04, 2003 6:00 PM Subject: Re: [PEDA] eight-layer stackup Jami, you missed a few important points. Generating a netlist and loading it into your PCB is not hard to do. It is a few more mouse clicks (maybe 20 seconds more work) than just hitting update. Your time is surely not that valuable, is it?? I am sure that this may work, but I was not thinking along those lines primarily since the last big mother of a BGA board that I did was done from an OrCAD netlist, where I don't think those options were available to me. Also see below. like I said: generate a netlist - it gives you the option to generate single pin nets if you want - ie a net for every unconnected pin. load the netlist into the PCB. I cant really envision a place that I would want to have a net for every unconnected pin in the design. This seems to be jumping thru extra hoops just to make Protel DRC happy. I only would want a net on the unconnected BGA pins that I would want to connect to a via so that that connection would be accessible from the back of the PCB. Juggling the netlist to generate all the extra nets seems to me to be an extra step that is not going to be understood by the next guy who happens to have to work on the design a couple of years from now when I may not be here. Also see below. I could also solve the problem by turning off certain rule checking, but that is not the answer. By doing that, I may miss a real error. I would rather have a dogbone trace and via flagged as an error, than have to override the ability to catch another single node net that really was an error. Now, if this is not the first iteration of the PCB (ie you haven't just placed all the parts on the board, its possible some preroutes will have nets already assigned to them) And particularly if you have just changed nets around on pins, as happens with FPGAs at layout time. you need to go to the net manager in the PCB editor and unlock the primitives of the prerouted BGA, then select all the primitives. Do a global edit on selected tracks, and selected VIAS to set them all to NO NET Then lock them all again. Then, you do that update free primitives from component pads thing. Now you won't have to make up any funny rules in your PCB, and you won't have to sit there after a DRC working out what are valid shorted nets and what aren't. It's a pain, but the only way I know to update prerouted footprints properly. Using the update PCB menu item does not allow this, and so when you're working with pre-routed BGA footprints, it is a better idea to work with netlists, even if it isn't as immediately convenient. This kind of sounds like some of the things you mention here are some of the things we all may do anyway in our approach to BGA routing. In this respect see my parallel resopnse in this thread to Dennis. On the other hand, juggling things around netlist wise, such as your selecting vias above and then setting them to NO NET and then locking them, seems like much more than I want to get into. I don't ever want to have to manually edit any net in the netlist or in the design. To me the netlist is sacred, and I never want to have to diddle around with it. That is my on real baseline in the design that I personally feel should never be touched. Getting back to Michael's original question in this thread: DRC ... is great other than the dogbones I had to route to the via on all the unused pins of the BGA. Any way to create rules for this so I do not get violations during DRC?, I simply stated that I didn't think that there was an easy way to do it short of putting them on the schematic. What I should have said, and what I really meant, was that I didn't think that there was an easy way to do it short of putting them on the schematic, without playing tricks on Protel or having to do anything non standard. I have a very strong aversion to having to do anything non standard in Protel, just to get things done and acceptable to Protel DRC. As discussed in your other post on Saturday, Protel DRC is not always right. Yes, there have been times that I have had to explain to someone that something really was not an error, simply because Protel thought it was an error (the error discussed in your other thread on Saturday regarding a trace crossing a split in an unrelated plane is a perfect example). Yes, there is a matter of personal pride in doing a design in Protel that has no DRC errors. I would rather have the DRC error, which to anyone is obviously really not an error anyway, than to have to have something in the final design that could possibly be missed or not understood by the next guy to work on the project. This is why I brought up the issue in the other post as to the acceptability of certain DRC errors. - As for my board (not
Re: [PEDA] A little OT - PCB labelling
The following link is a company that makes a laser PCB marking system. Don't know what kind of cost there is but it has a great cool factor! http://www.pcbdriller.com/pcb_marking.htm Greg - Original Message - From: Stephen Casey [EMAIL PROTECTED] To: Protel forum [EMAIL PROTECTED] Sent: Thursday, June 05, 2003 7:17 AM Subject: [PEDA] A little OT - PCB labelling Hello all, What methods of labelling would you recommend for unique identification of PCBs. We have been using thermal printed labels for serial numbers etc, but these are destroyed if a board is reworked. The boards have an area for hand writing serial numbers, but this is removed when solvent cleaning! I need a simple method of labelling individual boards, that'll withstand high temperatures and solvents! Any ideas? Thanks a lot. Steve. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
Brady and others make various poly-whatever label stock that can be laser or thermal transfer printed onto. See http://catalog.bradyserve.com/cgi-bin/ncommerce3/CategoryDisplay?cgmenbr=2cgrfnbr=21753CTcount=1 Some of these labels will even take the high temperatures of a reflow oven. See BRADY B-652 DOT MATRIX / LASER PRINTABLE HIGH TEMPERATURE POLYIMIDE LABEL at: http://www.info.bradycorp.com/TDS/tdsv1r0.nsf/b14eec34add0a9e1802565080049eca9/085b600b0a208f958625688c005f40d4?OpenDocument Get a Brady catalog and see if your thermal printer can be used as a thermal transfer printer. Otherwise go to laser printed or preprinted labels that you can then enter the number into the syste, from the label as opposed to using the system to generate the number. Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
I feel the same way about Salesmen. Regards, Steve Smith Product Engineer Staco Energy Products Co. Web Site: www.stacoenergy.com -Original Message- From: Stephen Casey [mailto:[EMAIL PROTECTED] Sent: Thursday, June 05, 2003 11:17 AM To: Protel EDA Forum Subject: Re: [PEDA] A little OT - PCB labelling As an aside, and at the risk of causing offence, is it just me or is every QA inspector a failed Engineer? Every time I get audited they always say 'Hey, I used to be an Engineer'. Well, I am an Engineer, and can't fathom why anybody who wanted to do engineering, and was good at it, would want to move into QA inspection. I'll stop now - My blood pressure is on the rise! * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] how to control GND connections
Leo, Within your schematic on those components where you want additional control of the ground routing I place a net of GND_Uxx_1 where Uxx is the device and 1 is the pin number. This gives me unique single pin nets. On the pwb you can then route them as you wish and use the virtual short technique (as has been described here). Or as I typically do, I'll route them as I wish and then short them to ground manually which then gives me DRC errors which are easy to recognize as OK as is because on the way I've named the nets (i.e. it's OK to short GND_Uxx_1 to GND). I'll then delete those errors from the report (but that's just between you and me). John Leo Potjewijd wrote: Hello again. I've been tossing and turning this problem over and over and stil haven't a workable solution. I do not want every via or component pin that is in the GND net to connect to the GND plan, only certain ones; I want to control where the current enters the plane. Putting arcs around them works, but is not correctly handled by the DRC: on one board I ended up with too many arcs and no connection to GND.. Luckily the fab house made a comment on those arcs and I could save the otherwise useless boards by specifying what arc to remove. Is there a way to do this that at least generates a DRC warning? OKok I got the warning that there were primitives on the GND plane but that didn't help much: I usually have stackup and other texts/markers on every copper layer. The warning didn't specify any of them so I wrongly assumed it was moating about my texts and such. Maybe someone in the forum has figured this out, or has some otherwise useful comments. Any help is (as always) greatly appreciated. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] how to control GND connections
Leo, I do a split-plane going around only the pins I want to connect (similar to going around picking up +15 pins and making room for the other split-plane to pick up -15). I have also used fills but don't like that as well as split-planes. Jeff Adolphs Lake Shore Cryotronics, Inc. -Original Message- From: Leo Potjewijd [mailto:[EMAIL PROTECTED] Sent: Thursday, June 05, 2003 11:48 AM To: [EMAIL PROTECTED] Subject: [PEDA] how to control GND connections Hello again. I've been tossing and turning this problem over and over and stil haven't a workable solution. I do not want every via or component pin that is in the GND net to connect to the GND plan, only certain ones; I want to control where the current enters the plane. Putting arcs around them works, but is not correctly handled by the DRC: on one board I ended up with too many arcs and no connection to GND.. Luckily the fab house made a comment on those arcs and I could save the otherwise useless boards by specifying what arc to remove. Is there a way to do this that at least generates a DRC warning? OKok I got the warning that there were primitives on the GND plane but that didn't help much: I usually have stackup and other texts/markers on every copper layer. The warning didn't specify any of them so I wrongly assumed it was moating about my texts and such. Maybe someone in the forum has figured this out, or has some otherwise useful comments. Any help is (as always) greatly appreciated. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] eight-layer stackup
One place where you'd want every pin in a net is if you do a exhaustive connectivity check of your bare board before loading components. John JaMi Smith wrote: I cant really envision a place that I would want to have a net for every unconnected pin in the design. This seems to be jumping thru extra hoops just to make Protel DRC happy. -- John M. Cardone Electro-Mechanical Dsgn. Engr. Grp. M/S 125-14R Mechanical Engineering Section, 352 4800 Oak Grove Dr.NASA / Jet Propulsion Laboratory Pasadena, Ca 91109MailTo:[EMAIL PROTECTED] Tel: 818.354.5407 Fax: 818.393.4399 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
We do have a Maxim device on the board (Superb little things - I try to put one on everything I design), but we also need some human readable labelling (don't ask me why - ISO900 (or whatever today's new quality initiative is called) nonsense!). Now if they would just put a silicon serial number AND an RS232 xcvr pair in the SAME IC, that would be great. Nearly all my designs get an RS-232 interface, even if it's just a PIC-based system. ISO9000, blecchh! No one ever produced a quality product only by following ISO9000 documented procedures. You've got to have the CORRECT procedures to begin with, and a good design. Some industrial equipment companies I know hang lots of ISO9000 paper on their lobby walls, but they would do more to improve their products if they would heed my advice about how they wire their machines. No, I'm not naming names. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Stephen Casey [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, June 05, 2003 11:17 AM Subject: Re: [PEDA] A little OT - PCB labelling * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] how to control GND connections
There is a No Connect Design rule. I use this rule a lot on through hole connectors when I want the +5V to go to the 1000uF capacitor before it connects down to the power plane. Since this is a design rule, DRC knows about it and will flag an error if you never get around to connecting that node to its net. I've only used it on pads to power planes -- don't know if it'll work for via's and I'm too lazy to check right now. Good luck, Jeff Stout - Original Message - From: Leo Potjewijd [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Thursday, June 05, 2003 10:47 AM Subject: [PEDA] how to control GND connections Hello again. I've been tossing and turning this problem over and over and stil haven't a workable solution. I do not want every via or component pin that is in the GND net to connect to the GND plan, only certain ones; I want to control where the current enters the plane. Putting arcs around them works, but is not correctly handled by the DRC: on one board I ended up with too many arcs and no connection to GND.. Luckily the fab house made a comment on those arcs and I could save the otherwise useless boards by specifying what arc to remove. Is there a way to do this that at least generates a DRC warning? OKok I got the warning that there were primitives on the GND plane but that didn't help much: I usually have stackup and other texts/markers on every copper layer. The warning didn't specify any of them so I wrongly assumed it was moating about my texts and such. Maybe someone in the forum has figured this out, or has some otherwise useful comments. Any help is (as always) greatly appreciated. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] how to control GND connections
Hi Leo I make a pad class including every pad I want not connected directly to a plane then setup a design rule to not connect them. As for via's don't use them use free pads with a unique name so you can also include them into the Pad class. The DRC will still see them as not connected if you miss routing a pin. - Original Message - From: Leo Potjewijd [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Friday, June 06, 2003 1:47 AM Subject: [PEDA] how to control GND connections Hello again. I've been tossing and turning this problem over and over and stil haven't a workable solution. I do not want every via or component pin that is in the GND net to connect to the GND plan, only certain ones; I want to control where the current enters the plane. Putting arcs around them works, but is not correctly handled by the DRC: on one board I ended up with too many arcs and no connection to GND.. Luckily the fab house made a comment on those arcs and I could save the otherwise useless boards by specifying what arc to remove. Is there a way to do this that at least generates a DRC warning? OKok I got the warning that there were primitives on the GND plane but that didn't help much: I usually have stackup and other texts/markers on every copper layer. The warning didn't specify any of them so I wrongly assumed it was moating about my texts and such. Maybe someone in the forum has figured this out, or has some otherwise useful comments. Any help is (as always) greatly appreciated. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] PCI pins...
Hi, I'm designing a PCI card and I just want to know what to do with the unused 3.3V and 5V pads. Counting that there are many of them, should I use one capacitor for each of them or it could be possible to put more than one 3.3 or 5V pad to one single capacitor (according to the PCI specs, I just assure 0.01uf for each power pad)? What would you do to save space? (I'm using a solid ground plane and power plane on the inner layers of my board) Thanks for your help Tufaredian - Do you Yahoo!? Free online calendar with sync to Outlook(TM). * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] need of pentium library for schematics
Hi Dear Guru's Iam designing a pentium III based card if anybody has schematic library please forward to me , and footprints of that please forward to me , thanx in advance from masthi Get Your Private, Free E-mail from Indiatimes at http://email.indiatimes.com Buy The Best In BOOKS at http://www.bestsellers.indiatimes.com Bid for Air Tickets @ Re.1 on Air Sahara Flights. Just log on to http://airsahara.indiatimes.com and Bid Now ! * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] stackups - Capacitance - Book Recommendation Wanted
hi , I know some of the highspeed books where he discussed a lot about stackups, capacitance and other topics in detail the black magic book high speed digital design by harward jhonson and matarial is available on the net regarding this Regards masthi Protel EDA Forum wrote: There are obviously a lot of analog things to worry about when designing a fast, dense digital board. I fought a large digital board I did through 3 iterations by simply trying different things without fully knowing what I was doing. It eventually worked but I don't know if my next design will! I would appreciate it if someone could recommend some books on high speed board design that cover topics such as stackups, capacitor resonances, trace thickness, and any other important issues. Of course, I would prefer a cookbook approach if possible since I don't want to get into the heavy math of it all if I can avoid it. Thanks, Ray Mitchell Get Your Private, Free E-mail from Indiatimes at http://email.indiatimes.com Buy The Best In BOOKS at http://www.bestsellers.indiatimes.com Bid for Air Tickets @ Re.1 on Air Sahara Flights. Just log on to http://airsahara.indiatimes.com and Bid Now ! * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
How about a debate on QA then... perhaps not. (so here I go)... I was involved with writing QA for 9000, in fact every engineer and manager had to contribute. In a nutshell, you say what you do and then you consistently do what you have said . That's about it. In many ways it makes jobs so much easier having consistent process documents. Work can be handed over to colleagues with confidence and the whole review process is much simplified. Any engineer worth their salt, no matter how eccentric, would at one time have kept very detailed notes and would have been regarded as superfluous otherwise. QA in this context is just a way of retaining, disseminating and applying this knowledge. Rob Bagotronix Tech Support To: Protel EDA Forum [EMAIL PROTECTED] [EMAIL PROTECTED]cc: tronix.com Subject: Re: [PEDA] A little OT - PCB labelling 05-Jun-2003 09:57 PM Please respond to Protel EDA Forum We do have a Maxim device on the board (Superb little things - I try to put one on everything I design), but we also need some human readable labelling (don't ask me why - ISO900 (or whatever today's new quality initiative is called) nonsense!). Now if they would just put a silicon serial number AND an RS232 xcvr pair in the SAME IC, that would be great. Nearly all my designs get an RS-232 interface, even if it's just a PIC-based system. ISO9000, blecchh! No one ever produced a quality product only by following ISO9000 documented procedures. You've got to have the CORRECT procedures to begin with, and a good design. Some industrial equipment companies I know hang lots of ISO9000 paper on their lobby walls, but they would do more to improve their products if they would heed my advice about how they wire their machines. No, I'm not naming names. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Stephen Casey [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, June 05, 2003 11:17 AM Subject: Re: [PEDA] A little OT - PCB labelling * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - PCB labelling
Thank you to everybody for such fast and comprehensive responses - It's much appreciated. I've passed all your suggestions on to the Production Manager, so it's his problem now! Thanks again. Steve. P.S. Sorry about the QA comments - I hope it doesn't get out of control ;o) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] how to control GND connections
Thank you all for the comprehensive tips on this subject. For this project I'll stick with the pad class/rule solution, when things get really tough I can always switch to the zero Ohm and virtual short solutions. Leo * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - ISO9000 was :PCB labelling
to contribute. In a nutshell, you say what you do and then you consistently do what you have said . That's about it. In many ways it makes jobs so much easier having consistent process documents. Work can be handed over to colleagues with confidence and the whole review process is much simplified. Any engineer worth their salt, no matter how eccentric, would at one time have kept very detailed notes and would have been regarded as superfluous otherwise. QA in this context is just a way of retaining, disseminating and The idea behind ISO9000 is just plain common sense (I put common in quotes because common sense really isn't very common). So why do we need a trendy business school graduate buzzword to invoke it? Because the trendy business school graduates need to justify their existence and oversized paychecks and golden parachutes somehow ;-) One of the difficulties with implementing ISO9000 is getting everyone to document their procedures adequately. This is especially difficult when it involves any of these folks: 1) Shop (blue collar) workers 2) Engineers who are borderline incompetent 3) Primadonnas In the case of (1), many shop workers have developed techniques or methods over the years to do (or to not do!) their jobs. They see any attempt to document this as a threat to their indispensibility. In other words, it's a job security issue with them. They feel that if their job is documented, they will be fired and replaced by a lower paid worker. And this feeling is not entirely born of paranoia; worker replacement happens quite often. Sometimes it's with a lower paid domestic worker, other times it's done by closing the factory and moving the work to an overseas factory. In the case of (2), lack of documentation can be used by barely competent or incompetent engineers to disguise their inadequacies. If the magic is in their head, it's not out there for anyone to critique or subject to the scientific method. The goal of this is once again, job security. In the case of (3), these folks are offended that you would even question how they do something. Because if they do it, it by definition must be correct. And to try to capture the subtleties and nuances of their knowledge and methods would be both futile and offensive! Sometimes the primadonnas really are good at their job. But occasionally, you will find a person that is both (1) and (3), or (2) and (3), that is, a blue collar primadonna, or an incompetent engineer primadonna. What fun that is! These people are incapable of learning, because they think they know it all already. In any case, it's amazing to me how some of these people can befuddle those around them into thinking they are all that. True story: at one of our customer's sites, there once was a guy in their customer service department who everyone thought was a nice guy. And most of the time he could fix the machines. But no matter how many times and in how many ways you ask him to document or explain what he did, you would never get any information out of him. It was rather maddening to me when I had to help him diagnose a problem with the control system. I would ask him questions which he never would answer in a useful manner. So all I could do was dream up all possible failure modes and tell him how to solve each one. I guess that was his way of acquiring all the repair knowledge without having to understand any of it. So who was the clever one? It wasn't me! He worked for that company until he decided to retire. And everyone thought he was really good at his job. How would you document the engineering process? Would it go something like this: 1) Brainstorm and generate ideas 2) Draw schematics and diagrams 3) Run simulations 4) Design prototypes 5) Build prototypes 6) Test prototypes 7) Refine prototypes 8) Until done goto (1) Wow, that was easy! With engineering process documentation like this, I am so replaceable! Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, June 06, 2003 4:25 AM Subject: Re: [PEDA] A little OT - PCB labelling How about a debate on QA then... perhaps not. (so here I go)... I was involved with writing QA for 9000, in fact every engineer and manager had to contribute. In a nutshell, you say what you do and then you consistently do what you have said . That's about it. In many ways it makes jobs so much easier having consistent process documents. Work can be handed over to colleagues with confidence and the whole review process is much simplified. Any engineer worth their salt, no matter how eccentric, would at one time have kept very detailed notes and would have been regarded as superfluous otherwise. QA in this context is just a way of retaining, disseminating and applying this knowledge. Rob * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To
Re: [PEDA] A little OT - PCB labelling
05/06/2003 20:38:25, Greg Olson [EMAIL PROTECTED] wrote: The following link is a company that makes a laser PCB marking system. Don't know what kind of cost there is but it has a great cool factor! http://www.pcbdriller.com/pcb_marking.htm Yeah - I run one of these - http://www.synrad.com/fenix/ On really tight boards, you can burn a human-readable number onto the routed edge of the PCB - no need to leave a label area, or you can stick your own numbers / barcodes onto the top of ICs, if that's the only space you've got. It also does excellent front panel marking for prototypes (anodised aluminium works superbly) . Movies of it are at http://www.synrad.com/Applications/video_clips.htm and there's endless opportunities for big-laser fun :) http://pub.se7ens.net/lists/cam7/unnecessary_toaster.jpg Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - ISO9000 was :PCB labelling
On Fri, 06 Jun 2003 08:08:09 -0400, you wrote: The idea behind ISO9000 is just plain common sense (I put common in quotes because common sense really isn't very common). So why do we need a trendy business school graduate buzzword to invoke it? Because the trendy business school graduates need to justify their existence and oversized paychecks and golden parachutes somehow ;-) The idea behind ISO9000 is self propagation. It spreads down the supply chain like an infectious disease. I wonder what percentage of companies would have ISO9000 were it not for ISO9000 induced pressure from thier customers? Single digit is my guess. Perhaps that is an indication of its real value. Cheers, Terry. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Fw: A little OT - ISO9000 was :PCB labelling
The problem with ISO is that it protects incompetent engineers and transform them into suppose to be intelligent managers. Those people hide behind the ISO monster that they create to keep there job. On the long term When all businesses will be ISO (I hope not) what will be the point. They will have to invent another system so that they can be ISO. May be we can start a naming contest for that futuristic new system: here is a suggestion: STUPID. System Tracking Universal Procedure Integrated Documentation Not Bad :) Yves Dubois PCB designer Raytron LTD Montreal - Original Message - From: Terry Harris [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, June 06, 2003 12:33 PM Subject: Re: [PEDA] A little OT - ISO9000 was :PCB labelling On Fri, 06 Jun 2003 08:08:09 -0400, you wrote: The idea behind ISO9000 is just plain common sense (I put common in quotes because common sense really isn't very common). So why do we need a trendy business school graduate buzzword to invoke it? Because the trendy business school graduates need to justify their existence and oversized paychecks and golden parachutes somehow ;-) The idea behind ISO9000 is self propagation. It spreads down the supply chain like an infectious disease. I wonder what percentage of companies would have ISO9000 were it not for ISO9000 induced pressure from thier customers? Single digit is my guess. Perhaps that is an indication of its real value. Cheers, Terry. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] A little OT - ISO9000 was :PCB labelling
Amen -Original Message- From: Terry Harris [mailto:[EMAIL PROTECTED] Sent: Friday, June 06, 2003 12:34 PM To: Protel EDA Forum Subject: Re: [PEDA] A little OT - ISO9000 was :PCB labelling On Fri, 06 Jun 2003 08:08:09 -0400, you wrote: The idea behind ISO9000 is just plain common sense (I put common in quotes because common sense really isn't very common). So why do we need a trendy business school graduate buzzword to invoke it? Because the trendy business school graduates need to justify their existence and oversized paychecks and golden parachutes somehow ;-) The idea behind ISO9000 is self propagation. It spreads down the supply chain like an infectious disease. I wonder what percentage of companies would have ISO9000 were it not for ISO9000 induced pressure from thier customers? Single digit is my guess. Perhaps that is an indication of its real value. Cheers, Terry. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fw: A little OT - ISO9000 was :PCB labelling
Amen -Original Message- From: Yves Dubois [mailto:[EMAIL PROTECTED] Sent: Friday, June 06, 2003 3:56 PM To: Protel EDA Forum Subject: [PEDA] Fw: A little OT - ISO9000 was :PCB labelling The problem with ISO is that it protects incompetent engineers and transform them into suppose to be intelligent managers. Those people hide behind the ISO monster that they create to keep there job. On the long term When all businesses will be ISO (I hope not) what will be the point. They will have to invent another system so that they can be ISO. May be we can start a naming contest for that futuristic new system: here is a suggestion: STUPID. System Tracking Universal Procedure Integrated Documentation Not Bad :) Yves Dubois PCB designer Raytron LTD Montreal - Original Message - From: Terry Harris [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, June 06, 2003 12:33 PM Subject: Re: [PEDA] A little OT - ISO9000 was :PCB labelling On Fri, 06 Jun 2003 08:08:09 -0400, you wrote: The idea behind ISO9000 is just plain common sense (I put common in quotes because common sense really isn't very common). So why do we need a trendy business school graduate buzzword to invoke it? Because the trendy business school graduates need to justify their existence and oversized paychecks and golden parachutes somehow ;-) The idea behind ISO9000 is self propagation. It spreads down the supply chain like an infectious disease. I wonder what percentage of companies would have ISO9000 were it not for ISO9000 induced pressure from thier customers? Single digit is my guess. Perhaps that is an indication of its real value. Cheers, Terry. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fw: A little OT - ISO9000 was :PCB labelling
i told my story before but ... i had a board once put on hold and missed a major deadline ISO shop the called and said that my outside dimension string read 5.000 inches but when they measured the drawn outline it measured 4.999 inches i was out of the office by the time the 'deviation exception' form was filled out and signed off by them a whole week was lost i pointed out that the routing tolerance was .005 inches anyway, why did you put it on hold? they said because we are ISO i told them i was sorry to hear that the same junk is going on with my sheet metal suppliers now Dennis Saputelli Yves Dubois wrote: The problem with ISO is that it protects incompetent engineers and transform them into suppose to be intelligent managers. Those people hide behind the ISO monster that they create to keep there job. On the long term When all businesses will be ISO (I hope not) what will be the point. They will have to invent another system so that they can be ISO. May be we can start a naming contest for that futuristic new system: here is a suggestion: STUPID. System Tracking Universal Procedure Integrated Documentation Not Bad :) Yves Dubois PCB designer Raytron LTD Montreal - Original Message - From: Terry Harris [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, June 06, 2003 12:33 PM Subject: Re: [PEDA] A little OT - ISO9000 was :PCB labelling On Fri, 06 Jun 2003 08:08:09 -0400, you wrote: The idea behind ISO9000 is just plain common sense (I put common in quotes because common sense really isn't very common). So why do we need a trendy business school graduate buzzword to invoke it? Because the trendy business school graduates need to justify their existence and oversized paychecks and golden parachutes somehow ;-) The idea behind ISO9000 is self propagation. It spreads down the supply chain like an infectious disease. I wonder what percentage of companies would have ISO9000 were it not for ISO9000 induced pressure from thier customers? Single digit is my guess. Perhaps that is an indication of its real value. Cheers, Terry. -- Dennis Saputelli = send only plain text please! - no HTML == ___ Integrated Controls, Inc. www.integratedcontrolsinc.com 2851 21st Streettel: 415-647-0480 San Francisco, CA 94110 fax: 415-647-3003 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] PCI power pins...
I'm using a on-board voltage regulator in order to provide power to my IC. What should I do with all the unused 3.3V and 5V pins? should I use a high freq decoupling cap of 0.01uF for each unused pin? can I tie more than one 3.3 or 5V pins and save some capacitors - save space? I'd appreciate any help on this... Regards Peter - Do you Yahoo!? Free online calendar with sync to Outlook(TM). * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
