Re: [PEDA] Getting a polygone pour out of the way for updates

2003-12-15 Thread Mike Ingle
Sorry to say, it made PCB editing sluggish, followed by a crash (99SE win2k,
RADEON 9000 dual 1600x1200, 1gb mem, 2.6ghz Athalon).

Mike Ingle
- Original Message -
From: [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
Sent: Monday, December 15, 2003 3:16 AM
Subject: Re: [PEDA] Getting a polygone pour out of the way for updates


 In a message dated 12/15/2003 4:25:40 AM Eastern Standard Time,
 [EMAIL PROTECTED] writes:


  I just tried your tip on a board I'm working on, and it crashed DXP
 and
  99SE! I experimented a bit, and it seems like if can draw one huge
 line
  somewhere in the polygon, it's ok. If it can't draw anything, an AV
 occurs
  in ADVPCB.DLL. I can close the AV and then do an orderly shutdown of
 the
  app.
 
  I'm going to try this with a couple boards to see if it's consistent.
  (20 minutes...)
 
  It's not consistent, but it does happen on several boards. (just not
 all of
  them) It does it in DXP, so I'm going to file a bug report.
 

 That's odd. I've used that trick on a number of boards with nary a crash
 that
 I could attribute to it. I've certainly seen my share of other crashes,
 of
 course, although lots less since I moved from Win95 to Win2K. And I've
 always
 used it with a width setting so wide that it can't draw any primitives
 in the
 polygon - that was the whole point. I'd be interested if you find what
 feature
 of the board makes the difference.

 Steve Hendrix





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Re: [PEDA] Getting a polygone pour out of the way for updates

2003-12-10 Thread Mike Ingle
Cool!
- Original Message - 
From: [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
Sent: Wednesday, December 10, 2003 8:04 AM
Subject: [PEDA] Getting a polygone pour out of the way for updates


 I just wanted to share a tip for a difficulty that I've seen discussed
 here 
 many times, just an alternative to the solutions presented here in the
 past.
 
 I needed to make some modifications to a previously laid-out board which
 had 
 ground pours on both sides of the board. Deleting the polygons and
 recreating 
 them later was a problem because they had irregular shapes. All I did
 was to 
 increase the width of primitives in the polygon to 2000 mils (yes, 2
 inches 
 wide). That leaves the polygon entirely intact and in place; in fact, I
 can even 
 click or dblclk where it should be and have the polygon show up in the 
 selection list or open the appropriate dialog box. However, all other
 traces (pun 
 intended!) of it are gone from the board, allowing me to push parts
 around and 
 lay tracks at will, without green lights lighting up all over. When I'm
 done, 
 I simply set the width back to the original 20 mils and allow the
 rebuild. 
 Presto! The polygon is back just like it was, only now with all the
 right 
 clearances on the new features.
 
 Hope this helps somebody.
 
 Steve Hendrix
 
 


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[PEDA] Testpoint report.ipc

2003-12-02 Thread Mike Ingle
For the first time I sent along the testpoint report.ipc.  Even after carefully 
re-generating my cam files, my boardhouse (Sierra Proto Express) claimed that my 
gerbers didn't match.

What is up?  How can I verify prior top sending my files?  Is the testpoint report 
useful?

Mike

PS what has happened to the list?

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[PEDA] pick and place report

2003-11-22 Thread Mike Ingle
Hi all,

This job will be my first where a pick and place machine is used.  I have
some confusion regarding bottom side components.

How do people generally handle the pick and place report?  Do you re-orient
the results so that X is increasing facing the bottom of the board (so that
the bottom looks like the top).  What is the transoform on rotation.  I see
that Protel buggers it, but it doesn't give the same answer as if the
component were on the top layer?

Basically what massaging should be needed besides linking to the compnent
data base to get full component info?

Mike



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Re: [PEDA] NetMeeting

2003-10-30 Thread Mike Ingle
I have not tried net meeting, but timbuktu used to crash pretty easily.
They both work as video drivers I assume, and PROTEL does seem to be pretty
hard on video drivers. Not a lot of help for your problem, other than doubts
about its feasability.

Mike
- Original Message -
From: Michael Binning [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
Sent: Thursday, October 30, 2003 8:27 AM
Subject: [PEDA] NetMeeting




 Hello all,

 Has anybody tried sharing Protel 99SE over NetMeeting?  We are trying to
do
 it my company, so that anybody logged into the meeting can see the design,
 but NetMeeting does not seem to like Protel.

 Once I have NetMeeting engaged, I can only do the most basic functions in
 Protel, like zooming, flicking between sheets.  Anything more causes a
 major crash in Protel, sometimes requiring a reboot to recover.

 Has anybody see or heard of this before?

 Mike.

 Michael Binning
 (Applications Engineer)
 Zarlink Semiconductor
 Cheney Manor Ind. Est.
 Swindon
 Wiltshire
 SN2 2QW
 Tel. 0/+44 1793-518234
 Fax. 0/+44 1793-518012
 mailto:[EMAIL PROTECTED]
 http://www.zarlink.com






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[PEDA] sierra proto express

2003-10-15 Thread Mike Ingle
We are considering using sierra proto express for some 1 day turn 6 layer
boards (5 5 design rules, controlled impedance, fineline bga)

Has anyone on the list used them, and to what success?  Is their qualty
acceptable?


Mike



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Re: [PEDA] Simulation component

2003-07-10 Thread Mike Ingle
Dave,

If you place the library siov.lib in the protel\lib\sim\ecos  (you must
create the ecos directory) then you will be able to use the siov component
wih the part name specified as S20K275 (as on sch)  or whichever component
you want.  The gotcha here is that I tried to make the simulation work, but
there are differences in PSICE, and SPICE3 or whatever PROTEL SPICE engine
is used.  At least this will get the spice simulation code into PROTEL for
you.  You will have to keep modifying siov.lib until it works.

FYI: the steps involved are:
1 create the sch symbol
2 update the readonly/library lines in the description
line 1: type  subckt(x)   **everything I have done so far is a subckt
line 2: model  modelname this is the name of the part in your library.
There must be a corresponding:  .SUBCKT modelname xxx   in your library
file.
line 3: file lists the library file name.
line 4:  maps the pins on the sch symbol to the .subckt line in the sim file
example:  opamp using pins 2,3,4,6,7  as in- in+ v- out v+ correspondingly
might be pins=1:[3,2,7,4,6]   and the sim file would have the .subckt line
in the order: in+ in- v+ v- out
line 5: takes line 4 and sends it to the sim file with the number of pins
wanted by the sim file
as far as I can tell, the %1 references the first pin in line4 ...

I always use a boilerplate from a working sym symbol.

If you are able to make the conversion work, please send me the working
version as I want to learn more about how to convert libraries.  This is the
first one I haven't been able to make work.

Best of luck,
Mike
- Original Message -
From: [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
Sent: Wednesday, July 09, 2003 11:15 PM
Subject: Simulation component


 Mike,

 Thanks for your kind offer... the attached zip file contains the PSpice
 files downloaded from the EPCOS web site.

 (See attached file: var_psp.zip)

 Cheers

 Dave


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Re: [PEDA] Simulation component

2003-07-09 Thread Mike Ingle
email me a text spice  file, and I will make you the simulation component
- Original Message -
From: [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Wednesday, July 09, 2003 12:31 AM
Subject: [PEDA] Simulation component



 Hi,

 I am trying to create a simulation component using a PSpice model for a
 Varistor. The PSpice model has been down loaded from the EPCOS website for
 their SIOV varistors. The file has a SIOV subcircuit, followed by lots of
 subcircuits for each of the devices in the range. I have no Spice manuals
 and so am struggling with just the Protel manual. The specific part I need
 to simulate is SIOV-S20K275 can anyone help?


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 CONFIDENTIALITY : This  e-mail  and  any attachments are confidential and
 may be privileged. If  you are not a named recipient, please notify the
 sender immediately and do not disclose the contents to another person, use
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Re: [PEDA] Simulation Data

2003-07-03 Thread Mike Ingle
I would like the script.  This has been an issue for me too.

Mike
- Original Message -
From: J rg Guttmann [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, July 03, 2003 2:07 AM
Subject: Re: [PEDA] Simulation Data


Hello John

as far as I know, there is no such button or option inside
protel P99 SE available.

I've done this for the transient analysis data in the following
way:

0) Run your simulation within P99 SE.
1) export the *.sdf file from your ddb (if you are using the
   ddb storage) to a folder at the windows file system.
2) Then you can open and examine the file with an editor, pfe for
   example.
3) The *.sdf File konsists of some ASCII parts with konfiguration
   informations and some binary parts containig the simulation
   data stored as float numbers.
4) I've wrote a perl skript to extrakt the simulation data from
   the sdf-file, konvert it to ascii and stored the data in an new
   file wich can be used bei gnuplot or scilab for example.

Thats the best solution I found.
If you can run perl scripts on your machine then I can send you
the script. It should be easy to change it from transient analysis
data to ac analysis.

Hope this helps.

Dipl. Ing. J rg Guttmann
eMail: [EMAIL PROTECTED]
===
Visit our Web Site:   http://www.imar-navigation.de
===
iMAR GmbH
Gesellschaft f r inertiale Mess-, Automatisierungs- und Regelsysteme
Systems for Inertial Measuring, Automation and Control
Im Reihersbruch 3
D-66386  St. Ingbert / Germany

Tel.: +49-(0)6894-9657-34
Fax : +49-(0)6894-9657-22


  - Original Message -
  From: John Waugaman
  To: Protel EDA Forum
  Sent: Tuesday, July 01, 2003 4:45 PM
  Subject: [PEDA] Simulation Data


  Is there any way to output the data used to produce the various
simulation output screens to an ASCII file for use in other programs?
Specifically, I'm interested in obtaining this data for the AC Analysis
simulation option so that I can plot simulated model data along with
data from a network analyzer to produce one of those simulated versus
measured plots.  I can't seem to find any option for outputting data
which is frustrating since the data must exist internally to be plotted
in the first place!

  John Waugaman
  [EMAIL PROTECTED]








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Re: [PEDA] 99SE on win2k running slow

2003-06-17 Thread Mike Ingle
I am not positive, but I believe you can install/reinstall a win2k service
pack (2?)  and it will replace your data access components.

Mike
- Original Message -
From: [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
Sent: Tuesday, June 17, 2003 12:39 AM
Subject: [PEDA] 99SE on win2k running slow


 Hi all,
 I have a problem with Protel 99 SE (sp6) on my win2k laptop.
 It was working fine until I installed mySQL database for another project
 after which protel is so slow to open that it appears to have hung the
 machine. I removed mySQL and rebooted, but same problem.
 I have tried re-installing Protel but it still takes forever.
 Has anyone seen this before ? I am guessing that the data access
 component of protel or perhaphs win2k has been alterted and now protel
 cannot find whatever hooks it requires.
 Bill.








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Re: [PEDA] Switch Mode Model

2003-03-13 Thread mike ingle
Can't help with the Protel model, but Linear tech has a free simulator for
most of their parts which I found very useful.


Mike
- Original Message -
From: Dennis Gibson [EMAIL PROTECTED]
To: Protel Tech [EMAIL PROTECTED]
Sent: Saturday, March 08, 2003 5:31 PM
Subject: [PEDA] Switch Mode Model


 G'day,

 Can anyone please point me to a freeware switch mode regulator Protel
simulation model?
 Something like an MC34025 would be nice.

 Thanks
 DG

 --
 

 Dennis Gibson, Electronics Unit
 Research School of Physical Sciences  Engineering
 Australian National University, Canberra, ACT 0200
 Australia

 Ph: (02) 6125 2607  [Intl: +61 2 6125 2607]
 Fx: (02) 6125 4433  [Intl: +61 2 6125 4433]

 Email: [EMAIL PROTECTED]

 (VK1DG)
 







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Re: [PEDA] Is forum traffic down?

2002-11-07 Thread Mike Ingle
#6.

Definitely not dxp here..

Mike
- Original Message -
From: Bagotronix Tech Support [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, November 07, 2002 2:10 PM
Subject: Re: [PEDA] Is forum traffic down?


 Yeah, message traffic has been slow for me too.

 Could be attributable to a lot of things, but mass migration to DXP is
 probably not one of them.

 Possiblities:
 1) List server problems (probably not)
 2) List censorship (maybe rants and off-topics from folks like me are
being
 filtered out?)
 3) Everyone's doing something else besides PCB design right now.
 4) Economy is in the toilet, some have lost their jobs or don't have
 contract work right now.
 5) Holiday mindset setting in, folks have other things on their minds
 6) Everyone's over on the off-topic list flaming each other about guns,
 sports, Windows vs. Linux, Delphi vs. [insert favorite bloatware rapid app
 development suite], mouse and KLUNK bugs ;-)

 Best regards,
 Ivan Baggett
 Bagotronix Inc.
 website:  www.bagotronix.com


 - Original Message -
 From: Linden Doyle [EMAIL PROTECTED]
 To: PEDA [EMAIL PROTECTED]
 Sent: Thursday, November 07, 2002 4:51 PM
 Subject: [PEDA] Is forum traffic down?


  Hi all,
 
  I've been getting very little traffic from the forum in the past week.
  Is it just my system or has everybody gone to the DXP forum?
 
  Messages are at the 3 or 4 a day level where previously 20 per day would
 not
  be uncommon.
 
 
  Thanks
 
  Linden Doyle
  Product Development Engineer
  Zener Electric Pty Ltd.
 
  Ph: +61 2 9795 3600
  Fax: +61 2 9795 3611
  [EMAIL PROTECTED] mailto:ldoyle;zener.net




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[PEDA] 1000V HV clearance.

2002-10-08 Thread Mike Ingle

I have a quick turn pcb with  1000V @ app 1ma max.

What trace/plane separation is required for UL/CE?

Mike

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Re: [PEDA] Protel clone on the way?!?!?!

2002-09-10 Thread Mike Ingle

I purchased Auto-Trax from Protel along with The initial windows schematic
software.  Way back when they were in Santa Clara Ca.

Mike

riginal Message -
From: Bagotronix Tech Support [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Tuesday, September 10, 2002 9:25 AM
Subject: Re: [PEDA] Protel clone on the way?!?!?!


 Wasn't AutoTrax the predecessor to Protel?

 I wonder if the original DOS code has been recycled into a Windows app?
Did
 anyone on this list use the original DOS AutoTrax software?  How does this
 compare?

 Best regards,
 Ivan Baggett
 Bagotronix Inc.
 website:  www.bagotronix.com


 - Original Message -
 From: Stephen Casey [EMAIL PROTECTED]
 To: Protel forum [EMAIL PROTECTED]
 Sent: Tuesday, September 10, 2002 7:32 AM
 Subject: [PEDA] Protel clone on the way?!?!?!


  Hello all,
 
  I haven't looked in great depth at this, so draw your own conclusions:
 
  http://www.autotraxeda.com/
 
  Interesting, no?
 
  Steve.
 
  
  * Tracking #: FDE37C3C1A14CE49AE5E6D600B3ABF48B8E75D4C
  *
  
 


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[PEDA] Matrox = bad ??? g550 ??

2002-07-24 Thread Mike Ingle

I must have missed the thread on the new Matrox Para  card.  Did look
at it briefly, after I upgraded to my current system (dual 2ghz athalon,
matrox g550 1g ddr)  Works great so far, but I have only briefly perused
old designs in Protel right now I am heavy into the embedded Linux and FPGA
code that go with this project.  Anyway is there a proble I should concern
myself with re the g550?  To date I have had the understanding that Matrox
cards and drivers were the  SAFE way to go with PROTEL.  And to date my
g200 and older Matrox Mellenium have performed well when other cards at
work haven't.

Mike


On 2002.07.24 14:17 Brian Guralnick wrote:
 Here is my take on the situation:
 
 If, every mouse  video card combination I have used to date
 auto-scrolls  manipulates any other software's windows fine
 without bugs  clunking, WHY should there be a special case for Protel
 where bugs should be acceptable when you happen to own not
 the correct combination of hardware?
 
 The only way I would NOT consider this a bug, is if, and only if,
 Protel / Altium made clear print on their hardware system
 requirements that you should never use ATI, or Matrox video cards, with
 these specific mice, or, mention that the auto-pan may
 malfunction under these circumstances.
 
 When purchasing such an expensive product  an expensive professional
 PC, I would consider this auto-pan issue fundamental,
 since when using Protel, I plan to design some PCBs.  If it were not for
 this group, Protel EDA Forum, my new development PC would
 might have had the new Matrox Parhelia only to find out that this 600$
 card would turn out to be a lemon with Protel.  I can't even
 chance getting a professional work-station grade NVIDIA card.  For all I
 know, slight differences in it's GPU code might lock up the
 auto-pan as well.  Sad to say, I'm going to use a cheap GF4MX.  The same
 card which is in my current system.  It's the only way I
 could be certain that a 2.5GHz system will not run more sluggishly than
 my current 1.0GHz system.  This is the main reason why I
 will not upgrade to ATS.  If Altium/Protel can not hire a single coder
 who has good experience debugging, or correcting odd windows
 glitches where 99% of existing other software has no issues with the same
 hardware, I can not in confidence dish out more money to
 get the next software which probably has the same,  perhaps new draw
 backs.
 
 
 Brian Guralnick
 [EMAIL PROTECTED]
 Voice (514) 624-4003
 Fax (514) 624-3631
 
 
 - Original Message -
 From: Tony Karavidas [EMAIL PROTECTED]
 To: Protel EDA Forum [EMAIL PROTECTED]
 Sent: Wednesday, July 24, 2002 4:28 PM
 Subject: Re: [PEDA] Speaking of Protel Bugs.
 
 
  I'm tired of talking to you about this. I understand it's a problem for
 you
  and it's terrible that's it causing you so much grief. But as easily as
 you
  say IT IS PROTEL'S FAULT AND IT IS THEIR RESPONSIBILITY TO FIX THE
 BUG
  why can't you seem to grasp your own words when you tell us changing
 your
  mouse fixes the problem?
 
  Don't you think this sentence could be true: IT IS MICROSOFT'S MOUSE
 DRIVER
  FAULT AND IT IS THEIR(MS) RESPONSIBILITY TO FIX THE BUG
 
  Microsoft Mouse = Bug
  Logitech Mouse != Bug
  MS Mouse on Jami's system = Bug
  MS Mouse on Tony's system != Bug
 
  You admit that PROTEL WORKS with a Logitech mouse.
  You hear from me that PROTEL WORKS with a Microsoft Mouse (on MY
 system)
 
  Why do you insist it's Protel's fault? Maybe they could be generous and
 find
  a 'workaround' for your screwed up mouse, but I certainly don't blame
 them
  for it.
 
  I'm done!
 
  Tony
 
 
 
 
   -Original Message-
   From: JaMi Smith [mailto:[EMAIL PROTECTED]]
   Sent: Wednesday, July 24, 2002 12:58 PM
   To: Protel EDA Forum
   Cc: JaMi Smith
   Subject: Re: [PEDA] Speaking of Protel Bugs.
  
  
  
   - Original Message -
   From: Tony Karavidas [EMAIL PROTECTED]
  
   snip
  
 The real issue is that statements like:
  No it's not unstable. (Not for me at least) That is exactly
 what I'm using
  for a mouse.
  I'm using whatever driver that came with Win2000.
 gloss over the problem. The operative phrase is (Not for me at
 least), and
 that is a primary indication that could in fact be a Protel
 problem, simply
 by virtue of the fact that it is so inconsistant. (In
   reality, the very
 nature of the problem itself points the finger at Protel).
   
What!? You have examples of people that use the MS wheel mouse just
 fine
with P99SE.
   
  
   That is exactly what I was responding to here - someone saying that
 they
   were using a Microsoft Wheel Mouse and the software delivered with
 Windowa
   2000 (which is Intellimouse), and he was saying that it worked just
 fine.
   Ask him.
  
Next, you state you GOT RID of your MS mouse and purchased a
 Logitech
   mouse
and all your problems went away and you STILL blame Protel?
   

Re: [PEDA] PPC to word insertion

2002-07-10 Thread mike ingle

I reccomend adobe acrobat for pcb files.
However, version 4 on w2000 sp2  does not work on sch files.  For those I
use efax.  For low cost if you subsribe to efax, you can use their prit
driver/display software to export to tiff or jpeg.

Does anyone know if acrobat 5 works with sch files?

Mike
- Original Message -
From: Yuriy Khapochkin [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Wednesday, July 10, 2002 7:37 AM
Subject: [PEDA] PPC to word insertion


 Does anybody know how to insert PPC (PCBPrint) image into Microsoft Word?
 I would appreciate any ideas better, than printing - scanning.

 Yuriy Khapochkin.

 
 * Tracking #: A90690A739593B4B829B4449AA8525A82604F7AC
 *
 


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Re: [PEDA] Anyone know of a Altera listserver? and Single/Dual CPU

2002-07-02 Thread mike ingle

Ok,

So it seems that the consensus here is that twin CPU machines are
desireable.
I am in a quandry because the goal here truly is to maximize productivity.

So, what influences my productivity?

Right now I am in a max plus II design cycle where I am waiting on compiles
for up to 10 min.  watching 99% CPU usage assigned to max2win.

It seems that the fastest possible solution to the single problem of compile
time is:

fasted possible CPU.
highest possible memory bandwidth.

Since the problem is only going to run on a single processor (current
software rev anyway) is it not true that the compile time will be minimized
in a single CPU configuration (MAX speed...)  Of note the single CPU 2.53ghz
boards w/ pc1066  rambus memory seem to be the fastest CPU/memory bandwidth
configuration available.

I have 3 other computers including my old 1ghz athalon available.  So, I can
check my e-mail... on the other machines while waiting.

I currently don't use the auto-router (high speed mixed
analog/digital/ecl...), although there may be a reason to in the future
(like if the new autorouter from PROTEL is worth beans.

I can live with the single processor limits on Max plus II. (OS slow as
molassis during compiles)
I can live with one processor using PROTEL (no autorouter), although an OS
available during sims would be nice;)

Any seasoned guesses out there on performance increase
(compiles/autorouting/sim) from  1Ghz athalon 100Mhz fsb to:

1.  Dual Athalon MP2000+ 1gb 266Mhz DDR. (around $2500)

2.  2.53 Ghz P4  533mhz fsb  1gb pc1066 rambus. ( around $2500

3.  dual xeon  2.4 400mhz fsb  1gb pc800 rambus.  (over $5k)

By the way in no way do I disagree with the 2 processor vs 1 processor for
overall usability, but the SOLE justification right now for the new machine
is a productivity increase on compiles.  We all know though that there will
of course be later requirements.

Oh, and one more time: does anyone know of an altera listserver?  I can't
get newsgroups until I wring out some stuff w/ my ISP (pacbell dsl).

Thanks again,

Mike




* Tracking #: FD5D6646A251974798B62B497F11CE74E237106C
*


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[PEDA] Anyone know of a Altera listserver? and Single/Dual CPU

2002-07-01 Thread mike ingle

Compilation timess are getting too slow on my pokey old 1Ghz Athalon ;)
I use the same computer for Protel and Max plus II.  .  As I understand it
Protel is not multi-threaded, and does not benefit much from dual cpu 

Altera apps claims they all use dual cpu units.  They also claimed that Max
plus II does benfit.  So, Anyone out here have any suggestions?

Also the old video card question for Protel.
Currently using Matrox g200.
Any reccomends?
Want a RELIABLE system.

Mike




* Tracking #: 69248771D43D294393F5A56935493745797B32A3
*


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Re: [PEDA] Protel PLD/CUPL Question

2002-06-11 Thread mike ingle

I would consider the PLD section of PROTEL a dead design tool.
I would either use the free wincupl or go to a commercial compiler from one
of the big boys.

Mike
Using altera parts and Max plus 2


- Original Message -
From: matt [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Tuesday, June 11, 2002 7:14 PM
Subject: [PEDA] Protel PLD/CUPL Question


 We have a customer who are using Protel 99se (sp6) . We are doing a
 complex RF design for this company which includes a small CPLD . They've
 selected a specific CPLD from Atmel due to lots of other parameters , and
we
 have to live with the customer's choice (not under our control -besides it
 seemed an ok choice ).
  Unfortunately , in Protel 99se , the CPLD wizard parts selection menu
 offers most of Atmel's CPLD's, _except_ for the one we want to use ( the
 1504asl ) . Moreover , Atmel has a free trial version of Protel 99se  on
 their website (only includes schematic and CPLD/CUPL) , unfortunately
 packaged together with lots of other useless nonsense (for us) . It
installs
 by default a VHDL compiler , plus some FPGA stuff and screws up the
already
 installed full version of Protel 99se .

 All attempts to identify the library and/or configuration files that allow
 the Atmel trial version of Protel99se to include the 1504asl part have
 failed . We're too late in the game to change parts, boards are already
 made, RF sections are working but we can't configure the full blown Protel
 99se to select our part and generate our CPLD file for the Atmel
atf1504asl
 . We could use other means to generate the CPLD design but our client
wants
 to maintain everything under Protel if possible . Atmel also offers a free
 version of WINCUPL as an alternative , unfortunately Logical Devices
stopped
 sellign and supporting this package and we don't want to generate a new
 design using a dead CAD tool.
   Any help would be greatly appreciated .

 Best Regards,

 Matt Tudor , MSEE
 http://www.gigahertzelectronics.com



 
 * Tracking #: 149A41898E79C74394543BAF7BA71D00CDF350CF
 *
 


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Re: [PEDA] simcode

2002-05-26 Thread mike ingle

The online help.
Also when tring to add components, I looked at how PROTEL had done it with
supported components.
Try one of the demo simulations.

Mike
- Original Message -
From: Ken Henrich [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Saturday, May 25, 2002 6:39 PM
Subject: Re: [PEDA] simcode


 Hi Mike,

 Thanks for the reply. Have you found any other description of simcode
aside
 from that which is in the Protel manual?

 Regards
 Ken



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Re: [PEDA] simcode

2002-05-25 Thread mike ingle

I use the simcode with success usually.  I previously used PSpice, but find
that hte PROTEL spice is good as far as the simulations go.  I sure miss the
probes though.  I am finding that with experience I can get the same info
from PROTEL, but that it is harder to learn.

Mike
- Original Message -
From: Ken Henrich [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Friday, May 24, 2002 5:27 AM
Subject: [PEDA] simcode


 Hi,

 Does anyone know of a better simcode description than that in the Protel
 handbook?

 Regards
 Ken


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Re: [PEDA] controlled impedance traces ?

2002-03-04 Thread Mike Ingle

In use Hyperlynx line sim  to calculate impedance from stackup, trace width,
copper thickness, plating thickness, dielectric constant.  There are good
write-ups with tables/equations in the LVDS section of the national semi
website.

Regarding Advanced circuits:   I believe I have read something to the
effedct that they do not necessarily follow your stackup (prepreg/core width
definitions)  Yuo should contact them and get a recommended stackup, and
verification that they will manufacture to that stackup.

Mike

-Original Message-
From: rimas [mailto:[EMAIL PROTECTED]]
Sent: Monday, March 04, 2002 7:07 PM
To: Protel EDA Forum
Subject: [PEDA] controlled impedance traces ?


hi there,

i suppose this question doesn't have to do with protel specifically, but i
was hoping someone could answer it for me or at least point me in the right
direction.  (i'm not a full time PCB layout person by the way)  i'm
presently laying out a board with a big xilinx fpga and a gigabit ethernet
phy chip on it.  the datasheet for the gigabit chip says that the
connections between chips need to be done with 50 ohm impedance
traces.  how do i calculate the impedance of a trace ?  it seems like trace
width and stackup order are the only two variables i have to play with.  i
am planning to have protos of this board made by advanced circuits, in case
that makes any difference.

thanks for any help,

-rimas

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Re: [PEDA] 3D views of PCB?

2002-03-03 Thread Mike Ingle

FOR 99SE SP6

bottom of the explorer box is a outline of a PC card.
grab it with your cursor and drag it to rotate.  I prefer to check the axis
constraint box.

Mike

-Original Message-
From: Leonard Gabrielson [mailto:[EMAIL PROTECTED]]
Sent: Sunday, March 03, 2002 2:02 PM
To: PROTELEDA
Subject: [PEDA] 3D views of PCB?


Hi everybody,

Does anybody remember how to rotate the 3D view of the PCB?  Maybe it
doesn't rotate anymore??
Any help appreciated.

Len


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Re: [PEDA] 3D views of PCB?

2002-03-03 Thread Mike Ingle

Works well on my Matrox G200.  Abiet slow.

Mike

-Original Message-
From: Tony Karavidas [mailto:[EMAIL PROTECTED]]
Sent: Sunday, March 03, 2002 3:04 PM
To: Protel EDA Forum
Subject: Re: [PEDA] 3D views of PCB?


Use the little window to the left of the main window. When you put the
cursor in there, it shows up as a curved quad arrow cursor, and you hold
down the left mouse button while moving in there.

The 3D viewer still sucks though. It doesn't even paint correctly on my card
with new Nvidia drivers. I wonder exactly what cards it does work on
properly? I have tried it on three machines and three different cards, and I
see graphic anomolies on every one of them.

Maybe it will be improved in Phoenix???

Tony


 -Original Message-
 From: Leonard Gabrielson [mailto:[EMAIL PROTECTED]]
 Sent: Sunday, March 03, 2002 2:02 PM
 To: PROTELEDA
 Subject: [PEDA] 3D views of PCB?


 Hi everybody,

 Does anybody remember how to rotate the 3D view of the PCB?
 Maybe it doesn't rotate anymore??
 Any help appreciated.

 Len

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Re: [PEDA] Trying to trace junk mail listing.

2002-03-01 Thread Mike Ingle

I also got it.

-Original Message-
From: Brian Guralnick [mailto:[EMAIL PROTECTED]]
Sent: Friday, March 01, 2002 2:14 PM
To: Protel EDA Forum
Subject: [PEDA] Trying to trace junk mail listing.


Has anyone else here got mail from e-teknet?  I've been especially
careful,
but, somehow, I got on their email list.


Brian Guralnick



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Re: [PEDA] Printing in 3D View mode

2002-02-25 Thread Mike Ingle

Mine prints OK.

Setup  99SE sp6  w2k
printer postscript (qms colorscript 1000 level 2,  actually a printer hooked
to a LINUX box running ghostscript)

Mike

-Original Message-
From: JaMi Smith [mailto:[EMAIL PROTECTED]]
Sent: Monday, February 25, 2002 11:41 AM
To: Protel EDA Forum
Cc: JaMi Smith; JaMi Smith
Subject: [PEDA] Printing in 3D View mode


I am trying to print a 3D View, and while I am going thru the motions,
and everything appears to be OK, I don't get any output.

I have tried via the PCB Toolbar (PCBPrint:PrintPreview), and also thru
the File Menu (FilePrint), but neither get me any output, either to a
printer or Acrobat PDF File.

Is it me, or is it Protel?

JaMi Smith


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Re: [PEDA] PCB view from bottom of board??

2002-02-22 Thread Mike Ingle

Re doing it w/ Gerbers...   I haven't watched this whole (hole ;) )  thread,
so I hope I am not being redundant.  Anyway,  You can quickly mirror the
bottom layer in CAMTASTIC.  I have never bothered to print from CAMTASTIC,
but it looks to be capable.  I will be printing the mirrored layer Monday or
Tuesday, and will follow up w/ its sucess.  Creating the mirror took about 3
strokes.

Mike

-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Friday, February 22, 2002 6:03 PM
To: Protel EDA Forum
Subject: Re: [PEDA] PCB view from bottom of board??


On 07:01 PM 22/02/2002 +1100, Geoff Harland said:
Bottom line: if Altium have visions of providing an inverting feature in
Phoenix, then this should be provided in a form which inverts the *entire*
PCB; there should not be an additional option (or alternative
implementation) of inverting *just* selected items.

It is debatable as to what *should* happen when the L key is pressed, but
attempting to implement an inversion of objects which are currently in a
selected state (and *just* those objects) does have the potential to
produce
nasty results. Does anyone else have any thoughts on this matter?

Regards,
Geoff Harland.

I usually don't want to invert the board as an end to itself - I just want
to sometimes be able to work from the bottom - so just a viewpoint thing
not a database thing would serve most of my purposes. An invert maybe
useful when laying up SM components both side on a panel and using the
alternate rows flipped technique of minimising pick and place machine
setup.  But doing this with Gerbers instead of the PCB is possible of
course.

Also, Abd ul-Rahman's comments about design re-use are valid.  Hmmm - maybe
it is time to re-visit the invert server... I think if we made the
compromise that it only dealt with visible entities (so did not try to play
games with layer pairs, design rules etc), only affected Top and Bottom
Layer entities and  associated layers, did not support undo (this was a big
cause of problems) then we could release something that makes a good fist
of typical inversion requirements - the existing beta server would be cut
back to achieve this.  Any interest in a cut down server that did not try
to fully invert the whole database but just the top and bottom layers?

And I personally would not be doing anything on this until I saw what
Phoenix had - since we have requested bottom-viewing, inversion and mech
layer associativity (all these being somewhat related) it would not
surprise me to see that there was not something there in the next version -
they are, after all, nice marketable features.

Ian Wilson

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Re: [PEDA] results of performance problems

2002-02-21 Thread Mike Ingle

Are you really running w95?  I suppose you may have noticed that w2k  is the
currently preferred base OS for PROTEL.  Although who can take a few days
off to reintall eberything and get it working.

Mike

-Original Message-
From: Bob Jones [mailto:[EMAIL PROTECTED]]
Sent: Thursday, February 21, 2002 2:11 PM
To: [EMAIL PROTECTED]
Subject: [PEDA] results of performance problems


Hi All,

This is what I've found out while trying to increase the performance of my
computer:

1). The file that was causing my processor to have 100% usage all the time
was a file called DNETC.EXE, which is located in the c:\windows\system
directory. This is from a company called Distributed Computing
Technologies, Inc. It's product name is distributed.net client. This app
apparently uses the computers idle time, but gives back the cpu when it's
needed by another program.

I have no idea where this came from and it's not on any other computer. It
appears to be some type of monitoring program that updates their web site
over the Internet whenever I log on. All of this without you ever knowing .
I don't recall ever volunteering for anything like this so I've removed it
from the startup and everything seems to run the same - cpu now fluctuates %
.
I found this out by using a program called wintop.exe. It shows you which
programs are running and what % of cpu time they are taking. If anyone is
interested in it ..go to
http://www.microsoft.com/windows95/downloads/contents/wutoys/w95kerneltoy/
there will be a Windows 95 Kernel Toys Set download.

2). While this didn't fix my performance issues ( remember 2 minutes 12
seconds to move text),  it at least rules it out. What has made a
performance increase was to follow some advise on a Compaq users site.

- First Run MSCONFIG - go to Start menu / Run  type msconfig  press ok,
then choose the
startup tab   delete whatever startup items you don't need.
Be warned, some of these programs MUST start at Startup
or Windows will fail. Before doing anything else, click
the Cleanup button to remove obsolete items. A good rule of thumb: if a
file's path begins
 with
c:\Windows\ then you should leave it alone.

then click on system.ini, (top left)
- In your system.ini, add the line ConservativeSwapfileUsage=1 under
[386enh]


- Then delete your temporary internet files, right click on start, choose
explore,
then in the list on the left hilite temporary internet files, press edit
(top left),
then select all, then top right press delete - yes.
- you can also delete the temporary internet files using the internet
options, which
ever is easier for you.


- Now Run Scandisk, then Defrag your drives,
(if your defrag won't complete it's task, then use this:
www.powerdefrag.com
-(it'll reboot into defrag using your system tools with no programs running,
so it's
much more effective).

This has made my computer feel snappy, but to move that same text was
still unacceptable. Below is a chart for what increase performance:
0805 deviceSOP
device
--
Original performance:082:12
--
after processor and :061:47
Compaq suggestions
--
with DRC on/basic rules:04   :13
--
with DRC off/ basic rules:02:10

This performance I can live with although still slower than the other
computer and it has all rules on.

Thanks all of you for your help, I haven't yet tried all my options from
you, but I need to move on.
I'm over and out!

Bob Jones
Digitized Technologies
2 Summit Road
P.O.Box 7284
06712-1541
Prospect, CT. 06712-1541
Tel: 203-758-6312
Fax: 203-758-3338
email: [EMAIL PROTECTED]
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Notice:  This message is intended solely for the person to whom it
is addressed.  Unintended recipients will be legally responsible for
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Re: [PEDA] RF footprints

2002-02-20 Thread Mike Ingle

I place a split plane with a 1 mil (or smaller) border.  Then I trace around
the border with a track on the plane of the desired width (50 mil).  I leave
an opening where I want it (say under the ADC for example).  Effectively
this shors there and still passes DRC.

 Mike

-Original Message-
From: Damon Kelly [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, February 20, 2002 5:51 PM
To: Protel EDA Forum
Subject: Re: [PEDA] RF footprints


Yes, I would really like a Tie Net entity!

Particularly (or most commonly) for the analog ground and digital ground
situation. I set different nets in the schematic, but when it comes time to
layout the PCB, the DRC spits the dummy when I tie the two grounds together
at the star point.

Does anyone have a work-around for this?
i.e. keep the two grounds (AGND and DGND) separate, EXCEPT for the nominated
tie point

Damon Kelly
Hardware Engineer


 -Original Message-
 From: Ian Wilson [mailto:[EMAIL PROTECTED]]
 Sent: Thursday, 21 February 2002 11:25
 To: Protel EDA Forum
 Subject: Re: [PEDA] RF footprints


 On 04:25 PM 20/02/2002 -0800, JaMi Smith said:

 In view of your understanding of the problem, I take it then that you
 too agree that there is a need for this issue to be
 presented to Protel.
 
 Really, not ranting,
 
 JaMi

 No, but care must be taken with language - mine was carefully
 chosen to be
 rude.  I am not sure if you wanted to create the impression of
 superciliousness but I am afraid that is the impression I
 took away from a
 reply that starts:

 Abdul,
 
 Well ~
 
 You're almost right . . .
 
 A typical RF Choke on a PCB is a certain length conductor
 (typically 1/4

 (Especially after the last recent round of email designed to
 goad the only
 list member who *really* takes that time to understand the
 subtleties of
 each persons questions and responses.)

 Anyway on to matters of substance - Yes, I would like a Tie
 entity that was
 able to safely control the shorting of nets. This entity should be
 embeddable in library components as well as be able to be
 used as a free
 entity.  It should not constrain us as to what width it has
 and ideally
 what shape it can take.  IMO, it should certainly allow for safe net
 collisions in the following forms:
 1) track to track  (tracks include arcs)
 2) track to pad
 3) track to fill
 4) fill to fill
 5) pad to pad may be difficult but may also be a nice feature.

 I would also like the Allow Short Circuits design rule to
 have region and
 object scopes.  This has been discussed before.  At the time it was
 discussed in the manner in which we have found has results
 with Protel now
 Altium.  That is constructive discussion about where the flaw
 maybe and
 then suggestions for how it can be better.

 Many of us who were part of the debacle of P99 and then the major
 improvements in P99SE have learnt that cryptic comments like Go ask
 Protel have no beneficial effect.  Much better to present the
 issue,  state what you would like and then have a calm, warts-and-all
 discussion.  Protel do watch this list and, I am sure,note
 when consensus
 is forming and also, I am sure, go away and think about methods of
 implementing some of the features that we have not been able
 to agree on
 how best to implement.

 Lecture off,
 Ian Wilson


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Re: [PEDA] Writing messages all day . . PLEASE stop!

2002-02-19 Thread Mike Ingle

JaMi,

No, I don't have to be reading this thread, but I have, and as such, I find
it offensive that someone who sounds very disgruntled, has chosen this list
to vent in.

Mr lomax has been of enourmous benefit to me as an engineer who must
occasionally do a layout using PROTEL.  Both from a PROTEL usage point of
view, and as a board designer.  I get the impression that I am not alone on
this.

You embarrass yourself.  If not for Mr Lomax, then please stop for your own
benefit.

Mike


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Re: [PEDA] recovery using backup files follow up

2002-01-28 Thread Mike Ingle

I have successfully imported all files. After removing the old files and
renaming the imported backup files back to the old file names, the hiearchy
was no longer in place.

I was able to move from the top level of the hiearchy down, causing the
lower level file to automatically open.  I could not move back up, nor was
the hiearchy displayed in the explorer.  I closed and re-opened.  No change.
Finally I ran an ERC, and this fixed the hiearchy.

Mike

-Original Message-
From: Mike Ingle [mailto:[EMAIL PROTECTED]]
Sent: Saturday, January 26, 2002 11:01 AM
To: Protel EDA Forum
Subject: [PEDA] recovery using backup files


My daughter accidentally turned off my Protel computer, and when I re-opened
my design, a couple days work were gone.  I have successfully imported the
PCB from the backup directory.  It now has a new name though.  I am hoping
to recover the sch files I had changed also, but would like to keep the file
names the same, and keep my hiearchy intact.  Any suggestions.

mike

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[PEDA] recovery using backup files

2002-01-26 Thread Mike Ingle

My daughter accidentally turned off my Protel computer, and when I re-opened
my design, a couple days work were gone.  I have successfully imported the
PCB from the backup directory.  It now has a new name though.  I am hoping
to recover the sch files I had changed also, but would like to keep the file
names the same, and keep my hiearchy intact.  Any suggestions.

mike

-Original Message-
From: Bob Wolfe [mailto:[EMAIL PROTECTED]]
Sent: Saturday, January 26, 2002 10:22 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Auto router


Dwight,
Unrelated to actual Router Setup but,
Just a question only .015 inch gap for Tip  Ring to all other nets,
that might be good for between Tip and Ring Or is it not the actual
Tip  Ring coming directly from CO but rather further down stream
that connects to some sort of  system station card then ultimately to a
phone???
Bob
Robert M. Wolfe, C.I.D.
[EMAIL PROTECTED]
- Original Message -
From: Dwight Harm [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Friday, January 25, 2002 10:14 PM
Subject: Re: [PEDA] Auto router


 I use the autorouter often, but:
 - I only use Route All
 - Boards are not too complex, e.g., 5x7, 4-layer, some fine-pitch but no
 BGA.
 - I use a layer-specific keepout, but I pre-routed all the nets within
that
 area.

 FWIW, I did a Report of my design rules, and the ones marked Rule
Followed
 By Router are listed at the end of this message. (I deleted some
Clearance
 Constraint rules for specific nets; they're all similar to the first one
 shown.)

 If you search the archives, I think there have been discussions of
 successfully doing BGA pre-fan-outs.

 -Original Message-
 From: Ted Tontis
 Sent: Friday, January 25, 2002 9:20 AM

 I can get the auto router to route the manual fan outs, and in some
 locations I can get the auto router to just route the area I have
selected.
 I can never get the auto router to route the board without it
 looking like it went through a skeet competition. This is why I figured I
 would fan out the board by hand then area route the board and do it in
 sections. I left just enough room to get the tracks in between the vias,
 trying to keep it nice neat. This is not working as well as I had hoped.
Can
 any one share one success story with the auto router and possibly share
the
 setup they used. I know that there a only a few design rules that are
 related to the auto router, maybe I am just missing one?

 Thank you,
 Ted
 -

Clearance Constraint :
 Enabled = YesName = TipRingClearance
  Scope1 = TipRingVoltage
  Scope2 = Board
  Connectivity = Different Nets
  Gap = 15mil
  Rule Followed By Router
 Enabled = YesName = ClearanceShort1X2
  Scope1 = HDR-1X2-SH-T
  Scope2 = HDR-1X2-SH-T
  Connectivity = Different Nets
  Gap = 0mil
  Rule Followed By Router
 Enabled = YesName = Clearance
  Scope1 = Board
  Scope2 = Board
  Connectivity = Different Nets
  Gap = 8mil
  Rule Followed By Router
Width Constraint :
 Enabled = YesName = EdgePullBack
  Scope = No Net
  Minimum = 8mil
  Maximum = 50mil
  Preferred = 8mil
  Rule Followed By Router
 Enabled = YesName = PowerWidth
  Scope = Power
  Minimum = 10mil
  Maximum = 15mil
  Preferred = 12mil
  Rule Followed By Router
 Enabled = YesName = GroundWidth
  Scope = Grounds
  Minimum = 10mil
  Maximum = 20mil
  Preferred = 10mil
  Rule Followed By Router
 Enabled = YesName = Width
  Scope = Board
  Minimum = 8mil
  Maximum = 20mil
  Preferred = 8mil
  Rule Followed By Router
Routing Topology :
 Enabled = YesName = RoutingTopology
  Scope = Board
  Topology = Shortest
  Rule Followed By Router
Routing Layers :
 Enabled = YesName = RoutingLayers
  Scope = Board
  Layers = Routing Layers
  Rule Followed By Router
Routing Corners :
 Enabled = YesName = RoutingCorners
  Scope = Board
  Style = 45-Degree
  Minimum = 50mil
  Maximum = 200mil
  Rule Followed By Router
Routing Via Style :
 Enabled = YesName = RoutingVias
  Scope = Board
  Min H. Size = 16mil
  Max H. Size = 20mil
  Pref. H. Size = 16mil
  Min Width = 32mil
  Max Width = 40mil
  Pref. Width = 32mil
  Style =
  Rule Followed By Router
 --end


* * * * * * * * 

Re: [PEDA] Protel 99 se SP4 on Windows XP Home

2002-01-07 Thread Mike Ingle

While in general agreement that I am not interested in moving to XP, one is
faced with the fact that almost all new PCs come with it.  Thus usres buying
partticularly name brand PCs are going to be faced with using XP, or coming
up with an old license for win 2k (my preference).

I hate that Protel  is going to have to invest engineering effort into XP
compatability rather than autorouter and other basic feature upgrades.
Basically as I see it we are all going to be paying for the fact that XP is
not compatible with previous windows versions.  Protel has no choice but to
make their product compatible with the latest version of windows.

Mike


-Original Message-
From: Sean James [mailto:[EMAIL PROTECTED]]
Sent: Monday, January 07, 2002 9:58 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Protel 99 se SP4 on Windows XP Home


Why is anybody bothering with a lousy piece of software like XP in the first
place?
Sean James
PCB Designer
Telecast Fiber Systems, Inc.
102 Grove Street
Worcester, MA 01605
(TEL) 508.754.4858 x33
(FAX) 413.541.6170

- Original Message -
From: [EMAIL PROTECTED]
To: proteledaforum [EMAIL PROTECTED]
Sent: Saturday, January 05, 2002 5:46 AM
Subject: [PEDA] Protel 99 se SP4 on Windows XP Home


I attempted to find a faq for this forum but failed. I hope this question
has not been over-asked.
I have a new PC with WinXP home, when Protel 99 se is installed. XP help and
support fails to run. System info fails to run, sfc /scannow fails to run. A
comlete format and re-install is required to get these items operational
again and they fail immediately when Protel 99 se is installed. I know that
the Protel site shows Win 2000 compatibility and not XP but does anyone know
a workaround for the problems with XP?
Or has anyone else experienced the same problems but do not know a
workaround?

Regards

[EMAIL PROTECTED]
Posted from Association web site by: Derek Ellis




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Re: [PEDA] R: First announcement of Phoenix by Altium

2001-12-05 Thread Mike Ingle

It looks to me like the logical answer here is:

We get all of the features of ATS EXCEPT free upgrade to next version.  And
on purchase of the upgrade we receive all of the features.  They want there
money for the next release.  Which while I wish it were different, I
actually think is reasonable.

Mike

-Original Message-
From: Jason Morgan [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, December 05, 2001 9:10 AM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] R: First announcement of Phoenix by Altium


Its seems Premier should inform their own staff better.


-Original Message-
From: Stephen Casey [mailto:[EMAIL PROTECTED]]
Sent: 05 December 2001 16:52
To: Protel EDA Forum
Subject: Re: [PEDA] R: First announcement of Phoenix by Altium


Jason,

Bettina at Premier definitely told me that as i paid before 1/10/01, I do
NOT get ATS, and will have to pay for the next release, but they don't know
how much.

Steve.

 -Original Message-
 From: Jason Morgan [mailto:[EMAIL PROTECTED]]
 Sent: 05 December 2001 16:30
 To: 'Protel EDA Forum'
 Subject: Re: [PEDA] R: First announcement of Phoenix by Altium


 I can confirms it's true (at least for the UK) I received the following
 flyer
 from Premier EDA

 www.cropwell.net/protel/protel99.jpg


 Looks like all of our shouting has paid off, lets just hope its all its an
 improvement
 on 99SE!!

 J.


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[PEDA] router settings

2001-11-26 Thread Mike Ingle

Unless there is some reason not to can the reply be posted so the rest of us
might benefit from the recommended router settings?  My other question here,
is why wouldn't the reply have been posted here in the first place?

Mike


-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Monday, November 26, 2001 12:27 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Antwort: Reply1 MS versus Linux



I can back that statement, Abd ul-Rahman. Last week I received a mail
directed only to me from Protel support concerning the setup of the router.
I had not turned to them directly; they had been reading my postings on
this thread.

Regards,

Gisbert Auge
N.A.T. GmbH




Abd
ul-RahmanAn: Protel EDA Forum
[EMAIL PROTECTED]
Lomax   Kopie:
marjan@noho.Thema:  Re: [PEDA] Reply1 MS versus
Linux
com

23.11.2001
21:49
Bitte
antworten an
Protel EDA
Forum






At 10:24 AM 11/23/01 -0500, Fred A Rupinski wrote:
  Has anyone seen Protel reply directly to this forum?

Yes, on 11/20/01, from Samual Sattel, regarding Protel usage

I did not find that post in my archive. I suspect that Mr. Sattel may have
written directly to Mr. Rupinski in response to a Rupinski post on this
list. That is not uncommon.

Protel, I was informed perhaps two years ago, has a policy that employees
do not post to this list except for Protelcsc, Protel Customer Service
Center, which occasionally pops in when they can easily clear up some
mystery that we have not handled for ourselves within a reasonable time.
Exceptions are quite rare. We are pretty sure that very many employees do
read this list, though perhaps fewer than was the case at one time, and
perhaps once in a while an employee gets carried away and responds
directly.

I have been asked by an employee on occasion to convey some information to
the list, a way around the restriction.

At one time Protel and the users had a fairly serious adversarial stance
toward each other; I think that the rule originated at that time. It was
far too easy for flame wars to start. There would be other reasons as well;
it can take a lot of time to write thoughtfully and it is perhaps not the
best usage of employee time. I know that Mr. Foley of Accel wrote on the
Accel user support list with a serious anti-time-wasting message directed
at the users as well as, perhaps, at employees. But we know what happened
to him, I don't think he is in the CAD business any more. I can say that
there were many Accel customers who, while they were insecure about the
future of the product when Protel took over, nevertheless were not sorry to
see Mr. Foley go.

Obviously, it is up to the users and their companies what is a waste and
what is not.

However, I *would* recommend a certain level of participation by certain
kinds of Protel employee. Imagine how we would feel if a development
engineer were actively asking us questions and reflecting on the answers.
Relations have improved to the point that serious rudeness from a few users
would be pretty strongly damped by the user community. Rules for employee
participation could be developed, such as, for example, that employees
would not respond to flames, that employees would need to be authorized by
Protel to participate here, and limits might be placed on what the
employees could reveal.

I do think, however, that the value of secrecy is vastly overblown. Some
matters properly remain secret, but secrecy clearly hampers communication
(well, duh!), and good communication between the developers and users could
greatly increase the pace of program improvement.

On the other hand, there are also other ways that communication could be
improved. A user panel is one possibility that has been mentioned; these
users would be under NDA so the secrecy issues would not be such a problem;
but they would be allowed to let the user community know that they were in
communication with Protel and could serve as a conduit for surveys, etc.


[EMAIL PROTECTED]
Abdulrahman Lomax
Easthampton, Massachusetts USA



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[PEDA] interactive routing doesn't route more than 1 route at a time before it exits interactive routing

2001-11-26 Thread Mike Ingle

Interactive routing used to allow me to continue on a new route by right
mouse clicking.
Now it exits interactive routing after each trace.

Does anyone know how to return to normal operation.

Mike

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Re: [PEDA] how to kill a spice simulation

2001-10-30 Thread Mike Ingle

there is a stop button with a white hand that is on the tooldbar of the
simulation display.
Mike
-Original Message-
From: Ken Henrich [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 30, 2001 6:22 AM
To: [EMAIL PROTECTED]
Subject: [PEDA] how to kill a spice simulation


Hi all,

Does anyone know how to kill a spice simulation that is taking too long?

tia

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Re: [PEDA] how to kill a spice simulation

2001-10-30 Thread Mike Ingle

My machine has always been able to respond...

-Original Message-
From: Coleman, Tim [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 30, 2001 7:23 AM
To: Protel EDA Forum
Subject: Re: [PEDA] how to kill a spice simulation


And when that doesn't work because the machine is just too far gone to be
able to do anything...

ctrl-alt-del



  -Original Message-
 From: Mike Ingle [EMAIL PROTECTED]  
 Sent: Tuesday, October 30, 2001 2:37 PM
 To:   Protel EDA Forum
 Subject:  Re: [PEDA] how to kill a spice simulation
 
 there is a stop button with a white hand that is on the tooldbar of the
 simulation display.
 Mike
 -Original Message-
 From: Ken Henrich [mailto:[EMAIL PROTECTED]]
 Sent: Tuesday, October 30, 2001 6:22 AM
 To: [EMAIL PROTECTED]
 Subject: [PEDA] how to kill a spice simulation
 
 
 Hi all,
 
 Does anyone know how to kill a spice simulation that is taking too long?
 
 tia

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Re: [PEDA] Windows 2000

2001-09-25 Thread Mike Ingle

I don't remember the specifics, but until I installed sp2 for win2k I had
problems.

Mike

-Original Message-
From: Ron Tupa [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, September 25, 2001 3:10 PM
To: Multiple recipients of list proteledausers
Subject: [PEDA] Windows 2000



Just loaded Service Pack 6 for Protel 99SE under Windows 2000.  When we
shut down, it hangs there for about a minute, then a message, Program
not responding , Program will be shut down and then shuts down.

Has anyone else seen this?

--
Ron Tupa
ElectroMechanical Engineer
Adtron Corporation
3710 East University
Phoenix, Arizona 85034
Telephone 602-735-0335
Fax 602-735-0359




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[PEDA] keep out around op-amp input.

2001-09-14 Thread Mike Ingle


I need to keep several mm clear around an op amp input.  On the power planes
this is easy, as I just place a fill on the plane, and that removes the
copper (I hope).

I am also placing a gnd pour on the top and bottom layers.  I have found
that a fill on the keep out layer works to keep the area clear of the
poly-plane, but causes DRC errors.  is there a more correct way to do this?

Mike ingle

Ancore

-Original Message-
From: Colby Siemer [mailto:[EMAIL PROTECTED]]
Sent: Friday, September 14, 2001 1:04 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Graphic cards and performance


Ahh... finally resubscribed after my most recent dislocation.

Hello again :)

Another possibility here is that it is not related to graphics or
performance issues related to hardware at all.

It is also possible(since selecting a via seemed to trigger it) that this is
just another instance of the slowdown caused while 'Analyzing Nets'

If that via was part of a large net, that is also likely connected to
polygons, then hiding that net will remove the pause.

Also... ATI(especially RAGE Chipset) has old long standing issues with
Protel and lock-ups.  Turning the hardware acceleration down one notch will
fix this in some cases.  As video cards are relatively in-expensive I have
always suggested buying a new card.  Last I remember the consensus for good
success and stability was placed on Matrox cards.

More and faster video memory will help with Screen redraws while moving
through a PCB...  but I don't think they help with much more than that.

I am currently using an ATI Radeon 64(after promising myelf I would never
again purchase ATI :) ) and I have had good performance with Protel(and
Excellent performance in my games)... no problems I can relate directly to
the video card... so maybe ATI has stepped things up a bit on their new
chipset.

Colby Siemer
- Original Message -
From: Andrew Ircha [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Friday, September 14, 2001 4:56 AM
Subject: [PEDA] Graphic cards and performance


 I noticed someone else mentioned they used a TNT card.

 I have NT4 on an 800MHz Athlon, with 1GB, but I often find Protel 99SE
 (SP6) pausing after simple operations (like selecting a via for
 example).

 I don't, however, think the graphics card is the latest and greatest.
 What do others think about how the graphics card they have affecting the
 performance of Protel 99SE?

 I have a Rage128 Pro (AGP 4x)

 Regards,
 --
 Andrew Ircha




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[PEDA] virtual short on power plane

2001-09-13 Thread Mike Ingle

I am trying to control curent paths in a mixed signal design.  I have
separate gounds, an over-all ground plane with isolated islands which
should only connect under an ADC.  I created a separate island with its own
net assignment and on the pcb implemented it by using a 0.1mil border all
the way around the island.

  This should effectively be a short?  HELP HERE.

I then traced the 0.1mil border with a 20mil line all the way around the
island, except where I wanted it to join.

Should this work?  The gerbers are created correctly.  What will happen at
the board house?  Is there something else I should do?

Thanks,

Mike Ingle
Ancore
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Thursday, September 13, 2001 4:11 PM
To: Protel EDA Forum
Cc: [EMAIL PROTECTED]
Subject: Re: [PEDA] (small unrelated bug found) (ex: Mechanikal Layers
are disappearing)


On 03:37 PM 13/09/2001 -0700, Brad Velander said:
Thanks guys,
 for confirming it is not a singular isolated problem (based on
response only). It is an annoying little problem which limits the
effectiveness of using Mech layers 5 - 16. I had thought it was a code
problem because it was consistent across a number of machines, video cards
and had always been present since we switched to P99SE with only the new
mech layers being effected.

Anybody out there have any ideas to fix or root out the cause of this
problem?

Has anybody brought this up with Protel Tech support, what was their
response?


I do not see the problem.  I have just been investigating and found a
different small bug that may affect database stability (but not badly I
suspect).

First, my config Win2k, nVidia TNT2 graphics.

I tried quite a few combinations of single layer mode (both locally for the
layers and globally and other options and preferences as I thought may
affect it.  I could not see the problem.

What we do not know is if it is a database issue, a configuration issue or
a machine issue.  If someone wants to email a file that shows the problem
*and* their RCS and *99SE.INI files (all zipped of course) I am prepared to
have a quick go and see what gives.

On to the (minor) bug - In doing the testing I enabled layers Mech 7 to 10,
I then placed a bunch of tracks on Mech 9 and 10.  I then double clicked
one of the Mech 9 tracks and changed its layer to Mech 7 (there were no
other entities on Mech 7).  In Design|Mechanical Layers... found that I was
still able to Mech 7 off, even though it had a track on it.  The database
had not correctly determined that there was an entity on the layer and so
allowed me to disable Mech 7.  Interestingly though, the track was still
visible and its colour remained correct for Mech 7. Double clicking this
track showed that the system though it was on Top Layer (possibly just
picking the lowest indexed enabled layer to display in the Edit Track layer
edit box).  Re-enabling Mech Layer 7 seemed to get everything sorted out
OK.  I did not try saving and re-opening the PCB file or the DDB.  Tech
support can do this (they have been CC'ed on this mail).  The fix is
presumably to improve the ability to check for entities on a layer before
allowing that layer to be disabled.

Ian Wilson

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Re: [PEDA] Spam trawlers in this group

2001-08-27 Thread Mike Ingle

I am getting it.  I am not subscribed to PCD mag.
I am also on embedded linux and LART groups.

-Original Message-
From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]]
Sent: Monday, August 27, 2001 4:43 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Spam trawlers in this group


On 04:27 PM 8/27/2001 -0700, Brad Velander wrote:
Michael,
 Possibly the EDA Tool Cafe is getting it from PCD Mag or some of
the
other Miller Freeman group publications, I just recently renewed a couple
of
subscriptions and supplied my email address for further subscription
renewals. That's got to be it, blame Pete Waddel, flame his butt at the
next
PCB Design Conference! 8^
 Possibly someone could make the enquiry of PCD? Check what they
state the email address shall or shall not be used for, etc.. I will try to
take a look at their subscription page tonight, anybody got a contact
within
the magazine itself?

Nah, doesn't compute.  I got the same thing, and I dropped my subscription
to PCD nearly a year ago. My guess is still that it comes from here, whether
by some ibsystem employee subcribing and violating the group policy or as
Mike Beavis suggested, through the archives.

The interesting thing, though, is that their site doesn't include Protel as
an EDA vendor...

In any case, I'm generating a list of possible reply addresses for a potent
deinculsion request addresses at ibsystems by PEDA members. More to come...

FWIW, ibsystems has been at this spam game for quite some time. See google
and enter ibsystems for more info

aj

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Re: [PEDA] IGNORE COMP LIB ACCESS POST

2001-08-14 Thread Mike Ingle

Just a note on this,  I kept getting burned by version ocntrol,  as you
change filenames to save back old versions, the library files stay with the
old filename until you update the pointer.  I have finally decided to have a
design file which is only for libraries, and not include library files in
designs.  Any better ideas out there for library management?

Mike

-Original Message-
From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, August 14, 2001 1:07 PM
To: 'Protel EDA Forum'
Subject: [PEDA] IGNORE COMP LIB ACCESS POST


i figured it out...  i needed to add the entire project ddb, not the
specific component library.  when i added the entire project ddb,
the new tmod.lib showed up in the access list.  it wasn't exactly
intuitive, but there's not a lot of that in protel anyway.

miker

 -Original Message-
 From: Robison Michael R CNIN
 Sent: Tuesday, August 14, 2001 2:54 PM
 To:   'Protel EDA Forum'
 Subject:  [PEDA] can't add component library access ??

 hello,

 its been a while since i built a component library and it was kinda
 tricky the first time so i just kept adding to the same lib and using
 it for all my jobs.  now i've come to where i need to create a new
 library and i'm having some trouble.  i created the library with no
 problem:  file/new/ and selected the schematic library icon.  but
 when i go back to my schematic, select the browse sch tab and hit
 add/remove and browse down in the change library file list dialog
 box to the ddb that my new lib was created in, and change the file
 type to lib, i only get a listing for the BACKUP of tmod.lib.

 thats not right, is it?  on a hunch, i closed the tmod.lib that i created
 and tried again, thinking that maybe it couldn't access an open file,
 but that didn't change anything.

 why is it that the change library dialog only wants to offer me a
 backup of the tmod.lib and not the lib itself?  what am i doing wrong?

 thanks, miker


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Re: [PEDA] Signal Integrity dialog locks up.

2001-08-07 Thread Mike Ingle

Hyperlynx  sells a signal integrity/emi tool that is supposed to be great.
I Use it before layout only, to set trace widths and look at signals vs
diferent termination schemes.

I have yet to successfully use the signal integrity tools in Protel.  They
don't seem, to be its shining star.  The basic layout, and auto-router are
OK, but certainly not up to Specctra standards.

In summary,  I think that the schamtic entry and board layout functionality
of Protel is as good as anything I have seen, and by reading the
correspondence on this list would say that the more expensive packages are
not better in this respect.   On the other hand, the addition of Specctra is
wise for auto-routing.  Do any other basic layout packages do a better
auto-routing job?

Just as a place to say this, I wish that there was a way that good FPGA
tools were integrated w/ the schematic capture, package (w/ good footprints
avail for layout).  I spend most of my time enterering 200+ pin symbols into
the schematic library, just to have to change them manually when I rev the
part.

mike


-Original Message-
From: Darryl Newberry [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, August 07, 2001 12:49 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] Signal Integrity dialog locks up.


OK, thanks everybody for your input on this issue. The list is a really
great resource.

The reality is I have about 6 board designs that have to go out for fast
turn proto this week and hopefully go into a commercial UL/FCC/CE/USB ready
product by September. I don't know what all YOU people do all day long, but
my boss doesn't want me to sit on my fat hairy ass for hours waiting for
$8000 bloatware to complete basic signal analysis. (No offense to those
whose bosses do--and please tell me where to send my resume! ;-) )

In summary, after using Protel for about 4 weeks to TRY to get a lot of real
work done, I have formed the opinion that it just basically sucks--lots of
cutesy trees, tabs, windows, icons and menus, lots of feature-itis, but not
much real engineering guts or ease of use. THE EMPEROR HAS NO CLOTHES!!! And
yes I CAN talk because I've spent the last 10 years designing various
commercial products with P-Cad, PADS, Accel/Tango EDA, and now Protel. About
the only positive thing I can say about Protel right now is that I am glad
that I wasn't the engineer who recommended purchasing two seats.
Unfortunately I am more or less forced to use it. OK, it _is_ better than
Xacto knife, Bishop Graphics, and a light table. ;-)

My apologies to those who have an irrational emotional attachment to Protel.
When I commit , I want results. I know it's not an apples-apples
comparison, but Specctra V10 routed the entire board 100%, in 5 passes over
2 layers, with more or less fab-ready results, in about 20 seconds, using
the default configuration. This gave me a warm fuzzy feeling, even when
considering we blew almost $11K on it with all the bells and whistles.

Now for another couple of questions:
1) Can anybody recommend a professional level SI/EMI simulator add-in/on
that integrates with either Protel or Specctra--one that actually works?

2) Since I have to keep on using Protel, should I get a dual CPU
workstation? What specs for W2K?

Darryl Newberry
Hardware Engineer
Freedom Scientific, Inc
2850 SE Market Pl
Stuart FL 34997
(561) 223-6443
http://www.freedomscientific.com


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Re: [PEDA] need a work around for the 100 sq in restriction

2001-05-07 Thread Mike Ingle

Just a thought, but could you scale all the footprints 1:2 and use 1/2 size
traces.  Then ask your board shop to plot 2:1?

-Original Message-
From: Mark E Witherite [mailto:[EMAIL PROTECTED]]
Sent: Monday, April 02, 2001 11:29 AM
To: Protel EDA Forum
Subject: [PEDA] need a work around for the 100 sq in restriction


Hi Everyone
I've been assigned to design a simple flex circuit. The problem is it
will
be 110 X 3.75 inches long. Is there a way to work around the
100 X 100 inch maximum work area? Any suggestions would be greatly
appreciated.
Cheers







Mark Witherite
Sr Research Technologist
Astronomy  Astrophysics
Penn State University
2565 Park Center Blvd
Suite 200
State College, PA.  16801
email [EMAIL PROTECTED]
telephone 814 865 9839
fax   814 865 9100
IPC PWB  Certified



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Re: [PEDA] [PROTEL EDA USERS]: test: my posts make it to the forum,right?

2001-05-07 Thread Mike Ingle

I received this.

-Original Message-
From: TSListServer [mailto:[EMAIL PROTECTED]]On
Behalf Of Drew Lundsten
Sent: Thursday, February 15, 2001 12:09 AM
To: Multiple recipients of list proteledausers
Subject: [PROTEL EDA USERS]: test: my posts make it to the forum, right?


For some reason I get all posts except my own, and I receive replies to
my posts so somebody out there gets them. Why don't I?

Drew



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[PEDA] sp6 installed?

2001-05-07 Thread Mike Ingle

I installed sp6 a while back, and could never get it to say includes sp6.
The program loads w thhe message includes sp5.
help says ver 6.5.2


Mike
-Original Message-
From: Brad Velander [mailto:[EMAIL PROTECTED]]
Sent: Monday, March 26, 2001 8:46 AM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] Searching Network for Floating License


Tony  Steve,
I believe that this was answered a while ago by Colby (ex-Protel
Tech support). His comment was that Protel had removed the ability to remove
the floating licenses check sometime recently in one of the service packs (5
or 6?). If my memory has failed me then someone will step in and correct it.

Sincerely,

Brad Velander
Lead PCB Design
Norsat International Inc.
#100 - 4401 Still Creek Dr.,
Burnaby, B.C., Canada.
V5C6G9.
voice: (604) 292-9089 (direct line)
fax:(604) 292-9010
email: [EMAIL PROTECTED]
www: www.norsat.com


 -Original Message-
 From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
 Sent: Saturday, March 24, 2001 4:03 AM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Searching Network for Floating License


 In a message dated 3/24/01 1:59:46 AM Eastern Standard Time,
 [EMAIL PROTECTED] writes:


  I just launched a project that I had created a few weeks
 ago and two dialog
  boxes popped up in succession stating the message above.
 I've never seen
  this message before.  Does anyone know why this would start
 happening?  I
  have service pack six installed.
 
 

 I have been seeing this as well, but didn't associate it with
 SP6 until you
 mentioned it. I can no longer find the box to turn off the
 fleating licenses,
 which I don't need, as a one-man shop. But I do have several
 PCs networked,
 even though I use Protel on only one of them. Anybody know
 where they hid the
 checkbox to turn off the search for floating licenses?

 Steve Hendrix

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Re: [PEDA] Memory Error

2001-05-07 Thread Mike Ingle

Myabe I'm not doing the same things, but I work w/ very large files, and
have never had Protel crash since getting rid of my ATI video card, and
replacing it w/ a Matrox.  I run P99se sp6 (now)  on a kt-7 raid 1ghz
athalon mainboard w/ 384M memory and a matrox g200 agp video card.  I use
the simulator, sch, pcb.  I also had no problems w/ nt4 sp6 (i think) and
p99se sp5 on a 250mhz pii asus mb w/ 128m.

Mike

-Original Message-
From: Tony Karavidas [mailto:[EMAIL PROTECTED]]
Sent: Monday, March 26, 2001 5:35 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Memory Error




 -Original Message-
 From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]]
 Sent: Monday, March 26, 2001 12:42 PM
 To: Protel EDA Forum
 Subject: Re: [PEDA] Memory Error


 On 01:20 PM 3/26/01 -0600, Ted Tontis said:
  I am running Protel 99SE SPK6 on W2K. After closing
 Protel down and
 open another application that takes up a large amount of memory, I get a
 memory error.  This is the first time I opened the task manager
 to see what
 was eating all the memory. I found Protel was still sucking memory even
 though it was closed.

 It was not, in fact closed, but had crashed. This actually happens quite
 often with Protel, at least under W95, NT4, and Win2k. I run into to it
 frequently, and I suspect that many others do, though I also suspect that
 they have no idea that it's happening most of the time.
 The program is choking on exit. IMO, it's just more of Delphi's
 questionable memory management (spelled: heap fragmentation
 errors galore)
 scheme at work, showing off it's prowess at causing problems. I know of
 only one other applications in my experience which shows the same
 proclivity towards these errors, and it is also written in...you guessed
 it...Delphi. Programmers like it! is not the same thing as stable or
 dependable or enjoyed by the end-user. Hmm.. that one ought'a
 generate
 a few snarling flames...g


Yeah, just like Microsoft Outlook 2000. I think I'm closing it, but there is
crap still running and when I open it again, it doesn't work unless I go
into Win2000 task manager and kill previous instantiations.

Tony

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