Re: [gem5-dev] Review Request: SLICC: Add a check function for State Machine

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/723/#review1320
---



src/mem/slicc/symbols/StateMachine.py


This print doesn't belong here.  It just makes the output verbose even if 
we don't want it to be.


- Nathan


On 2011-06-01 19:12:30, Nilay Vaish wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/723/
> ---
> 
> (Updated 2011-06-01 19:12:30)
> 
> 
> Review request for Default.
> 
> 
> Summary
> ---
> 
> SLICC: Add a check function for State Machine
> This patch adds a function for State Machines that will check
> whether the provided description in the .sm files includes some
> of the required functions, like getState() and setState().
> 
> 
> Diffs
> -
> 
>   src/mem/slicc/ast/MachineAST.py 681497e0356b 
>   src/mem/slicc/symbols/StateMachine.py 681497e0356b 
> 
> Diff: http://reviews.m5sim.org/r/723/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Nilay
> 
>

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Single Header File for Debug Flags

[nathan binkert]

> Well, I guess the recompilation tradeoff is worth the temporary annoyance of
> adding the specific debug flag header file everywhere.
>
> I'm also hoping that the new changes will allow us to eventually make
> compound flags of compound flags.
The changes are already in the tree (and have been for a while).  I
think compound flags of compound flags should work.

  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Single Header File for Debug Flags

[nathan binkert]

Oh, and I forgot.  Compound flags generate a header file as well.
debug/O3CPUAll.hh for example would have all of the flags that
O3CPUAll covers

On Wed, Jun 8, 2011 at 9:40 PM, nathan binkert  wrote:
>> What do people (mostly Nate) think about having a single header file for all
>> debug flags?
>>
>> Instead of "#include "debug/MyFlag.hh" for every flag you want in a DPRINTF,
>> you could say "#include "debug/debugflags.hh" and that would cover all the
>> debug flags available for DPRINTF.
>>
>> Would that (the old way?) not be more desirable then the new way of
>> including debug flags? Are there infrastructure things that make this
>> complicated?
>
> The whole reason I changed the flags around was to avoid the
> centralized file :)  The main problem with the centralized file is
> that if you add or remove a flag, you have to recompile just about
> everything.  There is no reason that you couldn't do localized
> includes for a set of flags though.  For example, you could add a file
> to the src/cpu/inorder directory called debugflags and include the few
> debug flags that you want and that way only the inorder CPU would be
> rebuilt if you added a flag to it.  Adding the centralized file back
> wouldn't be quite as bad as it was before since it would only be a
> centralized .hh file and not a centralized .cc file (which makes doing
> things like adding a flag for a unit test a real problem.)  I'm pretty
> sure it's not worth it though and the localized files that include a
> bunch of flags for each CPU model are probably as much as anyone
> really needs.
>
>  Nate
>
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Single Header File for Debug Flags

[nathan binkert]

> What do people (mostly Nate) think about having a single header file for all
> debug flags?
>
> Instead of "#include "debug/MyFlag.hh" for every flag you want in a DPRINTF,
> you could say "#include "debug/debugflags.hh" and that would cover all the
> debug flags available for DPRINTF.
>
> Would that (the old way?) not be more desirable then the new way of
> including debug flags? Are there infrastructure things that make this
> complicated?

The whole reason I changed the flags around was to avoid the
centralized file :)  The main problem with the centralized file is
that if you add or remove a flag, you have to recompile just about
everything.  There is no reason that you couldn't do localized
includes for a set of flags though.  For example, you could add a file
to the src/cpu/inorder directory called debugflags and include the few
debug flags that you want and that way only the inorder CPU would be
rebuilt if you added a flag to it.  Adding the centralized file back
wouldn't be quite as bad as it was before since it would only be a
centralized .hh file and not a centralized .cc file (which makes doing
things like adding a flag for a unit test a real problem.)  I'm pretty
sure it's not worth it though and the localized files that include a
bunch of flags for each CPU model are probably as much as anyone
really needs.

  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] changeset in m5: scons: rename TraceFlags to DebugFlags

[nathan binkert]

> Why not just let TraceFlags be interpreted as DebugFlags, so TraceFlags still 
> works for users.

For better or worse, I renamed trace flags to debug flags and I should
have changed the name of TraceFlags to DebugFlags when I did that, so
this was just correcting that and removing an inconsistency.

You can just do TraceFlags = DebugFlags in your sconscript to make it
continue to work.  I don't think many people have added TraceFlags and
even if they did, it's not much effort to fix.

  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] [m5-dev] Review Request: stats: move code that loops over all stats into python

[nathan binkert]

> I'm trying to call a global function implemented in C++ from a function in 
> the Python __init__.py file, how can I do that? Is that a good example that I 
> can follow?

Just add your function foo() to src/python/swig/core.i and then you
can access it from m5.internal.core.foo()

Most of the functions in core.i are examples for you.
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] [m5-dev] Review Request: stats: move code that loops over all stats into python

[nathan binkert]

> Where in the code is the signal from "kill -USR1" handled to dump stats?

% grep -nR USR1 src
src/sim/init.cc:97:signal(SIGUSR1, dumpStatsHandler);
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] changeset in m5: scons: rename TraceFlags to DebugFlags

[Nathan Binkert]

changeset 9228e00459d4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9228e00459d4
description:
scons: rename TraceFlags to DebugFlags

diffstat:

 src/SConscript  |   2 -
 src/arch/SConscript |   6 +-
 src/arch/arm/SConscript |   8 ++--
 src/arch/mips/SConscript|   2 +-
 src/arch/power/SConscript   |   2 +-
 src/arch/sparc/SConscript   |   4 +-
 src/arch/x86/SConscript |  10 +++---
 src/base/SConscript |  24 +++---
 src/base/vnc/SConscript |   2 +-
 src/cpu/SConscript  |  54 
 src/cpu/inorder/SConscript  |  44 +-
 src/cpu/o3/SConscript   |  24 +++---
 src/cpu/ozone/SConscript|  10 +++---
 src/cpu/pred/SConscript |   2 +-
 src/cpu/simple/SConscript   |   2 +-
 src/cpu/testers/directedtest/SConscript |   2 +-
 src/cpu/testers/memtest/SConscript  |   2 +-
 src/cpu/testers/networktest/SConscript  |   2 +-
 src/cpu/testers/rubytest/SConscript |   2 +-
 src/dev/SConscript  |  50 +++---
 src/dev/alpha/SConscript|   4 +-
 src/dev/arm/SConscript  |   8 ++--
 src/dev/mips/SConscript |   2 +-
 src/dev/sparc/SConscript|   2 +-
 src/dev/x86/SConscript  |  16 
 src/kern/SConscript |   6 +-
 src/mem/SConscript  |  34 ++--
 src/mem/cache/SConscript|   8 ++--
 src/mem/cache/tags/SConscript   |   4 +-
 src/sim/SConscript  |  34 ++--
 30 files changed, 185 insertions(+), 187 deletions(-)

diffs (truncated from 687 to 300 lines):

diff -r 483e936f44f0 -r 9228e00459d4 src/SConscript
--- a/src/SConscriptThu Jun 02 17:36:18 2011 -0700
+++ b/src/SConscriptThu Jun 02 17:36:21 2011 -0700
@@ -270,7 +270,6 @@
 if name in debug_flags:
 raise AttributeError, "Flag %s already specified" % name
 debug_flags[name] = (name, (), desc)
-TraceFlag = DebugFlag
 
 def CompoundFlag(name, flags, desc=None):
 if name in debug_flags:
@@ -280,7 +279,6 @@
 debug_flags[name] = (name, compound, desc)
 
 Export('DebugFlag')
-Export('TraceFlag')
 Export('CompoundFlag')
 
 
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/SConscript
--- a/src/arch/SConscript   Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/SConscript   Thu Jun 02 17:36:21 2011 -0700
@@ -126,7 +126,7 @@
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
 
-TraceFlag('IntRegs')
-TraceFlag('FloatRegs')
-TraceFlag('MiscRegs')
+DebugFlag('IntRegs')
+DebugFlag('FloatRegs')
+DebugFlag('MiscRegs')
 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/arm/SConscript
--- a/src/arch/arm/SConscript   Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/arm/SConscript   Thu Jun 02 17:36:21 2011 -0700
@@ -65,10 +65,10 @@
 SimObject('ArmNativeTrace.py')
 SimObject('ArmTLB.py')
 
-TraceFlag('Arm')
-TraceFlag('TLBVerbose')
-TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
-TraceFlag('Predecoder', "Instructions returned by the predecoder")
+DebugFlag('Arm')
+DebugFlag('TLBVerbose')
+DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
+DebugFlag('Predecoder', "Instructions returned by the predecoder")
 if env['FULL_SYSTEM']:
 Source('interrupts.cc')
 Source('stacktrace.cc')
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/mips/SConscript
--- a/src/arch/mips/SConscript  Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/mips/SConscript  Thu Jun 02 17:36:21 2011 -0700
@@ -41,7 +41,7 @@
 Source('dsp.cc')
 
 SimObject('MipsTLB.py')
-TraceFlag('MipsPRA')
+DebugFlag('MipsPRA')
 
 if env['FULL_SYSTEM']:
 SimObject('MipsSystem.py')
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/power/SConscript
--- a/src/arch/power/SConscript Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/power/SConscript Thu Jun 02 17:36:21 2011 -0700
@@ -45,7 +45,7 @@
 Source('utility.cc')
 
 SimObject('PowerTLB.py')
-TraceFlag('Power')
+DebugFlag('Power')
 
 if not env['FULL_SYSTEM']:
 Source('process.cc')
diff -r 483e936f44f0 -r 9228e00459d4 src/arch/sparc/SConscript
--- a/src/arch/sparc/SConscript Thu Jun 02 17:36:18 2011 -0700
+++ b/src/arch/sparc/SConscript Thu Jun 02 17:36:21 2011 -0700
@@ -44,8 +44,8 @@
 SimObject('SparcNativeTrace.py')
 
 SimObject('SparcTLB.py')
-TraceFlag('Sparc', "Generic SPARC ISA stuff")
-TraceFlag('RegisterWindows', "Register window manipulation")
+DebugFlag('Sparc', "Generic SPARC ISA stuff")
+DebugFlag('Register

[gem5-dev] changeset in m5: scons: rename some things from m5 to gem5

[Nathan Binkert]

changeset 483e936f44f0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=483e936f44f0
description:
scons: rename some things from m5 to gem5

The default generated binary is now gem5. instead of m5..
The latter does still work but gem5. will be generated first and
then m5. will be hard linked to it.

diffstat:

 src/SConscript |  18 +++---
 1 files changed, 11 insertions(+), 7 deletions(-)

diffs (56 lines):

diff -r c1a07ecb6619 -r 483e936f44f0 src/SConscript
--- a/src/SConscriptThu Jun 02 17:36:07 2011 -0700
+++ b/src/SConscriptThu Jun 02 17:36:18 2011 -0700
@@ -41,7 +41,7 @@
 
 import SCons
 
-# This file defines how to build a particular configuration of M5
+# This file defines how to build a particular configuration of gem5
 # based on variable settings in the 'env' build environment.
 
 Import('*')
@@ -61,8 +61,8 @@
 # get specifies a set of filters, only files that match those filters
 # will be accepted (unspecified filters on files are assumed to be
 # false).  Current filters are:
-# main -- specifies the m5 main() function
-# skip_lib -- do not put this file into the m5 library
+# main -- specifies the gem5 main() function
+# skip_lib -- do not put this file into the gem5 library
 #  -- unit tests use filters based on the unit test name
 #
 # A parent can now be specified for a source file and default filter
@@ -298,7 +298,7 @@
 env.Append(CPPPATH=Dir(extra_dir))
 
 # Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308 
+# Scons bug id: 2006 gem5 Bug id: 308
 for root, dirs, files in os.walk(base_dir, topdown=True):
 Dir(root[len(base_dir) + 1:])
 
@@ -866,8 +866,9 @@
 def makeEnv(label, objsfx, strip = False, **kwargs):
 # SCons doesn't know to append a library suffix when there is a '.' in the
 # name.  Use '_' instead.
-libname = 'm5_' + label
-exename = 'm5.' + label
+libname = 'gem5_' + label
+exename = 'gem5.' + label
+secondary_exename = 'm5.' + label
 
 new_env = env.Clone(OBJSUFFIX=objsfx, SHOBJSUFFIX=objsfx + 's')
 new_env.Label = label
@@ -943,7 +944,10 @@
 cmd = 'strip $SOURCE -o $TARGET'
 targets = new_env.Command(exename, progname,
 MakeAction(cmd, Transform("STRIP")))
-
+
+new_env.Command(secondary_exename, exename,
+MakeAction('ln $SOURCE $TARGET', Transform("HARDLINK")))
+
 new_env.M5Binary = targets[0]
 envList.append(new_env)
 
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] changeset in m5: copyright: Add code for finding all copyright b...

[Nathan Binkert]

usetts Institute of Technology
+Copyright (c) 1990-1993 The Regents of the University of California
+Copyright (c) 2006-2009 Nathan Binkert
+Copyright (c) 2001 The NetBSD Foundation, Inc.
+Copyright (c) 2010-2011 Gabe Black
+Copyright (c) 1994 Adam Glass
+Copyright (c) 1990-1992 MIPS Computer Systems, Inc.
+Copyright (c) 2004 Richard J. Wagner
+Copyright (c) 2000 Computer Engineering and Communication Networks Lab
+Copyright (c) 2001 Eric Jackson
+Copyright (c) 1990 Hewlett-Packard Development Company
+Copyright (c) 1994-1996 Carnegie-Mellon University.
+Copyright (c) 1993-1994 Christopher G. Demetriou
+Copyright (c) 1997-2002 Makoto Matsumoto and Takuji Nishimura
+Copyright (c) 1998,2001 Manuel Bouyer.
diff -r 23711432221f -r c1a07ecb6619 LICENSE
--- a/LICENSE   Thu Jun 02 14:36:35 2011 -0700
+++ b/LICENSE   Thu Jun 02 17:36:07 2011 -0700
@@ -1,4 +1,4 @@
-Copyright (c) 2000-2011 The Regents of The University of Michigan
+Copyright (c)  
 All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
diff -r 23711432221f -r c1a07ecb6619 src/SConscript
--- a/src/SConscriptThu Jun 02 14:36:35 2011 -0700
+++ b/src/SConscriptThu Jun 02 17:36:07 2011 -0700
@@ -516,7 +516,7 @@
 
 # Generate a file that wraps the basic top level files
 env.Command('python/m5/info.py',
-[ '#/AUTHORS', '#/LICENSE', '#/README', ],
+[ '#/COPYING', '#/LICENSE', '#/README', ],
 MakeAction(makeInfoPyFile, Transform("INFO")))
 PySource('m5', 'python/m5/info.py')
 
diff -r 23711432221f -r c1a07ecb6619 src/python/m5/main.py
--- a/src/python/m5/main.py Thu Jun 02 14:36:35 2011 -0700
+++ b/src/python/m5/main.py Thu Jun 02 17:36:07 2011 -0700
@@ -36,11 +36,8 @@
 
 usage="%prog [gem5 options] script.py [script options]"
 version="%prog 2.0"
-brief_copyright='''
-Copyright (c) 2001-2011
-The Regents of The University of Michigan
-All Rights Reserved
-'''
+brief_copyright=\
+"gem5 is copyrighted software; use the --copyright option for details."
 
 def parse_options():
 import config
@@ -52,8 +49,6 @@
 group = options.set_group
 
 # Help options
-option('-A', "--authors", action="store_true", default=False,
-help="Show author information")
 option('-B', "--build-info", action="store_true", default=False,
 help="Show build information")
 option('-C', "--copyright", action="store_true", default=False,
@@ -211,14 +206,7 @@
 
 if options.copyright:
 done = True
-print info.LICENSE
-print
-
-if options.authors:
-done = True
-print 'Author information:'
-print
-print info.AUTHORS
+print info.COPYING
 print
 
 if options.readme:
@@ -263,7 +251,7 @@
 
 verbose = options.verbose - options.quiet
 if options.verbose >= 0:
-print "gem5 Simulator System"
+print "gem5 Simulator System.  http://gem5.org";
 print brief_copyright
 print
 
diff -r 23711432221f -r c1a07ecb6619 util/find_copyrights.py
--- /dev/null   Thu Jan 01 00:00:00 1970 +
+++ b/util/find_copyrights.py   Thu Jun 02 17:36:07 2011 -0700
@@ -0,0 +1,273 @@
+#!/usr/bin/env python
+
+import os
+import re
+import sys
+
+from file_types import lang_type, find_files
+
+mode_line = re.compile('(-\*- *mode:.* *-\*-)')
+shell_comment = re.compile(r'^\s*#')
+lisp_comment = re.compile(r';')
+cpp_comment = re.compile(r'//')
+c_comment_start = re.compile(r'/\*')
+c_comment_end   = re.compile(r'\*/')
+def find_copyright_block(lines, lang_type):
+start = None
+if lang_type in ('python', 'make', 'shell', 'perl', 'scons'):
+for i,line in enumerate(lines):
+if i == 0 and (line.startswith('#!') or mode_line.search(line)):
+continue
+
+if shell_comment.search(line):
+if start is None:
+start = i
+elif start is None:
+if line.strip():
+return
+else:
+yield start, i-1
+start = None
+
+elif lang_type in ('lisp', ):
+for i,line in enumerate(lines):
+if i == 0 and mode_line.search(line):
+continue
+
+if lisp_comment.search(line):
+if start is None:
+start = i
+elif start is None:
+if line.strip():
+return
+else:
+yield start, i-1
+start = None
+
+elif lang_type in ('C', '

[gem5-dev] changeset in m5: copyright: clean up copyright blocks

[Nathan Binkert]

changeset 23711432221f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=23711432221f
description:
copyright: clean up copyright blocks

diffstat:

 src/arch/alpha/kgdb.h  |  4 ++--
 src/arch/alpha/remote_gdb.cc   |  4 ++--
 src/arch/arm/remote_gdb.cc |  4 ++--
 src/arch/generic/debugfaults.hh|  2 +-
 src/arch/sparc/remote_gdb.cc   |  4 ++--
 src/arch/x86/insts/badmicroop.cc   |  2 +-
 src/arch/x86/insts/badmicroop.hh   |  2 +-
 src/arch/x86/isa/formats/nop.isa   |  2 +-
 src/base/random_mt.cc  |  2 +-
 src/base/remote_gdb.cc |  4 ++--
 src/dev/ide_wdcreg.h   |  4 ++--
 src/dev/sparc/dtod.hh  |  2 +-
 src/mem/ruby/network/orion/Allocator/Arbiter.cc|  4 ++--
 src/mem/ruby/network/orion/Allocator/Arbiter.hh|  4 ++--
 src/mem/ruby/network/orion/Allocator/MatrixArbiter.cc  |  4 ++--
 src/mem/ruby/network/orion/Allocator/MatrixArbiter.hh  |  4 ++--
 src/mem/ruby/network/orion/Allocator/RRArbiter.cc  |  4 ++--
 src/mem/ruby/network/orion/Allocator/RRArbiter.hh  |  4 ++--
 src/mem/ruby/network/orion/Allocator/SWAllocator.cc|  4 ++--
 src/mem/ruby/network/orion/Allocator/SWAllocator.hh|  4 ++--
 src/mem/ruby/network/orion/Allocator/VCAllocator.cc|  4 ++--
 src/mem/ruby/network/orion/Allocator/VCAllocator.hh|  4 ++--
 src/mem/ruby/network/orion/Buffer/AmpUnit.cc   |  4 ++--
 src/mem/ruby/network/orion/Buffer/AmpUnit.hh   |  4 ++--
 src/mem/ruby/network/orion/Buffer/BitlineUnit.cc   |  4 ++--
 src/mem/ruby/network/orion/Buffer/BitlineUnit.hh   |  4 ++--
 src/mem/ruby/network/orion/Buffer/Buffer.cc|  4 ++--
 src/mem/ruby/network/orion/Buffer/Buffer.hh|  4 ++--
 src/mem/ruby/network/orion/Buffer/DecoderUnit.cc   |  4 ++--
 src/mem/ruby/network/orion/Buffer/DecoderUnit.hh   |  4 ++--
 src/mem/ruby/network/orion/Buffer/MemUnit.cc   |  4 ++--
 src/mem/ruby/network/orion/Buffer/MemUnit.hh   |  4 ++--
 src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc|  4 ++--
 src/mem/ruby/network/orion/Buffer/OutdrvUnit.hh|  4 ++--
 src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc |  4 ++--
 src/mem/ruby/network/orion/Buffer/PrechargeUnit.hh |  4 ++--
 src/mem/ruby/network/orion/Buffer/Register.cc  |  4 ++--
 src/mem/ruby/network/orion/Buffer/Register.hh  |  4 ++--
 src/mem/ruby/network/orion/Buffer/SRAM.cc  |  4 ++--
 src/mem/ruby/network/orion/Buffer/SRAM.hh  |  4 ++--
 src/mem/ruby/network/orion/Buffer/WordlineUnit.cc  |  4 ++--
 src/mem/ruby/network/orion/Buffer/WordlineUnit.hh  |  4 ++--
 src/mem/ruby/network/orion/Clock.cc|  4 ++--
 src/mem/ruby/network/orion/Clock.hh|  4 ++--
 src/mem/ruby/network/orion/Crossbar/Crossbar.cc|  4 ++--
 src/mem/ruby/network/orion/Crossbar/Crossbar.hh|  4 ++--
 src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.cc  |  4 ++--
 src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.hh  |  4 ++--
 src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.cc |  4 ++--
 src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.hh |  4 ++--
 src/mem/ruby/network/orion/FlipFlop.cc |  4 ++--
 src/mem/ruby/network/orion/FlipFlop.hh |  4 ++--
 src/mem/ruby/network/orion/OrionLink.cc|  4 ++--
 src/mem/ruby/network/orion/OrionLink.hh|  4 ++--
 src/mem/ruby/network/orion/OrionRouter.cc  |  4 ++--
 src/mem/ruby/network/orion/OrionRouter.hh  |  4 ++--
 src/mem/ruby/network/orion/TechParameter.cc|  4 ++--
 src/mem/ruby/network/orion/TechParameter.hh|  4 ++--
 src/mem/ruby/network/orion/Type.hh |  4 ++--
 src/mem/ruby/network/orion/Wire.cc |  4 ++--
 src/mem/ruby/network/orion/Wire.hh |  4 ++--
 src/sim/fault_fwd.hh   |  2 +-
 src/sim/root.cc|  2 +-
 src/sim/root.hh|  2 +-
 src/unittest/unittest.cc   |  2 +-
 src/unittest/unittest.hh   |  2 +-
 66 files changed, 121 insertions(+), 121 deletions(-)

diffs (truncated from 784 to 300 lines):

diff -r aa00cee9abb1 -r 23711432221f src/arch/alpha/kgdb.h
--- a/src/arch/alpha/kgdb.h Wed Jun 01 21:43:13 2011 -0700
+++ b/src/arch/alpha/kgdb.h Thu Jun 02 14:36:35 2011 -0700
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 1992, 1993
- * The Regents of the University of California.  All rights reserved.
+ * Copyright (c) 1992, 1993 The Regents of the University of California
+ * All righ

[gem5-dev] Review Request: scons: rename some things from m5 to gem5

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/727/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

scons: rename some things from m5 to gem5

The default generated binary is now gem5. instead of m5..
The latter does still work but gem5. will be generated first and
then m5. will be hard linked to it.


Diffs
-

  src/SConscript aa00cee9abb1 

Diff: http://reviews.m5sim.org/r/727/diff


Testing
---


Thanks,

Nathan

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request: scons: rename TraceFlags to DebugFlags

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/728/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

scons: rename TraceFlags to DebugFlags


Diffs
-

  src/SConscript aa00cee9abb1 
  src/arch/SConscript aa00cee9abb1 
  src/arch/arm/SConscript aa00cee9abb1 
  src/arch/mips/SConscript aa00cee9abb1 
  src/arch/power/SConscript aa00cee9abb1 
  src/arch/sparc/SConscript aa00cee9abb1 
  src/arch/x86/SConscript aa00cee9abb1 
  src/base/SConscript aa00cee9abb1 
  src/base/vnc/SConscript aa00cee9abb1 
  src/cpu/SConscript aa00cee9abb1 
  src/cpu/inorder/SConscript aa00cee9abb1 
  src/cpu/o3/SConscript aa00cee9abb1 
  src/cpu/ozone/SConscript aa00cee9abb1 
  src/cpu/pred/SConscript aa00cee9abb1 
  src/cpu/simple/SConscript aa00cee9abb1 
  src/cpu/testers/directedtest/SConscript aa00cee9abb1 
  src/cpu/testers/memtest/SConscript aa00cee9abb1 
  src/cpu/testers/networktest/SConscript aa00cee9abb1 
  src/cpu/testers/rubytest/SConscript aa00cee9abb1 
  src/dev/SConscript aa00cee9abb1 
  src/dev/alpha/SConscript aa00cee9abb1 
  src/dev/arm/SConscript aa00cee9abb1 
  src/dev/mips/SConscript aa00cee9abb1 
  src/dev/sparc/SConscript aa00cee9abb1 
  src/dev/x86/SConscript aa00cee9abb1 
  src/kern/SConscript aa00cee9abb1 
  src/mem/SConscript aa00cee9abb1 
  src/mem/cache/SConscript aa00cee9abb1 
  src/mem/cache/tags/SConscript aa00cee9abb1 
  src/sim/SConscript aa00cee9abb1 

Diff: http://reviews.m5sim.org/r/728/diff


Testing
---


Thanks,

Nathan

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request: copyright: Add code for finding all copyright blocks and create a COPYING file

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/726/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

copyright: Add code for finding all copyright blocks and create a COPYING file

The end of the COPYING file was generated with:
% python ./util/find_copyrights.py configs src system tests util

Update -C command line option to spit out COPYING file

[ Some notes on this change.  1) I could add the find_copyrights.py function to 
the build to automatically generate the list.  Should we do that?  For now, 
I've appended the list to the COPYING file.  We should also probably get rid of 
the AUTHORS file.  What do you all think? (either that or we should update it) ]


Diffs
-

  COPYING PRE-CREATION 
  LICENSE aa00cee9abb1 
  src/SConscript aa00cee9abb1 
  src/python/m5/main.py aa00cee9abb1 
  util/find_copyrights.py PRE-CREATION 

Diff: http://reviews.m5sim.org/r/726/diff


Testing
---


Thanks,

Nathan

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request: copyright: clean up copyright blocks

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/725/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

copyright: clean up copyright blocks

This is basically to make it easier to run the find_copyrights.py utility 
that's added in the next changeset.  It fixes some consistency of naming.  
(e.g. Advanced Micro Devices -> Advanced Micro Devices, Inc.)


Diffs
-

  src/arch/alpha/kgdb.h aa00cee9abb1 
  src/arch/alpha/remote_gdb.cc aa00cee9abb1 
  src/arch/arm/remote_gdb.cc aa00cee9abb1 
  src/arch/generic/debugfaults.hh aa00cee9abb1 
  src/arch/sparc/remote_gdb.cc aa00cee9abb1 
  src/arch/x86/insts/badmicroop.hh aa00cee9abb1 
  src/arch/x86/insts/badmicroop.cc aa00cee9abb1 
  src/arch/x86/isa/formats/nop.isa aa00cee9abb1 
  src/base/random_mt.cc aa00cee9abb1 
  src/base/remote_gdb.cc aa00cee9abb1 
  src/dev/ide_wdcreg.h aa00cee9abb1 
  src/dev/sparc/dtod.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/Arbiter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/Arbiter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/MatrixArbiter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/MatrixArbiter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/RRArbiter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/RRArbiter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/SWAllocator.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/SWAllocator.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/VCAllocator.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Allocator/VCAllocator.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/AmpUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/AmpUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/BitlineUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/BitlineUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/Buffer.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/Buffer.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/DecoderUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/DecoderUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/MemUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/MemUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/OutdrvUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/PrechargeUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/Register.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/Register.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/SRAM.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/SRAM.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/WordlineUnit.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Buffer/WordlineUnit.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Clock.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Clock.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/Crossbar.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/Crossbar.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/MatrixCrossbar.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Crossbar/MultreeCrossbar.cc aa00cee9abb1 
  src/mem/ruby/network/orion/FlipFlop.hh aa00cee9abb1 
  src/mem/ruby/network/orion/FlipFlop.cc aa00cee9abb1 
  src/mem/ruby/network/orion/OrionLink.hh aa00cee9abb1 
  src/mem/ruby/network/orion/OrionLink.cc aa00cee9abb1 
  src/mem/ruby/network/orion/OrionRouter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/OrionRouter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/TechParameter.hh aa00cee9abb1 
  src/mem/ruby/network/orion/TechParameter.cc aa00cee9abb1 
  src/mem/ruby/network/orion/Type.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Wire.hh aa00cee9abb1 
  src/mem/ruby/network/orion/Wire.cc aa00cee9abb1 
  src/sim/fault_fwd.hh aa00cee9abb1 
  src/sim/root.hh aa00cee9abb1 
  src/sim/root.cc aa00cee9abb1 
  src/unittest/unittest.hh aa00cee9abb1 
  src/unittest/unittest.cc aa00cee9abb1 

Diff: http://reviews.m5sim.org/r/725/diff


Testing
---


Thanks,

Nathan

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Debug Flags

[nathan binkert]

I'll post a diff to fix the SCons stuff very soon.  Just compiling
stuff to make sure it works.

The biggest problem with two namespaces is that it's a lot of code to
manage to support both of them.  The debug flags stuff is all over the
place: scons to generate the flags files, command line options, gdb
commands, C++ classes, and probably more.  I think we'll be able to
work through the confusion.

  Nate

On Wed, Jun 1, 2011 at 9:40 PM, Steve Reinhardt  wrote:
> OK, now that I'm at a keyboard: if we change the scons thing from
> TraceFlag() to DebugFlag(), then there's one set of flags with one set
> of names, it's all debug flags.  Some (currently most) of them are
> only used to control DPRINTFs, but they could be used for other
> things, and the same flag could in theory be used for both DPRINTFs
> and other things.
>
> All the --trace-* options solely control things related to DPRINTFs
> and/or exec tracing (I believe), so that's consistent too.
>
> It might not be the simplest scheme ever, but it sounds simpler than
> having distinct debug flags and trace flags.
>
> Steve
>
> On Wed, Jun 1, 2011 at 8:15 PM, Steve Reinhardt  wrote:
>> On my phone, so I'll be brief, but just fixing the scons to be consistent
>> sounds good to me.
>>
>> On Jun 1, 2011 6:55 PM, "Gabriel Michael Black" 
>> wrote:
>>> So, I think part of the confusion is that there are two names now,
>>> debug flags and trace flags, but they're different views of the same
>>> mechanism (yes? no?) It seems like the --trace* options are like the
>>> --debug* options, except their intended use is a subset of --debug*,
>>> specifically DPRINTFs. What about returning the DPRINTF ones to
>>> --trace-flags, etc., and introducing a separate parallel set of
>>> options and namespace for the debug stuff? There's some macro or
>>> something to check if trace flags are turned on, and that encourages
>>> their use as debug flags (although I think that use is minimal in the
>>> current code). We could introduce a new DEBUG_ON() macro (or a better
>>> name) and optionally eliminate the trace oriented one or make it
>>> internal to DPRINTFs only. I can think of some valid uses for keeping
>>> it like blocks of DPRINTFs like Ali added recently, but it blurs the
>>> line and could add to the confusion.
>>>
>>> By having two parallel systems, even though they're a bit redundant
>>> where they overlap, I think it introduces a clear conceptual
>>> separation between the two. Then it's clear what trace flags are for
>>> and when to use them, and also what debug flags are for and when to
>>> use them.
>>>
>>> We really have two different ideas budding off from each other
>>> (controlling tracing and debug features), and by partially bundling
>>> them together and partially distinguishing them that leads to
>>> confusion. The mental model is different from the way you have to
>>> control things, and trying to reconcile the two views makes the system
>>> hard to reason about.
>>>
>>> Gabe
>>>
>>> Quoting nathan binkert :
>>>
>>>> Ok, there has been a lot of confusion about debug flags and trace
>>>> flags. I changed the way the flags stuff worked from a compile
>>>> perspective which required me to make changes throughout the tree, so
>>>> I took the opportunity to rename the trace flags to debug flags. The
>>>> idea behind the change was that the flags can be used for things other
>>>> than tracing (I use them for breakpoints) and there is only one
>>>> namespace, so I just renamed it to debug (people did review that
>>>> change).
>>>>
>>>> So, I renamed --trace-flags to --debug-flags and --trace-flags-help to
>>>> --debug-flags-help. --trace-start, --trace-file, and --trace-ignore
>>>> stayed the same because those only affect the tracing portion of the
>>>> debugging stuff. I never renamed the TraceFlags SCons option to
>>>> DebugFlags.
>>>>
>>>> So, how do we clear up the confusion? Should I just fix the SCons
>>>> thing and people will just learn? Should I change the name back?
>>>> (There are a ton of places where this would change).
>>>>
>>>> Anyone care?
>>>>
>>>> Nate
>>>> ___
>>>> gem5-dev mailing list
>>>> gem5-dev@m5sim.org
>>>> http://m5sim.org/mailman/listinfo/gem5-dev
>>>>
>>>
>>>
>>> ___
>>> gem5-dev mailing list
>>> gem5-dev@m5sim.org
>>> http://m5sim.org/mailman/listinfo/gem5-dev
>>
> ___
> gem5-dev mailing list
> gem5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/gem5-dev
>
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Debug Flags

[nathan binkert]

Ok, there has been a lot of confusion about debug flags and trace
flags.  I changed the way the flags stuff worked from a compile
perspective which required me to make changes throughout the tree, so
I took the opportunity to rename the trace flags to debug flags.  The
idea behind the change was that the flags can be used for things other
than tracing (I use them for breakpoints) and there is only one
namespace, so I just renamed it to debug (people did review that
change).

So, I renamed --trace-flags to --debug-flags and --trace-flags-help to
--debug-flags-help.  --trace-start, --trace-file, and --trace-ignore
stayed the same because those only affect the tracing portion of the
debugging stuff.  I never renamed the TraceFlags SCons option to
DebugFlags.

So, how do we clear up the confusion?  Should I just fix the SCons
thing and people will just learn?  Should I change the name back?
(There are a ton of places where this would change).

Anyone care?

  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: Config: Add support for a Self.all proxy object

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/720/#review1265
---



src/python/m5/SimObject.py
<http://reviews.m5sim.org/r/720/#comment1742>

Does this do what you want?  It doesn't seem like it would recurse down the 
tree and find all nodes that match (or does it?)



src/python/m5/params.py
<http://reviews.m5sim.org/r/720/#comment1743>

what exactly is this doing?  Also, what happens if val is of length 2 and 
the first element is a list or tuple?  Seems like an error condition or you're 
doing something wrong.



src/python/m5/proxy.py
<http://reviews.m5sim.org/r/720/#comment1744>

Seems like Mr Doxygen should be documenting this file a bit better :)

Also, what does Parent.all do?  It'd be nice if you described Self.all and 
Parent.all in this file.


- Nathan


On 2011-05-26 19:17:18, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/720/
> ---
> 
> (Updated 2011-05-26 19:17:18)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> Config: Add support for a Self.all proxy object
> 
> 
> Diffs
> -
> 
>   src/python/m5/SimObject.py 3f37cc5d25bc 
>   src/python/m5/params.py 3f37cc5d25bc 
>   src/python/m5/proxy.py 3f37cc5d25bc 
>   src/sim/System.py 3f37cc5d25bc 
> 
> Diff: http://reviews.m5sim.org/r/720/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] registerThreadContext

[nathan binkert]

> For #1 and #4, these  are pretty much the same right? The contextID is
> really all possible sharers rather then just threadContext. Seems like you
> should keep the meaning of contextID as it pertains to thread and then
> generate a "sharerID" that would be a superset of the contextIDs. Objects
> that dont have an explicit thread but are sharing can just offset off the
> highest contextID. would that make sense?
Yeah, I guess #1 and #4 were more or less the same as written.  What
I'd really like to know is if we should have just one ID or two.  I'd
personally rather stick with one.  Maybe we just call it
memoryAccessID or sharerID and the contexts would just use that.  I'd
really rather avoid adding IDs for the sake of adding IDs, but if it
really makes sense, then we should do it.

> For #2,  I'd prefer not to further complicate that ThreadContext interface.
I'm not sure that it would complicate things much.  The idea is to
just put the things that are for memory requests into a base class and
have thread context derive from that.  So, not adding stuff, just
splitting the class into two parts.

> I thought the easiest way would be to use the port connections to traverse
> the system since something is already done for the snoop Port
> registration.The only trick would be for CPUs with multiple threads you need
> to ask out how many contexts it's going to share.
Yeah, it is doable.  It would probably be nice to have a routine that
is just designed to traverse the memory hierarchy and call a member
function on every object in the hierarchy.  I think registering with
the system gets the same effect and is potentially simpler.

  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] registerThreadContext

[nathan binkert]

Hi Everyone,

I'm trying to work with Lisa's patch to convert cache vector
statistics to record data on a per-context basis where context is
anything that executes instructions.  (Some things were per-CPU and
some things were per-thread and neither make sense).  She added a
parameter to each cache called "num_sharing_contexts" that would tell
the cache how many contexts could send that cache a request.  Indexing
into the vector was done by taking req->contextId and doing a modulo
with num_sharing_contexts.  DMA controllers would all get stuck in a
special additional bin.

There are two things I don't like about this scheme.  First,
configuring the parameter is a pain in the butt. Second, it's hard to
compare statistics from two different caches because their indexes are
different.  Third, you can't separate out DMA controllers.

So, what I did was get rid fo num_sharing_contexts and use the number
of contexts that were registered with the system with
registerThreadContext (adding one for the DMA controllers).  This
works for the common case, but doesn't work with the MemTester because
the memtester doesn't have a thread context to register.

I see a few options for solving this problem:
1) Separate out the contextId allocation from registerThreadContext so
things like DMA controllers and memtesters can get allocated a
contextID.
2) Create a base class for ThreadContext that is far simpler than the
current thread context and use that when registering.
3) Figure out contextID not by registration, but instead by doing a
traversal of the memory system.  This would require that we have some
sort of indication differentiating memory objects that can generate
requests and thus require a contextID and memory objects that can't
(caches, dram, pio devices, etc.).  We add a constructor parameter to
the MemObject base class.
4) Add a separate registration function for non Thread Contexts.

Thoughts?  Ideas?

  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] changeset in m5: style: Make the style hook work in directories ...

[Nathan Binkert]

changeset 8b0eee09deaf in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8b0eee09deaf
description:
style: Make the style hook work in directories other than the root.

diffstat:

 util/style.py |  13 -
 1 files changed, 8 insertions(+), 5 deletions(-)

diffs (43 lines):

diff -r 76095b05f4da -r 8b0eee09deaf util/style.py
--- a/util/style.py Mon May 23 14:29:23 2011 -0700
+++ b/util/style.py Tue May 24 21:19:31 2011 -0700
@@ -400,10 +400,12 @@
 if skip(fname):
 continue
 
-if whitespace.apply(fname, prompt):
+fpath = joinpath(repo.root, fname)
+
+if whitespace.apply(fpath, prompt):
 return True
 
-if sorted_includes.apply(fname, prompt):
+if sorted_includes.apply(fpath, prompt):
 return True
 
 try:
@@ -416,12 +418,13 @@
 if skip(fname):
 continue
 
+fpath = joinpath(repo.root, fname)
 regions = modregions(wctx, fname)
 
-if whitespace.apply(fname, prompt, regions):
+if whitespace.apply(fpath, prompt, regions):
 return True
 
-if sorted_includes.apply(fname, prompt, regions):
+if sorted_includes.apply(fpath, prompt, regions):
 return True
 
 return False
@@ -434,7 +437,7 @@
 verbose = 0
 stats = ValidationStats()
 for f in modified + added:
-validate(f, stats, verbose, None)
+validate(joinpath(repo.root, f), stats, verbose, None)
 
 if stats:
 stats.dump()
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request: slicc: add a protocol statement and an include statement

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/717/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

slicc: add a protocol statement and an include statement
All protocols must specify their name
The include statement allows any file to include another file.


Diffs
-

  src/mem/protocol/MESI_CMP_directory.slicc 3f37cc5d25bc 
  src/mem/protocol/MI_example.slicc 3f37cc5d25bc 
  src/mem/protocol/MOESI_CMP_directory.slicc 3f37cc5d25bc 
  src/mem/protocol/MOESI_CMP_token.slicc 3f37cc5d25bc 
  src/mem/protocol/MOESI_hammer.slicc 3f37cc5d25bc 
  src/mem/protocol/Network_test.slicc 3f37cc5d25bc 
  src/mem/protocol/RubySlicc_interfaces.slicc 3f37cc5d25bc 
  src/mem/protocol/SConscript 3f37cc5d25bc 
  src/mem/slicc/main.py 3f37cc5d25bc 
  src/mem/slicc/parser.py 3f37cc5d25bc 

Diff: http://reviews.m5sim.org/r/717/diff


Testing
---

Quick Regressions, Compile everything


Thanks,

Nathan

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request: slicc: cleanup slicc code and make it less verbose

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/716/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

slicc: cleanup slicc code and make it less verbose


Diffs
-

  src/mem/protocol/SConscript 3f37cc5d25bc 
  src/mem/slicc/ast/AST.py 3f37cc5d25bc 
  src/mem/slicc/main.py 3f37cc5d25bc 
  src/mem/slicc/parser.py 3f37cc5d25bc 
  src/mem/slicc/symbols/SymbolTable.py 3f37cc5d25bc 
  src/mem/slicc/util.py 3f37cc5d25bc 
  src/python/m5/util/__init__.py 3f37cc5d25bc 

Diff: http://reviews.m5sim.org/r/716/diff


Testing
---

Quick Regressions, Compile everything


Thanks,

Nathan

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request: grammar: better encapsulation of a grammar and parsing

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/715/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently.  This makes implementing an include statement as part
of a grammar possible.


Diffs
-

  src/arch/isa_parser.py 3f37cc5d25bc 
  src/mem/slicc/ast/AST.py 3f37cc5d25bc 
  src/mem/slicc/parser.py 3f37cc5d25bc 
  src/python/m5/util/grammar.py 3f37cc5d25bc 

Diff: http://reviews.m5sim.org/r/715/diff


Testing
---

Quick Regressions, Compile everything


Thanks,

Nathan

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request: style: Make the style hook work in directories other than the root.

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/714/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

style: Make the style hook work in directories other than the root.


Diffs
-

  util/style.py 3f37cc5d25bc 

Diff: http://reviews.m5sim.org/r/714/diff


Testing
---

Quick Regressions, Compile everything


Thanks,

Nathan

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: syscall emul: fix Power Linux mmap constant, plus other cleanup

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/710/#review1254
---

Ship it!


I didn't compile it or anything, but it looks good to me.

- Nathan


On 2011-05-23 16:48:45, Steve Reinhardt wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/710/
> ---
> 
> (Updated 2011-05-23 16:48:45)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> syscall emul: fix Power Linux mmap constant, plus other cleanup
> 
> We were getting a spurious warning in the regressions that turned
> out to be due to having the wrong value for TGT_MAP_ANONYMOUS for
> Power Linux, but in the process of tracking it down I ended up
> doing some cleanup of the mmap handling in general.
> 
> 
> Diffs
> -
> 
>   src/arch/power/linux/linux.hh 3f37cc5d25bc 
>   src/sim/process.cc 3f37cc5d25bc 
>   src/sim/syscall_emul.hh 3f37cc5d25bc 
> 
> Diff: http://reviews.m5sim.org/r/710/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Steve
> 
>

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: util/regress: make default action a more thorough regression

[nathan binkert]

>
> So I played around with this, and the first problem is that your current code 
> can't handle default values.  I fixed that in options.py, but it still 
> doesn't print the defaults nicely, e.g., instead of:
>
>   --test-variants=TEST_VARIANTS
> comma-separated build variants to test (default:
> 'opt')
>   --compile-variants=VARIANTS
> comma-separated build variants to compile only (not
> test) (default: 'debug,fast')
>
> we get:
>
> --test-variants=TEST_VARIANTS
> comma-separated build variants to test (default:
> '['opt']')
> --compile-variants=VARIANTS
> comma-separated build variants to compile only (not
> test) (default: '['debug', 'fast']')
>
> Not tragic, but I like the former better, so I may keep the original solution.
>
>
Maybe overkill, but you could probably subclass list and simply define a new
__str__ for it to get the printout that you like.

  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: Ruby: Convert to M5 Stats

[nathan binkert]

>
> I agree that makes sense in some instances, but I've found that when you do 
> that, it makes it hard to extract stats that can compare to runs of different 
> systems. For example, when I'm comparing stats across different systems, I 
> want to easily compare how many times a coherency miss fell within the 10-20 
> cycle range. When you don't have that, you have one run w/a stat range of 
> 10-20 and another with 10-50. That gets messy ... quick.
>
> That's why I think it's advantageous to define a bin size and then a 
> saturation point. Maybe called that "saturating histogram" instead of the 
> regular histogram.
>
> It was a easy fix for me to do in the Ruby tree, but if that's not something 
> straightforward for gem5, just mark that down as a @todo or limitation of the 
> histograms.
>
> The stat with fixed size bins is the distribution.  If you swap Histogram
with Distribution, basically the only change you need is to add a bin size.
 That said, the bins of the histogram will always be a power of 2 in size,
so if you have two histograms with different bin sizes, you can convert the
one with smaller bins to one with larger bins by just adding adjacent bins
(which is how the histogram itself automatically grows).  In the future, I
(or someone else) can add support in the python code to allow you to do this
pretty easily.

  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: Ruby: Convert to M5 Stats

[Nathan Binkert]

> On 2011-05-17 12:13:18, Nathan Binkert wrote:
> > src/mem/ruby/profiler/Profiler.cc, line 456
> > <http://reviews.m5sim.org/r/704/diff/1/?file=12599#file12599line456>
> >
> > How did you pick this magic number?  Can we at least make it a constant 
> > that is defined in a header file with an explanation as to how it was 
> > chosen?
> 
> Derek Hower wrote:
> All magic numbers came from whatever Ruby was doing before the conversion 
> (typically in the default initialization for Histograms). Making it a 
> constant sounds fine.
> 
> Korey Sewell wrote:
> I can attest to these hardcoded values being the root of many (not all!) 
> Ruby evils. 
> 
> This is the histogram bucket size and the tricky thing is these also get 
> reset with a clear(200) in the clearStats() function. The clearStats() 
> functions should get whacked (nate's comments below), but ideally, make the 
> histogram bucket size a parameter with a default value here.
> 
> Korey Sewell wrote:
> The histogram is initialized with size per bin and also number of bins. 
> 
> I really don't think this should be a constant (this has caused me some 
> headache before).
> 
> Instead, a parameter with a default value of 200 sounds about right, no? 
> Also, where does the bin size get initialized for the histogram stat? 
> (Another candidate for a default parameter.)

Yeah, a parameter does make sense.  As for bin size, that's automatic.  Bin 
sizes start at 1 and automatically double until they can hold all samples.


- Nathan


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/704/#review1237
---


On 2011-05-16 15:06:16, Derek Hower wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/704/
> ---
> 
> (Updated 2011-05-16 15:06:16)
> 
> 
> Review request for Default, Nathan Binkert, Korey Sewell, and Brad Beckmann.
> 
> 
> Summary
> ---
> 
> This patch contains changes to convert Ruby's stat handling to the M5-style 
> Stat class. The ultimate goal is to remove Profiler entirely, though this 
> patch only represents a (significant) step towards that goal. Some stats 
> remain in the Profiler, notably those that do not have an obvious object to 
> hold them (like Address Profiler) or those that I'm not sure what they do 
> (e.g., *wCC*). Also, this patch does not contain a Garnet stats conversion 
> (though the simple network is converted).
> 
> 
> Diffs
> -
> 
>   src/mem/ruby/network/simple/SimpleNetwork.hh UNKNOWN 
>   src/mem/ruby/network/simple/SimpleNetwork.cc UNKNOWN 
>   src/mem/ruby/network/simple/Throttle.hh UNKNOWN 
>   src/mem/ruby/network/simple/Throttle.cc UNKNOWN 
>   src/mem/ruby/profiler/AddressProfiler.hh UNKNOWN 
>   src/mem/ruby/profiler/AddressProfiler.cc UNKNOWN 
>   src/mem/ruby/profiler/CacheProfiler.hh UNKNOWN 
>   src/mem/ruby/profiler/CacheProfiler.cc UNKNOWN 
>   src/mem/ruby/profiler/MemCntrlProfiler.hh UNKNOWN 
>   src/mem/ruby/profiler/MemCntrlProfiler.cc UNKNOWN 
>   src/mem/ruby/profiler/Profiler.hh UNKNOWN 
>   src/mem/ruby/profiler/Profiler.cc UNKNOWN 
>   src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh UNKNOWN 
>   src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc UNKNOWN 
>   src/mem/ruby/system/CacheMemory.hh UNKNOWN 
>   src/mem/ruby/system/MemoryControl.hh UNKNOWN 
>   src/mem/ruby/system/Sequencer.hh UNKNOWN 
>   src/mem/ruby/system/Sequencer.cc UNKNOWN 
>   src/mem/ruby/system/System.cc UNKNOWN 
>   src/mem/slicc/symbols/StateMachine.py UNKNOWN 
> 
> Diff: http://reviews.m5sim.org/r/704/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Derek
> 
>

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] changeset in m5: gcc: fix an uninitialized variable warning from...

[Nathan Binkert]

changeset d1ce92fd3245 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d1ce92fd3245
description:
gcc: fix an uninitialized variable warning from G++ 4.5

diffstat:

 src/arch/arm/isa/insts/macromem.isa |  3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diffs (13 lines):

diff -r 79cf09f5a234 -r d1ce92fd3245 src/arch/arm/isa/insts/macromem.isa
--- a/src/arch/arm/isa/insts/macromem.isa   Wed May 18 03:06:07 2011 -0400
+++ b/src/arch/arm/isa/insts/macromem.isa   Wed May 18 11:06:23 2011 -0700
@@ -541,6 +541,9 @@
 for (unsigned i = 0; i < %(sRegs)d; i++) {
 destRegs.elements[i] = sourceRegs[i].elements[lane];
 }
+for (unsigned i = %(sRegs)d; i < %(dRegs)d * perDReg; ++i) {
+destRegs.elements[i] = 0;
+}
 
 %(unloadRegs)s
 ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: Ruby: Convert to M5 Stats

[Nathan Binkert]

> On 2011-05-17 12:13:18, Nathan Binkert wrote:
> > src/mem/ruby/profiler/AddressProfiler.cc, line 235
> > <http://reviews.m5sim.org/r/704/diff/1/?file=12593#file12593line235>
> >
> > .name should really have name() as part of the name.  Is the 
> > AddressProfiler not a SimObject() ?
> 
> Derek Hower wrote:
> I don't think it is.

Can I suggest that you create a name() function anyway and have some way to set 
the name variable?  This will facilitate conversion to a SimObject in the 
future and make things like DPRINTF work better (DPRINTF requires name())


- Nathan


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/704/#review1237
---


On 2011-05-16 15:06:16, Derek Hower wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/704/
> ---
> 
> (Updated 2011-05-16 15:06:16)
> 
> 
> Review request for Default, Nathan Binkert, Korey Sewell, and Brad Beckmann.
> 
> 
> Summary
> ---
> 
> This patch contains changes to convert Ruby's stat handling to the M5-style 
> Stat class. The ultimate goal is to remove Profiler entirely, though this 
> patch only represents a (significant) step towards that goal. Some stats 
> remain in the Profiler, notably those that do not have an obvious object to 
> hold them (like Address Profiler) or those that I'm not sure what they do 
> (e.g., *wCC*). Also, this patch does not contain a Garnet stats conversion 
> (though the simple network is converted).
> 
> 
> Diffs
> -
> 
>   src/mem/ruby/network/simple/SimpleNetwork.hh UNKNOWN 
>   src/mem/ruby/network/simple/SimpleNetwork.cc UNKNOWN 
>   src/mem/ruby/network/simple/Throttle.hh UNKNOWN 
>   src/mem/ruby/network/simple/Throttle.cc UNKNOWN 
>   src/mem/ruby/profiler/AddressProfiler.hh UNKNOWN 
>   src/mem/ruby/profiler/AddressProfiler.cc UNKNOWN 
>   src/mem/ruby/profiler/CacheProfiler.hh UNKNOWN 
>   src/mem/ruby/profiler/CacheProfiler.cc UNKNOWN 
>   src/mem/ruby/profiler/MemCntrlProfiler.hh UNKNOWN 
>   src/mem/ruby/profiler/MemCntrlProfiler.cc UNKNOWN 
>   src/mem/ruby/profiler/Profiler.hh UNKNOWN 
>   src/mem/ruby/profiler/Profiler.cc UNKNOWN 
>   src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh UNKNOWN 
>   src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc UNKNOWN 
>   src/mem/ruby/system/CacheMemory.hh UNKNOWN 
>   src/mem/ruby/system/MemoryControl.hh UNKNOWN 
>   src/mem/ruby/system/Sequencer.hh UNKNOWN 
>   src/mem/ruby/system/Sequencer.cc UNKNOWN 
>   src/mem/ruby/system/System.cc UNKNOWN 
>   src/mem/slicc/symbols/StateMachine.py UNKNOWN 
> 
> Diff: http://reviews.m5sim.org/r/704/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Derek
> 
>

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: Ruby: Convert to M5 Stats

[nathan binkert]

>
> These histograms dynamically size.
>
> Does the default in M5 do the same? and using the same resizing algorithm?
>
>
The histogram itself dynamically resizes, but the vector that's here doesn't
need to be dynamic.

  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: Ruby: Convert to M5 Stats

[nathan binkert]

>
> I had trouble getting my individual patches uploaded to review board (it
> said they were diffs?), so I merged them into one. You should ignore the
> first request that came through, as it is included below.



In the future, it's best to use the reviewboard mercurial extension and use
the command "hg postreview -o" to post a diff and "hg postreview -o -u -e
" to update a diff.

There's a bit of information here: http://gem5.org/Commit_Access


  Nate
___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [gem5-dev] Review Request: Ruby: Convert to M5 Stats

[Nathan Binkert]

src/mem/ruby/profiler/Profiler.cc
<http://reviews.m5sim.org/r/704/#comment1719>

More magic numbers.



src/mem/ruby/profiler/Profiler.cc
<http://reviews.m5sim.org/r/704/#comment1715>

This should probably be deleted.



src/mem/ruby/system/CacheMemory.hh
<http://reviews.m5sim.org/r/704/#comment1716>

If the profiler is a SimObject, regStats will automatically get called.



src/mem/ruby/system/Sequencer.hh
<http://reviews.m5sim.org/r/704/#comment1717>

Hmmm.  More vectors of histograms.  Can we make this an array instead?



src/mem/ruby/system/Sequencer.cc
<http://reviews.m5sim.org/r/704/#comment1720>

more magic numbers.



src/mem/slicc/symbols/StateMachine.py
<http://reviews.m5sim.org/r/704/#comment1721>

can we use name() ?



src/mem/slicc/symbols/StateMachine.py
<http://reviews.m5sim.org/r/704/#comment1722>

Can we avoid the dynamic allocation here?



src/mem/slicc/symbols/StateMachine.py
<http://reviews.m5sim.org/r/704/#comment1723>

Is this used outside of stats?



src/mem/slicc/symbols/StateMachine.py
<http://reviews.m5sim.org/r/704/#comment1724>

is this used outside of stats?


- Nathan


On 2011-05-16 15:06:16, Derek Hower wrote:
> 
> -------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/704/
> ---
> 
> (Updated 2011-05-16 15:06:16)
> 
> 
> Review request for Default, Nathan Binkert, Korey Sewell, and Brad Beckmann.
> 
> 
> Summary
> ---
> 
> This patch contains changes to convert Ruby's stat handling to the M5-style 
> Stat class. The ultimate goal is to remove Profiler entirely, though this 
> patch only represents a (significant) step towards that goal. Some stats 
> remain in the Profiler, notably those that do not have an obvious object to 
> hold them (like Address Profiler) or those that I'm not sure what they do 
> (e.g., *wCC*). Also, this patch does not contain a Garnet stats conversion 
> (though the simple network is converted).
> 
> 
> Diffs
> -
> 
>   src/mem/ruby/network/simple/SimpleNetwork.hh UNKNOWN 
>   src/mem/ruby/network/simple/SimpleNetwork.cc UNKNOWN 
>   src/mem/ruby/network/simple/Throttle.hh UNKNOWN 
>   src/mem/ruby/network/simple/Throttle.cc UNKNOWN 
>   src/mem/ruby/profiler/AddressProfiler.hh UNKNOWN 
>   src/mem/ruby/profiler/AddressProfiler.cc UNKNOWN 
>   src/mem/ruby/profiler/CacheProfiler.hh UNKNOWN 
>   src/mem/ruby/profiler/CacheProfiler.cc UNKNOWN 
>   src/mem/ruby/profiler/MemCntrlProfiler.hh UNKNOWN 
>   src/mem/ruby/profiler/MemCntrlProfiler.cc UNKNOWN 
>   src/mem/ruby/profiler/Profiler.hh UNKNOWN 
>   src/mem/ruby/profiler/Profiler.cc UNKNOWN 
>   src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh UNKNOWN 
>   src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc UNKNOWN 
>   src/mem/ruby/system/CacheMemory.hh UNKNOWN 
>   src/mem/ruby/system/MemoryControl.hh UNKNOWN 
>   src/mem/ruby/system/Sequencer.hh UNKNOWN 
>   src/mem/ruby/system/Sequencer.cc UNKNOWN 
>   src/mem/ruby/system/System.cc UNKNOWN 
>   src/mem/slicc/symbols/StateMachine.py UNKNOWN 
> 
> Diff: http://reviews.m5sim.org/r/704/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Derek
> 
>

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Review Request: gcc: fix an uninitialized variable warning from G++ 4.5

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/705/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

gcc: fix an uninitialized variable warning from G++ 4.5


Diffs
-

  src/arch/arm/isa/insts/macromem.isa fb0e525008c5 

Diff: http://reviews.m5sim.org/r/705/diff


Testing
---


Thanks,

Nathan

___
gem5-dev mailing list
gem5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/gem5-dev

Re: [m5-dev] Review Request: O3: Removed unnecessary unserialize instruction flags.

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/694/#review1233
---


Really?  Are you sure that really works?  Those registers are not renamed and 
things could go wrong.

- Nathan


On 2011-05-13 14:34:53, Yasuko Watanabe wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/694/
> ---
> 
> (Updated 2011-05-13 14:34:53)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> O3: Removed unnecessary unserialize instruction flags.
> 
> 
> Diffs
> -
> 
>   src/arch/alpha/isa/decoder.isa 54a65799e4c1 
> 
> Diff: http://reviews.m5sim.org/r/694/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Yasuko
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] changeset in m5: stats: delete mysql support

[Nathan Binkert]

t: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#include 
-
-#include "base/mysql.hh"
-#include "base/trace.hh"
-#include "debug/SQL.hh"
-
-using namespace std;
-
-namespace MySQL {
-
-inline const char *
-charstar(const string &string)
-{
-return string.empty() ? NULL : string.c_str();
-}
-
-ostream &
-operator<<(ostream &stream, const Error &error)
-{
-stream << error.string();
-return stream;
-}
-
-/*
- * The connection class
- */
-Connection::Connection()
-: valid(false)
-{
-}
-
-Connection::~Connection()
-{
-if (valid)
-close();
-}
-
-
-bool
-Connection::connect(const string &xhost, const string &xuser,
-const string &xpasswd, const string &xdatabase)
-{
-if (connected())
-return error.set("Already Connected");
-
-_host = xhost;
-_user = xuser;
-_passwd = xpasswd;
-_database = xdatabase;
-
-error.clear();
-
-mysql_init(&mysql);
-mysql_options(&mysql, MYSQL_OPT_COMPRESS, 0); // might want to be 1
-mysql_options(&mysql, MYSQL_READ_DEFAULT_GROUP, "odbc");
-if (!mysql_real_connect(&mysql, charstar(_host), charstar(_user),
-charstar(_passwd), charstar(_database),
-0, NULL, 0))
-return error.set(mysql_error(&mysql));
-
-valid = true;
-return false;
-}
-
-void
-Connection::close()
-{
-mysql_close(&mysql);
-}
-
-bool
-Connection::query(const string &sql)
-{
-DPRINTF(SQL, "Sending SQL query to server:\n%s", sql);
-error.clear();
-if (mysql_real_query(&mysql, sql.c_str(), sql.size()))
-error.set(mysql_error(&mysql));
-
-return error;
-}
-
-
-} // namespace MySQL
diff -r be7f03723412 -r d57afdcf38f5 src/base/mysql.hh
--- a/src/base/mysql.hh Thu May 12 11:19:35 2011 -0700
+++ /dev/null   Thu Jan 01 00:00:00 1970 +
@@ -1,426 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-

[m5-dev] changeset in m5: stats: move code that loops over all stats into...

[Nathan Binkert]

changeset be7f03723412 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=be7f03723412
description:
stats: move code that loops over all stats into python

diffstat:

 src/base/SConscript |   2 -
 src/base/statistics.cc  |  60 +++--
 src/base/statistics.hh  |  28 ++
 src/base/stats/info.hh  |   4 +-
 src/base/stats/mysql.cc |  52 +---
 src/base/stats/mysql.hh |  10 +++--
 src/base/stats/output.cc|  73 -
 src/base/stats/output.hh|  24 ++--
 src/base/stats/text.cc  |  29 +++
 src/base/stats/text.hh  |   5 +-
 src/base/stats/visit.cc |  41 ---
 src/base/stats/visit.hh |  59 -
 src/python/m5/simulate.py   |   2 +-
 src/python/m5/stats/__init__.py |  57 ++-
 src/python/swig/stats.i |  56 +++---
 15 files changed, 183 insertions(+), 319 deletions(-)

diffs (truncated from 858 to 300 lines):

diff -r 221013f9fd2f -r be7f03723412 src/base/SConscript
--- a/src/base/SConscript   Thu May 12 11:19:32 2011 -0700
+++ b/src/base/SConscript   Thu May 12 11:19:35 2011 -0700
@@ -71,9 +71,7 @@
 Source('loader/raw_object.cc')
 Source('loader/symtab.cc')
 
-Source('stats/output.cc')
 Source('stats/text.cc')
-Source('stats/visit.cc')
 
 if env['USE_MYSQL']:
 Source('mysql.cc')
diff -r 221013f9fd2f -r be7f03723412 src/base/statistics.cc
--- a/src/base/statistics.ccThu May 12 11:19:32 2011 -0700
+++ b/src/base/statistics.ccThu May 12 11:19:35 2011 -0700
@@ -433,66 +433,18 @@
 return root ? root->str() : "";
 }
 
-void
-enable()
-{
-typedef list::iterator iter_t;
-
-iter_t i, end = statsList().end();
-for (i = statsList().begin(); i != end; ++i) {
-Info *info = *i;
-assert(info);
-if (!info->check() || !info->baseCheck())
-panic("stat check failed for '%s' %d\n", info->name, info->id);
-}
-
-off_t j = 0;
-for (i = statsList().begin(); i != end; ++i) {
-Info *info = *i;
-if (!(info->flags & display))
-info->name = "__Stat" + to_string(j++);
-}
-
-statsList().sort(Info::less);
-
-for (i = statsList().begin(); i != end; ++i) {
-Info *info = *i;
-info->enable();
-}
-}
-
-void
-prepare()
-{
-list::iterator i = statsList().begin();
-list::iterator end = statsList().end();
-while (i != end) {
-Info *info = *i;
-info->prepare();
-++i;
-}
-}
-
 CallbackQueue resetQueue;
 
 void
-reset()
-{
-list::iterator i = statsList().begin();
-list::iterator end = statsList().end();
-while (i != end) {
-Info *info = *i;
-info->reset();
-++i;
-}
-
-resetQueue.process();
-}
-
-void
 registerResetCallback(Callback *cb)
 {
 resetQueue.add(cb);
 }
 
 } // namespace Stats
+
+void
+debugDumpStats()
+{
+Stats::dump();
+}
diff -r 221013f9fd2f -r be7f03723412 src/base/statistics.hh
--- a/src/base/statistics.hhThu May 12 11:19:32 2011 -0700
+++ b/src/base/statistics.hhThu May 12 11:19:35 2011 -0700
@@ -60,8 +60,8 @@
 #include 
 
 #include "base/stats/info.hh"
+#include "base/stats/output.hh"
 #include "base/stats/types.hh"
-#include "base/stats/visit.hh"
 #include "base/cast.hh"
 #include "base/cprintf.hh"
 #include "base/intmath.hh"
@@ -90,7 +90,7 @@
 void prepare() { s.prepare(); }
 void reset() { s.reset(); }
 void
-visit(Visit &visitor)
+visit(Output &visitor)
 {
 visitor.visit(*static_cast(this));
 }
@@ -738,7 +738,7 @@
 void reset() { }
 bool zero() const { return value() == 0; }
 
-void visit(Visit &visitor) { visitor.visit(*this); }
+void visit(Output &visitor) { visitor.visit(*this); }
 };
 
 template 
@@ -2933,28 +2933,10 @@
 return NodePtr(new SumNode >(val));
 }
 
-/**
- * Enable the statistics package.  Before the statistics package is
- * enabled, all statistics must be created and initialized and once
- * the package is enabled, no more statistics can be created.
- */
-void enable();
-
-/**
- * Prepare all stats for data access.  This must be done before
- * dumping and serialization.
- */
-void prepare();
-
-/**
- * Dump all statistics data to the registered outputs
- */
+/** Dump all statistics data to the registered outputs */
 void dump();
-
-/**
- * Reset all statistics to the base state
- */
 void reset();
+
 /**
  * Register a callback that should be called whenever statistics are
  * reset
diff -r 221013f9fd2f -r be7f03723412 src/base/stats/info.hh
--- a/src/base/stats/info.hhThu May 12 11:19:32 2011 -0700
+++ b/src/base/stats/info.hhThu May 12 11:19:35 2011 -0700
@@ -62,7 +62,7 @@
 const FlagsType __reserved =init | display;
 
 struct StorageParams;
-struct Visit;
+struct Outp

[m5-dev] changeset in m5: stats: better expose statistics to python.

[Nathan Binkert]

changeset 221013f9fd2f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=221013f9fd2f
description:
stats: better expose statistics to python.
Build a python list and dict of all stats and expose flags properly.

diffstat:

 src/python/SConscript   |2 +-
 src/python/m5/stats.py  |   66 
 src/python/m5/stats/__init__.py |  110 
 src/python/swig/stats.i |   48 +
 4 files changed, 159 insertions(+), 67 deletions(-)

diffs (271 lines):

diff -r 44f8c2507d85 -r 221013f9fd2f src/python/SConscript
--- a/src/python/SConscript Mon May 09 16:34:11 2011 -0400
+++ b/src/python/SConscript Thu May 12 11:19:32 2011 -0700
@@ -46,10 +46,10 @@
 PySource('m5', 'm5/params.py')
 PySource('m5', 'm5/proxy.py')
 PySource('m5', 'm5/simulate.py')
-PySource('m5', 'm5/stats.py')
 PySource('m5', 'm5/ticks.py')
 PySource('m5', 'm5/trace.py')
 PySource('m5.objects', 'm5/objects/__init__.py')
+PySource('m5.stats', 'm5/stats/__init__.py')
 PySource('m5.util', 'm5/util/__init__.py')
 PySource('m5.util', 'm5/util/attrdict.py')
 PySource('m5.util', 'm5/util/code_formatter.py')
diff -r 44f8c2507d85 -r 221013f9fd2f src/python/m5/stats.py
--- a/src/python/m5/stats.pyMon May 09 16:34:11 2011 -0400
+++ /dev/null   Thu Jan 01 00:00:00 1970 +
@@ -1,66 +0,0 @@
-# Copyright (c) 2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-
-import internal
-
-from internal.stats import schedStatEvent as schedEvent
-from objects import Root
-
-def initText(filename, desc=True):
-internal.stats.initText(filename, desc)
-
-def initMySQL(host, database, user='', passwd='', project='test', name='test',
-  sample='0'):
-if not user:
-import getpass
-user = getpass.getuser()
-
-internal.stats.initMySQL(host, database, user, passwd, project, name,
- sample)
-
-def initSimStats():
-internal.stats.initSimStats()
-
-def enable():
-internal.stats.enable()
-
-def dump():
-# Currently prepare happens in the dump, but we should maybe move
-# that out.
-
-#internal.stats.prepare()
-internal.stats.dump()
-
-def reset():
-# call reset stats on all SimObjects
-root = Root.getInstance()
-if root:
-for obj in root.descendants(): obj.resetStats()
-
-# call any other registered stats reset callbacks
-internal.stats.reset()
diff -r 44f8c2507d85 -r 221013f9fd2f src/python/m5/stats/__init__.py
--- /dev/null   Thu Jan 01 00:00:00 1970 +
+++ b/src/python/m5/stats/__init__.py   Thu May 12 11:19:32 2011 -0700
@@ -0,0 +1,110 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# Copyright (c) 2010 The Hewlett-Packard Development Company
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notic

Re: [m5-dev] Review Request: stats: better expose statistics to python.

[Nathan Binkert]

> On 2011-05-10 15:19:06, Ali Saidi wrote:
> > src/python/m5/stats/__init__.py, line 29
> > <http://reviews.m5sim.org/r/689/diff/1/?file=12548#file12548line29>
> >
> > Please add a this file does comment... e.g. This file provides 
> > accessors to all the m5 stats or something..

Actually, this file isn't new.  It's the result of a rename.  I'll try to add 
documentation nearer the end of all of these changes.


- Nathan


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/689/#review1221
-------


On 2011-05-10 06:08:21, Nathan Binkert wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/689/
> ---
> 
> (Updated 2011-05-10 06:08:21)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> stats: better expose statistics to python.
> Build a python list and dict of all stats and expose flags properly.
> 
> 
> Diffs
> -
> 
>   src/python/SConscript 44f8c2507d85 
>   src/python/m5/stats.py 44f8c2507d85 
>   src/python/m5/stats/__init__.py PRE-CREATION 
>   src/python/swig/stats.i 44f8c2507d85 
> 
> Diff: http://reviews.m5sim.org/r/689/diff
> 
> 
> Testing
> ---
> 
> quick regressions pass (though most recently run with review 690 and 691)
> 
> 
> Thanks,
> 
> Nathan
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: stats: better expose statistics to python.

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/689/#review1228
---



src/python/m5/stats/__init__.py
<http://reviews.m5sim.org/r/689/#comment1694>

Actually, this is fixed in the subsequent diff.  This code is already in 
the tree and was just part of the rename from stats.py to stats/__init__.py


- Nathan


On 2011-05-10 06:08:21, Nathan Binkert wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/689/
> ---
> 
> (Updated 2011-05-10 06:08:21)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> stats: better expose statistics to python.
> Build a python list and dict of all stats and expose flags properly.
> 
> 
> Diffs
> -
> 
>   src/python/SConscript 44f8c2507d85 
>   src/python/m5/stats.py 44f8c2507d85 
>   src/python/m5/stats/__init__.py PRE-CREATION 
>   src/python/swig/stats.i 44f8c2507d85 
> 
> Diff: http://reviews.m5sim.org/r/689/diff
> 
> 
> Testing
> ---
> 
> quick regressions pass (though most recently run with review 690 and 691)
> 
> 
> Thanks,
> 
> Nathan
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: stats: better expose statistics to python.

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/689/#review1227
---



src/python/m5/stats/__init__.py
<http://reviews.m5sim.org/r/689/#comment1692>

yeah, yeah.



src/python/m5/stats/__init__.py
<http://reviews.m5sim.org/r/689/#comment1693>

good point.


- Nathan


On 2011-05-10 06:08:21, Nathan Binkert wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/689/
> ---
> 
> (Updated 2011-05-10 06:08:21)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> stats: better expose statistics to python.
> Build a python list and dict of all stats and expose flags properly.
> 
> 
> Diffs
> -
> 
>   src/python/SConscript 44f8c2507d85 
>   src/python/m5/stats.py 44f8c2507d85 
>   src/python/m5/stats/__init__.py PRE-CREATION 
>   src/python/swig/stats.i 44f8c2507d85 
> 
> Diff: http://reviews.m5sim.org/r/689/diff
> 
> 
> Testing
> ---
> 
> quick regressions pass (though most recently run with review 690 and 691)
> 
> 
> Thanks,
> 
> Nathan
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: stats: move code that loops over all stats into python

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/690/#review1226
---


I guess I should have said something, but there are several more diffs to come 
down the road.  I just wanted to get some out of the way now.  By the end, 
there will be no output code in C++ at all.


src/python/m5/stats/__init__.py
<http://reviews.m5sim.org/r/690/#comment1691>

If you have a periodic dumping of stats because of an event and you get a 
dumpstats from an m5op or from kill -USR1, you don't want to dump twice in the 
same cycle because stuff just doesn't work well.


- Nathan


On 2011-05-10 06:08:36, Nathan Binkert wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/690/
> ---
> 
> (Updated 2011-05-10 06:08:36)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> stats: move code that loops over all stats into python
> 
> 
> Diffs
> -
> 
>   src/base/SConscript 44f8c2507d85 
>   src/base/statistics.hh 44f8c2507d85 
>   src/base/statistics.cc 44f8c2507d85 
>   src/base/stats/info.hh 44f8c2507d85 
>   src/base/stats/mysql.hh 44f8c2507d85 
>   src/base/stats/mysql.cc 44f8c2507d85 
>   src/base/stats/output.hh 44f8c2507d85 
>   src/base/stats/output.cc 44f8c2507d85 
>   src/base/stats/text.hh 44f8c2507d85 
>   src/base/stats/text.cc 44f8c2507d85 
>   src/base/stats/visit.hh 44f8c2507d85 
>   src/base/stats/visit.cc 44f8c2507d85 
>   src/python/m5/simulate.py 44f8c2507d85 
>   src/python/m5/stats/__init__.py PRE-CREATION 
>   src/python/swig/stats.i 44f8c2507d85 
> 
> Diff: http://reviews.m5sim.org/r/690/diff
> 
> 
> Testing
> ---
> 
> quick regressions pass (though most recently run with review 689 and 691)
> 
> 
> Thanks,
> 
> Nathan
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] Review Request: stats: delete mysql support

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/691/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

stats: delete mysql support

We can add it back within python in some future change.


Diffs
-

  SConstruct 44f8c2507d85 
  src/base/SConscript 44f8c2507d85 
  src/base/mysql.hh 44f8c2507d85 
  src/base/mysql.cc 44f8c2507d85 
  src/base/stats/mysql.hh 44f8c2507d85 
  src/base/stats/mysql.cc 44f8c2507d85 
  src/base/stats/mysql_run.hh 44f8c2507d85 
  src/python/m5/stats/__init__.py PRE-CREATION 
  src/python/swig/stats.i 44f8c2507d85 

Diff: http://reviews.m5sim.org/r/691/diff


Testing
---

quick regressions pass (though most recently run with review 689 and 690)


Thanks,

Nathan

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] Review Request: stats: move code that loops over all stats into python

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/690/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

stats: move code that loops over all stats into python


Diffs
-

  src/base/SConscript 44f8c2507d85 
  src/base/statistics.hh 44f8c2507d85 
  src/base/statistics.cc 44f8c2507d85 
  src/base/stats/info.hh 44f8c2507d85 
  src/base/stats/mysql.hh 44f8c2507d85 
  src/base/stats/mysql.cc 44f8c2507d85 
  src/base/stats/output.hh 44f8c2507d85 
  src/base/stats/output.cc 44f8c2507d85 
  src/base/stats/text.hh 44f8c2507d85 
  src/base/stats/text.cc 44f8c2507d85 
  src/base/stats/visit.hh 44f8c2507d85 
  src/base/stats/visit.cc 44f8c2507d85 
  src/python/m5/simulate.py 44f8c2507d85 
  src/python/m5/stats/__init__.py PRE-CREATION 
  src/python/swig/stats.i 44f8c2507d85 

Diff: http://reviews.m5sim.org/r/690/diff


Testing
---

quick regressions pass (though most recently run with review 689 and 691)


Thanks,

Nathan

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] Review Request: stats: better expose statistics to python.

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/689/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

stats: better expose statistics to python.
Build a python list and dict of all stats and expose flags properly.


Diffs
-

  src/python/SConscript 44f8c2507d85 
  src/python/m5/stats.py 44f8c2507d85 
  src/python/m5/stats/__init__.py PRE-CREATION 
  src/python/swig/stats.i 44f8c2507d85 

Diff: http://reviews.m5sim.org/r/689/diff


Testing
---

quick regressions pass (though most recently run with review 690 and 691)


Thanks,

Nathan

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] changeset in m5: work around gcc 4.5 warning

[Nathan Binkert]

changeset 44f8c2507d85 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=44f8c2507d85
description:
work around gcc 4.5 warning

diffstat:

 src/cpu/inorder/resource_pool.cc |  4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diffs (21 lines):

diff -r db269e704d07 -r 44f8c2507d85 src/cpu/inorder/resource_pool.cc
--- a/src/cpu/inorder/resource_pool.cc  Sat May 07 17:43:30 2011 -0400
+++ b/src/cpu/inorder/resource_pool.cc  Mon May 09 16:34:11 2011 -0400
@@ -260,7 +260,7 @@
 
 Tick when = cpu->nextCycle(curTick() + cpu->ticks(delay));
 
-switch (e_type)
+switch ((int)e_type)
 {
   case InOrderCPU::ActivateThread:
 {
@@ -505,7 +505,7 @@
 void
 ResourcePool::ResPoolEvent::process()
 {
-switch (eventType)
+switch ((int)eventType)
 {
   case InOrderCPU::ActivateThread:
 resPool->activateAll(tid);
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] gem5 Tutorial @ ISCA 2011

[nathan binkert]

Call for Participation: ISCA 2011 Tutorial
gem5: A Multiple-ISA Full System Simulator with Detailed Memory Modeling
Sunday, June 5, 2011
http://www.gem5.org

The gem5 simulator is a merger of two of the computer architecture
community’s most popular, open source simulators: M5 and GEMS. The
best features of each simulator have been combined to provide an
infrastructure capable of simulating multiple ISAs, CPU models, memory
system components, cache coherence protocols and interconnection
networks. The gem5 simulation team invites users, developers, and all
other interested parties to participate in a tutorial that will
highlight the key aspects of the gem5 simulator.

The first half of this full-day tutorial will be an organized
presentation focusing on gem5 usage and capabilities. The second half
is intended to be more free form where we will answer audience
questions on specific usage, including modification of the simulator
to enable new features.

Topics to be discussed include:
- Multiple ISA support (e.g. ARM and x86)
- Detailed and simple CPU models including “execute-in-execute”
in-order and out-of-order pipeline models.
- Cache coherence protocols using SLICC
- Interconnection network modeling (Crossbar, Mesh, etc.)
- Checkpointing and fast-forwarding

We look forward to your participation in the gem5 tutorial and hope
that by the end of the tutorial you’ll be able to utilize the gem5
infrastructure in your future research.

Thanks,
The gem5 Simulation Team
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] [m5-users] Tracing does not work

[nathan binkert]

> I was thinking og doing it since Nate is not around. I'll do it soon.


>> instance, "trace-flags", and "trace-file" are still accepted, but they
>> don't
>> do anything now.  They should be eliminated from the message.  We're also
>> missing the equivalent of "trace-start" and "trace-file".  Do you mind
>> cleaning that up?

Are you sure that trace-file doesn't work?  I've basically renamed
--trace-help to --debug-help, so the former can be removed.  Also I've
renamed --trace-flags to --debug-flags, so that one can be removed
too.  (I intended to, I just screwed up.)  The purpose of renaming
trace flags to debug flags is that the flags themselves can be used
for a lot more than tracing (I'm starting to use them to insert
debugging breakpoints, they're used for exec trace which is really a
different tracing facility, they can be used for whatever) and it
seemed odd to have two different classes of flags (though we could do
that if we wanted to).

The only error that I know of right now is that --trace-help and
--trace-flags still exist and silently act when they shouldn't.  I'm
compiling right now, but things are slow on my laptop.  I'll test out
--trace-file, but I'm not sure why that would have changed at all.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: Cache: fix vector stats in classic cache to have matching lengths

[nathan binkert]

>> I don't know.  Is it?  I haven't opened a file in dev/ in years.  Does this 
>> involve changing all device models?  Changing something in a port interface? 
>>  Which?  I don't know.  I have not looked into it at all.  I tried to page 
>> out as little of what I was doing to fix this vector length matching thing, 
>> and I don't want to delay getting back to other crap that I have to do.  I 
>> consider this a difference between "should" and "must".   I consider the 
>> vector thing a "must" - I introduced the code that broke it and it currently 
>> causes problems.  This is definitely a "should", IMHO.
>>
>> I've got to get to Crossfit now, I'm going to be late!
> It should be a one line change to DmaPort::dmaAction() in io_device.cc.

What's the status of this diff?

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/678/#review1206
---

Ship it!


looks reasonable to me.  I assume that it works.

- Nathan


On 2011-05-04 18:42:30, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/678/
> ---
> 
> (Updated 2011-05-04 18:42:30)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.
> 
> Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
> ExecKernel are set by default when Exec is specified.  Use minus
> sign with ExecUser or ExecKernel to remove user or kernel tracing
> respectively.
> 
> 
> Diffs
> -
> 
>   src/arch/alpha/utility.hh 5a9a639ce16f 
>   src/arch/alpha/utility.cc 5a9a639ce16f 
>   src/arch/arm/utility.hh 5a9a639ce16f 
>   src/arch/mips/utility.hh 5a9a639ce16f 
>   src/arch/power/utility.hh 5a9a639ce16f 
>   src/arch/sparc/utility.hh 5a9a639ce16f 
>   src/arch/x86/utility.hh 5a9a639ce16f 
>   src/cpu/SConscript 5a9a639ce16f 
>   src/cpu/exetrace.cc 5a9a639ce16f 
> 
> Diff: http://reviews.m5sim.org/r/678/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] changeset in m5: debug: fix help output

[nathan binkert]

> So --trace-start, --trace-ignore, and --trace-file didn't get renamed?

Yeah, the idea was that there was more to the flags than tracing, but
the start, ignore, and file things were specific to tracing.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: ruby-stats: support for dump_stats instruction

[Nathan Binkert]

> On 2011-05-03 17:45:41, Brad Beckmann wrote:
> > Can we change the name of Time in base/time.hh instead of Time in Ruby?  
> > Right now this patch touches 50+ Ruby files and a bunch of lines within 
> > those files just to change Time to RTime.  It seems that far fewer changes 
> > would be required to change the name of base/time.hh's version of Time.
> 
> Nathan Binkert wrote:
> While I wouldn't be opposed to changing the time in base/time.hh if we 
> needed both, but don't we need to move ruby away from its own version of Time 
> anyway?  Shouldn't we be using Tick?
> 
> Also, we've generally never shied away from changes that can be done with 
> a one line sed/perl script.
> 
> Gabe Black wrote:
> I was about to say something along these lines. This would be a good 
> chance to consolidate Ruby and M5 systems a little. It might be a good idea 
> to do the simple find/replace change on its own so the non-simple 
> non-find/replace stuff doesn't get lost as noise. I don't have deep feelings 
> one way or the other, though.
> 
> Korey Sewell wrote:
> This should be two diffs: 1 for rename and 1 for stat code. But since 
> they are related to getting dumpstats working I combined them both for the 
> sake of discussion.
> 
> Time isnt equivalent Tick or I would've happily made that change :). 
> 
> Time is really the Ruby Cycle count so if you change it to Tick then all 
> over the place you would have to convert to cycles when making comparisons 
> for request latencies and various parameters in Ruby. In the interim, maybe 
> changing Time to Cycle would work.
> 
> Alternatively, you could change Time to Tick, and then force all the 
> latencies throughout Ruby to be expressed in Ticks. This would have the nice 
> effect of setting the latencies for Caches and memory objects with a real 
> time (e.g. "1ns") instead of relative time (e.g. 1 cycle).
> 
> Brad Beckmann wrote:
> Eventually, we absolutely need Ruby to move away from its own version of 
> time and we are in the process to do just that.  Right now both Nilay and 
> Somayeh are working on two pretty complicated and substantial changes that 
> are on that path.  In particular, once Ruby supports functional accesses, 
> then it can supply data directly to the CPUs.  Once Ruby data is functional 
> memory, we can create cache warmup traces that include valid data.  Once we 
> have a cache warmup methodology that includes data and works more seamlessly 
> with unserialization, we can remove the Ruby event queue APIs.  Once we do 
> that, we can get rid of Ruby's notion of time...As you can tell, this is a 
> long process and we still have a ways to go, but that is the plan.
> 
> My hesitation with this patch is that it seems premature and it adds more 
> rebase/merging work for those of us who have other patches under development 
> that really need touch these same files and lines.
> 
> Overall, does this patch need to be checked in right now?  For instance, 
> do we need it to move Ruby stats to M5 stats or will moving to M5 stats 
> negate having to make this change?
>

Seems like a reasonable objection.  I've generally had success with running the 
search/replace routines directly on my patches when this sort of change 
happens, but if that doesn't work, then I wouldn't be opposed to renaming Time 
to TimeOfDay or RealTime or something like that.  I would like to make sure 
that Korey can continue working.


- Nathan


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/675/#review1195
---


On 2011-05-03 11:20:58, Korey Sewell wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/675/
> ---
> 
> (Updated 2011-05-03 11:20:58)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> ruby-stats: support for dump_stats instruction
> ***
> NOTE: The core changes for this diff are in Profiler.cc/hh, 
> stat_control.hh/cc, and pseudo_inst.cc
> 
> This is a first pass toward getting dump-stats functionality to work 
> "cleanly" for Ruby. As is, the patch works, but there needs to be discussion 
> over:
> - Changing Ruby typedef "Time" to "RTime" because it conflicts with the Time 
> class defined in base/time.hh (The majority of files

Re: [m5-dev] changeset in m5: debug: fix help output

[nathan binkert]

I'm not sure.  Something must have happened when I rebased my patch
queue.  I believe all that needs to happen is delete the 4 lines
relating to --trace-help and --trace-flags.  Can someone delete them
for me and make sure that M5 still runs correctly?  I'm out of town
and I'm really not going to be able to do anything for a couple of
days.

  Nate

> Note that running "m5 --help" still has the old names:
>
> Trace Options
> -
> --trace-help            Print help on trace flags
> --trace-flags=FLAG[,FLAG]
>                        Sets the flags for tracing (-FLAG disables a flag)
> --trace-start=TIME      Start tracing at TIME (must be in ticks)
> --trace-file=FILE       Sets the output file for tracing [Default: cout]
> --trace-ignore=EXPR     Ignore EXPR sim objects
>
>
> On Wed, May 4, 2011 at 7:07 AM, Nathan Binkert  wrote:
>
>> changeset 5a9a639ce16f in /z/repo/m5
>> details: http://repo.m5sim.org/m5?cmd=changeset;node=5a9a639ce16f
>> description:
>>        debug: fix help output
>>
>> diffstat:
>>
>>  src/base/debug.cc      |   4 ++--
>>  src/base/debug.hh      |  16 
>>  src/python/m5/debug.py |  28 
>>  3 files changed, 30 insertions(+), 18 deletions(-)
>>
>> diffs (115 lines):
>>
>> diff -r 3f49ed206f46 -r 5a9a639ce16f src/base/debug.cc
>> --- a/src/base/debug.cc Mon May 02 12:40:32 2011 -0700
>> +++ b/src/base/debug.cc Wed May 04 10:08:08 2011 -0400
>> @@ -101,14 +101,14 @@
>>  CompoundFlag::enable()
>>  {
>>     SimpleFlag::enable();
>> -    for_each(flags.begin(), flags.end(), mem_fun(&Flag::enable));
>> +    for_each(_kids.begin(), _kids.end(), mem_fun(&Flag::enable));
>>  }
>>
>>  void
>>  CompoundFlag::disable()
>>  {
>>     SimpleFlag::disable();
>> -    for_each(flags.begin(), flags.end(), mem_fun(&Flag::disable));
>> +    for_each(_kids.begin(), _kids.end(), mem_fun(&Flag::disable));
>>  }
>>
>>  struct AllFlags : public Flag
>> diff -r 3f49ed206f46 -r 5a9a639ce16f src/base/debug.hh
>> --- a/src/base/debug.hh Mon May 02 12:40:32 2011 -0700
>> +++ b/src/base/debug.hh Wed May 04 10:08:08 2011 -0400
>> @@ -44,6 +44,7 @@
>>   protected:
>>     const char *_name;
>>     const char *_desc;
>> +    std::vector _kids;
>>
>>   public:
>>     Flag(const char *name, const char *desc);
>> @@ -51,6 +52,7 @@
>>
>>     std::string name() const { return _name; }
>>     std::string desc() const { return _desc; }
>> +    std::vector kids() { return _kids; }
>>
>>     virtual void enable() = 0;
>>     virtual void disable() = 0;
>> @@ -77,7 +79,12 @@
>>  class CompoundFlag : public SimpleFlag
>>  {
>>   protected:
>> -    std::vector flags;
>> +    void
>> +    addFlag(Flag &f)
>> +    {
>> +        if (&f != NULL)
>> +            _kids.push_back(&f);
>> +    }
>>
>>   public:
>>     CompoundFlag(const char *name, const char *desc,
>> @@ -99,13 +106,6 @@
>>         addFlag(f15); addFlag(f16); addFlag(f17); addFlag(f18);
>> addFlag(f19);
>>     }
>>
>> -    void
>> -    addFlag(Flag &f)
>> -    {
>> -        if (&f != NULL)
>> -            flags.push_back(&f);
>> -    }
>> -
>>     void enable();
>>     void disable();
>>  };
>> diff -r 3f49ed206f46 -r 5a9a639ce16f src/python/m5/debug.py
>> --- a/src/python/m5/debug.py    Mon May 02 12:40:32 2011 -0700
>> +++ b/src/python/m5/debug.py    Wed May 04 10:08:08 2011 -0400
>> @@ -26,24 +26,36 @@
>>  #
>>  # Authors: Nathan Binkert
>>
>> +from UserDict import DictMixin
>> +
>>  import internal
>>
>> +from internal.debug import SimpleFlag, CompoundFlag
>>  from internal.debug import schedBreakCycle, setRemoteGDBPort
>> +from m5.util import printList
>>
>>  def help():
>>     print "Base Flags:"
>> -    for flag in flags.basic:
>> -        print "    %s: %s" % (flag, flags.descriptions[flag])
>> +    for name in sorted(flags):
>> +        if name == 'All':
>> +            continue
>> +        flag = flags[name]
>> +        children = [c for c in flag.kids() ]
>> +        if not children:
>> +            print "    %s: %s" % (name, flag.desc())
>>     print
>>     print "Compound Flags:"
>> -    for flag in flags.compound:
>> -        if flag == 'All':
>> +    for name in sorted(fla

[m5-dev] changeset in m5: debug: fix help output

[Nathan Binkert]

changeset 5a9a639ce16f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5a9a639ce16f
description:
debug: fix help output

diffstat:

 src/base/debug.cc  |   4 ++--
 src/base/debug.hh  |  16 
 src/python/m5/debug.py |  28 
 3 files changed, 30 insertions(+), 18 deletions(-)

diffs (115 lines):

diff -r 3f49ed206f46 -r 5a9a639ce16f src/base/debug.cc
--- a/src/base/debug.cc Mon May 02 12:40:32 2011 -0700
+++ b/src/base/debug.cc Wed May 04 10:08:08 2011 -0400
@@ -101,14 +101,14 @@
 CompoundFlag::enable()
 {
 SimpleFlag::enable();
-for_each(flags.begin(), flags.end(), mem_fun(&Flag::enable));
+for_each(_kids.begin(), _kids.end(), mem_fun(&Flag::enable));
 }
 
 void
 CompoundFlag::disable()
 {
 SimpleFlag::disable();
-for_each(flags.begin(), flags.end(), mem_fun(&Flag::disable));
+for_each(_kids.begin(), _kids.end(), mem_fun(&Flag::disable));
 }
 
 struct AllFlags : public Flag
diff -r 3f49ed206f46 -r 5a9a639ce16f src/base/debug.hh
--- a/src/base/debug.hh Mon May 02 12:40:32 2011 -0700
+++ b/src/base/debug.hh Wed May 04 10:08:08 2011 -0400
@@ -44,6 +44,7 @@
   protected:
 const char *_name;
 const char *_desc;
+std::vector _kids;
 
   public:
 Flag(const char *name, const char *desc);
@@ -51,6 +52,7 @@
 
 std::string name() const { return _name; }
 std::string desc() const { return _desc; }
+std::vector kids() { return _kids; }
 
 virtual void enable() = 0;
 virtual void disable() = 0;
@@ -77,7 +79,12 @@
 class CompoundFlag : public SimpleFlag
 {
   protected:
-std::vector flags;
+void
+addFlag(Flag &f)
+{
+if (&f != NULL)
+_kids.push_back(&f);
+}
 
   public:
 CompoundFlag(const char *name, const char *desc,
@@ -99,13 +106,6 @@
 addFlag(f15); addFlag(f16); addFlag(f17); addFlag(f18); addFlag(f19);
 }
 
-void
-addFlag(Flag &f)
-{
-if (&f != NULL)
-flags.push_back(&f);
-}
-
 void enable();
 void disable();
 };
diff -r 3f49ed206f46 -r 5a9a639ce16f src/python/m5/debug.py
--- a/src/python/m5/debug.pyMon May 02 12:40:32 2011 -0700
+++ b/src/python/m5/debug.pyWed May 04 10:08:08 2011 -0400
@@ -26,24 +26,36 @@
 #
 # Authors: Nathan Binkert
 
+from UserDict import DictMixin
+
 import internal
 
+from internal.debug import SimpleFlag, CompoundFlag
 from internal.debug import schedBreakCycle, setRemoteGDBPort
+from m5.util import printList
 
 def help():
 print "Base Flags:"
-for flag in flags.basic:
-print "%s: %s" % (flag, flags.descriptions[flag])
+for name in sorted(flags):
+if name == 'All':
+continue
+flag = flags[name]
+children = [c for c in flag.kids() ]
+if not children:
+print "%s: %s" % (name, flag.desc())
 print
 print "Compound Flags:"
-for flag in flags.compound:
-if flag == 'All':
+for name in sorted(flags):
+if name == 'All':
 continue
-print "%s: %s" % (flag, flags.descriptions[flag])
-util.printList(flags.compoundMap[flag], indent=8)
-print
+flag = flags[name]
+children = [c for c in flag.kids() ]
+if children:
+print "%s: %s" % (name, flag.desc())
+printList([ c.name() for c in children ], indent=8)
+print
 
-class AllFlags(object):
+class AllFlags(DictMixin):
 def __init__(self):
 self._version = -1
 self._dict = {}
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: ruby-stats: support for dump_stats instruction

[Nathan Binkert]

> On 2011-05-03 17:45:41, Brad Beckmann wrote:
> > Can we change the name of Time in base/time.hh instead of Time in Ruby?  
> > Right now this patch touches 50+ Ruby files and a bunch of lines within 
> > those files just to change Time to RTime.  It seems that far fewer changes 
> > would be required to change the name of base/time.hh's version of Time.

While I wouldn't be opposed to changing the time in base/time.hh if we needed 
both, but don't we need to move ruby away from its own version of Time anyway?  
Shouldn't we be using Tick?

Also, we've generally never shied away from changes that can be done with a one 
line sed/perl script.


- Nathan


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/675/#review1195
---


On 2011-05-03 11:20:58, Korey Sewell wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/675/
> ---
> 
> (Updated 2011-05-03 11:20:58)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> ruby-stats: support for dump_stats instruction
> ***
> NOTE: The core changes for this diff are in Profiler.cc/hh, 
> stat_control.hh/cc, and pseudo_inst.cc
> 
> This is a first pass toward getting dump-stats functionality to work 
> "cleanly" for Ruby. As is, the patch works, but there needs to be discussion 
> over:
> - Changing Ruby typedef "Time" to "RTime" because it conflicts with the Time 
> class defined in base/time.hh (The majority of files are renames)... Is there 
> a better name than "RTime"?
> 
> - Where is the right place for this RubyStatEvent code? I hesitated to do any 
> real cosmetic changes because of what impending stat changes might do. I have 
> two thoughts:
> (1) If Ruby Stats will be registered like old M5 stats, then this code would 
> nicely fold into the old "statEvent" code in sim_control.cc. "Fold into" 
> maybe too strong of a phrase even, as most of it should just naturally "work".
> (2) If Ruby Stats are not registered, then maybe placing this code into the 
> RubySystem class. I realized late that the "Profiler" and "Network" have two 
> different stats that they track so the RubySystem would be the right place 
> along with calling the namespace "RubyStats".
> 
> 
> Diffs
> -
> 
>   SConstruct 3f49ed206f46 
>   src/cpu/testers/rubytest/RubyTester.hh 3f49ed206f46 
>   src/cpu/testers/rubytest/RubyTester.cc 3f49ed206f46 
>   src/mem/ruby/buffers/MessageBuffer.hh 3f49ed206f46 
>   src/mem/ruby/buffers/MessageBuffer.cc 3f49ed206f46 
>   src/mem/ruby/buffers/MessageBufferNode.hh 3f49ed206f46 
>   src/mem/ruby/common/Consumer.hh 3f49ed206f46 
>   src/mem/ruby/common/Global.hh 3f49ed206f46 
>   src/mem/ruby/common/TypeDefines.hh 3f49ed206f46 
>   src/mem/ruby/eventqueue/RubyEventQueue.hh 3f49ed206f46 
>   src/mem/ruby/eventqueue/RubyEventQueue.cc 3f49ed206f46 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh 3f49ed206f46 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 3f49ed206f46 
>   src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh 3f49ed206f46 
>   src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh 
> 3f49ed206f46 
>   src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh 3f49ed206f46 
>   src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh 3f49ed206f46 
>   src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh 
> 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/InVcState.cc 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh 
> 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc 
> 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh 3f49ed206f46 
>   src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.cc 3f49ed206f46 
>   src/mem/ruby/

Re: [m5-dev] Review Request: SConstruct: automatically update .hg/hgrc with style hooks

[Nathan Binkert]

> On 2011-05-02 12:51:56, Nathan Binkert wrote:
> > SConstruct, line 247
> > <http://reviews.m5sim.org/r/668/diff/1/?file=12211#file12211line247>
> >
> > Should we prompt the user for permission?  That way the user would at 
> > least know that something happened.
> 
> Steve Reinhardt wrote:
> I doubt most people care.  How many would really say no?  Most people 
> just want things to be automatic.
> 
> If they really do care they can always edit it out later (the comments 
> will let them know where the hooks came from).
>
> 
> Nathan Binkert wrote:
> I agree that nobody would say no, but most people also would never notice 
> that it had happened because the message would just fly by if there was no 
> prompt.  I guess that you're arguing that that would be a good thing :)
> 
> Gabe Black wrote:
> Changing config files behind peoples back is a really bad idea in my 
> opinion. I know I've stopped using entire distros (Suse) because they mucked 
> with config files behind my back and perpetually broke my system. My configs 
> are mine, and the minimal level of respect for that would be if we asked 
> permission before we let ourselves in. I think leaving well enough alone and 
> having the user go in and fix it themselves is actually the best approach.

This isn't a config file in your homedir, it's the config file in the M5 repo 
and it will only be changed if you don't have it set up right, so it's not all 
that bad.  I have the same leaning that you do, so I think I'd rather see a 
prompt for the user, but I don't feel that strongly about it.


- Nathan


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/668/#review1173
---


On 2011-05-02 12:34:56, Steve Reinhardt wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/668/
> -------
> 
> (Updated 2011-05-02 12:34:56)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> SConstruct: automatically update .hg/hgrc with style hooks
> 
> Seems easier than pestering people about it.
> Note also that path is now absolute, so you don't get errors
> when invoking hg from subdirectories.
> 
> 
> Diffs
> -
> 
>   SConstruct 66a3187a6714 
> 
> Diff: http://reviews.m5sim.org/r/668/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Steve
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: SConstruct: automatically update .hg/hgrc with style hooks

[Nathan Binkert]

> On 2011-05-02 12:51:56, Nathan Binkert wrote:
> > SConstruct, line 243
> > <http://reviews.m5sim.org/r/668/diff/1/?file=12211#file12211line243>
> >
> > I know you didn't change this, but should we check for both hooks?  (I 
> > added the pre-qrefresh one a while ago)
> 
> Steve Reinhardt wrote:
> Doesn't make me much difference... seems pretty unlikely anyone would 
> have one and not the other though.
> 
> Nathan Binkert wrote:
> Old repos may not have the new hook. (I only found out that we could use 
> pre-qrefresh a few months ago).
> 
> Steve Reinhardt wrote:
> The only hitch is that if we just append the hook text when only one is 
> missing we'll get duplicates, like this:
> 
> [extensions]
> style = /home/stever/hg/amd/m5/util/style.py
> 
> [hooks]
> pretxncommit.style = python:style.check_style
> 
> # The following lines were automatically added by m5/SConstruct
> # to provide the m5 style-checking hooks
> [extensions]
> style = /home/stever/hg/amd/m5/util/style.py
> 
> [hooks]
> pretxncommit.style = python:style.check_style
> pre-qrefresh.style = python:style.check_style
> # End of SConstruct additions
> 
> I don't think it's a problem (my very limited testing hasn't shown 
> anything), but it is a little weird.  If you think this is OK, then I'll go 
> ahead and test for both.  Otherwise I could test for both, print a warning if 
> they're only half there, and only do the auto append if they're both missing.
>

I thought about that.  It's probably fine.  A warning is probably worth it.  
Though, again, if you don't stop output for the user, nobody will notice it, so 
maybe it doesn't matter


- Nathan


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/668/#review1173
---


On 2011-05-02 12:34:56, Steve Reinhardt wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/668/
> ---
> 
> (Updated 2011-05-02 12:34:56)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> SConstruct: automatically update .hg/hgrc with style hooks
> 
> Seems easier than pestering people about it.
> Note also that path is now absolute, so you don't get errors
> when invoking hg from subdirectories.
> 
> 
> Diffs
> -
> 
>   SConstruct 66a3187a6714 
> 
> Diff: http://reviews.m5sim.org/r/668/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Steve
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: Debug: Add a function to cause the simulator to create a checkpoint from GDB.

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/672/#review1182
---

Ship it!


Looks fine.


src/sim/debug.hh
<http://reviews.m5sim.org/r/672/#comment1620>

Maybe put a note that the definition is in eventq.cc?


- Nathan


On 2011-05-02 15:42:09, Ali Saidi wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/672/
> ---
> 
> (Updated 2011-05-02 15:42:09)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> Debug: Add a function to cause the simulator to create a checkpoint from GDB.
> 
> 
> Diffs
> -
> 
>   src/sim/debug.hh 3f49ed206f46 
>   src/sim/debug.cc 3f49ed206f46 
> 
> Diff: http://reviews.m5sim.org/r/672/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Ali
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: SConstruct: automatically update .hg/hgrc with style hooks

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/668/#review1176
---

Ship it!


Whether you decide to change this or not, it's a good idea.

- Nathan


On 2011-05-02 12:34:56, Steve Reinhardt wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/668/
> ---
> 
> (Updated 2011-05-02 12:34:56)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> SConstruct: automatically update .hg/hgrc with style hooks
> 
> Seems easier than pestering people about it.
> Note also that path is now absolute, so you don't get errors
> when invoking hg from subdirectories.
> 
> 
> Diffs
> -
> 
>   SConstruct 66a3187a6714 
> 
> Diff: http://reviews.m5sim.org/r/668/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Steve
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: SConstruct: automatically update .hg/hgrc with style hooks

[Nathan Binkert]

> On 2011-05-02 12:51:56, Nathan Binkert wrote:
> > SConstruct, line 247
> > <http://reviews.m5sim.org/r/668/diff/1/?file=12211#file12211line247>
> >
> > Should we prompt the user for permission?  That way the user would at 
> > least know that something happened.
> 
> Steve Reinhardt wrote:
> I doubt most people care.  How many would really say no?  Most people 
> just want things to be automatic.
> 
> If they really do care they can always edit it out later (the comments 
> will let them know where the hooks came from).
>

I agree that nobody would say no, but most people also would never notice that 
it had happened because the message would just fly by if there was no prompt.  
I guess that you're arguing that that would be a good thing :)


> On 2011-05-02 12:51:56, Nathan Binkert wrote:
> > SConstruct, line 243
> > <http://reviews.m5sim.org/r/668/diff/1/?file=12211#file12211line243>
> >
> > I know you didn't change this, but should we check for both hooks?  (I 
> > added the pre-qrefresh one a while ago)
> 
> Steve Reinhardt wrote:
> Doesn't make me much difference... seems pretty unlikely anyone would 
> have one and not the other though.

Old repos may not have the new hook. (I only found out that we could use 
pre-qrefresh a few months ago).


- Nathan


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/668/#review1173
---


On 2011-05-02 12:34:56, Steve Reinhardt wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/668/
> -----------
> 
> (Updated 2011-05-02 12:34:56)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> SConstruct: automatically update .hg/hgrc with style hooks
> 
> Seems easier than pestering people about it.
> Note also that path is now absolute, so you don't get errors
> when invoking hg from subdirectories.
> 
> 
> Diffs
> -
> 
>   SConstruct 66a3187a6714 
> 
> Diff: http://reviews.m5sim.org/r/668/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Steve
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: SConstruct: automatically update .hg/hgrc with style hooks

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/668/#review1173
---



SConstruct
<http://reviews.m5sim.org/r/668/#comment1609>

I know you didn't change this, but should we check for both hooks?  (I 
added the pre-qrefresh one a while ago)



SConstruct
<http://reviews.m5sim.org/r/668/#comment1610>

Should we prompt the user for permission?  That way the user would at least 
know that something happened.


- Nathan


On 2011-05-02 12:34:56, Steve Reinhardt wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/668/
> ---
> 
> (Updated 2011-05-02 12:34:56)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> SConstruct: automatically update .hg/hgrc with style hooks
> 
> Seems easier than pestering people about it.
> Note also that path is now absolute, so you don't get errors
> when invoking hg from subdirectories.
> 
> 
> Diffs
> -
> 
>   SConstruct 66a3187a6714 
> 
> Diff: http://reviews.m5sim.org/r/668/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Steve
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: debug: fix help output

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/666/#review1171
---



src/base/debug.hh
<http://reviews.m5sim.org/r/666/#comment1607>

I want a reference in the constructor for sure because I don't want people 
to pass NULL or anything like that.  Since I want a reference in the 
constructor, it's easier to have a reference here.


- Nathan


On 2011-04-28 16:48:33, Nathan Binkert wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/666/
> ---
> 
> (Updated 2011-04-28 16:48:33)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> debug: fix help output
> 
> 
> Diffs
> -
> 
>   src/base/debug.hh b02bca5aed04 
>   src/base/debug.cc b02bca5aed04 
>   src/python/m5/debug.py b02bca5aed04 
> 
> Diff: http://reviews.m5sim.org/r/666/diff
> 
> 
> Testing
> ---
> 
> --debug-help works for me now
> 
> 
> Thanks,
> 
> Nathan
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] Review Request: debug: fix help output

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/666/
---

Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
---

debug: fix help output


Diffs
-

  src/base/debug.hh b02bca5aed04 
  src/base/debug.cc b02bca5aed04 
  src/python/m5/debug.py b02bca5aed04 

Diff: http://reviews.m5sim.org/r/666/diff


Testing
---

--debug-help works for me now


Thanks,

Nathan

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] changeset in m5: event: fix PythonEvent

[Nathan Binkert]

changeset f2ec56fd42c0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f2ec56fd42c0
description:
event: fix PythonEvent
order of %includes since they matter for this case

diffstat:

 src/python/swig/event.i |  4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diffs (15 lines):

diff -r b02bca5aed04 -r f2ec56fd42c0 src/python/swig/event.i
--- a/src/python/swig/event.i   Mon Apr 25 14:18:08 2011 -0700
+++ b/src/python/swig/event.i   Thu Apr 28 16:45:17 2011 -0700
@@ -77,8 +77,10 @@
 %import "sim/serialize.hh"
 
 %include "base/types.hh"
+%include "sim/eventq.hh"
+
+// This must follow eventq.hh
 %include "python/swig/pyevent.hh"
-%include "sim/eventq.hh"
 
 struct CountedDrainEvent : public Event
 {
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] Code Reviewing

[nathan binkert]

Hi Everyone,

We don't have an official policy on code reviews, but I think we're
being a bit pedantic with them.  While I definitely want us to err on
the side of having code review is the author has any doubt, I think it
is completely unnecessary to have reviews on things like changing
comments and text in strings.  Similarly, obvious bug fixes (though
this is one of those subjective things that the author has to
consider) need not be reviewed.

What do you all think?  What is our policy?  Am I crazy? Should we
review everything?

   Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Trace not working

[nathan binkert]

Oh, one thing you need to do now is add

#include "debug/FlagCheck.hh"

To your .cc file.  I should probably write some new documentation
about that.  Basically, we're generating a header per flag now.  One
huge benefit of this is that you don't have to recompile the entire
system after you add a trace flag because they're localized.

  Nate

On Mon, Apr 25, 2011 at 9:38 PM, Beckmann, Brad  wrote:
> Maybe I'm doing something stupid here, but on a  clean checkout, the 
> following short patch encounters the subsequent compiler error:
>
> diff --git a/src/mem/SConscript b/src/mem/SConscript
> --- a/src/mem/SConscript
> +++ b/src/mem/SConscript
> @@ -57,6 +57,7 @@
>  TraceFlag('BusAddrRanges')
>  TraceFlag('BusBridge')
>  TraceFlag('LLSC')
> +TraceFlag('FlagCheck')
>  TraceFlag('MMU')
>  TraceFlag('MemoryAccess')
>
> diff --git a/src/mem/port.cc b/src/mem/port.cc
> --- a/src/mem/port.cc
> +++ b/src/mem/port.cc
> @@ -106,6 +106,7 @@
>  Port::setPeer(Port *port)
>  {
>     DPRINTF(Config, "setting peer to %s\n", port->name());
> +    DPRINTF(FlagCheck, "check setting peer to %s\n", port->name());
>
>     peer = port;
>  }
>
>
> Error:
>
> scons: Building targets ...
>  [     CXX] X86_SE_MOESI_hammer/mem/port.cc -> .do
> build/X86_SE_MOESI_hammer/mem/port.cc: In member function 'virtual void 
> Port::setPeer(Port*)':
> build/X86_SE_MOESI_hammer/mem/port.cc:109: error: 'FlagCheck' is not a member 
> of 'Debug'
>  [    SWIG] X86_SE_MOESI_hammer/python/m5/internal/vptype_IntLink.i -> 
> _wrap.cc, .py
>  [    SWIG] X86_SE_MOESI_hammer/python/m5/internal/vptype_AddrRange.i -> 
> _wrap.cc, .py
> scons: *** [build/X86_SE_MOESI_hammer/mem/port.do] Error 1
>  [    SWIG] X86_SE_MOESI_hammer/python/m5/internal/vptype_Process.i -> 
> _wrap.cc, .py
> scons: building terminated because of errors.
>
> Brad
>
>
>> -Original Message-
>> From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On
>> Behalf Of nathan binkert
>> Sent: Monday, April 25, 2011 5:29 PM
>> To: M5 Developer List
>> Subject: Re: [m5-dev] Trace not working
>>
>> > However, I am confused as well on how to add a new
>> TraceFlag/DebugFlag.  It seems that all the previous flags are still
>> specified using the "TraceFlag()" function, but I can't seem to be able
>> to specify a new one.    Also to be consistent, should we change the
>> name of the TraceFlag function to DebugFlag?
>>
>> You should still use the TraceFlag function in SCons.  Are you sure
>> this doesn't work?  And yes, I should probably rename TraceFlag to
>> DebugFlag.
>>
>>   Nate
>> ___
>> m5-dev mailing list
>> m5-dev@m5sim.org
>> http://m5sim.org/mailman/listinfo/m5-dev
>
>
> ___
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
>
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Trace not working

[nathan binkert]

> However, I am confused as well on how to add a new TraceFlag/DebugFlag.  It 
> seems that all the previous flags are still specified using the "TraceFlag()" 
> function, but I can't seem to be able to specify a new one.    Also to be 
> consistent, should we change the name of the TraceFlag function to DebugFlag?

You should still use the TraceFlag function in SCons.  Are you sure
this doesn't work?  And yes, I should probably rename TraceFlag to
DebugFlag.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] changeset in m5: stats: update 20.parser o3 now that it works. ...

[Nathan Binkert]

changeset b02bca5aed04 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b02bca5aed04
description:
stats: update 20.parser o3 now that it works.  realview-o3 works too.

diffstat:

 tests/long/10.linux-boot/ref/arm/linux/realview-o3/status |2 +-
 tests/long/20.parser/ref/x86/linux/o3-timing/simerr   |3 +-
 tests/long/20.parser/ref/x86/linux/o3-timing/simout   |9 +-
 tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt|  475 ++
 4 files changed, 483 insertions(+), 6 deletions(-)

diffs (truncated from 518 to 300 lines):

diff -r ea37585785ab -r b02bca5aed04 
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status Mon Apr 25 
12:23:37 2011 -0500
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status Mon Apr 25 
14:18:08 2011 -0700
@@ -1,1 +1,1 @@
-build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED!
+build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 passed.
diff -r ea37585785ab -r b02bca5aed04 
tests/long/20.parser/ref/x86/linux/o3-timing/simerr
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simerr   Mon Apr 25 
12:23:37 2011 -0500
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simerr   Mon Apr 25 
14:18:08 2011 -0700
@@ -4,5 +4,4 @@
 For more information see: http://www.m5sim.org/warn/437d5238
 warn: instruction 'fldcw_Mw' unimplemented
 For more information see: http://www.m5sim.org/warn/437d5238
-m5.fast: build/X86_SE/arch/x86/emulenv.cc:49: void 
X86ISA::EmulEnv::doModRM(const X86ISA::ExtMachInst&): Assertion 
`machInst.modRM.mod != 3' failed.
-Program aborted at cycle 582313255000
+hack: be nice to actually delete the event here
diff -r ea37585785ab -r b02bca5aed04 
tests/long/20.parser/ref/x86/linux/o3-timing/simout
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout   Mon Apr 25 
12:23:37 2011 -0500
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout   Mon Apr 25 
14:18:08 2011 -0700
@@ -5,9 +5,9 @@
 All Rights Reserved
 
 
-M5 compiled Apr 21 2011 13:30:37
-M5 started Apr 21 2011 13:42:45
-M5 executing on maize
+M5 compiled Apr 23 2011 16:56:34
+M5 started Apr 23 2011 17:38:09
+M5 executing on victors
 command line: build/X86_SE/m5.fast -d 
build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py 
build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
 Global frequency set at 1 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -71,3 +71,6 @@
   we like to eat at restaurants , usually on weekends 
   what did John say he thought you should do 
   about 2 million people attended 
+  the five best costumes got prizes 
+No errors!
+Exiting @ tick 584102039000 because target called exit()
diff -r ea37585785ab -r b02bca5aed04 
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
--- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txtMon Apr 25 
12:23:37 2011 -0500
+++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txtMon Apr 25 
14:18:08 2011 -0700
@@ -0,0 +1,475 @@
+
+-- Begin Simulation Statistics --
+host_inst_rate  88955   # 
Simulator instruction rate (inst/s)
+host_mem_usage 246024   # 
Number of bytes of host memory used
+host_seconds 17188.43   # 
Real time elapsed on the host
+host_tick_rate   33982273   # 
Simulator tick rate (ticks/s)
+sim_freq 1   # 
Frequency of simulated ticks
+sim_insts  1528988756   # 
Number of instructions simulated
+sim_seconds  0.584102   # 
Number of seconds simulated
+sim_ticks584102039000   # 
Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0   # 
Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits218742072   # 
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 237579384   # 
Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect   0   # 
Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect   16731555   # 
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted  252612908   # 
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups252612908   # 
Number of BP lookups
+system.cpu.BPredUnit.usedRAS0   # 
Number of times the RAS was used to get a target.
+system.c

Re: [m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

[nathan binkert]

> All that said, if you want to take the script and move things into
> m5.util, or rework it so it uses m5.util, or make it handle paths
> better, or whatever, I certainly won't try to stop you. I think my
> version is an improvement over the original, but it's definitely not
> perfect.

I didn't mean the whole thing.  I meant stuff that might be generally useful.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

[nathan binkert]

>
> I looked at it and it is similar, but it's different enough that they can't 
> be interchanged. My functions all allow passing a string in as standard input 
> and return the error code, but readCommand doesn't. I could extend it to take 
> an input string, but it's not clear how to return the output and the error 
> code without changing all the call sites and complicating all the code that's 
> working fine now without it. readCommand doesn't allow printing the command 
> before it's run so I'd have to add a wrapper to handle that, and it doesn't 
> handle adding 'sudo'. I think tying in readCommand would actually make 
> everything bigger and more complicated because it's not quite what I need and 
> I'd have to add a bunch of wrappers. Also wrapping all the possible 
> variations of Popen people might need (not that that's what you're saying, 
> but it heads that way) is probably also counter productive because at that 
> point you might as well just use Popen directly.
>
>
I totally agree.  If it doesn't work, it doesn't work.  Is it something
reusable that should go in m5.util?

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: network: convert links & switches to first class C++ SimObjects

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/653/#review1149
---


The main question I have about this code is, should new Ruby code adhere to the 
style guide instead of the old Ruby style?  Eventually, we should try migrate 
Ruby to the style guide, no?  (I'm mostly talking about variable naming here)

- Nathan


On 2011-04-22 15:16:58, Brad Beckmann wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/653/
> ---
> 
> (Updated 2011-04-22 15:16:58)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> network: convert links & switches to first class C++ SimObjects
> 
> This patch converts links and switches from second class simobjects that were
> virtually ignored by the networks (both simple and Garnet) to first class
> simobjects that directly correspond to c++ ojbects manipulated by the
> topology and network classes.  This is especially true for Garnet, where the
> links and switches directly correspond to specific C++ objects.
> 
> By making this change, many aspects of the Topology class were simplified.
> 
> 
> Diffs
> -
> 
>   configs/ruby/MESI_CMP_directory.py 914389024c33 
>   configs/ruby/MI_example.py 914389024c33 
>   configs/ruby/MOESI_CMP_directory.py 914389024c33 
>   configs/ruby/MOESI_CMP_token.py 914389024c33 
>   configs/ruby/MOESI_hammer.py 914389024c33 
>   configs/ruby/Network_test.py 914389024c33 
>   configs/ruby/Ruby.py 914389024c33 
>   src/mem/protocol/RubySlicc_Exports.sm 914389024c33 
>   src/mem/ruby/network/BasicLink.hh PRE-CREATION 
>   src/mem/ruby/network/BasicLink.cc PRE-CREATION 
>   src/mem/ruby/network/BasicLink.py PRE-CREATION 
>   src/mem/ruby/network/BasicRouter.hh PRE-CREATION 
>   src/mem/ruby/network/BasicRouter.cc PRE-CREATION 
>   src/mem/ruby/network/BasicRouter.py PRE-CREATION 
>   src/mem/ruby/network/Network.hh 914389024c33 
>   src/mem/ruby/network/Network.py 914389024c33 
>   src/mem/ruby/network/SConscript 914389024c33 
>   src/mem/ruby/network/Topology.hh PRE-CREATION 
>   src/mem/ruby/network/Topology.cc PRE-CREATION 
>   src/mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh 914389024c33 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh PRE-CREATION 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc PRE-CREATION 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py PRE-CREATION 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh 914389024c33 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 914389024c33 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py PRE-CREATION 
>   src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh 914389024c33 
>   src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc 914389024c33 
>   src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh 914389024c33 
>   src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc 914389024c33 
>   src/mem/ruby/network/garnet/fixed-pipeline/SConscript 914389024c33 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh PRE-CREATION 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc PRE-CREATION 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py PRE-CREATION 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh 914389024c33 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc 914389024c33 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py PRE-CREATION 
>   src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh 914389024c33 
>   src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc 914389024c33 
>   src/mem/ruby/network/garnet/flexible-pipeline/Router.hh 914389024c33 
>   src/mem/ruby/network/garnet/flexible-pipeline/Router.cc 914389024c33 
>   src/mem/ruby/network/garnet/flexible-pipeline/SConscript 914389024c33 
>   src/mem/ruby/network/orion/NetworkPower.cc 914389024c33 
>   src/mem/ruby/network/simple/SimpleNetwork.hh 914389024c33 
>   src/mem/ruby/network/simple/SimpleNetwork.cc 914389024c33 
>   src/mem/ruby/network/topologies/Crossbar.py 914389024c33 
>   src/mem/ruby/network/topologies/Mesh.py 914389024c33 
>   src/mem/ruby/network/topologies/MeshDirCorners.py 914389024c33 
>   src/mem/ruby/slicc_interface/AbstractController.hh 914389024c33 
>   src/mem/ruby/slicc_interface/Controller.py 914389024c33 
> 
> Diff: http://reviews.m5sim.org/r/653/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brad
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: ruby: moved topology to the top network directory

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/651/#review1147
---


Did you use hg mv?  The diff doesn't seem to include that information, though 
maybe reviewboard whacks that.

- Nathan


On 2011-04-22 15:16:44, Brad Beckmann wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/651/
> ---
> 
> (Updated 2011-04-22 15:16:44)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> ruby: moved topology to the top network directory
> 
> Moved the Topology class to the top network directory because it is shared by
> both the simple and Garnet networks.
> 
> 
> Diffs
> -
> 
>   src/mem/ruby/network/Network.cc 914389024c33 
>   src/mem/ruby/network/SConscript 914389024c33 
>   src/mem/ruby/network/Topology.hh PRE-CREATION 
>   src/mem/ruby/network/Topology.cc PRE-CREATION 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 914389024c33 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc 914389024c33 
>   src/mem/ruby/network/simple/SConscript 914389024c33 
>   src/mem/ruby/network/simple/SimpleNetwork.cc 914389024c33 
>   src/mem/ruby/network/simple/Topology.hh 914389024c33 
>   src/mem/ruby/network/simple/Topology.cc 914389024c33 
> 
> Diff: http://reviews.m5sim.org/r/651/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brad
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: ruby: moved topology to the top network directory

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/651/#review1146
---


Did you use hg mv?  The diff doesn't seem to include that information, though 
maybe reviewboard whacks that.

- Nathan


On 2011-04-22 15:16:44, Brad Beckmann wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/651/
> ---
> 
> (Updated 2011-04-22 15:16:44)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> ruby: moved topology to the top network directory
> 
> Moved the Topology class to the top network directory because it is shared by
> both the simple and Garnet networks.
> 
> 
> Diffs
> -
> 
>   src/mem/ruby/network/Network.cc 914389024c33 
>   src/mem/ruby/network/SConscript 914389024c33 
>   src/mem/ruby/network/Topology.hh PRE-CREATION 
>   src/mem/ruby/network/Topology.cc PRE-CREATION 
>   src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc 914389024c33 
>   src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc 914389024c33 
>   src/mem/ruby/network/simple/SConscript 914389024c33 
>   src/mem/ruby/network/simple/SimpleNetwork.cc 914389024c33 
>   src/mem/ruby/network/simple/Topology.hh 914389024c33 
>   src/mem/ruby/network/simple/Topology.cc 914389024c33 
> 
> Diff: http://reviews.m5sim.org/r/651/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Brad
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] changeset in m5: tests: updates for stat name change

[Nathan Binkert]

changeset 6e368a935ac0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6e368a935ac0
description:
tests: updates for stat name change

diffstat:

 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout |  
  4 +-
 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt  |  
 28 +-
 tests/long/00.gzip/ref/arm/linux/o3-timing/simout   |  
  4 +-
 tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt|  
 28 +-
 tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |  
  4 +-
 tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt  |  
 28 +-
 tests/long/00.gzip/ref/x86/linux/o3-timing/simout   |  
  4 +-
 tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt|  
 28 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |  
  5 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt  |  
 48 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout  |  
  5 +-
 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt   |  
 28 +-
 tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout   |  
  4 +-
 tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt|  
 28 +-
 tests/long/10.mcf/ref/arm/linux/o3-timing/simout|  
  4 +-
 tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt |  
 28 +-
 tests/long/10.mcf/ref/x86/linux/o3-timing/simout|  
  4 +-
 tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt |  
 28 +-
 tests/long/20.parser/ref/arm/linux/o3-timing/simout |  
  4 +-
 tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt  |  
 28 +-
 tests/long/20.parser/ref/x86/linux/o3-timing/simerr |  
  3 +-
 tests/long/20.parser/ref/x86/linux/o3-timing/simout |  
  7 +-
 tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt  |  
473 --
 tests/long/30.eon/ref/alpha/tru64/o3-timing/simout  |  
  4 +-
 tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt   |  
 28 +-
 tests/long/30.eon/ref/arm/linux/o3-timing/simout|  
  4 +-
 tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt |  
 28 +-
 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout  |  
  4 +-
 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt   |  
 28 +-
 tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout|  
  4 +-
 tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt |  
 28 +-
 tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout   |  
  4 +-
 tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt|  
 28 +-
 tests/long/50.vortex/ref/arm/linux/o3-timing/simout |  
  4 +-
 tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt  |  
 28 +-
 tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout|  
  4 +-
 tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt |  
 28 +-
 tests/long/60.bzip2/ref/arm/linux/o3-timing/simout  |  
  4 +-
 tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt   |  
 28 +-
 tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout|  
  4 +-
 tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt |  
 28 +-
 tests/long/70.twolf/ref/arm/linux/o3-timing/simout  |  
  4 +-
 tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt   |  
 28 +-
 tests/long/70.twolf/ref/x86/linux/o3-timing/simout  |  
  4 +-
 tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt   |  
 28 +-
 tests/quick/00.hello/ref/alpha/linux/o3-timing/simout   |  
  4 +-
 tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt|  
 28 +-
 tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout   |  
  4 +-
 tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt|  
 28 +-
 tests/quick/00.hello/ref/arm/linux/o3-timing/simout |  
  4 +-
 tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt  |  
 28 +-
 tests/quick/00.hello/ref/mips/linux/o3-timing/simout|  
  4 +-
 tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt |  
 28 +-
 tests/quick/00.hello/ref/power/linux/o3-timing/simerr   |  
  2 +-
 tests/quick/00.hello/ref/power/linux/o3-timing/simout 

[m5-dev] changeset in m5: stats: ensure that stat names are valid

[Nathan Binkert]

changeset d69720504203 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d69720504203
description:
stats: ensure that stat names are valid

diffstat:

 src/base/statistics.cc |  34 ++
 1 files changed, 34 insertions(+), 0 deletions(-)

diffs (47 lines):

diff -r acf4b902c02e -r d69720504203 src/base/statistics.cc
--- a/src/base/statistics.ccWed Apr 20 19:07:45 2011 -0700
+++ b/src/base/statistics.ccWed Apr 20 19:07:46 2011 -0700
@@ -138,9 +138,43 @@
 {
 }
 
+bool
+validateStatName(const string &name)
+{
+if (name.empty())
+return false;
+
+vector vec;
+tokenize(vec, name, '.');
+vector::const_iterator item = vec.begin();
+while (item != vec.end()) {
+if (item->empty())
+return false;
+
+string::const_iterator c = item->begin();
+
+// The first character is different
+if (!isalpha(*c) && *c != '_')
+return false;
+
+// The rest of the characters have different rules.
+while (++c != item->end()) {
+if (!isalnum(*c) && *c != '_')
+return false;
+}
+
+++item;
+}
+
+return true;
+}
+
 void
 Info::setName(const string &name)
 {
+if (!validateStatName(name))
+panic("invalid stat name '%s'", name);
+
 pair p =
 nameMap().insert(make_pair(name, this));
 
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] changeset in m5: stats: one more name violation

[Nathan Binkert]

changeset acf4b902c02e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=acf4b902c02e
description:
stats: one more name violation

diffstat:

 src/cpu/o3/lsq_unit_impl.hh |  2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diffs (12 lines):

diff -r 914389024c33 -r acf4b902c02e src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh   Wed Apr 20 19:07:44 2011 -0700
+++ b/src/cpu/o3/lsq_unit_impl.hh   Wed Apr 20 19:07:45 2011 -0700
@@ -188,7 +188,7 @@
 if (Impl::MaxThreads == 1) {
 return iewStage->name() + ".lsq";
 } else {
-return iewStage->name() + ".lsq.thread." + to_string(lsqID);
+return iewStage->name() + ".lsq.thread" + to_string(lsqID);
 }
 }
 
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: Cache: fix vector stats in classic cache to have matching lengths

[Nathan Binkert]

> On 2011-04-22 18:51:32, Nathan Binkert wrote:
> > src/mem/cache/base.hh, line 503
> > <http://reviews.m5sim.org/r/654/diff/1/?file=11759#file11759line503>
> >
> > This can pretty easily be done with a template:
> > 
> > template 
> > void
> > incThreadVectorStat(PacketPtr pkt, STAT &stat)
> > {
> > }
> > 
> > I'm pretty sure that you could even do this:
> > 
> > template 
> > STAT::Proxy &
> > getThreadVectorStat(PacketPtr pkt, STAT &stat[])
> > {
> > if (pkt->req->hasContextId()) {
> > return stat[pkt->cmdToIndex()][pkt->req->contextId() % 
> > _numSharingContexts];
> > } else {
> > assert(pkt->req->contextId() == -1);
> > assert(FULL_SYSTEM);
> > return stat[pkt->cmdToIndex()][_numSharingContexts];
> > }
> > 
> > And do this:
> > getThreadVectorStat(pkt, misses)++;
> > getThreadVectorStat(pkt, misses) += 1;
> > 
> > Actually, it may just be cleaner to have a function that returns the 
> > index.  Then you don't need all of the template mubmo jumbo.
> 
> Lisa Hsu wrote:
> I did a single pass of trying to pass a reference of a stat to a 
> function.  When it didn't work immediately, I went to macro.  I have enough 
> other stuff to do that that level of beauty for a dying memory model is kinda 
> irrelevant to me right now, and it's not clear to me that it's more beautiful 
> either.
> 
> Something returning the index seems messier to me.  Then you'd need:
> 
> int index = getIndex(pkt);
> statName[pkt->cmdToIndex()][index]++;  
> 
> everywhere, instead of:
> 
> incrementStat(pkt, statName);
> 
> or
> 
> incrementStat(pkt->req->contextId(), statName);
> 
> I think the latter two are prettier than the first.  I might switch to 
> the 3rd before I push.

It's not that macros are ugly, but they tend to be much more difficult to debug 
and make code more brittle.  A macro in a .cc file is one thing, but in a 
header, we should really try to avoid it if at all possible.  And just because 
some day, hypothetically in the future, code may be thrown away doesn't mean 
that we should allow it to become more brittle.


> On 2011-04-22 18:51:32, Nathan Binkert wrote:
> > src/mem/cache/base.hh, line 505
> > <http://reviews.m5sim.org/r/654/diff/1/?file=11759#file11759line505>
> >
> > _numSharingContexts has the + 1 in it for devices.  Is that a problem?  
> > Seems like you need a parameter to know that.
> 
> Lisa Hsu wrote:
> I have a comment in the patch that explains it.  It has nothing to do 
> with devices and everything to do with switching CPUs.  if you have switch 
> CPUs, you will have N*2 contexts and throughout the course of simulation 
> you'll mostly care about [N, 2N).  Hence, the mod.

I understand that, but if _numSharingContexts includes the device (which it 
does if your in FULL_SYSTEM mode, when you do the mod, you'll be off by one.  
(At least I'm pretty sure that's true.)  Think of this.  We have 2 cores and 1 
device.  if you're talking to the last core which is core 3 (2N - 1) Then 
you're going to do 3 % 3 and you're going index to zero instead of one.


> On 2011-04-22 18:51:32, Nathan Binkert wrote:
> > src/mem/cache/base.hh, line 507
> > <http://reviews.m5sim.org/r/654/diff/1/?file=11759#file11759line507>
> >
> > Maybe you can use a constant to indicate the -1 is a device.  Also, 
> > let's make sure that you initialize to something other than -1.
> 
> Lisa Hsu wrote:
> Why?  Devices never set the id so this assertion confirms that the id is 
> never set.  It's more that if it has come from a device, something had better 
> not have set the contextId, otherwise something is broken.

It would be ideal if we always explicitly set the ID on every request.  That 
way we don't get random wrong answers.


> On 2011-04-22 18:51:32, Nathan Binkert wrote:
> > src/mem/cache/cache_impl.hh, line 1021
> > <http://reviews.m5sim.org/r/654/diff/1/?file=11762#file11762line1021>
> >
> > Is it not possible to figure out which thread caused the wb?
> 
> Lisa Hsu wrote:
> this isn't recording who caused the wb, this is recording who is getting 
> written back.

Right, but if we don't know the tid, is there something tid related that we do 
know that could be interestin

Re: [m5-dev] Review Request: Cache: fix vector stats in classic cache to have matching lengths

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/654/#review1142
---



src/mem/cache/base.hh
<http://reviews.m5sim.org/r/654/#comment1564>

This can pretty easily be done with a template:

template 
void
incThreadVectorStat(PacketPtr pkt, STAT &stat)
{
}

I'm pretty sure that you could even do this:

template 
STAT::Proxy &
getThreadVectorStat(PacketPtr pkt, STAT &stat[])
{
if (pkt->req->hasContextId()) {
return stat[pkt->cmdToIndex()][pkt->req->contextId() % 
_numSharingContexts];
} else {
assert(pkt->req->contextId() == -1);
assert(FULL_SYSTEM);
return stat[pkt->cmdToIndex()][_numSharingContexts];
}

And do this:
getThreadVectorStat(pkt, misses)++;
getThreadVectorStat(pkt, misses) += 1;

Actually, it may just be cleaner to have a function that returns the index. 
 Then you don't need all of the template mubmo jumbo.



src/mem/cache/base.hh
<http://reviews.m5sim.org/r/654/#comment1566>

_numSharingContexts has the + 1 in it for devices.  Is that a problem?  
Seems like you need a parameter to know that.



src/mem/cache/base.hh
<http://reviews.m5sim.org/r/654/#comment1565>

Maybe you can use a constant to indicate the -1 is a device.  Also, let's 
make sure that you initialize to something other than -1.



src/mem/cache/cache_impl.hh
<http://reviews.m5sim.org/r/654/#comment1568>

This makes me think that some sort of index function is the right way to go.



src/mem/cache/cache_impl.hh
<http://reviews.m5sim.org/r/654/#comment1569>

Is it not possible to figure out which thread caused the wb?



src/mem/cache/cache_impl.hh
<http://reviews.m5sim.org/r/654/#comment1567>

I think we should force context IDs to be set even by devices.



src/mem/cache/cache_impl.hh
<http://reviews.m5sim.org/r/654/#comment1570>

Index function.


- Nathan


On 2011-04-22 17:16:05, Lisa Hsu wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/654/
> ---
> 
> (Updated 2011-04-22 17:16:05)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> Cache: fix vector stats in classic cache to have matching lengths
> 
> 
> Diffs
> -
> 
>   configs/common/CacheConfig.py 914389024c33 
>   src/cpu/base.cc 914389024c33 
>   src/mem/cache/BaseCache.py 914389024c33 
>   src/mem/cache/base.hh 914389024c33 
>   src/mem/cache/base.cc 914389024c33 
>   src/mem/cache/blk.hh 914389024c33 
>   src/mem/cache/cache_impl.hh 914389024c33 
>   src/mem/cache/tags/base.cc 914389024c33 
>   src/mem/cache/tags/lru.cc 914389024c33 
> 
> Diff: http://reviews.m5sim.org/r/654/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Lisa
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] what scons can do

[nathan binkert]

> Is that 1%/99% a statement of a clean build for m5.fast?  I think the much 
> more common case is you edit one .cc file and rebuild.  In that situation, it 
> sure seems like a lot more than 1% of the time is spent by scons regenerating 
> and reanalyzing SLICC files.
>
> Whatever it may be, it sure would be great if we could speed things up.  I'm 
> happy to help however I can.

On a clean build maybe it's 1/10.  It doesn't regenerate the SLICC
files, it only parses them which only takes half a second (or probably
less).  It's other SCons internal machinery that's so darned slow.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: O3: Tighten memory order violation checking to 16 bytes.

[nathan binkert]

Did this ever get committed?  I'm running into this bug with 20.parser.

  Nate

On Wed, Mar 30, 2011 at 8:46 AM, Ali Saidi  wrote:

>This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/520/
>
> I think the updated patch addresses all of your issues Gabe. I tested it with 
> an opt binary and one problem jumped out in x86 for 20.parser an assert:
> m5.opt: build/X86_SE/arch/x86/emulenv.cc:49: void 
> X86ISA::EmulEnv::doModRM(const X86ISA::ExtMachInst&): Assertion 
> `machInst.modRM.mod != 3' failed.
>
> It looks like the assert shouldn't be there and is hit during some miss 
> speculation.
>
>
> - Ali
>
> On March 30th, 2011, 8:41 a.m., Ali Saidi wrote:
>   Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
> Nathan Binkert.
> By Ali Saidi.
>
> *Updated 2011-03-30 08:41:48*
> Description
>
> O3: Tighten memory order violation checking to 16 bytes.
>
> The comment in the code suggests that the checking granularity should be 16
> bytes, however in reality the shift by 8 is 256 bytes which seems much
> larger than required.
>
>   Diffs
>
>- src/cpu/base_dyn_inst.hh (d54b7775a6b0)
>- src/cpu/o3/O3CPU.py (d54b7775a6b0)
>- src/cpu/o3/lsq_unit.hh (d54b7775a6b0)
>- src/cpu/o3/lsq_unit_impl.hh (d54b7775a6b0)
>
> View Diff <http://reviews.m5sim.org/r/520/diff/>
>
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] what scons can do

[nathan binkert]

> Maybe so... I think there's a subconscious impression that it takes a while
> because there's a phase in the build that takes a noticeable amount of time
> and that's all the output you see.  If in fact that delay is 10% running
> SLICC and 90% scons doing other stuff silently then I agree it's not such a
> big deal.
I think it's more like 1%/99% :)

> One psychological solution would be to reduce the amount of output from
> SLICC, making it a less obvious target for annoyance when you're waiting for
> a build...
I agree.  I'll take a look into it.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] what scons can do

[nathan binkert]

> Making it not work that way would likely be very painful. The parser part is
> finicky (like they all are in any language) and we have lots and lots of
> very intricate code built on top of it in the form of the descriptions
> themselves.
Perhaps we should talk about it on the phone.  Making it so that you
have an AST and then processing the AST should be a pretty easy
operation.  I'm looking at what you have and I don't see why it should
be difficult at all.  That said, the question is, is the AST enough to
generate the files that you want.  I bet it is, or could be with minor
modifications.

I have a fair amount of experience using ply now and I think I can help you out.

BTW: your trick for ##includes is not necessary.  I can improve
grammar.py so that you can do things like #include within the lexer.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] what scons can do

[nathan binkert]

> Are you sure?  Running SLICC every time just to get a (typically unchanging)
> list of files is not exactly instantaneous, and the names of the SLICC
> output files hardly ever change.  What about this approach:
It is pretty fast (and this includes starting the python interpreter)
0.48s user 0.03s system 99% cpu 0.514 total

> 1. store the list of output files
> 2. scons builds a dependence graph based on that stored list
> 3. when the SLICC files change and actually need to be re-parsed, we compare
> the output file list generated as a side effect with the stored list
> 4. if those lists differ, scons blows itself away and starts over
> 5. if not, we can get by without parsing the SLICC files at all in the
> common case where you're rebuilding the binary and none of the SLICC inputs
> have changed
>
> Yes, step 4 is ugly and expensive, but the key is that it should hardly ever
> happen.  "Make the common case fast", and all that.  If we commit the output
> file lists to hg, it wouldn't even need to happen on a clean build.
>
> Just brainstorming...

I think you're pre-optimizing.  How long does the ISA parser actually
take to parse the files?

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] what scons can do

[nathan binkert]

> That doesn't really fit with how the ISA files work. They get broken into an
> AST, but that gets consumed as it goes,
Does it have to be?

> and it has a lot of anonymous python
> in it that just gets executed somehow. I want to move more into the python,
> so the AST will be less and less useful.
Does the AST not contain enough information to know what files are
being generated?  The anonymous python itself creates files?  That
sounds crazy.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] what scons can do

[nathan binkert]

> A mechanism where I can say binary foo needs file bar, and then when I tell
> it to build foo it build's it with bar, and bar doesn't get mixed in to
> other things. I think you're new widget that was like mercurial patch guards
> would help with that, right? You could have a guard for each extra target.
Ah, I see.  I personally wouldn't use any of that.  Don't use Source
or PySource or that sort of thing.  Just set up normal looking
SConscript files with their own targets and such.  The
Source/PySource/etc. stuff is really about building the m5 binary and
dealing with all of the variations that we have.

> I'm not sure how SLICC is structured, but it might be hard to get out file
> information without running the whole description, depending on how the
> multi-file output thing is implemented.
In SLICC, we parse the entire file using the ply grammar and generate
the AST in both phases.  In one phase, you walk the AST simply to
figure out which files will be generated.  In the other, you actually
do the generation.  I'm suggesting that you do that as well, the files
aren't that long and I bet that parsing the ISA desc files and
generating the AST takes a second or so.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] changeset in m5: python: fix another bug from changes to main.py

[Nathan Binkert]

changeset 914389024c33 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=914389024c33
description:
python: fix another bug from changes to main.py

diffstat:

 configs/common/cpu2000.py |  2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diffs (12 lines):

diff -r a9d06c894afe -r 914389024c33 configs/common/cpu2000.py
--- a/configs/common/cpu2000.py Wed Apr 20 18:45:03 2011 -0700
+++ b/configs/common/cpu2000.py Wed Apr 20 19:07:44 2011 -0700
@@ -155,7 +155,7 @@
 cwd = process_args.get('cwd')
 
 if not cwd:
-from m5.main import options
+from m5 import options
 cwd = options.outdir
 process_args['cwd'] = cwd
 if not isdir(cwd):
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] what scons can do

[nathan binkert]

> Anyway, it seems like it would be useful to be able to have multiple
> binaries that can be built by scons, specifically the utility stuff and
> unit tests. That way we could avoid having a hodge podge of small build
> systems which are either isolated or not in not quite the right ways. I
> know some of Nate's recent changes suggested this was going to get
> easier. Could you quickly summarize what that's all about, Nate?
What changes are you thinking of?  I'm not sure that anything I've
done makes this easier or harder.  I think it's just a matter of
creating SConscript files that the SConstruct file sources.

> Also, I was thinking about how to handle the dependencies/generated
> files/custom language issue a little while back, and what I kept coming
> back to were schemes where scons would use a cache of dependency
> information which it would regenerate if any of the input files which
> determined outputs and/or dependencies changed. The problem is that
> scons would need to run once and possibly regenerate its cache, and then
> run again to actually run. Is this sort of multi-pass setup possible
> somehow without major hacks?
I've looked into this in depth and I think that SCons just sucks for
this sort of thing.  I've seen a few different proposals for dealing
with this, but they all seem to suck.  Basically SCons builds the
dependence graph up front and then walks it.  It doesn't seem to be
able to build it on the fly.  (WAF is different in this regard.)  That
said, there are hacks out there to get around this, but I haven't
managed to get them to work and I'm not sure if they're fragile or
not.

> When you run for the first time, scons would see that foo.isa.dep
> doesn't exist. During it's build phase, it would run foo.isa through the
> system and see that it generated foo_exec.cc and bar_exec.cc and put
> that into foo.isa.dep (as actual SConscript type code, or flat data,
> or...). When scons ran the second time, it would read in foo.isa.dep and
> extract the dependencies from it and build that into the graph. It
> wouldn't construct foo.isa.dep again since all its inputs were the same,
> and it would still capture all those dependencies. This time around, the
> larger binary would see that it depended on foo_exec.cc and bar_exec.cc
> and that those depend on foo.isa.dep (as a convenient aggregation point
> of all *.isa files involved). If foo.isa changed later, foo.isa.dep
> would be out of date and have to be regenerated, and then foo_exec.cc
> and bar_exec.cc, and then the main binary.
Running SCons twice in the way you suggest would be FAR slower than
just running SLICC and the ISA parser twice the way we do.  Also,
notice that when SLICC is run twice, the modes are very different.
The first time it is run, it does parse the files, but only to figure
out what the dependencies are.  The second time it runs, it is run in
the mode to actually generate the files.  We parse all files twice
anyway to get the dependency information (scanners parse things like
.cc and .hh files to figure out dependencies with #includes, though
they basically just use regexes to do it).  I think you should do this
with the ISA parser.

> Also related to scons are those .pyc files that end up scattered around
> the source tree. I know I asked about those a long, long time ago, but
> why are they there? Why don't they end up in the build directories?
SCons itself imports the m5 library so it can get access to the
SimObject building stuff and m5.util.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: Util: Replace mkblankimage.sh with the new gem5img.py.

[Nathan Binkert]

> On 2011-04-18 21:20:49, Nathan Binkert wrote:
> > util/gem5img.py, line 51
> > <http://reviews.m5sim.org/r/644/diff/1/?file=11664#file11664line51>
> >
> > I'm not going to make you change it or anything, but this whole class 
> > seems to me to be a bit overkill, no?
> > 
> > __notRoot = None
> > def needSudo():
> > if __notRoot is None:
> > __notRoot = os.geteuid() != 0
> > return __notRoot
> > 
> > BTW: we also have m5.util.Singleton
> 
> Gabe Black wrote:
> Yes and no. This came about because the original script had a warning 
> about using sudo which I wanted to preserve. I made it possible to run only 
> part of the script, and if you run a part that doesn't need sudo (like just 
> creating an appropriately sized file) then the warning might be confusing. I 
> also didn't want the warning to show up multiple times if sudo was used more 
> than once. It's a little clumsy, but I didn't see any obvious alternative 
> that would get the behavior I wanted. Feel free to convince me to drop the 
> warning.

You can add the error message to the code that I pasted above.  I was just 
saying that the singleton was a bit much and just serves to confuse things.  
The _notRoot thing is probably overkill too.  Since this is not performance 
code, no reason not to just check geteuid() each time.

None of this matters much though.


> On 2011-04-18 21:20:49, Nathan Binkert wrote:
> > util/gem5img.py, line 64
> > <http://reviews.m5sim.org/r/644/diff/1/?file=11664#file11664line64>
> >
> > This is pretty similar to m5.util.readCommand which made me think that 
> > it might be nice if we put your utility functions here in m5.util
> 
> Gabe Black wrote:
> Can I use m5.util from an arbitrary python script? If I can that's good 
> to know. Also, how does readCommand work? Does it pass through stdout/stderr 
> or capture it? Depending on the answer it might be an appropriate replacement 
> for this or the subsequent getOutput, but changing only one obscures the 
> similarities between the two functions. If you're advocating adding a new 
> version of readCommand that has the other behavior then that makes sense. I 
> also funnel text into stdin for input, and I think sudo happens to still work 
> because it goes around any redirection I set up.

Yes, you can.  Several scripts do that.  You have to get it into your path 
though.  Check out the style hook.  I suggest just looking at readCommand and 
the examples to see exactly what it does.


> On 2011-04-18 21:20:49, Nathan Binkert wrote:
> > util/gem5img.py, line 106
> > <http://reviews.m5sim.org/r/644/diff/1/?file=11664#file11664line106>
> >
> > Here is where you could suggest that it is in /sbin or /usr/sbin
> 
> Gabe Black wrote:
> I'm not sure what telling them where it might be would accomplish since 
> the script still wouldn't be able to find/use it. I may just not understand 
> what you're getting at.

I'm simply saying that changing the user's path to add other locations to 
search seems sketchy to me.  Perhaps for /usr/sbin and /sbin, it's ok though 
and I'm just being paranoid.


> On 2011-04-18 21:20:49, Nathan Binkert wrote:
> > util/gem5img.py, line 25
> > <http://reviews.m5sim.org/r/644/diff/1/?file=11664#file11664line25>
> >
> > This makes me feel uneasy for a script that you're likely to call using 
> > sudo.  I know it's overly paranoid, but why not just simply give the user a 
> > tip if the program is not found (which you have to deal with anyway.)
> 
> Gabe Black wrote:
> I'm not necessarily advocating doing things this way, but this is what 
> the original script was doing. This script should not be called with sudo 
> since it calls it internally, although I suppose it could. I don't know why, 
> but I think if you use sudo to like the script does, you have to make sure 
> you use an absolute path to the target binary. There were some posts to back 
> that up online and that's also what the original script was doing. To get 
> that path, the script calls "which", and for that to find things that are 
> normally only usable by root it needs to also search in /sbin and /usr/sbin. 
> If a program isn't found the script will complain and die.

I guess I think complain and die is the right thing to do.  I don't like the 
idea of any script screwing with my path.  I guess that's just my paranoia.


- Nathan


---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org

Re: [m5-dev] Error while compiling (changeset 8229)

[nathan binkert]

I say commit it then.

  Nate

> The bug exists in 8246. Following works for me -
>
>
> diff -r a9d06c894afe src/base/stats/mysql.hh
> --- a/src/base/stats/mysql.hh   Wed Apr 20 18:45:03 2011 -0700
> +++ b/src/base/stats/mysql.hh   Thu Apr 21 15:28:29 2011 -0500
> @@ -37,6 +37,7 @@
>  #include 
>
>  #include "base/stats/output.hh"
> +#include "base/types.hh"
>  #include "config/use_mysql.hh"
>
>  namespace MySQL { class Connection; }
>
>
>
> --
> Nilay
> ___
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
>
>
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Review Request: util/regress: make default action a more thorough regression

[Nathan Binkert]

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/649/#review1140
---


I'm going to also send you my code for building.  I'd like to incorporate some 
of the ideas. So I can import regress (which would mean creating build.py or 
something like that) and use it directly in my environment.  (We can do that as 
a separate diff though).


util/regress
<http://reviews.m5sim.org/r/649/#comment1556>

While you're at it you could add the following to the help:

(0 to use total number of cores)



util/regress
<http://reviews.m5sim.org/r/649/#comment1557>

Another common option is --update-ref, can we add that here and pass it 
through?



util/regress
<http://reviews.m5sim.org/r/649/#comment1559>

I have nicer code for this sort of thing.  You can see it in 
src/python/m5/options.py, examples of usage in main.py

Look for action='append' (and notice the necessity of split)



util/regress
<http://reviews.m5sim.org/r/649/#comment1558>

Seems like we should fix this on the SCons side.  Is that difficult?  Also, 
does NOISA have any tests?  Seems like we could have a memory tester for NOISA.


- Nathan


On 2011-04-20 22:42:16, Steve Reinhardt wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/649/
> ---
> 
> (Updated 2011-04-20 22:42:16)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> ---
> 
> util/regress: make default action a more thorough regression
> 
> Changed the --variants option to --test-variants and added a new
> --compile-variants option for variants that are only compiled
> (not tested).  The former still defaults to 'opt' and the latter
> defaults to 'debug,fast'.
> 
> Also changed the behavior when no tests are specified from just
> compiling to running the 'quick' tests.
> 
> As a result, a plain 'util/regress' invocation will now compile
> (but not test) the debug and fast builds, and compile and run the
> quick regressions on the opt build.  This should be the default
> set of tests that are run before committing.  Since the nightly
> regressions use this same script, this will also be the new
> nightly regression behavior.
> 
> Test-only regressions can still be done by setting --compile=''.
> Compile-only regressions can be done by setting --test=''.
> 
> 
> Diffs
> -
> 
>   util/regress a9d06c894afe 
> 
> Diff: http://reviews.m5sim.org/r/649/diff
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Steve
> 
>

___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Introducing...InOrder AlphaFS!

[nathan binkert]

Great work!

On Thu, Apr 21, 2011 at 12:12 AM, Korey Sewell  wrote:
> For 1-4 wide, InOrder Cores running in ALPHA FS mode... Observe terminal
> output:
> "M5 console: m5AlphaAccess @ 0xFD02
> Got Configuration 623
> memsize 800 pages 4000
> First free page after ROM 0xFC018000
> HWRPB 0xFC018000 l1pt 0xFC04 l2pt 0xFC042000
> l3pt_rpb 0xFC044000 l3pt_kernel 0xFC048000 l2reserv
> 0xFC046000
> kstart = 0xFC31, kend = 0xFC855898, kentry =
> 0xFC31, numCPUs = 0x1
> CPU Clock at 2000 MHz IntrClockFrequency=1024
> Booting with 1 processor(s)
> ...
> Linux version 2.6.13 (h...@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP
> Sun Oct 8 ..
> Brought up 1 CPUs
> ...
> init started:  BusyBox v1.1.0 (2007.03.04-01:07+) multi-call binary
> mounting filesystems...
> EXT2-fs warning: checktime reached, running e2fsck is recommended
> loading script...
> "*
> **Two Words: "Yes Sir!"
>
> *More Than Two Words: InOrder is booting Linux!!!
>
> Getting to this point took about >30 patches, so I have a lot of
> patch-cleaning work to do before I can place it in the repo.
>
> Also, just because it boots doesn't mean I've tested it with any kind of
> real workload suite (e.g. SPEC or Parsec).  I don't have the bandwidth to
> complete stress test through all the benchmarks and test but if someone
> tries and something goes wrong, please post to the mailing list and I'll do
> my best to help you debug.
>
> Either way, I think this is a good milestone and I'll be adding the patches
> and the regression test for ALPHA_FS/10.linux_boot/InOrder-CPU within the
> next week (or two) and then eventually updating more things in our
> handy-dandy M5 status matrix:
> http://m5sim.org/wiki/index.php/Status_Matrix
>
> The next big thing I want to get in InOrder before the "gem5" official merge
> is complete is timing TLB translation and in the longer term microcode
> support. I can't say exactly when those will be added (again, not enough
> time for me to completely focus on this), but if anyone wants to try I have
> a good idea of what needs to be done and can assist.
>
> --
> - Korey
> ___
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
>
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Error while compiling (changeset 8229)

[nathan binkert]

> Because that file is being included regardless.  I'm actively trying
> to squash all of these bugs and I'll be committing some changes soon.
> This one is trivial to fix.

I can't reproduce this bug on my machine, even with USE_MYSQL=False.
Can you try the attached diff?  If it works for you, feel free to
commit it.  If it doesn't work, just fix it however you need to and
post a diff.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

[m5-dev] changeset in m5: fix some build problems from prior changesets

[Nathan Binkert]

changeset a9d06c894afe in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a9d06c894afe
description:
fix some build problems from prior changesets

diffstat:

 src/arch/arm/interrupts.hh|  1 +
 src/arch/arm/linux/system.cc  |  1 +
 src/arch/arm/table_walker.cc  |  3 +++
 src/dev/arm/amba_device.cc|  1 +
 src/dev/arm/amba_fake.cc  |  1 +
 src/dev/arm/gic.cc|  2 ++
 src/dev/arm/kmi.cc|  1 +
 src/dev/arm/pl011.cc  |  2 ++
 src/dev/arm/pl111.cc  |  2 ++
 src/dev/arm/timer_sp804.cc|  2 ++
 src/mem/slicc/symbols/Func.py |  1 +
 src/python/m5/main.py |  5 -
 src/python/m5/simulate.py |  2 +-
 13 files changed, 22 insertions(+), 2 deletions(-)

diffs (168 lines):

diff -r 95b2bf400ee4 -r a9d06c894afe src/arch/arm/interrupts.hh
--- a/src/arch/arm/interrupts.hhWed Apr 20 13:47:42 2011 -0700
+++ b/src/arch/arm/interrupts.hhWed Apr 20 18:45:03 2011 -0700
@@ -48,6 +48,7 @@
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/registers.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
 #include "params/ArmInterrupts.hh"
 #include "sim/sim_object.hh"
 
diff -r 95b2bf400ee4 -r a9d06c894afe src/arch/arm/linux/system.cc
--- a/src/arch/arm/linux/system.cc  Wed Apr 20 13:47:42 2011 -0700
+++ b/src/arch/arm/linux/system.cc  Wed Apr 20 18:45:03 2011 -0700
@@ -47,6 +47,7 @@
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Loader.hh"
 #include "kern/linux/events.hh"
 #include "mem/physical.hh"
 
diff -r 95b2bf400ee4 -r a9d06c894afe src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc  Wed Apr 20 13:47:42 2011 -0700
+++ b/src/arch/arm/table_walker.cc  Wed Apr 20 18:45:03 2011 -0700
@@ -42,6 +42,9 @@
 #include "arch/arm/tlb.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/TLB.hh"
+#include "debug/TLBVerbose.hh"
 #include "dev/io_device.hh"
 #include "sim/system.hh"
 
diff -r 95b2bf400ee4 -r a9d06c894afe src/dev/arm/amba_device.cc
--- a/src/dev/arm/amba_device.ccWed Apr 20 13:47:42 2011 -0700
+++ b/src/dev/arm/amba_device.ccWed Apr 20 18:45:03 2011 -0700
@@ -41,6 +41,7 @@
  */
 
 #include "base/trace.hh"
+#include "debug/AMBA.hh"
 #include "dev/arm/amba_device.hh"
 #include "dev/arm/amba_fake.hh"
 #include "mem/packet.hh"
diff -r 95b2bf400ee4 -r a9d06c894afe src/dev/arm/amba_fake.cc
--- a/src/dev/arm/amba_fake.cc  Wed Apr 20 13:47:42 2011 -0700
+++ b/src/dev/arm/amba_fake.cc  Wed Apr 20 18:45:03 2011 -0700
@@ -41,6 +41,7 @@
  */
 
 #include "base/trace.hh"
+#include "debug/AMBA.hh"
 #include "dev/arm/amba_fake.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
diff -r 95b2bf400ee4 -r a9d06c894afe src/dev/arm/gic.cc
--- a/src/dev/arm/gic.ccWed Apr 20 13:47:42 2011 -0700
+++ b/src/dev/arm/gic.ccWed Apr 20 18:45:03 2011 -0700
@@ -43,6 +43,8 @@
 
 #include "base/trace.hh"
 #include "cpu/intr_control.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/GIC.hh"
 #include "dev/arm/gic.hh"
 #include "dev/platform.hh"
 #include "dev/terminal.hh"
diff -r 95b2bf400ee4 -r a9d06c894afe src/dev/arm/kmi.cc
--- a/src/dev/arm/kmi.ccWed Apr 20 13:47:42 2011 -0700
+++ b/src/dev/arm/kmi.ccWed Apr 20 18:45:03 2011 -0700
@@ -43,6 +43,7 @@
 
 #include "base/vnc/vncserver.hh"
 #include "base/trace.hh"
+#include "debug/Pl050.hh"
 #include "dev/arm/amba_device.hh"
 #include "dev/arm/kmi.hh"
 #include "dev/ps2.hh"
diff -r 95b2bf400ee4 -r a9d06c894afe src/dev/arm/pl011.cc
--- a/src/dev/arm/pl011.cc  Wed Apr 20 13:47:42 2011 -0700
+++ b/src/dev/arm/pl011.cc  Wed Apr 20 18:45:03 2011 -0700
@@ -41,6 +41,8 @@
  */
 
 #include "base/trace.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/Uart.hh"
 #include "dev/arm/amba_device.hh"
 #include "dev/arm/gic.hh"
 #include "dev/arm/pl011.hh"
diff -r 95b2bf400ee4 -r a9d06c894afe src/dev/arm/pl111.cc
--- a/src/dev/arm/pl111.cc  Wed Apr 20 13:47:42 2011 -0700
+++ b/src/dev/arm/pl111.cc  Wed Apr 20 18:45:03 2011 -0700
@@ -42,6 +42,8 @@
 #include "base/bitmap.hh"
 #include "base/output.hh"
 #include "base/trace.hh"
+#include "debug/PL111.hh"
+#include "debug/Uart.hh"
 #include "dev/arm/amba_device.hh"
 #include "dev/arm/gic.hh"
 #include "dev/arm/pl111.hh"
diff -r 95b2bf400ee4 -r a9d06c894afe src/dev/arm/timer_sp804.cc
--- a/src/dev/arm/timer_sp804.ccWed Apr 20 13:47:42 2011 -0700
+++ b/src/dev/arm/timer_sp804.ccWed Apr 20 18:45:03 2011 -0700
@@ -39,6 +39,8 @@
 
 #include "base/intmath.hh"
 #include "base/trace.hh"
+#include "debug/Checkpoint.hh"
+#include "debug/Timer.hh"
 #include "dev/arm/gic.hh"
 #include "dev/arm/timer_sp804.hh"
 #include "mem/packet.hh"
diff -r 95b2bf400ee4 -r a9d06c894afe src/mem/slicc/symbols/Func.py
--- a/src/mem/slicc/symbols/Func.py Wed Apr 20 13:47:42 2011 -0700
+++ b/src/mem/slicc/symbols/Func.py Wed Apr 20

Re: [m5-dev] Error while compiling (changeset 8229)

[nathan binkert]

> Nate, since I have provided the option USE_MYSQL=False, why should mysql.hh
> even come in to picture?

Because that file is being included regardless.  I'm actively trying
to squash all of these bugs and I'll be committing some changes soon.
This one is trivial to fix.

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Error while compiling (changeset 8229)

[nathan binkert]

The solution is to #include "base/types.hh" in mysql.hh, but to be
honest, I'm not sure how this is even happening.  Perhaps you need to
blow away your build directory and compile again.  That said, I did
not compile with USE_MYSQL=False, so this could just be a bug that
shows up in that instance.

  Nate

On Wed, Apr 20, 2011 at 10:49 AM, Nilay Vaish  wrote:
> I am trying to compile m5 and the scons exits with errors.
> Following is the compilation command --
>
> scons -j 12 CXX=g++44 CC=gcc44 USE_MYSQL=False RUBY=True
> build/ALPHA_SE_MESI_CMP_directory/m5.fast
>
> and errors
>
> In file included from
> build/ALPHA_SE_MESI_CMP_directory/python/swig/stats_wrap.cc:3163:
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:52: error: 'uint16_t'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:63: error: 'uint16_t'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:73: error: 'size_type'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:75: error: 'size_type'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:81: error: 'uint64_t'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:83: error: 'uint16_t'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:156: error: ISO C++
> forbids declaration of 'DistData' with no type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:156: error: expected
> ',' or '...' before '&' token
>
>
> The command works till changeset 8228. It fails on 8229, the one on sorting
> included files.
>
> --
> Nilay
> ___
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
>
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] another compilation error in the tree (!!)

[nathan binkert]

I'm certain that I compiled the whole tree with debug, opt, and fast,
in addition to running regressions.  I pretty much do that every time.
 What I must not have done was compile all of the different coherence
protocols though (I didn't realize that more were run in regressions
since I last updated my script).  Why don't we make opt the default
for util/regress if that's the right thing to do?  Of course, then I
may forget to compile fast and have bugs due to that.  Running both
opt and fast on regress every time would fix it, but the number of
variants that we need to compile is getting ridiculous.  We need to
figure out a way to compile multiple coherence protocols into a single
binary and probably compile SE and FS into the same binary.

  Nate

> This has to do with DPRINTFs in Ruby code, so I think it's related to
> Nate's recent changes.  Note that the regressions pass because they
> run with m5.fast which compiles out DPRINTFs.  I'm pretty sure I've
> said this before, but I think we should run regressions with opt and
> not fast (at least some of the time).  Certainly people should run
> regressions with opt and not just fast before they commit, since this
> also gives the opportunity to catch run-time assertions.
>
> Steve
>
>
> % util/regress -k --variant=debug
> [...]
>  [     CXX] 
> ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_L1Cache_request_type_to_event.cc
> -> .do
> build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_L1Cache_request_type_to_event.cc:
> In member function 'L2Cache_Event
> L2Cache_Controller::L2Cache_L1Cache_request_type_to_event(CoherenceRequestType,
> Address, MachineID, L2Cache_Entry*)':
> build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_L1Cache_request_type_to_event.cc:32:
> error: 'RubySlicc' is not a member of 'Debug'
> scons: *** 
> [build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_L1Cache_request_type_to_event.do]
> Error 1
>  [     CXX] ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_addSharer.cc -> 
> .do
> build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_addSharer.cc:
> In member function 'void
> L2Cache_Controller::L2Cache_addSharer(Address, MachineID,
> L2Cache_Entry*)':
> build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_addSharer.cc:23:
> error: 'RubySlicc' is not a member of 'Debug'
> scons: *** 
> [build/ALPHA_SE_MESI_CMP_directory/mem/protocol/L2Cache_addSharer.do]
> Error 1
> scons: `build/ALPHA_SE_MOESI_CMP_directory/m5.debug' is up to date.
>  [     CXX] 
> ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_averageLatencyEstimate.cc
> -> .do
> build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_averageLatencyEstimate.cc:
> In member function 'int
> L1Cache_Controller::L1Cache_averageLatencyEstimate()':
> build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_averageLatencyEstimate.cc:9:
> error: 'RubySlicc' is not a member of 'Debug'
> scons: *** 
> [build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_averageLatencyEstimate.do]
> Error 1
>  [     CXX] 
> ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_updateAverageLatencyEstimate.cc
> -> .do
> build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_updateAverageLatencyEstimate.cc:
> In member function 'void
> L1Cache_Controller::L1Cache_updateAverageLatencyEstimate(int)':
> build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_updateAverageLatencyEstimate.cc:9:
> error: 'RubySlicc' is not a member of 'Debug'
> scons: *** 
> [build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L1Cache_updateAverageLatencyEstimate.do]
> Error 1
>  [     CXX] 
> ALPHA_SE_MOESI_CMP_token/mem/protocol/L2Cache_convertToGenericType.cc
> -> .do
> build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L2Cache_convertToGenericType.cc:
> In member function 'GenericRequestType
> L2Cache_Controller::L2Cache_convertToGenericType(CoherenceRequestType)':
> build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L2Cache_convertToGenericType.cc:15:
> error: 'RubySlicc' is not a member of 'Debug'
> scons: *** 
> [build/ALPHA_SE_MOESI_CMP_token/mem/protocol/L2Cache_convertToGenericType.do]
> Error 1
> ___
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
>
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Error while compiling (changeset 8229)

[nathan binkert]

You need changeset 8230.  You need the sort includes changeset and the
one following it that fixes bugs.

  Nate

> I am trying to compile m5 and the scons exits with errors.
> Following is the compilation command --
>
> scons -j 12 CXX=g++44 CC=gcc44 USE_MYSQL=False RUBY=True
> build/ALPHA_SE_MESI_CMP_directory/m5.fast
>
> and errors
>
> In file included from
> build/ALPHA_SE_MESI_CMP_directory/python/swig/stats_wrap.cc:3163:
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:52: error: 'uint16_t'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:63: error: 'uint16_t'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:73: error: 'size_type'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:75: error: 'size_type'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:81: error: 'uint64_t'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:83: error: 'uint16_t'
> does not name a type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:156: error: ISO C++
> forbids declaration of 'DistData' with no type
> build/ALPHA_SE_MESI_CMP_directory/base/stats/mysql.hh:156: error: expected
> ',' or '...' before '&' token
>
>
> The command works till changeset 8228. It fails on 8229, the one on sorting
> included files.
>
> --
> Nilay
> ___
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
>
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Stats Bug

[nathan binkert]

> There's more to it than that.  I started it yesterday and I'll post a diff
> today and you can see what I mean.
> So one question to you Nate, is what do you prefer, doing a single #if
> FULL_SYSTEM in the C++, or doing a if buildEnv[FULL_SYSTEM] in the python so
> that the value passed into the C++ is already correct?  Could probably be
> done in CacheConfig so that it's in a common place that people can't forget
> to do it.  It's totally a stylistic question.

Ok.  I eagerly await your diff.  (I really want to get all of this
stats stuff done.)

As for style, I guess it's probably better to do it in the python
since there is more knowledge there and in C++, it's just blindly
adding +1.  I do like the idea of eventually crawling the hierarchy in
C++ to figure this out though. (I don't want this patch to wait on
that code though).

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Re: [m5-dev] Stats Bug

[nathan binkert]

> Yes, Steve's got it right.  In the C++ you replace the instances of the 3
> lengths Nate mentions with a single var (that can be more aptly named as
> Steve wants) that is pythonically calculated and passed in from the
> configuration.  I'm making up words here :).
>
> I think I can do this tonight or tomorrow, I don't think it's that
> complicated, so yes, I'm healthy enough :).

I just posted a review.  I'm running tests right now.  Let me know if
this is what you all had in mind please.

http://reviews.m5sim.org/r/646/

  Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev