in quality come from meticulous attention to detail and every step
in the manufacturing process must be done as carefully as possible, not as
quickly as possible
-David Packard
Tim Fifield, CET
International Rectifier - Automotive
PS. If anybody knows of any similar forums or websites for OrCad
to export to a spreadsheet or do a global change in the
library editor to make this quick and easy? I don't care which software
package I do it in because I can go between the two with DXP.
Tim Fifield
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL
:50 PM 1/15/2004, Tim Fifield wrote:
It appears that my polygons are in direct connect mode when my design rules
state that they are in relief mode. Is there something I'm missing?
Probably. Let's go over the basics.
There are two sets of connection rules: those for copper pour and those for
inner
It appears that my polygons are in direct connect mode when my design rules
state that they are in relief mode. Is there something I'm missing?
Tim Fifield
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here in Silicon Valley. Tons of
crap like that get tossed around.
How about sticking them in some AS-foam in a small cardboard box? How many
parts are you trying to ship?
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]
Sent: Tuesday, October 28, 2003 5:37 AM
To: Protel
Well,
DXP is in the mail. Am I able to run DXP and 99SE on the same computer with
out issues?
Any tips or tricks I should know about?
Tim
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If I have a valid license of Protel registered to the company I work for am
I legally allowed to use it for work that I'm doing for another company?
Both companies are in a different field of electronics and would not be
competing in any way.
Tim Fifield
I can solder 0.5mm (19.685 mil) SMT IC's by hand no problem. BGAs are a different
story...
Tim Fifield
-Original Message-
From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED]
Sent: Wednesday, September 03, 2003 3:16 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Prototype Assembly House
It's a PITA to clear away that solder bridge from those small
pins.
All you need is more flux, and the broad side of a knife tip. Then reflow and wipe out
from the pins away from the device. Clean the solder off your tip and repeat.
Tim Fifield
When making a panel is it best to do it in Protel or a gerber tool such as
Camtastic?
Tim Fifield
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it for any
purpose or store or
copy the information in any medium. Thank you.
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]
Sent: Monday, August 25, 2003 10:06 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Geometric Center
Thanks John,
We had some hall sensors
Does anybody know how Protel 99SE calculates the geometric center (Mid x,y)
in the pick and place files?
Tim Fifield
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: Tim Fifield [mailto:[EMAIL PROTECTED]
Sent: Monday, August 25, 2003 4:28 PM
To: Protel EDA Forum
Subject: [PEDA] Geometric Center
Does anybody know how Protel 99SE calculates the geometric
center (Mid x,y) in the pick and place files?
Tim
As far as I am aware the midx, midy co-ordinates
and the
problem went away.
I'm glad the repair function works but the fact that it exists says
something
Tim Fifield
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Well, I've been informed that I'm going to be switching to DXP. Does anybody
have any words of wisdom to make this switch a little easier?
Are there any issues with loading DXP onto the same machine with 99SE?
Tim Fifield
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post
Can anybody point me to the correct IPC document or other documents that
specify which SMD packages can be wave soldered and the correct rotation to
prevent solder bridges, etc...
Tim Fifield, CET
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL
Ian,
I was not aware you could place layer specific keep outs. Thanks! Learn
something new everyday.
Tim Fifield
--
You can place a layer specific keepout. This is a track or a fill that you
place on a layer like any normal track, but you then tick the Keepout
attribute on the fill
too.
Tim Fifield, CET
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?
Tim Fifield
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I think I figured it out. What I did was just create a clearance rule for
those two specific net names for the 2 pads. Then I just connected the pour
with copper fills. It's not real pretty but I think it will work.
Thanks Ian for your help.
Tim
-Original Message-
From: Tim Fifield
for the
virtual short?
Should the board house be made aware of the virtual short so they do not
remove the neck?
Tim Fifield
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Please ignore. This is a test.
Tim Fifield
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Has anybody written a server or something that highlights all pads and
tracks (P99SE PCB) that have the same net when I simply drag my cursor over
them. I'm just looking to speed things up by getting not having to hit ESN
then click on the net then hit XA to deselect them all.
Tim Fifield, CET
Designer
Norsat International Inc.
Microwave Products
Tel (604) 292-9089 (direct line)
Fax (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com
Norsat's Microwave Products Division has now achieved ISO 9001:2000
certification
-Original Message-
From: Tim Fifield
So is there nobody who knows how to do this?
Tim
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, September 10, 2002 11:17 AM
To: Protel EDA Form
Subject: [PEDA] GND Plane Neck
I have 3 GND planes (3 different net names on the sch) I need to neck
together
guaranteeing a star point topology in your
grounds.
With the Lomax virtual short you'll loose this ability!
Hope this helps,
Emanuel
Tim Fifield wrote:
So is there nobody who knows how to do this?
Tim
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]]
Sent: Tuesday
can't get there from here (I think)...
Tim,
It sounds as if you intend to use the silkscreen layer for the assembly
info? A dangerous practice and extra work. Usually do all this stuff on a
separate mechanical layer. Then go the PDF route.
Joe
- Original Message -
From: Tim Fifield [EMAIL
Richard,
What I do is make a copy of the .ddb file (renaming it appropriately) and
create the assembly drawing from it. I delete all but the .pcb and print
preview files.
Then I auto position all ref des to center (with correct rotation).
In the print preview I use top and bottom overlays with
Does anyone have this BMPTOPCB.EXE file they don't mind emailing to me. I do
not wish to join the yahoo group.
Tim
-Original Message-
From: Tony Karavidas [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, September 03, 2002 8:13 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] Company logo
Total 1502 19724 21028 954
Tony Karavidas wrote:
You mean like the ones that all these $33/$34 board houses ask?
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]]
Sent: Friday, August 30, 2002 9:55 AM
Is it possible to get layer specific pad and component counts in P99SE?
Tim Fifield
* Tracking #: 87841C98C1CAC048A562FEA5B26AC5B550D55B87
You might try double clicking on the lower RH clock in Windows, and check
the settings on the Time Zone tab.
This appears to be correct as well.
Tim
-Original Message-
From: Frank Gilley [mailto:[EMAIL PROTECTED]]
Sent: Monday, August 12, 2002 3:41 PM
To: Protel EDA Forum
Subject: Re:
Is there a way to change the order of sch files under a .prj file in the
Design Manager Panel? I cannot click and drag them like I can my bookmarks
in my web browser.
Tim Fifield
* Tracking
Hmmm... I'm not sure what it could be. My computer clock and date are
reading correctly. I use Atomic Clock Sync v2.2. Perhaps my mail server or
something else is screwed up. I'm no computer wiz and don't have control
over any other computers other than mine. Sorry...
Tim
-Original
such as a
text lable, net name, pin, etc, press the TAB key which opens a dialog box.
Any thing you enter here will now be saved as the default entry for future
placements. Note that hitting TAB after the item is placed does not
effect the defaults.
Regards
Dave Lewis
Tim Fifield [EMAIL PROTECTED
I'm creating a connector footprint with two rectangle holes or slots for
mechanical stability. How do I create rectangle holes?
Tim Fifield
* Tracking #: F043784119037E49B6F4845F2C828DF67ED2F5AD
OK,
So everything seems to be ok except that when I look at a parts attributes
after an import nothing seems to change.
This is what I'm doing.
Export
1. In Schematic Editor. FileExportExport Schematic to Database.
2. I choose Part as my selected primitive.
3. I choose X and Y Loc, Lib Ref,
John,
I'm with you on the metric thing.
Tim
-Original Message-
From: John Ross [mailto:[EMAIL PROTECTED]]
Sent: Monday, July 29, 2002 4:14 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Altium Release Protel DXP ( What is new in protel
DXP?)
-Original Message-
From: Joe
How do I create a gerber file of the drill drawing (.GD1, .GD2, etc...) to
include a legend for the drill tool sizes? I remember it being there
sometime last year but cannot seem to reproduce it. I'm using CAMtastic
2000. Import Gerber Quick Load.
Tim Fifield
25, 2002 5:57 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Hot Linking
Tim Fifield wrote:
I want to export a schematic to a database so that I can try some hot
linking. The protel handbook (pg. 163) says: Select File Export to
Database to pop up the Export Database dialog.
Tim
could
read, contribute to, and be emailed only the reply of the threads you are
interested in. Take a look at the forums www.vwvortex.com, this is a great
site that is very well laid out and informative.
Tim Fifield.
-Original Message-
From: Tony Karavidas [mailto:[EMAIL PROTECTED]]
Sent
looking in the wrong spot?
The reason I want to do this is because I have a schematic drawn with
generic parts i.e. all resistors have LibRef of res3. I want to change
the schematics so each component has its own specific LibRef such as
ERJ-6ENF24R9V.
Tim Fifield
the schematics so each component has its own specific LibRef such as
ERJ-6ENF24R9V.
Tim Fifield
* Tracking #: AFBD0364E0C48B4C8C35978334A6393880320B4B
for that missing
selection:
Text: Export to Database
Process: ExportSchematicToDatabase
Params:
(I left params blank)
Stick that in your File/Export menu and it should look normal.
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, July 24, 2002 9:45
I have never had the autorouter work for me on anything more than a very
basic 2 sided pcb. Even then, I don't like what it does. I do everything
manually. Perhaps I need some training on how to run it properly
Tim
*
Just FYI
Design for breakaway tabs can be found in IPC Standard IPC- although I
personally don't find it very helpful...
Tim Fifield
-Original Message-
From: Danny Bishop [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, June 25, 2002 8:39 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA
the licensing incorrectly?
Tim Fifield
* Tracking #: E395FF4341496743A9A85023A9AF0870F88DEA19
As far as I know, it cannot be done with Protel 99SE.
Tim
-Original Message-
From: Christopher Rhomberg [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, June 18, 2002 3:02 PM
To: Protel EDA Forum
Subject: [PEDA] 3D MODELS FOR PROTEL99SE
Does anyone know how I can draw new 3D components for
.
The reason I'm asking on this forum is because I believe the PCB was drawn
with Protel in 1997.
The website is www.phytec.com, look under KitCon Development Boards. I
don't believe there is a picture of the actual 164 board on there though.
Tim Fifield, CET
International Rectifier - EMS Canada
Tel
Is there a way to change the title of a .prj file and the .sch files
underneath it along with the .PCB file, print preview, and CAM outputs all
at once? Or do I have to go and manually change them all?
Tim
* Tracking #:
a new .sch (in the projects directory) I go to
Design/Template/Set Template file name, add the .ddb with the .dot template,
select the template, and hit Ok. The logo appears every time. Works on all
the computers that are on the network.
Tim Fifield
-Original Message-
From: Dennis Saputelli
changing the grid and using the Move to Grid function but this seem to do
nothing.
Tim Fifield, CET
International Rectifier - EMS Canada
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The black silver oxide layer that will form has low electrical
conductivity...
Just out of curiosity, I thought silver oxide was conductive?
Thanks to all who helped with this thread. I'm reviewing them and haven't
made a decision yet...
Tim Fifield
-Original Message-
From: Mike Reagan [mailto:[EMAIL PROTECTED]]
Sent: Friday, April 12, 2002 9:49 AM
To: Protel EDA Forum
Subject: Re: [PEDA] PCB Panelization
Thank you Dennis
be much appreciated as
well.
Tim Fifield
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Shawn,
I get my 4 layer PCB's prototyped at Dynamic and Proto Circuits www.dapc.com
in ON. They seem to do a good job. My contact is Monica Georgi,
[EMAIL PROTECTED] I'd like to have a list of Canadian PCB houses though
Hope this helps,
Tim Fifield
-Original Message-
From: SHAWN
We use here it and find it very useful.
Tim
-Original Message-
From: Nicholas Cobb [mailto:[EMAIL PROTECTED]]
Sent: Monday, April 01, 2002 4:18 PM
To: Protel EDA Forum
Subject: [PEDA] Parts and Vendors
I know that this is off-topic, but I was wondering what everyone's opinion
about
Brian,
What should I do with these files?
Tim
-Original Message-
From: Brian Guralnick [mailto:[EMAIL PROTECTED]]
Sent: Thursday, March 28, 2002 2:55 PM
To: Protel EDA Forum
Subject: [PEDA] Monitor focusing.
Vastly improved, monitor focusing test pattern. Make sure when using, that
this will be
fixed on the next release...
Tim Fifield
-Original Message-
From: Darryl Newberry [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, March 20, 2002 6:09 PM
To: 'Protel EDA Forum'
Subject: Re: [PEDA] computer pauses
Set Polygon pour to Never. Then don't forget to repour them manually
performace was restored to 0-60 , but couldnt tell you what the real fix
is. The delay is gone, but next time I am going to use steps 1-4 again
without hesitation
Good Luck
Mike Reagan
- Original Message -
From: Tim Fifield [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent
to no hatching and it seemed to speed up the process.
If anybody has another thoughts on speeding this up, please fill me in.
4 layer PCB, 400+ comp., Online DRC is off...
I'm using P99SE SP6. Win 2K SP2 800MHz, 512MRAM.
Tim Fifield, CET
Can anybody tell me what the recommended test point pad size to be used with
the GenRAD GR228xi in circuit tester is? I think were using a combo II
board.
Our manufacturing dept. wants me to use a 100 thou diameter pad which seems
quite excessive to me. I currently have a 35 thou pad.
Tim
I've noticed those rounding errors as well.
Tim
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, March 12, 2002 12:57 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Is it a bug, or me?
Protel has a few problems with mm and inches. I've often seen small
Does anyone know if it's possible to create a toggle button on a tool bar
that toggles a specific layer on or off?
I like to turn the Top Overlay layer on and off frequently and find it
cumbersome to always go right click/options/ board layers then check the
box.
Tim Fifield
Upon further investigation, it appears that my 3D viewer is not working at
all. When I try to view a very simple double side rectangle pcb it just
shows a blank workspace and sometimes I get the same warning message. I
tried reinstalling the server but it didn't fix the problem. I used to be
able
When I try to view my pcb in the 3D viewer I get the following message and
then it just sits there, stares at me and won't let me press the ok button.
Board boundary is incomplete - calculated boundary will be used. Check that
the boundary on the Keep Out layer is closed, with their track ends
Mark,
The print preview has a little box that you can check to mirror the layer. I
just create a silkscreen layer with a mech outline and the silk screen you I
to see for my assy. dwgs. and have that box ticked for that printout. You
can do this for any other layer that you want.
Tim
This is a test. Please ignore
Tim
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I get a Warning: Unconnected net label on net ... when I run ERC in the
Sch editor. I'm trying to label a bus line with a the following net label
AD[15..0]
How do I resolve this warning?
Tim
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL
EDA Forum
Subject: Re: [PEDA] Warning: Unconnected net label
Tim Fifield wrote:
I get a Warning: Unconnected net label on net ... when I run ERC in the
Sch editor. I'm trying to label a bus line with a the following net label
AD[15..0]
How do I resolve this warning?
The bottom left corner
should work fine.
Regards
Andy Gulliver
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]]
Sent: 30 January 2002 16:22
To: Protel EDA Forum
Subject: Re: [PEDA] Warning: Unconnected net label
The bottom left corner of the net name is touching the bus it
applies
Is it possible to bring one or more of a parts read only fields from the
sch editor to the PCB layout? I wish to include the markings on the part
case (A read only field) in the assembly diagram.
Tim Fifield - Electronic Technologist
International Rectifier - EMS Canada
7020 Mumford Rd. Halifax
Does anyone have a list or reference for/of pcb design guidelines for the
automotive industry?
Specifically things like track width, min via hole and pads size, min
spacing, etc...
Perhaps guidelines for aerospace design would be useful?
Tim Fifield
This is a test, as I have not received mail from the group in two days.
Tim Fifield
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If I understand the question correctly, you can tile the windows to view
both at once.
Tim Fifield
[EMAIL PROTECTED]
International Rectifier
-Original Message-
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED]]
Sent: Friday, January 11, 2002 6:27 AM
To: proteledaforum
Subject: [PEDA
All of my rats nest lines (with the exception of a few) have disappeared.
How do I make them reappear?
Tim
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Never mind, found it. View/connections/show all.
Tim
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checked. The pad
is on the bottom of the board. What am I missing?
Tim
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Saturday, December 15, 2001 9:01 PM
To: Protel EDA Forum
Subject: Re: [PEDA] .TXT File generation
On 04:43 PM 13/12/2001 -0400, Tim Fifield said:
Thanks
My production facility (not pcb house) is asking for the following:
X/Y coordinates of components .TXT file
X/Y coordinates of test points/pads in .TXT file
Is it possible to generate those files in P99SE? If so, how?
Tim
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a
will output the X/Y co-ordinates of all your
testpoints, provided that you have set all the testpoints as such. Meaning
checked the testpoint box under the pad attributes menu.
Regards,
Lloyd
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]]
Sent: Thursday, December 13, 2001 9
when programming their PP machines will
verify and correct for offsets or inaccuracies in these numbers. I've seen
them do tria runs to figure out if all these numbers are correct.
Tony
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]]
Sent: Thursday, December 13, 2001 10:50
work and
restart windows.
Ignore
Quit
What is going on!? I've restarted 3 times now and the first thing I do gives
me that message.
I'm using 99SE SP6 with windows 2000 sp2.
Please help me!
Tim Fifield
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* To post a message: mailto
for audio s-video.
Brian Guralnick
- Original Message -
From: Tim Fifield [EMAIL PROTECTED]
To: Protel EDA Form [EMAIL PROTECTED]
Sent: Monday, November 26, 2001 11:44 AM
Subject: [PEDA] connector footprint
| Does anybody have a 99SE footprint for a Standard Circular DIN 5
Is it possible to have a layer specific keep out? I want a GND trace
connecting two components, however, there is a GND polygon between the two
components as well. I do not want the trace to touch the polygon. Is there a
way to do this without drawing the polygon around the track?
Tim
* * * * *
Does anybody have a 99SE footprint for a Standard Circular DIN 5 Pin
Receptacle, Right angle PCB mount?
Specifically, the part is SDS-50J from CUI Stack. www.cuistack.com
Tim Fifield
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* To post a message: mailto:[EMAIL PROTECTED
Jeff,
Try: Design/Netlist Manager/Menu/Update Free Primitives From Component Pads.
Tim
-Original Message-
From: Jeff Adolphs [mailto:[EMAIL PROTECTED]]
Sent: Monday, November 26, 2001 2:52 PM
To: Protel EDA Forum (E-mail)
Subject: [PEDA] Footprint 215
Hi! I used a Protel Footprint
Thanks to all for the help!
Tim
-Original Message-
From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, November 21, 2001 11:23 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Power Plane Clearance
At 04:19 PM 11/21/01 -0600, Jon Elson wrote:
It seems Protel only supports
oh, I just thought of another question...
What is your (Protel user) preferred clearance and connect style on the
power planes? A board I just finished had 20mil clearance and direct
connect. I'm wondering if 20mil is too much and if a relief connect would be
better.
Tim
* * * * * * * * * * *
In 99SE PCB editor I wish to connect vias to the unused pins of a 100 pin
QFP for debug. When I run DRC it gives me short circuit and clearance
violations. Is there a way to create a net for each pin in PCB but not the
schematic editor so I won't get the violations?
Tim Fifield
the schema editor ?
I do use square smd pads and/or round 32mil holes as
debugpins. The later having the advantage of a scope probe
holder.
Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
Tim Fifield wrote:
In 99SE PCB editor I wish to connect vias to the unused pins of a 100 pin
QFP for debug
Thanks to all who replied to this thread!
Tim.
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Monday, November 19, 2001 6:14 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Short Circuit: Pad/Fill
On 04:16 PM 19/11/2001 -0400, Tim Fifield said:
I've created an odd
Rob,
You can download the 99SE handbook as well as a handbook supplement from the
Protel website in PDF format. I agree, they are quite useful.
Tim Fifield
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. Is there any way to resolve this?
Tim Fifield
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Just curious... Does anybody use the 99SE autorouter for large PCB designs?
Do the majority of board designers do everything manually? I don't even
bother with the autorouter anymore, it's to messy. Perhaps I'm not setting
it up properly. What do you people do?
Tim Fifield
many buttons you have
to push to get good results! Also, keep in mind that an autorouter will
never be as smart as you, only faster than you.
Best regards,
Ivan Baggett
Bagotronix Inc.
website: www.bagotronix.com
- Original Message -
From: Tim Fifield [EMAIL PROTECTED]
To: Protel EDA Form
Edi,
We use:
Sch
PCB
Signal Integ.
CAM Man.
Print.
Database link, not 100% though.
Tim
-Original Message-
From: Edi Im Hof [mailto:[EMAIL PROTECTED]]
Sent: Friday, November 16, 2001 2:17 PM
To: Protel EDA Forum
Subject: [PEDA] Protel usage
Hi all
Regarding the questions about 3D
Fred,
To the best of my knowledge, there is no way to generate custom components
for use in 3D renderings for 99SE.
Tim
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