[PATCH v2 24/37] clk: rockchip: rk3576: Use correct TSADC clock register

[Jonas Karlman]

Parent and divider fields for CLK_TSADC are located in CLKSEL_CON59 not
in CLKSEL_CON58. Change to use correct CLKSEL_CON for the CLK_TSADC
clock.

Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
Changes in v2:
- Split from "rk3576: Fix trivial clock configuration errors"
- Add fixes tag
---
 drivers/clk/rockchip/clk_rk3576.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3576.c 
b/drivers/clk/rockchip/clk_rk3576.c
index 17f9b01ff0c8..e66368b01b5e 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -703,7 +703,7 @@ static ulong rk3576_adc_set_clk(struct rk3576_clk_priv 
*priv,
        case CLK_TSADC:
                src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
                assert(src_clk_div - 1 <= 255);
-               rk_clrsetreg(&cru->clksel_con[58],
+               rk_clrsetreg(&cru->clksel_con[59],
                             CLK_TSADC_DIV_MASK,
                             (src_clk_div - 1) <<
                             CLK_TSADC_DIV_SHIFT);
-- 
2.55.0