Keep the BPLL entry formatted in a similar way matching the other PLL entries for consistency.
Signed-off-by: Jonas Karlman <[email protected]> --- v2: Split from "rk3576: Fix trivial clock configuration errors" --- drivers/clk/rockchip/clk_rk3576.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index ce97997c73ea..75b705ffba2f 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -44,8 +44,7 @@ static struct rockchip_pll_rate_table rk3576_24m_pll_rates[] = { static struct rockchip_pll_clock rk3576_pll_clks[] = { [BPLL] = PLL(pll_rk3588, PLL_BPLL, RK3576_PLL_CON(0), - RK3576_BPLL_MODE_CON0, 0, 15, 0, - rk3576_24m_pll_rates), + RK3576_BPLL_MODE_CON0, 0, 15, 0, rk3576_24m_pll_rates), [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3576_LPLL_CON(16), RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_24m_pll_rates), [VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88), -- 2.55.0
