The PPLL registers belong to the PHP CRU, rather than the PMU CRU.
Rename the register macro and update the PPLL entry and users to reflect
this.
Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <[email protected]>
---
Changes in v2:
- Split from "rk3576: Fix trivial clock configuration errors"
- Add fixes tag
---
arch/arm/include/asm/arch-rockchip/cru_rk3576.h | 2 +-
drivers/clk/rockchip/clk_rk3576.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
index fb77fbd7307a..380151e0f8d5 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
@@ -127,11 +127,11 @@ struct pll_rate_table {
#define RK3576_SDMMC_CON0 0xC30
#define RK3576_SDMMC_CON1 0xC34
+#define RK3576_PHP_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE +
0x300)
#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE +
0x800)
#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE +
0xa00)
-#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE +
0x300)
#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE +
0x800)
#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE +
0xa00)
diff --git a/drivers/clk/rockchip/clk_rk3576.c
b/drivers/clk/rockchip/clk_rk3576.c
index a7110b86c063..ce97997c73ea 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -56,7 +56,7 @@ static struct rockchip_pll_clock rk3576_pll_clks[] = {
RK3576_MODE_CON0, 8, 15, 0, rk3576_24m_pll_rates),
[GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3576_PLL_CON(112),
RK3576_MODE_CON0, 2, 15, 0, rk3576_24m_pll_rates),
- [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128),
+ [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PHP_PLL_CON(128),
RK3576_MODE_CON0, 10, 15, ROCKCHIP_PLL_FIXED_MODE,
rk3576_24m_pll_rates),
};
@@ -2458,7 +2458,7 @@ static int rk3576_clk_probe(struct udevice *dev)
RK3576_SCRU_BASE + RK3576_MODE_CON0);
/* fix ppll\aupll\cpll */
writel(BITS_WITH_WMASK(2, 0x7U, 6),
- RK3576_CRU_BASE + RK3576_PMU_PLL_CON(129));
+ RK3576_CRU_BASE + RK3576_PHP_PLL_CON(129));
writel(BITS_WITH_WMASK(2, 0x7U, 6),
RK3576_CRU_BASE + RK3576_PLL_CON(97));
writel(BITS_WITH_WMASK(2, 0x7U, 6),
--
2.55.0
