At 11:14 PM 3/19/2002 -0500, Bob Wolfe wrote: >Thanks, >I am partially there, I have not selected that option to use ORCAD PORT >Setting. >That may in part be my problem?? Will look into it further. >What is happening is a bus of 0-15 is only seeing half of the nets across >sheets, >the nets are wires and there does not appear to be any overlap or mis >connection >of any of the ports involved. >The only way I seem to be able to get the connection to take place is >to delete and re-add the net labels in protel to those not happening. >This seems to work. But thanks I will look into it further.
Let me guess the basic problem. Mr. Wolfe is not running ERC and nailing down every error or warning. There are many conditions which can cause connectivity failure; most of them will create ERC errors or warnings. If replacing net labels fixes the problem, possible error conditions would include: (1) annotation used instead of net label. Annotation text should never match net labels in color, but Protel will cheerfully allow it. Plus a designer might be color-blind. I'd suggest that a "Hide Annotations" setting could be useful, and a warning if annotation text matches any net or port label in the design. For most of us, it would be enough at present to globally change all annotation text and net label text to differing colors. (2) difference in spelling between instances of a net label. For example, D1 might be on one page and Dl on another. These are *not* the same net label. (3) Net label placed with reference point not coincident with wire or pin or port end. Designers should be very careful when moving off a grid of 10; there are few good reasons for doing so, if any, except for graphical elements in the symbol library editor, a caution should be exercised to ensure that the hot spots of pins are on a grid of 10. (Schematic grid is in hundredths of an inch.) There are plenty of other causes for connectivity problems, but these are the ones which come to my mind upon reading that replacing net labels solves the problem. That would not affect, for example, incorrect connectivity from incorrect scope or incorrect implementation of the Port Only or Sheet Symbol/Sheet Entry scopes, which are quite demanding, they must be done just so. The documentation on this could be improved, particularly because Sheet Symbol/Sheet Entry is, in my opinion, the best for producing clear and error-free multipage schematics, and this scope also makes design re-use easier. Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://firstname.lastname@example.org * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *