Re: [m5-dev] Review Request: ARM: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/312/ --- (Updated 2010-11-17 22:30:03.651555) Review request for Default. Summary ---

Re: [m5-dev] Review Request: Params: Add parameter types for IP addresses in various forms.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/316/ --- (Updated 2010-11-17 21:40:33.030841) Review request for Default. Summary ---

[m5-dev] changeset in m5: Config: Change misleading "cycle" message to sa...

changeset 1252ec1c8714 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=1252ec1c8714 description: Config: Change misleading "cycle" message to say "tick". Most of the messages in the config scripts that report a time value already print "@ tick" followed

Re: [m5-dev] Review Request: Params: Add parameter types for IP addresses in various forms.

dn't you just > > point out this same bug in some existing code here? > > Gabe Black wrote: > < 256 yes, < 32 no. The max byte value is 255, but the netmask can have 0 > to 32 bits set I think, where 0 would be all possible IPs and 32 would be one >

Re: [m5-dev] Review Request: Params: Add parameter types for IP addresses in various forms.

at turning it back around. - Gabe --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/316/#review490 --- On 2010-11-17 13:54:35, Gabe Black wr

Re: [m5-dev] Review Request: Params: Add parameter types for IP addresses in various forms.

approach. - Gabe --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/316/#review489 --- On 2010-11-17 13:54:35, Gabe Black wrote: > > --

Re: [m5-dev] Review Request: O3: Fix fp destination register flattening, and index offset adjusting.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/282/#review486 --- Bump - Gabe On 2010-10-31 14:32:57, Gabe Black wrote

[m5-dev] Review Request: Params: Add parameter types for IP addresses in various forms.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/316/ --- Review request for Default. Summary --- Params: Add parameter types for IP add

[m5-dev] Review Request: Config: Change misleading "cycle" message to say "tick".

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/315/ --- Review request for Default. Summary --- Config: Change misleading "cycle" mess

Re: [m5-dev] Review Request: ARM: Take advantage of new PCState syntax.

se of exactly what's going on right now. > You're submitting your 2nd 50 lines of diff to change one number in > 50 places. Not cool. > > On Tue, Nov 16, 2010 at 1:34 PM, Gabe Black <mailto:gbl...@eecs.umich.edu>> wrote: > > This is an automatically generated e-m

Re: [m5-dev] Review Request: ARM: Take advantage of new PCState syntax.

an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/312/#review483 --- On 2010-11-15 04:28:11, Gabe Black wrote: > > --

Re: [m5-dev] changeset in m5: ARM: Add support for a dumb IDE controller

On 11/15/10 12:09, Ali Saidi wrote: > diffs (119 lines): > > diff -r 859e8bc1cdc2 -r 0731d632db76 configs/common/FSConfig.py > --- a/configs/common/FSConfig.py Mon Nov 15 14:04:03 2010 -0600 > +++ b/configs/common/FSConfig.py Mon Nov 15 14:04:03 2010 -0600 > @@ -209,6 +209,16 @@ > >

[m5-dev] changeset in m5: O3: Make O3 support variably lengthed instructi...

changeset 03efcdc3421f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=03efcdc3421f description: O3: Make O3 support variably lengthed instructions. diffstat: src/arch/alpha/predecoder.hh | 11 +- src/arch/mips/predecoder.hh | 11 +- src/arch/power/predecoder.hh |

[m5-dev] changeset in m5: Stats: Update the O3 fetch stats for SPARC.

changeset 634d88f0dbd4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=634d88f0dbd4 description: Stats: Update the O3 fetch stats for SPARC. diffstat: tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) di

Re: [m5-dev] Review Request: ISA: Get the parser to support pc state components more elegantly.

ISAs to use the new syntax. These could use more testing, as usual especially ARM, but I wanted to get them out there before I started traveling. Gabe Gabe Black wrote: > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/306/ > > > Review reques

[m5-dev] Review Request: ARM: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/312/ --- Review request for Default. Summary --- ARM: Take advantage of new PCState syn

[m5-dev] Review Request: Alpha: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/311/ --- Review request for Default. Summary --- Alpha: Take advantage of new PCState s

[m5-dev] Review Request: MIPS: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/310/ --- Review request for Default. Summary --- MIPS: Take advantage of new PCState sy

[m5-dev] Review Request: POWER: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/309/ --- Review request for Default. Summary --- POWER: Take advantage of new PCState s

[m5-dev] Review Request: SPARC: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/308/ --- Review request for Default. Summary --- SPARC: Take advantage of new PCState s

[m5-dev] Review Request: X86: Take advantage of new PCState syntax.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/307/ --- Review request for Default. Summary --- X86: Take advantage of new PCState syn

[m5-dev] Review Request: ISA: Get the parser to support pc state components more elegantly.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/306/ --- Review request for Default. Summary --- ISA: Get the parser to support pc stat

Re: [m5-dev] Cron /z/m5/regression/do-regression quick

Not me I hope. File system issues again? Cron Daemon wrote: > * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp > FAILED! > * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp > FAILED! > * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio

[m5-dev] isa_parser debug mode

Hi everybody. If you don't actively work on ISA descriptions or the parser, feel free to ignore this email. I've been working on the parser to better integrate the recent PC changes, and it's been useful to turn on the backtrace feature of the parser by setting debug=True at the top. This is a lot

Re: [m5-dev] Review Request: [mq]: pretty_scons.diff

1) Ali and I discussed some tweaks the other day. TRACEING should be TRACING, and MAKEISA would be better as CFG ISA if I remember right. Otherwise I'm happy with the strings. 2) Now that you mention it, left justified might be better. I don't have a really string opinion. I still don't really lik

Re: [m5-dev] Review Request: CPU: Fix bug when a split transaction is issued to a faster cache

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/304/#review478 --- This seems ok, although I won't claim to understand all of the possible i

Re: [m5-dev] Review Request: ARM: Fix SRS instruction to micro-code memory operation and register update.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/305/#review477 --- Ship it! Looks ok. You could put the sp index into a temporary variable a

[m5-dev] changeset in m5: Params: Fix an off by one error and a misleadin...

changeset f440cdaf1c2d in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f440cdaf1c2d description: Params: Fix an off by one error and a misleading comment. diffstat: src/python/m5/params.py | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diffs (21 lines):

[m5-dev] changeset in m5: SimObject: Add a comment near clear_child that ...

changeset 611fe187288e in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=611fe187288e description: SimObject: Add a comment near clear_child that it's unlikely to be called. diffstat: src/python/m5/SimObject.py | 7 ++- 1 files changed, 6 insertions(+), 1 deletions

Re: [m5-dev] Review Request: O3: Make O3 support variably lengthed instructions.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/281/ --- (Updated 2010-11-11 04:44:28.434315) Review request for Default. Summary ---

[m5-dev] changeset in m5: SPARC: Clean up some historical style issues.

changeset 340b6f01d69b in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=340b6f01d69b description: SPARC: Clean up some historical style issues. diffstat: src/arch/sparc/asi.cc | 501 src/arch/sparc/asi.hh

Re: [m5-dev] Review Request: O3: Make all instructions that write a misc register not perform the write until commit.

> On 2010-11-10 08:07:39, Steve Reinhardt wrote: > > So it looks like whether you call setMiscReg() or setMiscRegNoEffect() then > > you buffer the update and call setMiscReg() later... i.e., even if you > > called setMiscRegNoEffect() originally you end up calling setMiscReg() at > > commit.

Re: [m5-dev] changeset in m5: ARM: Make all ARM uops delayed commit.

On 11/10/10 10:12, Ali Saidi wrote: > > On Wed, 10 Nov 2010 09:49:19 -0800, Steve Reinhardt > wrote: > >> >> >> On Wed, Nov 10, 2010 at 9:42 AM, Ali Saidi > > wrote: >> >> On Wed, 10 Nov 2010 09:37:54 -0800, Steve Reinhardt >> mailto:ste...@gmail.com>> wrote: >> >>

Re: [m5-dev] Review Request: Scons: Try to make SCons output prettier.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/299/#review471 --- Generally I'm in favor of this, but I think two characters are too few, an

Re: [m5-dev] Review Request: ARM: Implement a CLCD Frame buffer

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/294/#review457 --- I assume this is a step towards VNC accessible video output. There are som

Re: [m5-dev] Review Request: imported patch ext/simd_opclasses.patch

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/297/#review453 --- I found one instance where I think the line got too long, but there was AL

Re: [m5-dev] Review Request: ARM: Add a Keyboard Mouse Interface controller

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/295/#review455 --- This is mostly ok, but there are some small tweaks needed I think. src/d

Re: [m5-dev] Review Request: imported patch ext/arm_gdb.patch

> On 2010-11-09 11:50:33, Gabe Black wrote: > > Instead of packing/unpacking 32 bit values in 64 bit registers, why don't > > we template the base class on the type of register it's going to hold. I > > think the changes to the base class would be minimal, and

Re: [m5-dev] Review Request: ARM: Add support for a dumb IDE controller

> On 2010-11-08 17:56:14, Nathan Binkert wrote: > > src/dev/ide_ctrl.cc, line 454 > > > > > > Is this something that we should deal with on a per device basis, or is > > this a more generic thing? Also, is this something tha

Re: [m5-dev] Review Request: O3: prevent a squash when completeAcc() modifies misc reg through TC.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/296/#review449 --- Ship it! It would be nice not to propagate the "convoluted way" this is d

Re: [m5-dev] Review Request: ARM: Add support for switching CPUs

> On 2010-11-09 11:37:23, Gabe Black wrote: > > src/cpu/simple_thread.cc, line 159 > > <http://reviews.m5sim.org/r/290/diff/1/?file=5049#file5049line159> > > > > What happens to the old TLB? What if you wanted to switch to a new one? > > I'm assu

Re: [m5-dev] Review Request: imported patch ext/arm_gdb.patch

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/293/#review446 --- Instead of packing/unpacking 32 bit values in 64 bit registers, why don't

Re: [m5-dev] Review Request: ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/291/#review444 --- This seems reasonable. Have you measured the actual performance impact? -

Re: [m5-dev] Review Request: ARM: Add support for switching CPUs

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/290/#review443 --- src/cpu/simple_thread.cc

[m5-dev] changeset in m5: scons: Work around for old versions of scons mi...

changeset f97a5f4d0879 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f97a5f4d0879 description: scons: Work around for old versions of scons mistaking strings for sequences. diffstat: SConstruct| 32 ext/libelf/SConscript

[m5-dev] changeset in m5: SimObject: Use "self" when calling the clear_ch...

changeset e2e8ca8d9640 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=e2e8ca8d9640 description: SimObject: Use "self" when calling the clear_child method. diffstat: src/python/m5/SimObject.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (12 lines):

Re: [m5-dev] Review Request: scons: Replace the build_dir parameter to SConscript with variant_dir.

On 11/09/10 09:37, nathan binkert wrote: >> My change seems to work, but in the process of wedging that old a >> version of scons onto my system (no portage support, no download, had to >> get it from svn, had to manually "install" it). It looks like there are >> a few places where >> >>main.A

Re: [m5-dev] Review Request: SimObject: Use "self" when calling the clear_child method.

On 11/09/10 08:15, nathan binkert wrote: >> This code was apparently never called before, and I think I landed on >> it by accident. Could there be anything else like that? Maybe we should >> put together a test configuration? > Do you know what you did to exercise it? I don't recall writing thi

Re: [m5-dev] Review Request: SimObject: Use "self" when calling the clear_child method.

This code was apparently never called before, and I think I landed on it by accident. Could there be anything else like that? Maybe we should put together a test configuration? Gabe On 11/08/10 23:37, Gabe Black wrote: > --- > This

[m5-dev] Review Request: SimObject: Use "self" when calling the clear_child method.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/301/ --- Review request for Default. Summary --- SimObject: Use "self" when calling the

Re: [m5-dev] changeset in m5: X86: Fix X86_FS compilation.

t, or what? I think there may be one or two people out there that have done some of this on their own already (I'm thinking of Joel specifically) and their insight would also be helpful. Gabe On 11/08/10 12:43, Gabe Black wrote: > changeset f4362ffd810f in /z/repo/m5 > details: http://

[m5-dev] changeset in m5: X86: Fix X86_FS compilation.

(30 lines): diff -r f61e079ad05e -r f4362ffd810f src/arch/x86/linux/system.cc --- a/src/arch/x86/linux/system.cc Mon Nov 08 13:59:35 2010 -0600 +++ b/src/arch/x86/linux/system.cc Mon Nov 08 12:43:38 2010 -0800 @@ -37,6 +37,7 @@ * Authors: Gabe Black */ +#include "arc

Re: [m5-dev] Review Request: ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/256/#review435 --- Most of these comments are pretty minor, but I think my comment for timing

Re: [m5-dev] Review Request: ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.

I've been meaning to look at it. Please wait. Gabe Ali Saidi wrote: > Any comments? Can I push this? > > Ali > > On Nov 5, 2010, at 7:27 PM, Ali Saidi wrote: > > >> --- >> This is an automatically generated e-mail. To reply, visit: >> htt

Re: [m5-dev] Review Request: scons: Replace the build_dir parameter to SConscript with variant_dir.

On 11/06/10 17:12, Gabe Black wrote: > On 11/06/10 15:56, Gabe Black wrote: >> On 11/05/10 18:06, nathan binkert wrote: >>>> Might be good to download a scons-local 0.98.1 and verify this works, but >>>> otherwise I'm happy. >>> I suggest that

[m5-dev] changeset in m5: scons: Replace the build_dir parameter to SCons...

changeset c10bc8ad3f97 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=c10bc8ad3f97 description: scons: Replace the build_dir parameter to SConscript with variant_dir. The build_dir parameter name has been deprecated and replaced with variant_dir. This ch

Re: [m5-dev] Review Request: scons: Replace the build_dir parameter to SConscript with variant_dir.

On 11/06/10 15:56, Gabe Black wrote: > On 11/05/10 18:06, nathan binkert wrote: >>> Might be good to download a scons-local 0.98.1 and verify this works, but >>> otherwise I'm happy. >> I suggest that you do that. Remember the last time I had that swig >>

Re: [m5-dev] Review Request: scons: Replace the build_dir parameter to SConscript with variant_dir.

On 11/05/10 18:06, nathan binkert wrote: >> Might be good to download a scons-local 0.98.1 and verify this works, but >> otherwise I'm happy. > I suggest that you do that. Remember the last time I had that swig > problem? These programs sometimes lie about what their version > supports. > > N

[m5-dev] Review Request: scons: Replace the build_dir parameter to SConscript with variant_dir.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/288/ --- Review request for Default. Summary --- scons: Replace the build_dir parameter

Re: [m5-dev] Review Request: sim: Use forward declarations for ports.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/285/#review428 --- Ship it! Seems like a good idea to me. - Gabe On 2010-11-03 16:12:10,

[m5-dev] "build_dir has been deprecated"

I went to build ALPHA_FS just now, and I must have upgraded scons as part of my most recent system update because now I get a bunch of the following warnings. scons: warning: The build_dir keyword has been deprecated; use the variant_dir keyword instead. File "/home/gblack/m5/repos/m5/build/ALPHA

[m5-dev] Review Request: O3: Fix fp destination register flattening, and index offset adjusting.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/282/ --- Review request for Default. Summary --- O3: Fix fp destination register flatte

[m5-dev] Review Request: O3: Make O3 support variably lengthed instructions.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/281/ --- Review request for Default. Summary --- O3: Make O3 support variably lengthed

[m5-dev] changeset in m5: ISA, CPU, etc: Create an ISA defined PC type that...

changeset 65d338a8dba4 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=65d338a8dba4 description: ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed

[m5-dev] changeset in m5: Ref output: Update refs for PCState change.

changeset 9d60c5339ae5 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=9d60c5339ae5 description: Ref output: Update refs for PCState change. diffstat: tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini | 2 +- tests/long/00.gzip/ref/sparc/

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

visit: http://reviews.m5sim.org/r/255/#review426 --- On 2010-10-27 21:48:56, Gabe Black wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/255/ > -

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

supposed to be) functionally equivalent I think. - Gabe --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/255/#review424 --- On 2010-10-27 21:48:56, Gabe Black wrote: > > --

[m5-dev] changeset in m5: X86: Fault on divide by zero instead of panicing.

changeset f299139501f7 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f299139501f7 description: X86: Fault on divide by zero instead of panicing. diffstat: src/arch/x86/isa/microops/regop.isa | 21 + 1 files changed, 13 insertions(+), 8 deletions(

[m5-dev] changeset in m5: X86: Make syscalls also serialize after.

changeset 6333e66ce74b in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=6333e66ce74b description: X86: Make syscalls also serialize after. diffstat: src/arch/x86/isa/decoder/one_byte_opcodes.isa | 2 +- src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 ++-- 2 files c

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/255/ --- (Updated 2010-10-27 21:48:56.137714) Review request for Default. Summary (updated

Re: [m5-dev] Review Request: ARM: Make all ARM uops delayed commit.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/279/#review423 --- It looks like you used it properly in the diff, but you're not making -all

Re: [m5-dev] Cron /z/m5/regression/do-regression quick

Would someone please nuke these so they rerun? I'm guessing the mount point had problems yesterday, and since there haven't been any commits its just reusing those results. Alternatively someone could tell me what to do and I could go do it. Gabe Cron Daemon wrote: > * build/ALPHA_SE/tests/fa

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

Gabe Black wrote: > Steve Reinhardt wrote: > >> On Sun, Oct 24, 2010 at 11:21 PM, Gabriel Michael Black >> wrote: >> >> >>> If you have ISA X and it needs to set the PC in some weird way y, then you >>> need an method for Y on the

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

Steve Reinhardt wrote: > On Sun, Oct 24, 2010 at 11:21 PM, Gabriel Michael Black > wrote: > >> If you have ISA X and it needs to set the PC in some weird way y, then you >> need an method for Y on the PC object. You also need an operand Y that knows >> how to use y to manage the PC. The ISA nee

Re: [m5-dev] Cron /z/m5/regression/do-regression quick

More mount point? Cron Daemon wrote: > * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp > FAILED! > * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic > FAILED! > * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp > FAILE

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

0-22 13:28:26, Nathan Binkert wrote: > > src/cpu/inorder/resource_pool.9stage.cc, line 216 > > <http://reviews.m5sim.org/r/255/diff/11/?file=4387#file4387line216> > > > > Unrelated? Vestigial. It took two tries to get InOrder con

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

p://reviews.m5sim.org/r/255/diff/11/?file=4440#file4440line78> > > > > Does the PCState patch really obviate the need to check CPUIDs and > > contextIDs too? This seems unrelated to me. No, this was a mistake. I've readded those lines. - Ga

Re: [m5-dev] changeset in m5: O3: Get rid of a bunch of commented out lines.

I didn't. They look more like utility functions that outlived their usefulness to me. Gabe Ali Saidi wrote: > Did you check why these were commented out? It sort of looks like they were > used for debugging... > > Ali > > On Oct 24, 2010, at 2:43 AM, Gabe Black wro

Re: [m5-dev] stores that update their base registers

Gabriel Michael Black wrote: > Quoting Steve Reinhardt : > >> On Fri, Oct 22, 2010 at 10:57 AM, Gabe Black >> wrote: >>>> Is this just to get STUPD to be a single uop instead of two >>>> uops that communicate via a temp reg, without forcing dependent

Re: [m5-dev] static stat?

dual instructions. We never destroy > a static inst when we created it right? Perhaps we could have each static > inst hold an execution count that the code could then aggregate by opcode at > the end of the simulation. > > Ali > > On Oct 24, 2010, at 2:29 PM, Gabe Black wrote

[m5-dev] static stat?

I'm going to instrument M5 to count the number of stupd microops that get executed during a run, and I thought it would be nice to use the fancy stats system we have. Because I want an aggregate of all the times a stupd is executed, I'd like to set up a static stat I can increment that isn't associ

Re: [m5-dev] PAL mode detection in the fetch stage of O3

On 10/23/10 18:18, Ali Saidi wrote: > On Oct 19, 2010, at 12:57 PM, Gabe Black wrote: > >> Gabe Black wrote: >>> nathan binkert wrote: >>> >>>>> Whether there's an interrupt available is already tracked by ISA >>>>> depend

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

It looks like I confused reviewboard. My replies are there, though, if you follow the link. Gabe On 10/24/10 00:30, Gabe Black wrote: > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.

[m5-dev] changeset in m5: O3: Get rid of a bunch of commented out lines.

changeset f166f8bd8818 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f166f8bd8818 description: O3: Get rid of a bunch of commented out lines. diffstat: src/cpu/o3/rob_impl.hh | 172 - 1 files changed, 0 insertions(+),

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

Since replying inline to your top level review isn't possible on reviewboard, I'll respond to that part here and the rest there. Also, thank you to you and Nate for your reviews. I took a little longer than I'd have liked to get back to you considering how much I pestered you guys :-), but I didn't

Re: [m5-dev] Review Request: ISA, CPU, etc: Create an ISA defined PC type that abstracts out ISA behaviors.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/255/#review413 --- - Gabe On 2010-10-14 00:01:15, Gabe Black wrote

Re: [m5-dev] X86 performance

On 10/23/10 01:04, Gabe Black wrote: > On 10/23/10 00:56, Gabe Black wrote: >> On 10/22/10 21:23, nathan binkert wrote: >>>> What do you mean by "given a certain prefix"? X86's encoding is fairly >>>> amorphous, and it's not always possible

Re: [m5-dev] X86 performance

On 10/23/10 00:56, Gabe Black wrote: > On 10/22/10 21:23, nathan binkert wrote: >>> What do you mean by "given a certain prefix"? X86's encoding is fairly >>> amorphous, and it's not always possible to tell early on how big an >>> instruction

Re: [m5-dev] X86 performance

On 10/22/10 21:23, nathan binkert wrote: >> What do you mean by "given a certain prefix"? X86's encoding is fairly >> amorphous, and it's not always possible to tell early on how big an >> instruction will be. It's possible in general of course, so it depends >> on what you actually mean there. Wo

[m5-dev] changeset in m5: Configs: Stop setting the "mem" parameter in sp...

changeset fa706473bcd5 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=fa706473bcd5 description: Configs: Stop setting the "mem" parameter in splash2 config files. This parameter is no longer used, and trying to set it like these scripts were gives a sim

Re: [m5-dev] X86 performance

nathan binkert wrote: >> I'd still really encourage you to work on cutting out the middleman >> and find a way to go straight from raw bytes to StaticInsts via a >> cache. I really don't see any long-term benefit to doing this in two >> stages. I agree that we don't want a proliferation of code p

[m5-dev] Review Request: Configs: Stop setting the "mem" parameter in splash2 config files.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/278/ --- Review request for Default. Summary --- Configs: Stop setting the "mem" parame

Re: [m5-dev] X86 performance

Steve Reinhardt wrote: > So I've always felt that for x86 we should move to having the raw > instruction bytes and a length field in the StaticInst so that we can > check for decode page cache hits without going through the predecoder. > Wouldn't this solve both of your problems, since in the hit

Re: [m5-dev] stores that update their base registers

Steve Reinhardt wrote: > Having instructions internally manage undoing state like that in what > is supposed to be a functional description of instruction semantics > seems pretty odd to me. I confess that I haven't followed all the ins > and outs of this issue closely, but what problem is this ch

[m5-dev] changeset in m5: X86: Implement genMachineCheckFault.

changeset 32496de51017 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=32496de51017 description: X86: Implement genMachineCheckFault. Even though this shouldn't ever be used, it might get called speculatively and shouldn't panic. diffstat: src/arch/x8

[m5-dev] changeset in m5: ISA: Simplify various implementations of comple...

changeset 7733c562e5e3 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=7733c562e5e3 description: ISA: Simplify various implementations of completeAcc. diffstat: src/arch/alpha/isa/mem.isa | 15 + src/arch/arm/isa/templates/mem.isa | 36 +

[m5-dev] changeset in m5: X86: Make syscall instructions non-speculative ...

changeset ce987fa77797 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=ce987fa77797 description: X86: Make syscall instructions non-speculative in SE. diffstat: src/arch/x86/isa/decoder/one_byte_opcodes.isa | 3 ++- src/arch/x86/isa/decoder/two_byte_opcodes.isa | 6 +

[m5-dev] changeset in m5: ARM: Don't pretend to writeback registers in in...

changeset fe91d5e2c374 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=fe91d5e2c374 description: ARM: Don't pretend to writeback registers in initiateAcc. diffstat: src/arch/arm/isa/templates/mem.isa | 19 --- 1 files changed, 0 insertions(+), 19 delet

[m5-dev] X86 says hello

Hey! I just successfully ran hello world in x86 on O3! This does NOT imply that x86 works generally on O3, only that it didn't choke on its own tongue running hello world. There are still significant holes to be filled in, major performance issues to sort out, etc. Also, this won't be available to

[m5-dev] X86 performance

I have a simple change which adds code to x86's STUPD microop that saves the old value of the base register into a backup int as described before. I wanted to know how that affected performance of x86 simulation because I expected it to be very minor, but I wanted to make sure. Unfortunately runnin

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