* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing passed.
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic passed.
* build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed.
*
I'm not seeing that thread in the archives...(no mail list search feature)?
anybody recall the subject line there?
On Mon, Feb 23, 2009 at 11:58 PM, Ali Saidi sa...@umich.edu wrote:
Take a look at one of the mailing list archives.
Ali
On Feb 23, 2009, at 11:51 PM, Korey Sewell wrote:
So
This is the mail system at host daystrom.m5sim.org.
I'm sorry to have to inform you that your message could not
be delivered to one or more recipients. It's attached below.
For further assistance, please send mail to postmaster.
If you do so, please include this problem report. You can
delete
http://thread.gmane.org/gmane.comp.emulators.m5.devel/2314/focus=2328
Ali
On Feb 25, 2009, at 10:21 AM, Korey Sewell wrote:
I'm not seeing that thread in the archives...(no mail list search
feature)?
anybody recall the subject line there?
On Mon, Feb 23, 2009 at 11:58 PM, Ali Saidi
Can you commit?
Thanks,
Nate
On Wed, Feb 25, 2009 at 8:59 AM, Ali Saidi sa...@umich.edu wrote:
That fixed it.
Ali
On Feb 25, 2009, at 1:37 AM, nathan binkert wrote:
Sorry. It should be event.Event... Does that fix it?
On Tue, Feb 24, 2009 at 10:27 PM, Ali Saidi sa...@umich.edu wrote:
Please run all the regressions before you do. I'm almost ready to push
and I'd hate to start checking everything again.
Gabe
nathan binkert wrote:
Can you commit?
Thanks,
Nate
On Wed, Feb 25, 2009 at 8:59 AM, Ali Saidi sa...@umich.edu wrote:
That fixed it.
Ali
On Feb 25, 2009, at
This change won't affect the regressions. It's only when you use the
--trace-start command line option.
On Wed, Feb 25, 2009 at 9:29 AM, Gabe Black gbl...@eecs.umich.edu wrote:
Please run all the regressions before you do. I'm almost ready to push
and I'd hate to start checking everything
changeset bdef71accd68 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bdef71accd68
description:
CPU: Get rid of translate... functions from various interface classes.
diffstat:
19 files changed, 74 insertions(+), 420 deletions(-)
src/arch/x86/isa/microops/ldstop.isa
changeset 73084c6bb183 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=73084c6bb183
description:
ISA: Replace the translate functions in the TLBs with translateAtomic.
diffstat:
21 files changed, 40 insertions(+), 38 deletions(-)
src/arch/alpha/tlb.cc |
changeset 41b18fe25a0e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=41b18fe25a0e
description:
SPARC: Adjust a few instructions to not write registers in initiateAcc.
diffstat:
3 files changed, 27 insertions(+), 15 deletions(-)
src/arch/sparc/isa/decoder.isa
changeset 8091ac99341a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8091ac99341a
description:
CPU: Implement translateTiming which defers to translateAtomic, and
convert the timing simple CPU to use it.
diffstat:
15 files changed, 454 insertions(+), 198
changeset 09065e8e9c50 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=09065e8e9c50
description:
X86: Update stats for in place TLB miss handling.
diffstat:
24 files changed, 233 insertions(+), 231 deletions(-)
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
changeset 29cecf4fe602 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=29cecf4fe602
description:
X86: Fix the timing mode of the page table walker.
diffstat:
2 files changed, 25 insertions(+), 28 deletions(-)
src/arch/x86/pagetable_walker.cc | 47
changeset 541097c69e22 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=541097c69e22
description:
X86: Add makeAtomicResponse to the read/write functions of x86 devices.
diffstat:
8 files changed, 16 insertions(+)
src/arch/x86/interrupts.cc |2 ++
src/dev/x86/cmos.cc
changeset b702f4fdf16c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b702f4fdf16c
description:
X86: Add a check to chks which raises #GP(selector) if selector is NULL
or not in the GDT.
diffstat:
2 files changed, 9 insertions(+), 2 deletions(-)
changeset 6776001c9b92 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6776001c9b92
description:
X86: Add a check to chks to verify a task state segment descriptor.
diffstat:
2 files changed, 11 insertions(+), 2 deletions(-)
src/arch/x86/isa/microasm.isa |2
changeset 76fc2c3e10d2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=76fc2c3e10d2
description:
X86: Fix segment limit checking.
diffstat:
1 file changed, 13 insertions(+), 11 deletions(-)
src/arch/x86/isa/microops/regop.isa | 24 +---
diffs (42
changeset 3d7f94358641 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3d7f94358641
description:
X86: Make exceptions handle stack switching.
diffstat:
1 file changed, 17 insertions(+), 16 deletions(-)
src/arch/x86/isa/insts/romutil.py | 33
changeset 8a633e6a8df1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8a633e6a8df1
description:
X86: Implement the longmode versions of the syscall instruction.
diffstat:
2 files changed, 111 insertions(+), 4 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa
changeset c24a1ffc4ad0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c24a1ffc4ad0
description:
X86: Implement the sysret instruction in long mode.
diffstat:
2 files changed, 79 insertions(+), 5 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa |
changeset ecbd27e5d1f8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ecbd27e5d1f8
description:
X86: Add a trace flag for tracing faults.
diffstat:
3 files changed, 31 insertions(+), 2 deletions(-)
src/arch/x86/SConscript |1 +
src/arch/x86/faults.cc | 24
changeset 8d6e40f38063 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8d6e40f38063
description:
X86: Move where CS is set so CPL checks work out.
diffstat:
1 file changed, 13 insertions(+), 11 deletions(-)
src/arch/x86/isa/insts/romutil.py | 24
changeset f2bfe08dc873 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f2bfe08dc873
description:
X86: Use atCPL0 for accesses that are part of CPU machinery.
diffstat:
1 file changed, 10 insertions(+), 10 deletions(-)
src/arch/x86/isa/insts/romutil.py | 20
changeset c92d57f579b1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c92d57f579b1
description:
CPU: Don't fetch when executing a macroop.
If the CPL changes mid macroop, the end of the instruction might not be
priveleged enough to execute the beginning.
changeset 156cc0770e74 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=156cc0770e74
description:
CPU: Update stats now that there's no fetch in the middle of macroops.
diffstat:
21 files changed, 273 insertions(+), 270 deletions(-)
changeset 7d7df4ad7486 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7d7df4ad7486
description:
X86: Actually check page protections.
diffstat:
1 file changed, 12 insertions(+)
src/arch/x86/tlb.cc | 12
diffs (22 lines):
diff -r 4bbd6239223c -r
changeset c3d88393a1f3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c3d88393a1f3
description:
X86: Add IRQ4 to the Intel MP tables.
diffstat:
1 file changed, 18 insertions(+)
configs/common/FSConfig.py | 18 ++
diffs (28 lines):
diff -r
changeset 516eda09c743 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=516eda09c743
description:
X86: Check src1 for illegal values since that's the index we actually
use.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |
changeset 1c9bea4afc53 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1c9bea4afc53
description:
X86: Add classes that break out the bits of the DR6 and DR7 registers.
diffstat:
1 file changed, 32 insertions(+)
src/arch/x86/miscregs.hh | 32
changeset 80c3baea7444 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=80c3baea7444
description:
X86: Update stats now that prefetch is implemented.
diffstat:
6 files changed, 106 insertions(+), 123 deletions(-)
tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr
changeset d42d507ccdb1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d42d507ccdb1
description:
X86: Implement the mov to debug register intructions.
diffstat:
2 files changed, 12 insertions(+), 2 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa
changeset 367ac7cae7b5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=367ac7cae7b5
description:
X86: Make rdcr use merge and the mov to control register instructions
use the right operand size.
diffstat:
2 files changed, 3 insertions(+), 1 deletion(-)
changeset df55109af564 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=df55109af564
description:
X86: Make the TSS type check actually return a fault if it fails.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |2 +-
changeset c30088a243ad in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c30088a243ad
description:
X86: Add segmentation checks for ldt related descriptors and selectors.
diffstat:
2 files changed, 14 insertions(+), 2 deletions(-)
src/arch/x86/isa/microasm.isa |
changeset 177534612ec0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=177534612ec0
description:
X86: Implement the lldt instruction.
diffstat:
2 files changed, 52 insertions(+), 1 deletion(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa |2
changeset 504e13722ce9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=504e13722ce9
description:
SPARC: Get rid of the setCWP function.
diffstat:
2 files changed, 25 deletions(-)
src/arch/sparc/intregfile.cc | 20
src/arch/sparc/intregfile.hh |
changeset 102863870b47 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=102863870b47
description:
SPARC: Get rid of flattenIndex in the int register file.
diffstat:
2 files changed, 10 deletions(-)
src/arch/sparc/intregfile.cc |8
changeset 34e658a2c4c0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=34e658a2c4c0
description:
SPARC: Get rid of the state keeping track of register frames.
diffstat:
2 files changed, 78 deletions(-)
src/arch/sparc/intregfile.cc | 47
changeset 871fccb3fb7a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=871fccb3fb7a
description:
X86: Implement IST stack switching.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/insts/romutil.py |2 +-
diffs (12 lines):
diff -r
changeset 04ed7a1d9904 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=04ed7a1d9904
description:
Devices: Make the RTC device reflect the use of BCD in its status
registers.
diffstat:
1 file changed, 3 insertions(+), 1 deletion(-)
src/dev/mc146818.cc |4 +++-
40 matches
Mail list logo
