[PATCH v2 19/37] clk: rockchip: rk3576: Use correct mode register for VPLL

[Jonas Karlman]

Change to use correct PLL mode register when VPLL rate is changed.

Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
Changes in v2:
- Split from "rk3576: Fix trivial clock configuration errors"
- Add fixes tag
---
 drivers/clk/rockchip/clk_rk3576.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3576.c 
b/drivers/clk/rockchip/clk_rk3576.c
index 92bde425b0ee..abfd57e2447e 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -49,7 +49,7 @@ static struct rockchip_pll_clock rk3576_pll_clks[] = {
        [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3576_LPLL_CON(16),
                     RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_24m_pll_rates),
        [VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88),
-                     RK3576_LPLL_MODE_CON0, 4, 15, 0, rk3576_24m_pll_rates),
+                    RK3576_MODE_CON0, 4, 15, 0, rk3576_24m_pll_rates),
        [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3576_PLL_CON(96),
                      RK3576_MODE_CON0, 6, 15, 0, rk3576_24m_pll_rates),
        [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3576_PLL_CON(104),
-- 
2.55.0