Re: [casper] C API

Hi Charles: The Roach C/C++ library is already part of Roach PowerPC Linux OS. The OS running on Roach is call Borph developed by the Berkeley Uni. All the registers and buffer will be visible as part of the OS device driver after the BOF file is excuted. Your C executable file has to be compi

Re: [casper] The casper library status

Hi Andrew: Thanks a lot for your graceful help. It is very clear for me. Cheers Wan -Original Message- From: Andrew Martens [mailto:martens.and...@gmail.com] Sent: Thursday, 28 April 2011 9:19 PM To: Francois Kapp Cc: Cheng, Wan (CASS, Marsfield); millen...@skatelescope.org; Beresford,

[casper] the support of windows 64bits

Hi: I want to install the casper library to windows 64bits. But will the mkbof.exe work in windows 64bits? Or someone has the 64bits version mkbof.exe? Thanks Wan

[casper] The delay in pfb_real_fir

Hi: I have not update my library for some time. Today after I upgrade to the latest library, I find the delay of converter in pfb_real_fir becomes Nan. This is the details of the error: "The parameters set for this block did not match the expected signatures. Specifically, - The block was u

Re: [casper] Green FFT fixed

Hi Jason: The plots you sent is a accumulated result or it is a single FFT output. Thanks Wan -Original Message- From: Jason Manley [mailto:jasonman...@gmail.com] Sent: Thursday, 17 June 2010 7:31 PM To: Cheng, Wan (CASS, Marsfield) Cc: casper@lists.berkeley.edu Subject: Re: Green FFT

Re: [casper] Green FFT fixed

Hi Jason: Thanks. This will also explain why the latest casper library cannot work with me. But it seems that FFT block can always work when I setup it up at first time. But I cannot modify it because it will be broken. Cheers Wan -Original Message- From: Jason Manley [mailto:jasonma

Re: [casper] Green FFT fixed

Hi Jason: I guess if I build my own blocks with 'i' or 'j' as a loop, it would be a problem. But if I If I did not write any matlab scripts and only use the casper library standard green block, I would not be affect. Is this right? And could you clarify in which case user can overwrite the casp

Re: [casper] DC part of FFT output

Hi Dan: Thanks a lot. Your suggestions are really useful and helpful. Cheers Wan -Original Message- From: Dan Werthimer [mailto:d...@ssl.berkeley.edu] Sent: Monday, 18 January 2010 11:43 AM To: Cheng, Wan (CASS, Marsfield) Cc: jasonman...@gmail.com; casper@lists.berkeley.edu Subject:

Re: [casper] DC part of FFT output

Hi Dan: Thanks for your information again. But I am not still not very sure about how the noise floor steps is generated. Do you believe this is because I am using the maximum dynamic range? I can achieve some improvement if I use smaller dynamic range? Thanks Wan -Original Message-

Re: [casper] DC part of FFT output

HI Dan: Thanks a lot. I will try your solution. In fact, I thought I could put a register there in order to tune it. Thanks Wan -Original Message- From: Dan Werthimer [mailto:d...@ssl.berkeley.edu] Sent: Friday, 15 January 2010 12:47 PM To: Cheng, Wan (CASS, Marsfield) Cc: jasonman..

Re: [casper] DC part of FFT output

Hi Jason: Thanks for your important information. But one point I could not understand is the shift bits of FFT. I guess it is used to shift the output at every FFT stage. So why data only in top 10 bits? 10 bits data multiplies 8 bits coeff, the data should be in all 18 bits? Wan -Origi

Re: [casper] DC part of FFT output

Hi Dan: Thanks for your suggestions. I believe we get enough SNR and dynamic range. We just suspect if there are some potential problems in our design. Calibration is our current solution, and I believe it will work well in our system. And I tried all different rounding options, I found round

Re: [casper] DC part of FFT output

Hi Liu: Thanks for your suggestion. We are using a 10 bit ADC card, so the input to PFB for us is fix_10_9. The noise floor steps only become obvious if we use higher channels FFT, such as 32K, and accumulate for some time. Thanks Wan From: Zhiwei Liu [mailto

Re: [casper] DC part of FFT output

Hi Aaron: Thanks for your reminding. I am pretty sure my input is quite low compared to the full scale. Thanks again. Wan From: Aaron Parsons [mailto:aaronrpars...@gmail.com] Sent: Wednesday, 13 January 2010 3:19 PM To: Dan Werthimer Cc: casper@lists.berkeley.e

Re: [casper] ROACH progress.

Hi Glenn: I updated casper library last week. I found the 32K FFT could not generate right output even I modified the max coefficient depth to 13 which helps me fix this problem last time. 16K FFT is all right. Any suggestions? Thanks a lot. Wa n From: G Jon

Re: [casper] Capser FFT output level with Matlab FFT output level

Hi Andrew: Thanks. Your answer is very clear and solve my problem. I should divide it by 2^9 to get right power level. And I still could not understand one thing: The casper fft spectrum output for a single carrier (1 point) looks much narrower than mablab float point fft and fix point fft(3 p

Re: [casper] Fwd: Re: SPDO ROACH spectrometer

Hi Jason: Thanks for your quick reply. But I am still not sure how I can use KATCP to transfer binary files. What I did is to capture the output of wordread command which is in ASCII and transfer the data back to my program. I only can see the ASCII data. Is there any other way to read it? Th

Re: [casper] Fwd: Re: SPDO ROACH spectrometer

Hi Jason: I guess the latest CPLD is quite important for us. But for Uboot, I am not sure. Will all PPC registers be re-initialized again in the linux core? Or the linux core use default value initialized by Uboot? Will Uboot load OS into Dram before set the program pointer to the OS start addr

Re: [casper] Fwd: Re: SPDO ROACH spectrometer

Hi Jason: Thanks for you help. But I could not find the tut4 in workshop. Could you please provide me the exact link? Thanks. As I know, the KATCP only provide data in ASCII. Is this right? And for KATCP, all command and data are transferred by network. But we expeirence some network failure w

Re: [casper] Fwd: Re: SPDO ROACH spectrometer

Hi Jason: As Kjetil mentioned, we are only working on OS. The OS crash and network problem appears without our program running. Cheers Wan -Original Message- From: Jason Manley [mailto:jasonman...@gmail.com] Sent: Wednesday, 4 November 2009 7:22 PM To: Wormnes, Kjetil (ATNF, Marsfiel

Re: [casper] Fwd: Re: SPDO ROACH spectrometer

Hi Jason: Could you please let me know how do you get data using KATCP? I also used KATCP for a while. But I can not find an efficient way to read a large mount data from FPGA, like 1GB data stored in the Dram. And there are a few difficulties as well. Such as, network is not reliable, OS crash

[casper] How to get the FPGA or Roach temperature

Hi: Is there anyway I can get the FPGA or Roach temperature? Thanks Wan

Re: [casper] Fwd: Re: SPDO ROACH spectrometer

Hi Jason: Thanks for your information. We did experience the SSH error, such as bad packet length or Corrupted MAC address. I am not exactly sure if it is a software bug or not. I had used SSH for a long time. I did not see any connection broken so frequently like Roach. The Ethernet problem

Re: [casper] The Roach GPIO error in casper library

Hi Henry: Thanks for your suggestions. It solved this problems. Cheers Wan -Original Message- From: Henry Chen [mailto:hche...@ssl.berkeley.edu] Sent: Monday, 19 October 2009 10:58 AM To: casper@lists.berkeley.edu Subject: Re: [casper] The Roach GPIO error in casper library Hi Wan,

Re: [casper] Slow HD write speed

Hi David: I recompile the kernel without OHCI. And the disk write is much faster. Problem is solved. Thanks a lot. Cheers Wan -Original Message- From: David George [mailto:david.geo...@ska.ac.za] Sent: Thursday, 15 October 2009 6:31 PM To: Wormnes, Kjetil (ATNF, Marsfield) Cc: casper

Re: [casper] The Roach GPIO error in casper library

Hi David: It seems to start working now. But I have not finished the compiling. I check the mhs file, the function is implemented correctly. Hope all pin definition are right. Wan -Original Message- From: David George [mailto:david.geo...@ska.ac.za] Sent: Friday, 16 October 2009 6:0

Re: [casper] The Roach GPIO error in casper library

Hi David: Thanks for your information. But I find after update to the head release, I could not compile my design any more. An error is received: # ## Block objects creation ## # Problem with block: a10hs1/XSG core config Error using ==>

[casper] The Roach GPIO error in casper library

Hi All: When I use ROACH:GPIO in casper library, I was told "undefined routing table for hardware system: ROACH(gpioA)". It is an error, and I can not generate bitstream. Anybody has some idea about this error? Thanks Wan

Re: [casper] ROACH progress.

Hi Dan: The problem is fixed by using all the coefficients. And I also check the size of coefficient of different size FFT. I found FFT size(bits number) is always equal or smaller than the coefficient size. So I guess the coefficients are not picked up correctly in Casper design? Any idea?

Re: [casper] How to read and write ADC register

Hi David: Thanks for your information. My problem is I did not add a more entry in the core_info.tab file. Now I could read and write the ADC control memory space. But I meet another problem immediately. It seems that only one of 6 bus2ip_ce will response my read and write. Is there anyone ha

[casper] How to read and write ADC register

Hi: I am working on a customized designed ADC board for Roach. The address is allocated successfully showed in platgen.log Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC... Address Map for Processor epb_opb_bridge_inst (00-0x) sys_block_inst opb0 (0x0002-0x0002fff

Re: [casper] bit width setting of pbf filter and fft widtband

Hi Mark: Thanks for your help. Wan -Original Message- From: Mark Wagner [mailto:mwag...@eecs.berkeley.edu] Sent: Wednesday, 22 July 2009 8:11 AM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@lists.berkeley.edu Subject: Re: [casper] bit width setting of pbf filter and fft widtband Hi Wan

[casper] bit width setting of pbf filter and fft widtband

Hi: Is there any instructions to set the bit width of PFB and FFT? When I set output bitwidth of PBF to 25, I get a wrong spectrum output. But it works well when the bitwidth is set to 18. I guess something might be over flow in the FFT block. Any idea on the bitwidth of PFB and FFT? Thanks

Re: [casper] The max frequency of DD2 DRAM of ROACH

Hi David: Thanks for your answer. Wan -Original Message- From: David George [mailto:david.geo...@ska.ac.za] Sent: Wednesday, 1 July 2009 4:57 PM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@lists.berkeley.edu Subject: Re: [casper] The max frequency of DD2 DRAM of ROACH Hi Wan. The DRA

[casper] The max frequency of DD2 DRAM of ROACH

Hi: What's the max frequency of DRAM on Roach? From Xilinx MIG user guide page 323, it seems that only 150MHz is possible. Any idea? By the way, what's the current status of DRAM of Roach? All library working, or still in development. Thanks Wan

Re: [casper] about the shift input of FFT

Hi Andrew: Thank you so much Andrew. It is very clear for me. Cheers Wan From: Andrew Martens [mailto:martens.and...@gmail.com] Sent: Thursday, 25 June 2009 4:06 PM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@lists.berkeley.edu Subject: Re: [casper] about the sh

[casper] How to use the read command in tcpborph server?

Hi: The 'wordread' command works perfectly in my program. But it is a little bit slow. I would like use 'read' command. But I could not get right data through my tcp socket. Anybody has some example code to show me how to use tcpborph server 'read' command? Thanks Wan

Re: [casper] about the shift input of FFT

Hi Andrew: Thanks for your help. I am not really sure what's the 'convert with overflow indication'. Anyway, I could read the FFT output correctly now. Thanks again. Wan From: Andrew Martens [mailto:martens.and...@gmail.com] Sent: Monday, 22 June 2009 8:48 PM

Re: [casper] about the shift input of FFT

Hi Andrew: Thanks for your information. I am still not sure on next two options in fft_wideband_real: Number bits above which to store stage's coeffcients in BRAM Number bits above which to store stage's delay in BRAM Thanks Wan From: Andrew Martens [mailto:ma

Re: [casper] about the shift input of FFT

Hi Andrew: Now I can find the OF output from FFT module is high. Does this mean the FFT is overflow? But I already set all shift bit to '1'. I an not very sure how many shift bits the FFT module has. I just give it 32 bits width '1'. Thanks Wan From: Andrew M

[casper] about the shift input of FFT

Hi: Could anyone give me some idea on the function of shift input pin of FFT? I find some example design set it to all 1s. This means every stage are set to shift 1. What does this mean? Thanks Wan

Re: [casper] problem of ADC 1.1 card with Roach

Hi Henry: Thanks. But if I remove my 3 wire constraints from the library data folder UCF file, I could not see any 3 wire constraints in the implement UCF file. So I guess for some reason, this part could not function in my design. Do they function in your design? Wan -Original Message---

Re: [casper] problem of ADC 1.1 card with Roach

Hi Henry: Could you please tell me where are they? I could not see the 3 wire control pin constraints in the gen_ucf.m of @xps_adc. Thanks Wan -Original Message- From: Henry Chen [mailto:hche...@ssl.berkeley.edu] Sent: Friday, 19 June 2009 10:22 AM To: Cheng, Wan (ATNF, Marsfield) Cc

Re: [casper] problem of ADC 1.1 card with Roach

Hi David: Thanks you for your help. I rebuild my design today. It seems all right now. I can read valid data from all diff pairs. I might not do right thing in the first build. Thanks for your information again. By the way, the in capsper 10.1 trunk, I did not find the pin allocation for the

[casper] question on sync pulse

Hi: After reading the memo of sync pulse, I still feel a little bit confused. I use a PFB in my design. So I guess I have to include the order of PFB into the calculation. The order of PFB is 2. But there are two stage in the PFB. There are 2 taps in the second stage as well. So I set the reor

Re: [casper] problem of ADC 1.1 card with Roach

HI George: Thanks for your help. I find ADC chip is not set into a right mode because only 2 of 4 diff pairs give me right data. So I find the 3 wire control pins are not allocated in the UCF file. I modify the UCF file according to the schematic. But I find I still could not get right data an

[casper] problem of ADC 1.1 card with Roach

Hi: Now I am using ADC 1.1 card with Roach. I find two things: 1. I could not find the three control wires in the FPGA UCF file. 2. After I add the three control wires into UCF file, I could not see the clock output from FPGA. Anybody had used the ADC card with Roach? Thanks Wan

Re: [casper] The failure in compiling the cross compiler

Hi Billy: The problem is fixed. Thanks Wan -Original Message- From: William Mallard [mailto:w...@berkeley.edu] Sent: Saturday, 6 June 2009 2:28 PM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@lists.berkeley.edu Subject: Re: [casper] The failure in compiling the cross compiler wan.ch..

Re: [casper] FW: How to use snap?

Hi Glenn: Thanks for your quick answer. Now I could read ADC data from Roach through the snap_bram. But unfortunately, it seems that the data I read is not right. I am using the tcpborphserver at port 7147.The command is wordread. Do you have some experience with Roach? Thanks Wan __

Re: [casper] FW: How to use snap?

HI Glenn: Thanks for your great help. By the way, what's the offset when I read from snap_bram? 1 or 4? Thanks Wan From: G Jones [mailto:glenn.calt...@gmail.com] Sent: Wednesday, 27 May 2009 11:31 AM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@lists.berkeley.ed

[casper] The failure in compiling the cross compiler

Hi: I meet a failure when I try to compile the powerpc cross compiler. At this step: $ dpkg-buildpackage -us -uc -rfakeroot -b > ../gcc.build 2>&1 || echo 'Build error.' I received: dpkg-checkbuilddeps: Unmet build dependencies: automake1.9 gawk dpkg-buildpackage: warning: Build dependencies/co

Re: [casper] FW: How to use snap?

Hi Glenn: Thanks for your help. The only thing I am surprised is I could read the snap_ram out by specifying the offset. Cheers Wan From: G Jones [mailto:glenn.calt...@gmail.com] Sent: Wednesday, 27 May 2009 11:31 AM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@

[casper] FW: How to use snap?

Hi Henry: Could you please give me some idea about snap block? Thanks Wan From: Cheng, Wan (ATNF, Marsfield) Sent: Tuesday, 26 May 2009 4:44 PM To: 'casper-boun...@lists.berkeley.edu' Subject: FW: How to use snap? Any idea? How can I access the whole block ram

Re: [casper] Roach issue: Stale NFS file handle error is reported

Hi Janson: Only update the Uboot and Roach core? My understanding is the new uboot will boot from USB stick instead of on board busybox? Or the busybox on board also need to be upgraded? Thanks Wan -Original Message- From: Jason Manley [mailto:jasonman...@gmail.com] Sent: Tuesday, 26

Re: [casper] Roach issue: Stale NFS file handle error is reported

Hi Jason: We have found what the problem is. I have to use reboot command before I shutdown or reboot Roach. Or the file system might be broken. I think this is why. But why reboot could not work? I am told the runlevel could not determined. Following information is given: roach:~# reboot WA

Re: [casper] Roach issue: Stale NFS file handle error is reported

Hi Jason: I find another thing interesting. If I modify the /etc/network/interfaces file at other PC, and then replace the file with the modified file, the problem does not appear. Any idea? Thanks Wan -Original Message- From: Jason Manley [mailto:jason_man...@hotmail.com] Sent: Fr

Re: [casper] Roach issue: Stale NFS file handle error is reported

Hi Jason: Any idea? Thanks Wan -Original Message- From: Cheng, Wan (ATNF, Marsfield) Sent: Friday, 22 May 2009 4:48 PM To: 'Jason Manley' Cc: casper@lists.berkeley.edu Subject: RE: [casper] Roach issue: Stale NFS file handle error is reported Hi Jason: Thanks for you great help. I r

Re: [casper] Roach issue: Stale NFS file handle error is reported

Hi Jason: Thanks for you great help. I reformat my USB stick and copy a fresh Roach core into it. Then I insert the following configuration into /etc/network/interfaces with VI. auto eth0 iface eth0 inet static address 130.155.199.211 netmask 255.255.240.0 gateway 130.155.192.2 Then I reboot th

Re: [casper] Roach issue: Stale NFS file handle error is reported

Hi Jason: Thanks for your great help. But even auot eth0 is added, the network still could not come up automatically. And my USB file system is FAT32 R/W. I am not sure what the file system is for the on board flash. I agree with you that this should be a filesystem problem. I think this pro

[casper] Roach issue: Stale NFS file handle error is reported

Hi: In order to set a static IP address to roach Ethernet port, I insert the following configuration to the /etc/network/interfaces: iface eth0 inet static address 130.155.199.211 netmask 255.255.240.0 gateway 130.155.192.2 dns-nameservers 130.155.194.32 130.155.192.40 Then I ifdown eth0 ifup

Re: [casper] an issue of the ethernet port of Roach

Hi William: A proxy agent set in the APT configure. I rename the 99proxy and fix this problem Thanks for your help. Cheers Wan -Original Message- From: William Mallard [mailto:w...@berkeley.edu] Sent: Friday, 22 May 2009 2:36 PM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@lists.berk

[casper] an issue of the ethernet port of Roach

Hi: I have to turn on and turn off Roach ethernet port before it works. The commands I used: ifdown eth0 ifup eth0 Or it could not work. I try to insert these two commands into init script. But it is not successful. Any idea? Thanks Wan

[casper] roach apt-get could not find right server

Hi: I am trying to use the apt-get install on the Roach debian. But it seems it always try to download file from a private IP address 192.168.1.21. roach:~# apt-get install dhcp Reading package lists... Done Building dependency tree... Done The following NEW packages will be installed: dhcp 0

Re: [casper] FPGA could not be configured

Hi Jason: Thanks for your suggestion. And is there any known working Roach core available now? I also suspect the Roach board we have might be faulty because I found the CPLD on our Roach is blank. I am not sure if the board we have is tested properly or not. If I have a working core, I could

Re: [casper] FPGA could not be configured

Hi: I could build a ROACH core finally today. The size is much bigger 1GB than the core I downloaded from wiki trunk 250MB. But the core could not boot and an error imformation is kept showing: Can't open /dev/ttyS0: No such file or directory process '/sbin/getty 115200 ttyS0' (pid 324) exited.

Re: [casper] FPGA could not be configured

Hi William: Just for your information. I receive the following error information: cocoparra-mm:/usr/local/src/cross-toolchain-powerpc# cd gcc-4.3-4.3.2/ cocoparra-mm:/usr/local/src/cross-toolchain-powerpc/gcc-4.3-4.3.2# export GCC_TARGET=powerpc cocoparra-mm:/usr/local/src/cross-toolchain-powerp

Re: [casper] FPGA could not be configured

Hi William: I think the instructions for obtaining and building the kernel could not be followed. I do my best to follow it. But some errors always come out after a few steps. I still face some compiling errors after solving a lot of fails. I guess I need a serious Linux programming training.

Re: [casper] FPGA could not be configured

Hi Henry: I try to download a bitstream which is created with pof file at same time with JTAG. It is successful. Have you made any progress with Roach Debian core? Can you run pof file with that core? Thanks. Wan Attached Jtag download log: // *** BATCH CMD : Program -p 1 Maximum TCK operat

Re: [casper] FPGA could not be configured

Hi Henry: I am quite sure the target platform is for SX95T. Please see the following par message: #--# # Starting program par # par -w -ol high system_map.ncd system.ncd system.pcf #--# Release 10.1.03 -

Re: [casper] DRAM on ROACH

Hi David: Is the library is available now? Wan -Original Message- From: David George [mailto:david.geo...@ska.ac.za] Sent: Wednesday, 14 January 2009 5:18 PM To: Cheng, Wan (ATNF, Marsfield); casper@lists.berkeley.edu Subject: DRAM on ROACH Hi Wan. We use the Xilinx Memory Interface

Re: [casper] usage of snapshot 64

Hi Andrew: Thanks for your information. But it could not help me. I mean the documents do not tell me how the CPU read the data from the block ram. I only know how to write data into block ram through the documents. Wan From: Andrew Siemion [mailto:siem...@berk

[casper] usage of snapshot 64

Hi Anybody could tell me how to use snap64? From the description, I could not see how the CPU could access the memory in FPGA. It seems that the CPU could not write address into the snap64 to specify the accessing address. Wan

Re: [casper] DRAM on ROACH

Hi David: Thanks for your answer. But I am afraid this core is not included into the released 10.1 library. Could you please email this core to me? Thanks Wan -Original Message- From: David George [mailto:david.geo...@ska.ac.za] Sent: Wednesday, 14 January 2009 5:18 PM To: Cheng, Wan

[casper] Any body has the DD2 DRAM controller for the ROACH card?

I know the ROACH card is tested, but any body has the controller code or library? Thanks. Wan

Re: [casper] the recapture bits are lost in ADC interface

Hi David: Thanks. I checked the map report and it gives me a lot of removing warning. Some warning are showed here: WARNING:LIT:243 - Logical network flowtest2_adc_user_data_valid has no load. WARNING:LIT:395 - The above warning message base_net_load_rule is repeated more times for the

[casper] the recapture bits are lost in ADC interface

Hi: I am working with 10.1 library. For the following code in the adc_interface.vhd ADC_DATA_DDR: for i in adc_dataeveni'range generate adc_dataeveni_ddr: ddr_input port map ( clk => adc_clk, d => adc_dataeveni(i), qrise => adc_datai_ddr(i + 24), qfall => adc_datai_ddr(i + 8) );

Re: [casper] Toolflow basics

Hi Henry: Thanks Henry. I guess the pcores ports creation are quite different from class to class. Some class, like ADC, some ports information are created from constructor function because these ports could not be seen in the simulink design. Some classes, like xps_bram, are created from gen_m

Re: [casper] The ADC module in ROACH

Hi Henry: Thanks for your great help. And by the way, I find the Xilinx gateway out block which I drag from the Xilinx blockset can not been identified by the command: gateways_blk_out = find_system(blk, 'FollowLinks','on','LookUnderMasks','all','masktype','Xilinx Gateway Out Block') But the

[casper] The ADC module in ROACH

Hi: Anybody has the full version UCF file of ROACH board? I find only some pins are located in the UCF file of 10.1 library. And where is ADC VHDL code included into top level design? I guess it is the system.mhs file. But I find the gen_xps_files could not include the ADC module into system.m

Re: [casper] Casper 10.1 library issue

Hi Dan: That will be good. I will do my best. Hope I could help on Casper development. By the way, how does someone build designs for roach successfully without running BORPH? Thanks Wan -Original Message- From: Dan Werthimer [mailto:d...@ssl.berkeley.edu] Sent: Friday, 21 November 200

Re: [casper] Casper 10.1 library issue

Hi Henry: Why we have to use bee_xps to generate the bitstream instead useing sysgen? Wan -Original Message- From: Henry Chen [mailto:hche...@ssl.berkeley.edu] Sent: Friday, 21 November 2008 10:23 AM To: Cheng, Wan (ATNF, Marsfield) Cc: martens.and...@gmail.com; casper@lists.berkeley.e

Re: [casper] Casper 10.1 library issue

Hi: Thanks Andrew. Any anyone know how we could use these matlab script files? Are they linked to simulink automatically or we have to use them during the library development manually? Thanks Wan From: Andrew Martens [mailto:martens.and...@gmail.com] Sent: Thu

Re: [casper] Casper 10.1 library issue

Hi Andrew: Thanks for your information. I agree that it is not a simple process. Except the casper_library and casper_library, there is another mystery fold in 10.1 library, XPS_lib. Could you tell me what's this for? Another question is: how sysgen could find correct HDL files/cores when we ge

Re: [casper] Question on control software on the ROACH

Hi John: Could you tell me where is the snap block? Is it a customized block? Thanks Wan -Original Message- From: John Ford [mailto:jf...@nrao.edu] Sent: Saturday, 8 November 2008 12:33 AM To: Cheng, Wan (ATNF, Marsfield) Cc: casper@lists.berkeley.edu Subject: Re: [casper] Question on

[casper] Question on control software on the ROACH

Hi all: I just could not find any documents in casper web site talking about the control software running in the PowerPC. So my first question is how can I use the interface between FPGA and PowerPC? For example, how can I design a block memory which can be written by ADC module and can be rea

Re: [casper] Casper library basic setup

Hi Henry: Thanks for your reply. I am not sure what's your mean that 2^11 real FFT gives 2^10 complex channels. Could you please give me deeper explanation? My understanding is only half output sequence is positive frequency and the output sequence is separated into two. So the pulse period is

Re: [casper] Casper library basic setup

Hi Henry: I resend my simple design file to you and could you please help to check anything wrong with it? I think there are only three type of input signal: Sync, shift and AD output. Now I can not see anything wrong with them. But output still is period pulse instead of single pulse spectrum.

Re: [casper] Casper library basic setup

Hi Andrew: Another strange thing is I still get the output no matter I set Sync to "0" or "1". I think Sync could be considered as a sync reset signal. I should not get anything out if I fix the sync to "1". Wan From: Andrew Martens [mailto:martens.and...@gmail

Re: [casper] Casper library basic setup

Hi Andrew: Thanks. I change the sync period. But it looks still wrong. I put the modified mdl file again. Anybody could find something wrong? The attached are the mdl file and the output wave. Thanks Wan From: Andrew Martens [mailto:martens.and...@gmail.com] S

Re: [casper] Casper library basic setup

Hi Andrew: Thanks for your help. According the sync_memo: My example is: 2 order-2 reorder blocks, order-9 unscrambler, 4 input, 2048 channels. minimum sync period = 2*9*2048/4 = 9216. And I set the counter to 9215. I guess the sync period is all right. Wan F

[casper] Casper library basic setup

Hi all: I build a very basic module with PFB and FFT. But the output looks not right. Anybody has anyidea? What's wrong with it? The attached is the mdl file. Thanks. Wan RFI_test5.mdl Description: RFI_test5.mdl

Re: [casper] Casper 10.1 library issue

HI Andrew: Thank you for your answer. Now I have better idea on how the libraries are organized. What I am do is to setup the simulink simulation. Do you know the difference among several FFT module provided in the casper library? They are : fft_biplex_real_2x fft_biplex_real_4x fft fft_wideba

Re: [casper] Casper 10.1 library issue

HI Laura: Thanks for your help. You are right. If I set more samples per period, it is more difficult for me to find the difference. I setup the sine wave according your setting, the difference is obvious. I think you explanation for the ADC internal structure is correct. The extra delay in O1

Re: [casper] Casper 10.1 library issue

Hi Laura: When I set the sample time of sine wave to 1/8, all outputs are still same. I look at the subsystem of ADC module, and I find, except O1 has 1 more cycle delay, all other channel have same function. I am not sure how the ADC is implement. Do you have any idea? Thanks Wan __