[PATCH v2 26/37] clk: rockchip: rk3576: Use correct PLL rate for UART divisor

[Jonas Karlman]

Calculate the UART divisor from the CPLL rate instead of the GPLL rate
when CPLL is selected as parent clock.

Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
---
Changes in v2:
- Split from "rk3576: Fix trivial clock configuration errors"
- Add fixes tag
---
 drivers/clk/rockchip/clk_rk3576.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3576.c 
b/drivers/clk/rockchip/clk_rk3576.c
index 7908a3c95765..a7110b86c063 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -1843,7 +1843,7 @@ static ulong rk3576_uart_set_rate(struct rk3576_clk_priv 
*priv,
                div = DIV_ROUND_UP(priv->gpll_hz, rate);
        } else if (!(priv->cpll_hz % rate)) {
                clk_src = CLK_UART_SEL_CPLL;
-               div = DIV_ROUND_UP(priv->gpll_hz, rate);
+               div = DIV_ROUND_UP(priv->cpll_hz, rate);
        } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0) % rate)) {
                clk_src = CLK_UART_SEL_FRAC0;
                div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, 
CLK_UART_FRAC_0), rate);
-- 
2.55.0