The BPLL con registers are located in the main CRU and not in the
BIGCORE CRU.
Remove the unused and incorrect RK3576_BPLL_CON macro.
Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
Signed-off-by: Jonas Karlman <[email protected]>
---
Changes in v2:
- Split from "rk3576: Fix trivial clock configuration errors"
- Add fixes tag
---
arch/arm/include/asm/arch-rockchip/cru_rk3576.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
index 380151e0f8d5..12257797445e 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
@@ -140,7 +140,6 @@ struct pll_rate_table {
#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE +
0x800)
#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE +
0xa00)
-#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE +
0x300)
#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE +
0x800)
#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE +
0xa00)
--
2.55.0
