I think that the query language is a very important basis.
>From this point Protel can easily make further dialog boxes which eliminates
having to understand the query language. So that the queries can be
conducted more like was available in Protel99SE.
This will ease the transition for many peop
Manhatten length is the sum of the x and y lengths of a particular route.
In most cases it's assumed to be the shortest distance to route between two
points. For a starting point of (2,6) and a finish point of (10,12) the
Manhatten distance is 8+6 = 14.
> -Original Message-
> From: Mr.
day, February 12, 2004 5:43 PM
Subject: Re: [PEDA] What's wrong with my query language program
> On 03:32 PM 12/02/2004, Bevan Weiss said:
> >IsOblique will get all tracks whose angle is not a multiple of 90degrees.
> >Hence if you have a 60degree track it will also be picked up
IsOblique will get all tracks whose angle is not a multiple of 90degrees.
Hence if you have a 60degree track it will also be picked up...
> Are they short tracks? Your query will pick up all short tracks
regardless
> of angle - lets say you have the PCB units set to metric. Lets say you
> have a
Try it using the division... it makes more sense if you're trying to judge
based on an angle.
As for how to remove the fractional part, you would simply use the round
function. However it looks like this is not working properly (at least I
can't get it to)
Can someone else try something simple lik
IL PROTECTED]>
Sent: Thursday, February 12, 2004 10:14 AM
Subject: Re: [PEDA] What's wrong with my query language program
> you need to you use the abs value of each coordinate
>
> Bevan Weiss wrote:
>
> > - Original Message -
> > From: "Mr. Zhang Yan
- Original Message -
From: "Mr. Zhang Yangtian" <[EMAIL PROTECTED]>
To: "Protel" <[EMAIL PROTECTED]>
Sent: Thursday, February 12, 2004 4:47 AM
Subject: [PEDA] What's wrong with my query language program
> I had write one line of query language in ProtelDXP as the following:
>
> IsTr
What kind of mirroring are you actually talking about?
horizontal or vertical?
And how are you creating your PCB footprint?
should be with pin 1 (of say a DIP) in the upper left hand corner
Then when you place the footprint on the top layer of your board pin 1 will
again be in the upper left hand
Hmm you say selection box. I assume you mean dropdown box?
The global criterion for the selection is 'Any', 'Same', 'Different' I
think.
So you had this set on 'Same'?
The selection box itself is just a property of the particular item you've
selected, and is only used if the criterion is set to
And now for the whole thing...
> now for the real quiz
> what is the true derivation of the term 'BNC' ?
> i have heard many differing and 'authoritative' answers
Amphenol believe that they invented the entire connector, and hence it's
named after the engineer that designed it: Carl Concelman.
BN
> now for the real quiz
> what is the true derivation of the term 'BNC' ?
> i have heard many differing and 'authoritative' answers
Amphenol have the opinon that they developed the entire connector
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Make sure that there are no pins on the net defined as open collector
outputs. This would be the most obvious cause of the problem. Other than
that, perhaps the model that you're using for a particular component (IBIS
or similar) has one of the pins on the net designated as an open collector
outp
This came up not so long ago.
Protel has problems with certain traces when they contain loops in the paths
etc.
Otherwise in the signal integrity module, you should be able to select the
nets and get a list of the components on the net. From that you can change
the component model used.
It doesn'
> Hi all
>
> On several occasions I've seen postings here, that suggest checking Gerber
> files for nefarious errors.
> I've examined these files and found them to be text files full of data (a
> lot like EPS files).
> I'm hoping that checking Gerber files doesn't mean understanding the data!
> 8-)
> Hi everybody,
>
> I have a question about the ground and power planes and signal layers that
I must use on my printed circuit board.
>
> This board mainly consists of a virtex 2000 part ( FG1156 ball grid
array,XCV2000E).
>
> I have followed the "xilinx board routability" guidelines and accord
> > > Firstly ALWAYS run anti-virus software.. either that or shut down your
> > > email
> > > both will do the same job.
> > I don't get the people that can state this with such certainty. I
refuse
> to
> > run an antivirus program on my computer, however have shut down all the
> > 'bonus' featur
> Firstly ALWAYS run anti-virus software.. either that or shut down your
email
> both will do the same job.
I don't get the people that can state this with such certainty. I refuse to
run an antivirus program on my computer, however have shut down all the
'bonus' features of Outlook so that all em
> > From: JaMi Smith [mailto:jamismith@;sbcglobal.net]
>
> > With that, I will pose 3 questions to the forum.
> >
> > 1. Should I install an anti-virus program?
> >
> I think so. You already own it, and have had it installed on your machine
> before. and its better to have protection on a machine t
- Original Message -
From: "Robert M. Wolfe" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Sunday, November 03, 2002 1:22 PM
Subject: Re: [PEDA] Silkscreen over pads
> To All,
> Just a thought.
> If there is no means of DRC'ing silkscreen
> with repsect to pads (or
Thanks, I had completely forgotten about those situations where a ground
plane isn't being used...
There are several ways that I can think of to do this, if you give the
router info on the maximum size of the current through the connection, and
the maximum voltage drop across the connection (impl
ther opinions on this are welcome.
Just an update,
Thanks for your time,
Bevan Weiss
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for protel that would allow me to make my own
> >autorouter.
> > > >I know that it seems like a lot of work, however it would really make
the
> > > >product (protel) more functional in my terms.
> > > >
> > > >Any information that people could provide
protel) more functional in my terms.
> >
> >Any information that people could provide me in terms of server
development
> >would also be appreciated.
> >
> >I'm also wondering whether development of a server can be done in C, or
> >whether delphi is the only op
If you've turned off all the design rules, then which layers have you set
the autorouter to use?? This is a design rule...
The other rules to consider, are which corners the router will create and a
clearance between the conductors (gap spacing). These are needed by the
autorouter, else where ca
It's very easy to use, you just set up what the output device is, what the
input device is (in terms of pins) on a particular net. You set up the
output and input device family
Then you can transmit a waveform (rising edge, falling edge, clock) down the
line. And get the waveform at each node.
> >> Once you take over a net you can double click on a pin in the net and
> >> change the model and stimulus for that pin.
> >
> > Is there a way to assign a component a whole IBIS file (ie the IBIS file
> for
> > that component includign pins etc) as opposed to just each individual
> pin??
> > I
- Original Message -
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, October 11, 2002 4:29 AM
Subject: Re: [PEDA] signal integrity
> > It always says that there are warnings about my PCB, however it seems to
> > work fine when I let it continue. I ass
s the
CY22393FC IBIS file.
Any suggestions as to how to rememdy this, or will I have to dig around in
the IBIS specifications and insure that the files I wish to import are all
correctly defined?
Thanks,
Bevan Weiss
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t
> Allot of work? That's probably the biggest understatement I've hear this
> year!
>
> But don't let me discourage you.
>
> If you can succeed in doing this - a whole team of programmers at Protel
> still have not - you will make many friends and allot of money.
&
development
would also be appreciated.
I'm also wondering whether development of a server can be done in C, or
whether delphi is the only option.
Thanks,
Bevan Weiss
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site that would have some hints and
tips.
Thanks,
Bevan Weiss
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Ensure that you've got compress on save (or something of the sort) selected.
Deselect it temprarily, then click on COMPRESS manually. Once the compress
has run, click the compress on save back on.
The other things to check for are...
Surplus documents in the deleted items bin, surplus text file
Is the SDK for Protel99SE available without signing a NDA??
If so, where would one obtain it?? The protel site has very little left on
99SE
- Original Message -
From: "Darren" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Saturday, October 05, 2002 12:32 PM
Subjec
hope is for four layers and about
> >US$51 per board (for about 3boards). However if the traces are more
widely
> >spaced then perhaps six layers will be needed, in which case I'd have to
> >look for a cheaper manufacturer.
> >
> >Thanks for the reply,
> >Bevan
or. I assume that you don't have access to HyperLynx or similar
> simulation tools?
>
> John Haddy
>
>
>
> > -Original Message-
> > From: Bevan Weiss [mailto:[EMAIL PROTECTED]]
> > Sent: Friday, 27 September 2002 4:07 PM
> > To: Protel
How would you even solder a 1020pin BGA (I assume that's 32x32 with the four
central balls missing?)
I say that you'd need to use blind vias, with a lot of layers (I've never
worked on BGA's but would imagine that you might get 4rows/columns per
layer). My estimate would require around 8layers.
very cheap 6layer boards. My current hope is for four layers and about
US$51 per board (for about 3boards). However if the traces are more widely
spaced then perhaps six layers will be needed, in which case I'd have to
look for a cheaper manufacturer.
Thanks for the reply,
Bevan Weiss
ld be
greatly appreciated, I can't seem to get much info from my tutors, it would
seem it's slightly above most of them :(
Thanks guys,
Bevan Weiss
- Original Message -
From: "Tony Karavidas" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMA
x27;m sure that many of you have had this kind of situation before and have
some advice. It's for a student design project and the deadline is quickly
approaching.
Thanks,
Bevan Weiss
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I'm pretty sure that the value that must be present in the part type field
is the actual value of the component. Ie for an inductor, its inductance
value etc. I might however be wrong on this (it wouldn't be a first).
- Original Message -
From: "Thomas Josefsson" <[EMAIL PROTECTED]>
To:
ember 24, 2002 7:22 PM
Subject: Re: [PEDA] PCB component designator orientation
> 24/09/2002 02:10:16, "Bevan Weiss" <[EMAIL PROTECTED]> wrote:
>
> >This comes about through using the autoplacer
> >to obtain a starting point for component placement (just got
"shortcuts" of all sub-sheets (that
are
> supposed to be copies of the master channel), and you use Complex-->Simple
> to convert these to real sheets.
>
> Another tip is to keep a copy of the shortcuts (in a sub folder), so that
if
> you have to edit the master (and go th
Hi,
yet another question...
I'm using the autoplacer (in statistical mode) to place the starting
positions for my components.
I would however like to seperate out where some components go. I have some
RF stuff, that I would like to keep physically seperate from the digital
stuf. Is there any e
Hi,
another question.
When performing a BOM on a complex heirachy schematic layout, I don't seem
to get components called out right... It's always deficient.
with two sheet symbols (with the same schematic), and a holding schematic
ie total.sch->audio.sch
->audio.s
e finalising the
PCB.
Thanks,
Bevan Weiss
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