Re: [PEDA] OT: Trace Spacing For 110 Volt Relay Contacts....?
In my experience, it can be a bit more complicated than a simple matter of Track width/Space requirements. Many Euro safety specs are _much_ tighter than North American specs, in part (I believe) to exclude foreign competition. Many items, such as connectors, relays, opto- isolators and other AC mains-related items, do not pass Euro standoff requirements based on conductor spacing. Every isolation item on the board has to be designed to meet the standards of the target market. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Internal plane problems
Afshin,
Addition of the secondary planes has to be done in a certain way,
or Protel has trouble allocating the plane areas. To add secondary
Split Planes, it's necesary to create holes on the Primary Plane
by editing its vertices (ie, by doing Edit Move Polygon Vertices,
selecting the polygon, then dragging the handle {a small cross in the
middle of a side of the plane polygon} to a new location). Continue
until sufficient space is created for the new Split Plane, and add the new
plane. Though the edges of the Split Planes can coincide, be sure not to
overlap copper areas of the various planes.
Also note that the Primary Plane must not be closed, or completely
enclosing any Secondary Plane. You must break the margin of the
Primary Plane toward the edge of the board to create a gap in the
Primary Plane for each Secondary Plane. Protel's Help system has an
example, I believe. Check Plane current density and signal layer paths to
determine the best place to create these gaps.
These are supposed to be hard and fast rules, but I've had boards that
checked and ran OK even with small embedded Split Planes. But the
procedure should be followed, since DRC results and plane connection
assignment is unpredictable if it's not.
I'm sure others have more tips.
Brian
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Re: [PEDA] Internal plane problems
Thanks, Dave... Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber problem
Is it the Drill Report that's telling you about the holes? Or the DRC? What does the Hole Size Editor Tool list as holes? Anything odd? Can you locate a zero sized hole on the board from data in the Text Drill File? One thing to try is to select all zero holes and attempt a global change to, say, 100mil; that can help you to visualize what's going on. (Of course, you'll have to deselect SMD pads and other good zero-holes.) It may be that you somehow wound up with zero diameter holes on a mechanical or drill drawing or keepout layer. I think the drill generator will output data for any holes on all layers, whether they are visible or not. Make sure All Used Layers are turned on for display. Try to repair the database using the tool under the green down arrow in the upper left of the toolbar area. You have to close the .ddb before you can repair it. Good luck * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] P-CAD Importation
Good day, all; I've been asked to revise a PCB generated under P-CAD. I'm using '99SE/SP6. On trying to import the .PCB file, I get the message Unsupported File Format. On trying to import the .Sch file, I get a system crash due to an illegal driver call.. The native files are dated 10/06/01, so may be in a pre- P-CAD 2001 format. Has anyone successfully imported older P-CAD PCB or .SCH files? Thanks- Brian Sherer Foothill Services LLC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P-CAD Importation
Thanks, Robert. I tried to import it both the ASCII (.PDF) and the default (.PCB) formats. he .PCB attempt produced the Unrecognised File Format error, with a suggestion that ACCEL files should be loaded as ASCII. So I renamed the file .PDF and tried to import. All I got was a black screen, and a check of Layers Used gave none. What version of Protel did you use to import the P-CAD files? And, do you recall the P-CAD version they were generated under? I've since been told the files I have were done under P-CAD 2001/SP1. Brian At 05:43 PM 12/4/02 -0500, you wrote: On trying to import the .PCB file, I get the message Unsupported File Format. On trying to import the .Sch file, I get a system crash due to an illegal driver call.. Has anyone successfully imported older P-CAD PCB or .SCH files? Are they in ascii format? I seem to recall something about the import being ascii format not binary. But then my memory has been known to be faulty at times. I imported one or two pcad files a while back more for testing than anything since most of the pcad support my boss has been doing since he knows it better. Also I'd rather he got to do the cussing at the way our former employees stupidly did their designs (like routing tracks on power planes using two different layers). Robert D. LaMoreaux MTS Systems Corp. Powertrain Technology Division 4622 Runway Blvd. Ann Arbor, MI 48108 734-822-9696 Fax 734-973-1103 Main Desk 734-973- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Strange behaviour 99SE SP6 WinXP SP1
Glennn, is it possible that with all the reinstalling that the shortcut is pointing at a secondary link or even a second (possibly backup) copy of '99SE? It sounds like it's pointing at a link rather than the executable, in any case. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] polygon fill, thanks Brian
I'm glad that Mr Rohmberg got his fills filled, but I don't think it was from Mr. Sherer's advice, which is, unfortunately, incorrect, I just verified it. I stand correctedThanks. Can't understand how I've never run into the problem! Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] polygon fill
Chris- I had second thoughts. You may not be copying, but creating a polygon on a board having an existing polygon. Protel gets confused if you create a polygon which lies within or overlaps another polygon (with a different net name) on the same layer. See Protel's Help topics. A Split Plane must be used in this case. In brief, the added Polygon is made using the Place Split Plane option; the polygons may NOT overlap, and an inner polygon must NOT be fully enclosed by the outer polygon. To created space for the inner polygon, the outer polygon may be edited to break its outline and move the resulting vertices, to create a hole in the outer polygon. Then you place the inner polygon in the hole. Hope this helps. Brian At 06:09 PM 11/2/02 +0200, you wrote: Hi all, I am using Protel 99SE and cannot figure out why when I drop a polygon plane, which I choose to be GND it drops the plane over all the pads and tracks in the area. I have my netlist correct, I think I have set the polygon plane right by setting not to remove dead copper. I still cannot get it working properly. If I click on any of the tracks around there each one has it's separate net name so why should the polygon cover them. Regards Chris * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OT - Bare board storage
Ben, we've had good results storing bare boards for many months in the Saran Wrap sheeting that many fabricators use to bundle boards for shipping. Saran has the unique property among commonly available materials that it is a very good gas and vapor barrier, and will exclude oxygen from the package. Polyethylene (the soft, slightly bluish material) is _not_ a good barrier, due to micropores. Bare boards shipped in polyethylene should be over-wrapped with Saran Wrap if they are to be stored for more than a month or so. Saran Wrap is the US trade name for polyvinylidene dichloride film. You can get it at any supermarket (at least here in the US). Don't get heavy duty type. The regular thickness conforms and seals better. Brian At 10:35 AM 10/11/02 +0200, you wrote: Although offtopic I like to submit a question to this forum because you guys are all professionals. More and more we need to store bare boards for a period of 3 months or even longer. Are there any requirements or so to prevent the boards from aging and/or absorbing moisture etc.? How do you guys handle this issue? Best regards, Met vriendelijke groet, Ben Uijtenhaak [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 1000V HV clearance.
Hi, Mike- UL will be happy with spacings that will lead to disaster in practical application. Use at least the VDE spacing of 8mm edge to edge. In fact, though, even this is marginal for 1KV; eventual contamination will cause tracking across the PCB surface. Motorola had a good Apps Note on applying Opto-Isolators which gives some useful tips. They are supposed to stand off 2.5KV. Best is to add 125mil wide non-plated slots between 1KV and all other conductors, or allow a half inch or more across bare FR4. Spray-on conformal coating can be added if low leakage is a must, possibly the case if you're only generating 1mA. And don't let the proto fall in your lap during testing Brian At 01:31 PM 10/8/02 -0700, you wrote: I have a quick turn pcb with 1000V @ app 1ma max. What trace/plane separation is required for UL/CE? Mike * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Overlapping Polygons in 99SE
Scott- If I read your post correctly, it appears that you are placing the polygons and _then_ assigning them to the selected net, rather than assigning the polygon to its final net while in the polygon placement dialog box. I've gotten mysterious results when trying this for overlapping polygons, including shorted nets as reported by the DRC even when the offending polygon is moved outside of the active board area, and an inability to select the latest polygons for removal (phantom polygons, reported under some past posts, I think). I've found it necessary to assign the polygon to its final net before placing the polygon, but when this is done have had no polygon Netlist/DRC problems. Brian At 06:28 AM 9/12/02 -0700, you wrote: Scott, I cannot follow your explanation of your process as presented below. However, the previous issues that I raised are the only times that I have ever seen a polygon overlap another polygon. I used multiple polygons all the time, sometimes just to make sure that some areas get polygon fills into smaller areas I use separate polygons of the same net over one another. I realize that you are trying to do the opposite but in my experience your task should be a no brainer. So you must have some condition set which allows this different net polygon overlapping to occur, plain and simple. It actually sounds like you pour them overlapping intentionally, well that should not occur and you are doing something to allow it to occur. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Norsat's Microwave Products Division has now achieved ISO 9001:2000 certification -Original Message- From: Scott Ellis [mailto:[EMAIL PROTECTED]] Sent: Wednesday, September 11, 2002 5:33 PM To: Protel EDA Forum Subject: Re: [PEDA] Overlapping Polygons in 99SE Yes all your comments were very obvious. I will try and be a little clearer. Using a single layer board for simplicity - place a polygon and connect to GND. Place another polygon which overlaps the first, connect to VCC. Now pick up and move the second polygon so that it no longer overlaps. Notice that where the two polygons overlapped, they both have tracks. Reason for doing this: I have a PCB milling machine but no software. I can use the method previously posted to generate the tool path from an isolation polygon with the clearance set to 1mil. Works great except if I have other polygons on the board. My next approach is to edit the text version of the PCB file, grab all the track primitives that make up the polygons that are meant to be there, turn them into normal free primitives and then generate the isolation polygon. It just strikes me as odd that the polygon pours over something that is obviously another net, and that the DRC doesn't think that this is a problem! Scott Ellis Manager Novatex Research - Excellence in Electronic Research Development [EMAIL PROTECTED] 41 Yule Road, Merewether, Newcastle, NSW 2291, Australia Ph 0412 988408 Fax 02 49636058 * Tracking #: 41E57E03B9D4B243AE13A0EFB336625FC402E2EE * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Address select jumper using 0R links...
A simple method I've used several times is to indicate on the schematic the two select resistors, calling them out as 0805s, then simply placed them such that the ends which are commoned on the schematic physically lie on top of each other with their bodies in-line. Selection is by loading one or the other footprint. I create a special 0805 Library part having no overlay lines at their ends, to reduce confusion for the assemblers. Note that the Component Placement Rules must be turned off (my default setup) or a special rule could possibly be created to allow a placement exception for these two parts. Pick and Place works normally. DRC sees them correctly, since their overlapping pads have the same net. Brian I need to select the address of a card using 0R (0805) links, and I want to create a footprint with 3 SM pads, and be able to specify the link be loaded 1-2 or 2-3, without having to manually edit the Pick and Place file. I don't mind using two different SCH components (since changing will happen rarely), or even two PCB footprints. Any ideas? Can I have a 3 pad PCB footprint and only load a 2 terminal part? Will the PnP generator get confused? Damon Kelly Hardware Engineer * Tracking #: C1202B4B1ED77546B73B3AF7DCF053DCA6A7A7AB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Assembly house referral request
Hi, all; A client is having trouble locating a reasonably priced assembly house for a precision analog PCI card having fairly high density and requiring scrupulous attention to processing cleanliness. Board has a few 19mil lead pitch chips along with 26mil and larger chips, and about 30% throughhole hand-adds. They aren't trick boards; we've hand-assemble many samples in 8-10 hours with a 95%+ turn-on rate. Run sizes are moderate, and they'd prefer to stay in Washington, Oregon or California. BC is a possibility, but I expect crossing the border might be an on-going annoyance/expense. Any tips would be appreciated. Brian [EMAIL PROTECTED] * Tracking #: 40A8C3A74B1DD544B837320468EB2ACF1050C34E * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB Rules question
Michael, I've handled this issue by offsetting the Keep Out tracks/arcs outside the physical edge of the board by a fixed amount, say 10mils. If the board is to have Polygons or Planes, you may have to create a temporary set of keepouts to control polygon/plane pours to a wider clearance; if these polygon control keepouts are made with a unique track width, they can be easily selected and moved off-board for later DRC operation. Note that most board houses will be unhappy with copper closer than 10mils to the physical edge of the board, as the outer copper can get ripped up during routing. They may be willing to do it, but will probably need a special fab note which OKs damage to the copper. Brian At 03:23 PM 8/29/02 +0200, you wrote: Now to something completly different ... I use Protel 99SE SP6 and i want to create / modify my design rules so that there will be no drc errors if a pad and / or a track is touching the keep out. Imagine a pad placed inside the pcb-outline and keepout's but the outter diameter of that pad is not inside the keepout as the outer diameter is bigger than the relative distance of the pad to the keepout. the reason is that a have to place pads at the edge of the pcb that there is no gap between the pad / track an the keepout (the outline of the pcb) so the copper will be directly at the end of a pcb side ... yes i know that there should be normaly a gap of about 20-25mil but in this case i realy need the pads and tracks be placed at the edged .. i have tried to setup some design rules like Clearance Rule A: Object Kind (Via; TH-Pad; Tracks/Arcs) B: Object Kind (KeepOuts) Any Net Minimum Clearance 0mil but all i enter in these dialog box still produces DRC erros as if it is in general not allowed to place anything directly with no gap to a keepout. well of course i could ignore these messages, but i prefer a final pcb without any drc error messages. any ideas ? Dipl.-Ing. (FH) Michael Schmitt Baumer Ident GmbH Entwicklung / Development Department Hertzstr. 10 D-69469 Weinheim Deutschland / Germany Tel. +49 (0) 6201 9957 - 30 Fax. +49 (0) 6201 9957 - 99 E-Mail : [EMAIL PROTECTED] Web: http://www.baumerident.com/ * Tracking #: B20D94969EBD90418293584CEC291816420C6E43 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Supress HTML in Eudora
Edi, I have Eudora 4.0.1 and can find no option for supressing display of HTML. Where do I find that switch? Brian At 09:53 AM 8/16/02 +0200, you wrote: I have been trying to use Mozilla for e-mail also, but it seems to have a bug that crashes when trying to import large message folders from OE. So I am stuck with OE for now. Why? There are other e-mail clients than those integrated in the browser. I use Eudora, so I can disables the launch of programms from a message and executables in HTML content. I never had such intrusive spam as you described. Edi Im Hof Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com * Tracking #: 124090705574554089F24785885A48109BCBB023 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Highlighting dead copper on P99SE
Deselect Remove Dead Copper on Polygon Pour Setup Dialog box. Repour Polygon(s). Brian At 12:10 PM 8/9/02 -0500, you wrote: At 12:41 AM 8/10/2002 +0800, Katinka Mills wrote: Hi all, Quick Q, I have a 2 layer PCB with top and bottom ground planes (like to balance up my copper) how do I hilight dead copper, I do not want to remove it, just need to see it so I can add vias to make it not dead :o) Should be easy, but the help menu has no topic on dead copper (does not even find the word dead ?? ) isolated copper? I'm surprised that it generates isolated copper. I can't think of a good reason to do that.. * Tracking #: 6CBA8AFABF308645B4F4718F27AFD3FD2CCE213F * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Connection to Power Planes
Yves, I've found that a sure-fire way to avoid netlist conflicts in this situation is to create a second Schematic part for each IC to be decoupled, changing its power pin Name from VCC or VDD to something like U25_PWR. Replace the original Sch component with this part. This will netlist correctly to your decoupling components. Each Sch part so treated will have to have a unique name for its power pin, or they will all be lumped into the same net. Brian At 04:10 PM 8/1/02 -0400, you wrote: Hi All, I am routing a 4-layer board with only through hole components. I need to connected the supply pins of my IC's to the supply plane but I would like to go through a decoupling cap first. Is there an easy way for have those pins not connected to the plane? Thanks Yves Dubois Senior PCB Designer. Raytron LTD Montreal, Quebec Canada. * Tracking #: 90502D2E8745104AB51B9641E64976EF99B7E2BC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] rectangle hole?
Tim- I use a method very similar to Mr. Velander with good results (ie, no calls from the Fab CAM operators). My Fab drawing is added to the Drill Drawing Layer so as to be included with the Drill Size listing, and is included with all jobs. A few notes: 1- Explicitly call out all hole sizes used as mechanical markers as Marker hole for Slots. Slots are xxMil wide NPT (or Plated). Hole center marks center of xxMil too used to rout slot. 2- If a fairly large routing tool is to be used, be sure to locate marker holes with an offset toward the center of the desired cutout to accommodate the radius of the tool and the clearance radius at the corner. This can be calculated from the tool diameter. If space is tight, you can request that the majority of the cutout be routed with say a 100Mil tool, and specify that the corners are to be routed to a smaller specified radius using say a 20 or 30Mil finish rout. This is far faster for the fab house. 3- I draw and dimension each cutout and notch explicitly on the Drill Drawing Layer to exactly indicate the desired feature. This is good backup info when using a multiplicity of marker hole sizes, as Protel isn't the greatest for checking hole sizes by selection. Some fab CAM operators prefer to work only from the dimensional drawing info only, as it allows them great freedom in tool and path selection. 4) Don't assume the fab house can't or won't drill a 1Mil hole. I had a call from an offshore house telling me that Laser-drilling the 1, 2, and 3Mil holes would take an extra day or two! I find a good rule of thumb is to specify _everything_, with wide but fixed tolerances for don't care items. The old USSR had the right idea: Anything not Required is Forbidden! Brian * Tracking #: 8992B0379032D04B9AEBCB5F6789C839B21EE559 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] rectangle hole?
Brad- The 1mil shop was located in Europe. They claimed to be doing precision fab at die level, so may have been sputtering the plating (or some other James Bond type method). Needless to say, their quote was astronomical and went directly to the circular file As the old saying goes, Be careful what you wish for... you may get it! Brian * Tracking #: 3F3F763F590F2C4DA00CD6047FA30842EA6A2AA9 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP Discussion
InterestingIn my neck of the woods (NW US), to bag something is to abandon it as useless, but without extreme prejudice Brian At 07:32 PM 7/30/02 -0700, you wrote: In the US, 'to bag' generally means the same thing. I think some places it means to 'capture' or 'get lucky' but I'm not sure where... * Tracking #: F89D03FC4C3FC14E9ADC95FB81F22D9EE5A6763E * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Kudos
I guess I'm in the minority, but I find the Protel user interface quite powerful and, for the most part, intuitively consistent across servers. The labyrinthine command interface of Autocad and PCB packages using a similar interface (like Pads) are tedious and extremely trying. Protel is missing a bet by not offering a stand-alone full-featured Mechanical CAD package based on the 99SE interface. But *Please*, Protel, be sure to maintain full two-way file conversion with all ACAD File Formats ever released! Brian * Tracking #: 732E05315EAC2942A3FEB2F75BD40D71CF4E8FD5 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Acrobat 5 on Schematics
I have Adobe Acrobat v5.0.5 under Win'98 and '99SE SP6 with 512 MB RAM, and it works OK on Schematic files with the exception that arcs of certain diameters located within 20% of the right edge of the sheet are not rendered at all. This includes such objects as the arcs used to create AND gates. It also fails to render certain specific larger font sizes, such as 20pt. These are for the most part B sheets; the effect doesn''t seem related to sheet size or circuit complexity. I'm using the default Acrobat settings. Brian Foothill Services LLC At 09:49 AM 7/10/02 -0700, you wrote: I reccomend adobe acrobat for pcb files. However, version 4 on w2000 sp2 does not work on sch files. For those I use efax. For low cost if you subsribe to efax, you can use their prit driver/display software to export to tiff or jpeg. Does anyone know if acrobat 5 works with sch files? Mike - Original Message - From: Yuriy Khapochkin [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, July 10, 2002 7:37 AM Subject: [PEDA] PPC to word insertion Does anybody know how to insert PPC (PCBPrint) image into Microsoft Word? I would appreciate any ideas better, than printing - scanning. Yuriy Khapochkin. * Tracking #: A90690A739593B4B829B4449AA8525A82604F7AC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] OS bugs WAS: Problems with schematic annotate function.
Not quite.We provide a service, not manufacture a product. Our clients set the target product functionality, and specify performance. If the computer trade were based on a service model, I'm sure we'd have much better software functionality. Brian you forgot: Buy this new PCB. It has new features... Oops, I forgot, for readers of THIS forum, that's what a) put the bread on the table, and b) what fuels all of this upgrade stuff in the first place (not to mention, what goes into that cell phone, automobile, TV, and computer, the last being the forcing function that drives the OS upgrade, to accommodate the new features the PCB brings to the consumer's PC) aj * Tracking #: 624CAFFFCC71CF4292E5E2F129F890D8FEC9CDD1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] ''Access violation'' problem
Thanks, Matt. I think you should have prefaced your attachment by saying Now, don't shoot the messenger, but Does anyone know if the offending driver might have been included in one of Microsoft's Critical Updates? I'm still running Win'98 with 99SE SP6, but suddenly began to experience such errors recently after such an Update. I'm reluctant to reload everything (and I mean _everything_ ) without identifying the real problem. Brian Foothill Services * Tracking #: D1D3899FE9CBE148A4704DCB7E4C0CDAD401BD50 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] LIB Request ISA 16Bit
With Protel open to a .ddb and Documents tab selected, choose New PCB Document, then select Wizards tab. This will allow you to generate a standard card in several formats. You'll want the AT card, either long or short. The Schematic symbol may be available, but I wasn't able to find it quickly. But it's easy to build, and most people like to use a favorite presentation. Brian At 11:27 AM 6/12/02 +0200, you wrote: has anybody a PCB LIB containing an ISA Connector 16-Bit ? and the SCH symbol ready ? I thought this is included in the Protel Libs / Wizard but i cannot find it. Thanks a Lot. Dipl.-Ing. (FH) Michael Schmitt Baumer Ident GmbH Entwicklung / Development Department Hertzstr. 10 D-69469 Weinheim Deutschland / Germany Tel. +49 (0) 6201 9957 - 30 Fax. +49 (0) 6201 9957 - 99 E-Mail : [EMAIL PROTECTED] Web: http://www.baumerident.com/ * Tracking #: 5FF6614CC7FA98419DEE0EA1EC22BE254A271386 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Auto router just stops...
It is a female by nature and has mood swings to boot. ! Vive la difference! Think of autorouters as as job security -Brian * Tracking #: 19A89E2E4577644A85AD72E9AF83E5AB58E45961 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] help, how do i make rectangular holes in components and on the pcb itself?
Ken, I've done this by creating cutouts of the proper size (tiny) using say four 1mil holes on 5mil pads. I included on the Drill Drawing a detail showing routing a rectangular cutout from these sets of 1mil holes. You _must specify_ Plate Through for all these special cutouts. Note that you won't get absolutely square corners due to the radius of the routing tool; the fab house can tell you what their minimum radius is. Be sure to allow for the corner radii and routing tolerance (usually 3mils excess for tolerance at each corner) in sizing the cutouts. Brian Foothill Services LLC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Protel / MSoft
My personal reservation to Altium's new pricing structure is that both Microsoft and Protel have historically used a Toss it and catch it model for software development: Write the code and release it with known bugs, and repair such bugs as become negative sales issues. No other type of product that I am aware of survives introduction with known defects, because they're forced to observe product liability laws. Until we have legislation requiring product performance to a level of competency similar to that of, say, an electric toothbrush, we're going to be subjected to software requiring six Service Patches to reach utility. Perhaps XP is much more stable than earlier flavors of Microsoft, but it has the same odor: Use and maintain XP, or soon all the expensive Microsoft products you've been supporting for all these years will be useless. Altium's brave new world has the same feel. 99SE is already a powerful tool inspite of it's problems, and for my work, the mechanics of layout is no longer a major item in the critical path. Second, and more importantly, I suspect that not all patches to the latest product will be released before our free support period runs out, leaving me to pay $1600/Yr for bug removal. I don't feel this is acceptable in a package costing $8000. Any comments? Brian Foothill Services LLC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel / MSoft
Mike, I agree with your comments regarding M$. Much of the software industry is adopting what I think of as the Exploding Menu school of software design. I don't _want_ an animated desktop. Like you, I have a service bureau. My machine is a tool, not a gameboy, and anything that distracts from the job at hand costs me money. I need bullet-proof file management and security tools, and I'm being asked to fund eye-candy. I have the feeling that Protel is headed down the same road, and for the same reasons. Once the basic OS or App is fairly well developed, it becomes hard to entice users to upgrade. The only options they have are to add inconsequential but visually exciting frills, or to create the necessity to purchase upgrades to cure bugs. 99SE was a great tool at $3900 for small shops and service bureaus, and was very cost effective. None of the new Protel features I've heard discussed seem to justify the doubling in price. Protel is just now getting around to dimensioning tools after 10 years. I already have to maintain Autocad to cover Protel's shortcomings in DXF/DWG. If I have to budget $1600/Yr for software, I'm opting for Eagleware, something much more useful for me than a new routerI doubt I'll live long enough to see RF tools even at the maintenance price they're asking. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Drawing Dashed Lines in Schematic
Sure. Begin placing a Graphical Line (NOT a wire) on the schematic, then hit the Tab key to open the polyline properties dialog box. Pull down the line style tab and select dashed or dotted as desired. Once finished with the dashed line, you'll have to reselect solid line. You can also edit existing solid lines by doubleclicking on a placed line and change it's style. Select area and Global Change work also. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] negation character redux
Hi, Dennis; I use, and have often seen used, the slash (/) for negation on pin signal names as well as Net names. Seems to work OK. eg: /OUTPUT for negative output. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Linux experiences
Thanks to both Jon and Jason. Think I'll give it a try, next major crash. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Linux
Hi, all; Has anyone successfully run 99SE SP6 on any flavor of Linux? Any tips on Linux version/vendor, or GUI? Thanks for any info Brian Sherer Foothill Services LLC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autopan in PCB (99SE)
Be sure the active screen is maximized, too; at times it may appear to be maximized but is not. I've seem some unusual effects when the cursor reaches the edge of a non-maximized screen in PCB and SCH. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Power plane questions
Hi, Matt; Let me ask first how you created the circular board with the segmented Planes. Did you draw a circle using a 50mil arc of, say, Internal Plane 1, then add 50 mil Tracks of Internal Plane 1 copper to force segmentation of the circle? If so, you are creating endless headaches for yourself, as Protel's DRC machine will probably not be able to correctly resolve what it will interpret as many overlapping physical Planes and many Planes connected to overlapping Nets. A better (maybe the only) way to place multiple planes is to: 1- Create a physical board using an arc of say 1mil width on the Keepout Layer, having the arc laying on the edge of the desired finished board. 2- Create a Design Rule for Power Plane Clearances of , say, 20mils. This will insure that all copper is at least 20mils inside the boundary of the physical board. Fabricators are generally happy with 20mil plane clearances, though they will work to clearances much tighter if requested tobut their fallout will be higher during test and they will charge accordingly. 3- Load your Netlist. You can leave the components unlocated for now. 4- Use Place Split Plane to add each desired Plane, assigning it to the proper Net and Layer using the dialog box for each Place Split Plane. If for instance you want a pie-shaped board, begin each Plane at the center of the pie and extend the plane _beyond_ the keepout arc so that all portions of the Split Plane Boundary are outside the arc. Then move to the next wedge of the pie and Place the next Split Plane. Extend _all_ Split Planes as you add them to extend beyond the Keepout arc. You can place the boundary track of one Split Plane directly on top of the boundary track of another Split Plane, though you don't _have_ to. You will be able to edit the Plane segments later if needed by using Edit/Move/ SplitPlaneVertices; when it asks you to click on the desired plane, the planes boundaries will be highlighted and can be clicked on to grab the vertices etc. NOTE: Do Not Overlap Planes! Mother Protel doesn't like it. You should wind up with a bunch of Planes whose edges either coincide or lie adjacent to each other. Any copper not enclosed by a Plane boundary will be dead copper, and although not electrically connected to circuitry, may act like an antenna. Try to avoid dead copper areas. If you double click on any Plane segment, the resulting edit dialog box should show you the plane as having the correct Layer and Net. Note also that the width of the track used to Place the Plane is in effect the width of the boundary void in the copper plane when the Gerbers are generated. So, two adjacent planes having 20mil boundaries will generate Gerbers having the planes separated by 20mils total. On the clearance issue, best to set up the Design Rules for Power Plane Clearances and let Protel manage copper setbacks during Gerber generation. To try to do it manually is frustrating and nedlessly time- consuming. Keep in mind that the board house only sees Gerber data and won't be confused by the means used to create the data. As an aside, Polygon Pours are placed in a similar manner. However, their screen presentation is very different, being displayed in Positive rather than Negative copper. You can use both on the same board, but NOT on the same layer. A Plane Layer must have ONLY the Plane on it. Anything else is used to indicate a Plane Keepout Object unless electrically connected in the Netlist. DO NOT try to form conductors in Plane Copper by forcing voids to create traces or Planes-within-Planes. Protel becomes very troubled, and the DRC will NOT report these pseudo-objects correctly. If you must mix Plane-type areas with Track-type areas on a given layer, use Polygon Pours and Tracks on a Mid Layer. Good luck! Brian Foothill Services LLC At 03:02 PM 5/19/02 -0700, you wrote: I'm working on laying out my first board with power planes and I have a few questions. 1. I placed an arc on the plane (my board is circular) to form a circle all the way around the edge of the board. The idea is to keep the plane away from the edge of the board. The assigned net for the arc is No Net. Is this the correct procedure for keeping the plane away from the edge of the board? 2. The arc is 50 mils wide. Since I placed the arc directly on top of the board outline, I expect to get 25 mils of clearance from the board edge to the plane. In general, is that enough clearance? 3. I have split the plane into multiple nets. The tracks that indicate the boundaries are 45 degree and 90 degree tracks. Recall I have an arc on my board edge. Because the 45/90 tracks and the arc are not compatible, the tracks extend outside of the arc to avoid tiny slivers of plane near the board edge. Is there a better way to do this? For example, can I define the regions with mostly 45/90 tracks but add an arc at the board edge to complete the region? Will the way I have done this likely confuse the board house?
Re: [PEDA] Print preview bug on Arcs
I'm having a somewhat similar problem when trying to print schematics to Adobe Acrobat. Arcs on the right 20% of the schematic are not printed to the PDF. The effect removes the rounded portion of gate symbols (And, Or, etc). Anyone seen this, or have any tips? I'm running 99SE SP6 on Win'98 with 512MB ram, no apps open except Protel and Acrobat. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Ground plane floods on top and bottom of PCB
Another quick method is to do top and bottom pours with the Remove Dead Copper option turned off, then simply drop vias on dead copper that should be connected to the opposite side Ground pour. Most areas can be dealt with quickly this way. Of course, one side or the other must be connected to the continuous ground, or double-sided dead copper results! Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] FW: Access violation -- Is it a Protel bug?
Ian Wilson's questions are good ones. Did you enter the schematic and generate the Netlist? If you entered the schematic, and if it is an option, I would begin by resetting all Identifiers to ?. That is, do a global change of all R's to R?, all C's to C?, etc, for all components. Then use Tools/ Annotate to reannotate all ? components. Then generate a new Netlist and try loading that. Be sure to have all required PCB Libraries open for component footprints called for by the Netlist. Good luck! Brian At 04:14 PM 4/16/02 -0700, you wrote: Brian, I am using Protel 99SE sp6. The operation systems is Window 2000. I have over 500 mb of Ram. Tried to load a netlist to a new PCB document. There is no warning for the netlist report. I am not sure what I should do to solve the problem. Do you have any suggestion? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] NPT mounting holes
It's useful to have a pad of finite size so that it'll be visible as a reminder in case you have (Show) Pad Holes turned off on the Design\Options panel. Best to make an NPT pad up as a single-layer pad on the Drill Drawing Layer; this avoids creating objects on the Mask Layers during Gerber generation, and eliminates error messages during DRC. I use 10mil diameter pad for standard boards, with the hole size adjusted to suit. Brian Foothill Services LLC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] footprint for key-finger/keypad
There are several technologies used for keypads; among them are snap-domes (metal domes with 3 tabs that enter plated holes, and a bump that contacts a center pcb pad); elastomeric (an insulating plastic sheet with round conductive rubber pads that contact matching conductive grids located on the PCB below each rubber pad); and keypad assemblies (which have the contacts buried between plastic layers of a flexible film, with connector tails for row and column). Or the whole thing may come pre-assembled in a keypad module, with pins like any other component. The layout varies widely for the different types, so it's best to get the preferred PCB layout from the manufacturer for the exact part number or family you'll be using. Be sure to bet their recommendation for contact plating, often specified as gold. If it's to be gold (or other) plating, you'll have to do a drawing showing the area to be plated, as the fabricator will need to mask off all unplated areas. Brian Foothill Services LLC At 08:29 PM 3/20/02 +0800, you wrote: Hi, I'm going to start a layout with key-pad but I can't find any recommend footprint for it? Any advice or help on this? Thanks! Ciao... Adeline * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Voltage standoff of FR4
A useful guideline is to look to the various standards for conductor spacing to yeild a safe voltage standoff. A reasonable minimum of 8mm for 2500V standoff between conductors on the same side of the board will give you a good chance to avoid tracking or arcing along the surface due to normal contamination. Moisture absorption has a significant effect, too; even properly cured FR4 will absorb .5% water, which can elevate leakage currents and thus reduce both puncture and tracking voltage. Often slots are added to the board between conductors to reduce tracking effects, for instance between A and K of a diode multiplier string, or to isolate the input and output pins of Optoisolators. I've seen many failures due to tracking, but none due to puncture. Brian At 02:48 PM 3/18/02 -0800, you wrote: Sean, the standard answer from IPC for general purpose (Epoxy E-glass) FR4 (is there such a thing today?)is 39,400 Volts/mm (approx. 62,500V at 0.062). This is derived from a test using 0.125mm and they warn that it should not be considered linear for high voltage applications with minimal dielectric spacing, i.e. less then 0.09mm (0.0035). Don't think that counts for most general designs, that would be 3.5mil laminate. Now a word of warning. This would be through the dielectric, not around the edge of the material, through air, nor over the surface(s). Considering most applications and the means for contamination of these surfaces, I would be checking the surface or around the edge requirements as well. Especially is there is copper near the board edges. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11. -Original Message- From: Sean James [mailto:[EMAIL PROTECTED]] Sent: Monday, March 18, 2002 2:15 PM To: Protel EDA Forum Subject: [PEDA] Voltage standoff of FR4 What is the voltage standoff (front to back) for .062 FR4? Sean James PCB Designer Telecast Fiber Systems 102 Grove Street Worcester, MA 01603 TEL 508-754-4858 x33 FAX 413-541-6170 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PROTEL LIBRARY FOR AVR AVAIL
Not _this_ BrianThe Library Brian logged on as a visitor. Brian Sherer Foothill Services LLC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] hidden fields (maybe)
It's done in PCB rather than Schematic. If you only want to hide the Part Types normally shown on the PCB Footprint, you can globally change them to hidden, by clicking on any component on the PCB to pullup the edit panel, select global, go to the Comment Tab, and check the Hidden box. This will hide _all_ part types on the board. If you want to leave some visible (like Jxx, etc), you can Unhide their Part Type by selecting the one to be visible, the repeat the process above using a Global change parameter of All Selected. Another way is to Select All, then Deselect the individual parts you want to have _visible_ Part Type. Then click on one of the still selected parts and do a Global change with Attributes to Match By set to Same. Then go to Comments tab and check Hide. Brian At 09:51 AM 3/16/02 -0500, you wrote: hello, i altered a pcb by deleting the part types by merely clicking on them on the pcb and spacing in the field under attributes. there are probably about 250 components. just this morning i added a couple resistors to the schematic and updated the pcb, and to my horror, all those part types came back. how can i get rid of them without individually deleting each of them again on the pcb? i believe it has something to do with a global attributes set using hidden fields or field names in the schematic attributes, but i looked up names, hidden, and fields in the index and didn't get the job done. or maybe i could update the pcb from the schematic for just the two resistors i added. i don't know. i know i could just ignore the schematic and add the resistors by hand to the pcb, but the design rules check won't like that and i gain great comfort from running the design rules check and seeing all those zeros for the number of errors. thank you, miker * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Limitations on InternalPlane layers
Hi, Kiernan; Using Mid Layers with Polygon Pours and routed tracks works fairly well. Obviously, breaks in the Internal Plane can wreak havoc with controlled- impedance traces, switching-supply circuitry and the like, so it's good to confine this approach to areas where Plane continuity isn't critical. You can maximize continuity and minimize orphaned Plane connections by adhering as strictly as possible to orthogonality of the added internal traces; ie, Vertical on Mid 1 and Horizontal on Mid 2. Unfortunately, this adds vias to the outer copper. I find it easiest to rout all power and ground tags first, then outer copper traces, and finally pick up needed Mid Layer traces before pouring the Mid Layer Polygons. (I find the Plow-through distracting.) Actually, it is possible to use portions of Internal Planes for traces, but it's a multistep process. Basically, you create voids in the Internal Plane layer where you'd like to place traces, using area fills or wide tracks of the same Plane layer...these act as Keepouts for the Plane Layer generator. Then, insert a new layer into the board using he layer stack manager. Use the new layer to rout the few added traces by staying within the area of the keepout on the Internal Plane. After the board is routed and Gerbers generated (including the added layer), import the Gerbers into Camtastic, and using its tools, combine the extra layer with the Internal Plane having voids in the needed locations. Then save the Camtastic Gerbers as a new Gerber set. While this works, it adds steps and can be a nightmare to edit. Best used for emergencies! Brian At 02:34 PM 3/15/02 +, you wrote: I'm still on my first PCB under P99SE. I need to add quite a few extra routes, but the PCB is really dense. Can I route these on the InternalPlane layers? Should I have used Polygon pours on ordinary layers instead? If I am allowed to use the plane layers, then how can I tell whether I'm going to isolate some connections from others and how can I clean up where the trace ploughing would leave nasty slices / lost copper? Also on plane layers can I pull the plane completely away from a particular area? And finally, if I use a polygon on a normal layer, then how do I create the thermal reliefs? Sorry for all the questions. Thanks in advance. Kiernan Fitzpatrick - Join IrishCircle - IrishAbroad's premium service http://www.irishabroad.com/circle/ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Enclosures.
Try Flexibox, distributed by Powerbox USA: http://www.powerbox.se/ They have a range of sizes. Somewhat pricey, but sturdy and well thought out. Can't screen the front panel, though, so plan on added label cost. Brian At 01:43 PM 3/12/02 -0500, you wrote: I looking for a North American supplier for enclosures with heatsinks. If anyone knows where to buy, can you please contact me off list. Example cases: http://www.thlaudio.com/casebpwrE.htm Thank, Brian Guralnick please note the change in email address: [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 3D warning
Tim, in my experience DXF problems with splines and arcs seem to be import round-off errors. I've had some luck in regenerating the complex curve by manually re-entering the arcs by opening the original file in Autocad while the imported file is open in Protel, then editing the arcs one by one in Protel to match the exact Center, Radius, Start Angle and End Angle of each arc in the original ACAD boundary. Entering the exact numbers reported by ACAD for each arc seems to give Protel enough data to connect the dots with sufficient accuracy to force a continuous curve or spline. Pretty tedious, but it's worked in all the instances I've tried it on. Brian At 10:32 AM 2/28/02 -0400, you wrote: When I try to view my pcb in the 3D viewer I get the following message and then it just sits there, stares at me and won't let me press the ok button. Board boundary is incomplete - calculated boundary will be used. Check that the boundary on the Keep Out layer is closed, with their track ends touching at their centers. The tracks appear to be touching, when I grab each end of them. FYI.. The pcb outline was am import from AutoCAD and has lots or arcs in it. Anybody had this message before? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA]
LLoyd, I'd still suspect a hidden Identifier or Component Type associated with one of the parts that select when you Select Outside the board. Be sure to have Used Layers turned on, on the display options panel. Select the few components within the board that seem to have some part of them outside the board area. Double-click on them and check that neither the Component Identifier nor the Component Type is set to Hidden. If that doesn't show you the cause, you may have a trashed database. You can usually recover most easily by building a Component Library from the components on the board, select the component type in the Library, and Update that component from the Library. This will replace the component with its Identifier and Type reset to the default position. Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] help with a stack ??
Mike, I've run into trouble by assuming the board house would equalize dielectric thickness in the layer stack. Some do, some don't. I now add a fab note to equalize dielectric thickness +/- 10% to get an approximately known dielectric thickness. Or you can specify the prepreg thickness between critical copper layers, even in a proto. Brian Foothill Services LLC i have another question. this is iffy, but i'm a heathen designer anyway. this is just a proto board, and although i'd like controlled impedance, i don't want to pay for it. SO, what i am thinking is that if i get an 8-layer board at the standard 62 mil thickness, that they are going to be just about forced to give me between 6 to 8 mils between layers, without me ever having to spec it. does this sound right? thank you, miker * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB view from bottom of board??
Geoff, my experience with mirroring layouts (now several years in the past) was so disasterous that I gave it up. Connectivity of all copper objects became completely unreliable, not to say trash. Can 99SE/SP6 in fact mirror layouts and retain connectivity? Or are you referring to mirroring as an aid to viewing overlays and the like on a scratch board, while modifying and later using the true layout? Brian There is another possibility, but due care needs to be exercised if using it. That possibility is to select *everything* in the PCB file, and then mirror this about a vertical axis or horizontal axis. Since the release of SP6 (for Protel 99 SE), you will be presented with a warning box if the items about to be mirrored include components, because producing Gerber files from mirrored components will result in PCBs that can't have real world components installed on them. As such, if you do go for this option, you will then need to re-mirror everything again (and before producing Gerber files). (And when you do re-mirror everything again, the same warning box will be re-invoked; Protel is not conscious of whether components are currently in a mirrored state or not, because (unlike String objects) Component objects do *not* (currently) incorporate a Mirrored field (something which I am hoping will be rectified in Phoenix though).) If you add any new components to the PCB file while this is in a mirrored state, you should then mirror such components as well (to match the currently mirrored state of previously placed components, while keeping in mind that the second mirroring of the PCB file will *toggle* the (non-Protel-registered) mirrored status of *all* components within the PCB file at that time). That consideration is one example of why you need to be careful if you run with this procedure. Other aspects of going with this procedure is that Coordinate and Dimension objects do *not* mirror properly (and that indeed is also a problematic aspect with the alternative concept of inverting PCBs). However, as a PCB file has to be re-mirrored again at a later stage (to restore all components to an un-mirrored state), the associated problems are of a temporary nature (but re-check the locations and properties of any Coordinate objects following the second mirroring). * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Paste Array
Sean, I have had occasions when a Room was created during Paste Array operations. I'm not sure why it should be applied inconsistently, but it's my recollection that the area pasted into was already partially occupied, so perhaps it's intended as a conflict reminder. The Room, if that's what you're seeing, can be deleted if un-needed. Brian Sherer Foothill Services LLC At 08:47 AM 2/15/02 -0800, you wrote: Sean, could you explain a bit better. I have not seen anything which comes close to your description. You are talking about Paste Special, Paste Array in PCB aren't you? Is this grid a highlighted version of the normal grid dots/lines or is it something different imposed over the paste area? Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel Service Bureau in Toronto area?
Don't know of any in the Toronto area, but most Service Bureaus have global clients, and experienced designers are quite adept at asking the important questions. And most have Autocad or CadKey to help resolve mechanical issues. Schematic compatibility isn't necessarily an issue; unless a schematic is _heavily annotated, a Tango-format netlist usually suffices for PCB input data, along with the necessary mechanical and electrical requirements. But ask for references! Brian Sherer At 05:56 PM 1/29/02 -0500, you wrote: Any Protel designers in the Toronto area? Hi, I am a lurker (engineer) that was considering Protel because I work with a MFR that uses Protel, but I wanted them in the loop only AFTER the first prototypes were built. This list has made me realize that the complexity of learning such a package won't be worth it. Unfortunately, using the Protel web site and looking for service bureaus reveals NONE in the area. Also, how well does Protel work with using ORCAD for the front end schematics (the up to date ones, not the old SDT) assuming that I am willing to create library entries for every component to match them. btw, this list is impressive. _ Do You Yahoo!? Get your free @yahoo.com address at http://mail.yahoo.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Report Length of Selection
Hi- I find the Length of Selected Trace function in v2.8 very useful for adjusting clock lines and microstrips, and keep 2.8 around for this sole purpose. Has anyone located this function in 99SE? Brian Sherer Foothill Services LLC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Length of Selection
Thanks to Phil and Mark - found it with no problem. I'll have to check the list of tools carefully; maybe there's a tool for Associative Dimensioning hidden in there.:) Brian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autorouter Stability Problems
Hi, John- In my experience, the two likeliest possibilities are 1) database buffer overrun, and 2) phantom primitives that no longer exist but are being treated as real. 1) Protel doesn't flag buffer overruns at all, in any server. It can occur when for instance multiple Polygon Pours are used instead of Split Planes on a multilayer design. It seems that Polygons are handled as a multiplicity of primitives, while Split Planes are handled as single entities. Database size seems to grow exponentially if Polygon Pours are used. In a failure to initialize or crash situation, this is often related to item 2. 2) For a design that has been heavily edited, there may be Polygons or Split Planes that exist in the database but are not displayed, or that duplicate existing objects. This is very hard to find, as Protel only sees the topmost or most recent object if you try to double-click an area to query existing entities. The phantom objects are not directly editable, apparently because they have been officially deleted/modified, even though they still exist wherever Protel keeps track of electrical connectivity at each physical point of the board. There are two ways to deal with removal of duplicates. First, inspect the design and determine where the real planes/polygons should exist. Next, run Board Info and check that all such objects are accounted for. If there are extra objects, you'll have to delete them, by A) export to Spread / Delete offending objects / Import from Spread. Usually, the Spreadsheet server will also overflow. Don't panic. Go back to the original file and do a Select All. Now select Edit /Move and double click on each Polygon and Plane to cause the Select Object list box to appear. Inspect the list for duplicate objects. If a duplicate is found, choose one of the duplicates and move it to a neutral area well outside the active board area. Deselect Outside the area of the moved object, then Edit/Clear to permanently delete it. Deselect All, then repeat the process until all duplicate Polygons and Duplicate Planes are removed. There must be a 1:1 correspondence between the Number of Polygons in Board Info, and the actual Polygoncount by inspection. The autorouter will _not_ flag the extras, however, if it is able to successfully route, the DRC _will_ show the extra polygon as a clearance errors at each point of the polygon. This is the only way I have found to remove Phantom objects regardless of their size/complexity, and is useful for designs where repeated polygon edits have trashed the database. Brian Sherer Foothill Services LLC [EMAIL PROTECTED] At 09:32 AM 1/19/02 -0600, you wrote: Hi guys I have been trying to get a board autorouted (I have done more complicated boards than this one, although this is an odd shape) and am having lockups 2minutes into the routing process, etc. I have 2 workstations that I ve tried running this on, and both have the same result: (running 99SE with Service Pack 6, #6.6.7) Unable to initialize unless I select all the components, pre-routes, and track, copy them to a new file, then Update PCB from connected copper . This is an extreme pain, as I have to redo my layer stackup and design rules. Lockups after a couple of minutes into the autorouting process; Never goes to 100% completion, although once it went to 97%. Previously I routed a Pentium III board with very few problems, but this board is somewhat less complex (10 layers, 3274 pads) this has been an absolute nightmare! I have burned up 6 days trying to get this to run. Any ideas? Will I be forced to export to Specctra send it out to a design bureau (very undesirable) Any assistance will be greatly appreciated!!! * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Board Mirroring
Flipping is simple (Select All - Edit - Move - Flip Selection (use Flip to Same Side). You can also Select - Move - X or Y to flip horizontally or vertically around the cursor base point. But, at least in older builds, routed copper lost all Net Association, and Identifiers still had to be forced to mirror. But it may work to first lay out all bottom components, flip the board, add top components, then route all. Brian Sherer Foothill Services LLC Kenmore WA (425) 483-1546 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
