> > Is there a reason to prefer Vdd over GND? The spec sheets often just
say
Just to contradict what I've just said (assuming it got through)
One reason for choosing Vdd over GND is that it allows easy connection
of open collector/drain outputs during one of those oh so rare bodge moments
* *
> Is there a reason to prefer Vdd over GND? The spec sheets often just say
> "tied high or low...", and my knowledge of theory is too weak to even
guess
> at an answer. :)
Not really but I think I would prefer GND for no good reason. As Andy
Gulliver said it is preferable to
use a resistor of so
Is there a reason to prefer Vdd over GND? The spec sheets often just say
"tied high or low...", and my knowledge of theory is too weak to even guess
at an answer. :)
TIA,
Dwight Harm.
> -Original Message-
> From: Andy Gulliver [mailto:[EMAIL PROTECTED]]
> Sent: Wednesday, March 28, 2001
lt;[EMAIL PROTECTED]>
Sent: Wednesday, March 28, 2001 6:08 PM
Subject: [PEDA] OT: Unused CMOS inputs (was: Reference)
> Is there a reason to prefer Vdd over GND? The spec sheets often just say
> "tied high or low...", and my knowledge of theory is too weak to even
guess
&
On 03:08 PM 28/03/2001 -0800, Dwight Harm said:
>Is there a reason to prefer Vdd over GND? The spec sheets often just say
>"tied high or low...", and my knowledge of theory is too weak to even guess
>at an answer. :)
>TIA,
>Dwight Harm.
Doesn't matter - insignificant effect on leakage current.
Designers
---
"Dwight Harm" <[EMAIL PROTECTED]> on 03/29/2001 09:08:46 AM
Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
cc: (bcc: Clive Broome/sdc)
Subject: [PEDA] OT: Unused CMOS
http://www.bagotronix.com
- Original Message -
From: Dwight Harm <[EMAIL PROTECTED]>
To: 'Protel EDA Forum' <[EMAIL PROTECTED]>
Sent: Wednesday, March 28, 2001 6:08 PM
Subject: [PEDA] OT: Unused CMOS inputs (was: Reference)
> Is there a reason to prefer Vdd over GN
, 2001 3:09 PM
To: 'Protel EDA Forum'
Subject: [PEDA] OT: Unused CMOS inputs (was: Reference)
Is there a reason to prefer Vdd over GND? The spec sheets often just say
"tied high or low...", and my knowledge of theory is too weak to even guess
at an answer. :)
TIA,
Dwight Harm.
>
- Original Message -
From: Hamid A. Wasti <[EMAIL PROTECTED]>
>
> If that is really the case, then you do not need to tie the input external
to
> the chip :-) The internal pullup resistor will pull the input to a high
> state
Hamid,
I agree with you, what is the purpose of using the
Mike Reagan wrote:
> Here is my guess, the input of a cmos circuit (inside of the IC) though it
> has a high input impedance to gnd, they have an internal resistor internally
> tied from the gate to Vdd.
If that is really the case, then you do not need to tie the input external to
the chip :-)
At 03:08 PM 3/28/01 -0800, Dwight Harm wrote:
>Is there a reason to prefer Vdd over GND? The spec sheets often just say
>"tied high or low...", and my knowledge of theory is too weak to even guess
>at an answer. :)
Someone correct me if I am wrong, but my understanding is that it does not
matte
: 29 March 2001 01:34
> To: Protel EDA Forum
> Subject: Re: [PEDA] OT: Unused CMOS inputs (was: Reference)
>
>
> At 03:08 PM 3/28/01 -0800, Dwight Harm wrote:
> >Is there a reason to prefer Vdd over GND? The spec sheets often just say
> >"tied high or low...", and m
Mike Reagan wrote:
> > Is there a reason to prefer Vdd over GND? The spec sheets often just say
> > "tied high or low...", and my knowledge of theory is too weak to even
> guess
> > at an answer. :)
> > TIA,
> > Dwight Harm.
>
> Dwight,
> Here is my guess, the input of a cmos circuit (inside
Matt wrote
> For some logic device families the input current is much smaller in the
high
> state than in the low state .
>
> Best Regards,
> Matt Tudor , MSEE
> Elmar Technologies
>
Thanks for confirming my theory. But this is correct as far as I know
See my previous post
Mike Reagan
EDSI
Actually, I have sometimes daisy chained unused sections of a
HC14 or HC04 since the pins in question are adjacent and the
lengths of the nets are minimized. The first in the chain
connects to the nearest of Vcc and GND.
If I recall correctly, TTL gates required a series resistor (I
don't know wh
Dwight Harm wrote:
> Is there a reason to prefer Vdd over GND? The spec sheets often just say
> "tied high or low...", and my knowledge of theory is too weak to even guess
> at an answer. :)
Sometimes it doesn't matter, as in a completely unused gate. Sometimes it
does matter, such as a comp
Asymmetric input current is a characteristic of the TTL logic family but is not the
case for CMOS.
Even TTL compatible CMOS (eg. ACT or HCT families) has a symmetric and very high input
impedence (leakage currents of less than 1 uA) for both low and high inputs. TTL
compatibility is accomplish
> Is there a reason to prefer Vdd over GND? The spec sheets often just say
> "tied high or low...", and my knowledge of theory is too weak to even
guess
> at an answer. :)
> TIA,
> Dwight Harm.
Dwight,
Here is my guess, the input of a cmos circuit (inside of the IC) though it
has a high inp
> For some logic device families the input current is much smaller in the
high
> state than in the low state .
>
> Matt Tudor , MSEE
I would have thought that this would *normally* be a pretty academic
consideration. Any contemporary series of logic devices has very low input
currents for both Vs
Dwight Harm wrote:
>
> Is there a reason to prefer Vdd over GND? The spec sheets often just say
> "tied high or low...", and my knowledge of theory is too weak to even guess
> at an answer. :)
> TIA,
> Dwight Harm.
Unused inputs to an otherwise used section of an IC (eg: "unused"
set/clear inpu
-Original Message-
From: Mike Reagan <[EMAIL PROTECTED]>
To: Protel EDA Forum <[EMAIL PROTECTED]>
Date: Wednesday, March 28, 2001 6:41 PM
Subject: Re: [PEDA] OT: Unused CMOS inputs (was: Reference)
>I believe the advantage of tying the inputs to Vdd is so the device will
>c
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