if
there's a base Fault that's outside the namespace as well, but maybe that's
a sign that there's a larger renaming that should be done.
Also, Fault:FaultBase seems more consistent with other naming than
FaultVals:Fault; I'm curious what motivated the change.
Gabe Black
changeset e4c5fbbc8633 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e4c5fbbc8633
description:
SPARC: Implement the version of movcc that uses the fp condition codes.
diffstat:
src/arch/sparc/isa/decoder.isa | 28 +++-
1 files changed, 27
On 2010-05-08 11:08:07, Steve Reinhardt wrote:
src/arch/arm/insts/mem.hh, line 252
http://reviews.m5sim.org/r/20/diff/1/?file=181#file181line252
seems like this should go in a .cc file
Gabe Black wrote:
Wouldn't that prevent it from being inlined? Or do we not care since
changeset 56bbefb997fe in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=56bbefb997fe
description:
X86: The logic that handled the recently fixed corner case for div
wasn't quite right.
___
m5-dev mailing list
m5-dev@m5sim.org
changeset c52c581277bf in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c52c581277bf
description:
X86: Actual change that fixes div. How did that happen?
diffstat:
src/arch/x86/isa/microops/regop.isa | 8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
if
there's a base Fault that's outside the namespace as well, but maybe that's
a sign that there's a larger renaming that should be done.
Also, Fault:FaultBase seems more consistent with other naming than
FaultVals:Fault; I'm curious what motivated the change.
Gabe Black
On 2010-05-08 11:08:07, Steve Reinhardt wrote:
src/arch/arm/isa/formats/data.isa, line 41
http://reviews.m5sim.org/r/20/diff/1/?file=206#file206line41
Is there a reason we can't use predefined bitfields here (and a ton of
other places)?
Gabe Black wrote:
ARM defines
On 2010-05-11 14:15:10, Steve Reinhardt wrote:
src/arch/arm/isa/formats/data.isa, line 1138
http://reviews.m5sim.org/r/20/diff/1/?file=206#file206line1138
It looks like cases 1 3 (and 9 and 0xb) are identical; right? If so,
I think they should be merged; getting rid of
On 2010-05-08 11:08:07, Steve Reinhardt wrote:
Overall I'm kinda disappointed that most of the decode ended up in C++ and
not in the ISA description language (I know the latter would have required
some extensions)... now that it's in place and (presumably) working though,
I guess
changeset b9480b90cf18 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b9480b90cf18
description:
X86: Update the stats for the new aux vectors in the ruby regression.
I forgot to turn on ruby when updating the stats before.
diffstat:
changeset 24379f92cc10 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=24379f92cc10
description:
Merge.
diffstat:
src/base/stats/visit.hh | 5 -
src/kern/tru64/tru64.hh | 2 +-
src/sim/syscall_emul.hh | 6 --
3 files changed, 5 insertions(+), 8 deletions(-)
There have been failures the last couple days. I looked at one of them,
and simerr had
Traceback (most recent call last):
File string, line 1, in module
File /z/m5/regression/zizzer/m5/src/python/m5/main.py, line 359, in main
exec filecode in scope
File tests/run.py, line 70, in module
or a network issue. I did forget to update the X86_SE ruby stats
though, so that explains one of the failures.
Gabe
Gabe Black wrote:
There have been failures the last couple days. I looked at one of them,
and simerr had
Traceback (most recent call last):
File string, line 1, in module
File /z/m5
Hi, sorry if my earlier reply was a bit redundant with Ali's here. It
ended up in my spam filter somehow. Anyway, one nice thing about x86
systems is they all have the same core platform that's been the same
forever, and it's well understood and documented to the point that I
could find some
changeset b8f2983a1c88 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b8f2983a1c88
description:
X86: Update the base aux vector X86 processes install.
diffstat:
src/arch/x86/process.cc | 28 +---
src/arch/x86/process.hh | 4
2 files
changeset e46d048f7e69 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e46d048f7e69
description:
X86: Update stats for the updated auxilliary vectors.
diffstat:
tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini |2 +-
changeset abdcb0389716 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=abdcb0389716
description:
X86: Finally fix a division corner case.
When doing an unsigned 64 bit division with a divisor that has its most
significant bit set, the division code would
changeset 68195a20503b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=68195a20503b
description:
Statetrace: Fix compile problems with the AMD64 version of statetrace.
diffstat:
util/statetrace/arch/tracechild_amd64.cc | 19 ++-
changeset d9823ce926fa in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d9823ce926fa
description:
X86: Sometimes CPUID depends on ecx, so pass that in.
diffstat:
src/arch/x86/cpuid.cc | 3 ++-
src/arch/x86/cpuid.hh | 3
We'll check this in on Friday unless someone asks us to wait. Get your
shots in now while there's still time!
Gabe
Gabe Black wrote:
Hi everybody. This is definitely a gigantic change, but one of the nice
aspects of reviewboard seems to be that you can review whatever sized
portion
I'm not familiar with EDGE or TRIPS, but I'm very skeptical any changes
would need to be made to the isa parser to support it. Please explain
what your changes are for, and why you weren't able to use some other
existing mechanism to get the same effect. The parser as is is actually
very flexible
---
This is an automatically generated e-mail. To reply, visit:
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---
This should be considered a first pass review which doesn't address every
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/15/#review3
---
This is also a first pass review. I focused only on the ISA description
---
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This change is pretty close to ok. If you fix up the things mentioned below,
There are some style issues with this code, although it looks like they
might partially be holdovers from the original code. There should be
spaces before and after the =s, the if, the =, and after the )
and the ,s. else should be on the same line as the closing bracket
of the if, and you probably
Woops, sorry. No extra space before the if, just one after it. Also, if
you're fascinated by our particular set of rules and want to learn more
(or if you're just bored :) ), the actual style guide is here:
http://m5sim.org/wiki/index.php/Coding_Style
Gabe
Gabe Black wrote:
There are some style
Without looking into it too deeply what you're saying seems plausible.
The best place for this sort of initialization in SE mode is, in my
opinion, in the process initialization code. Conceptually it's sort of
like the OS constructing the process context. The situation sounds
similar to SPARC
Those are good questions to answer because they point either to
non-determinism in the CPU or host state leaking into the simulation.
Another thing people suggested way back when when I was trying to fix
something similar was to use netcat with tracediff to compare execution
across two known
So it doesn't get missed in the pile, this one failed.
* build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
FAILED!
Cron Daemon wrote:
* build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby
passed.
*
Steve Reinhardt wrote:
On Fri, Mar 26, 2010 at 10:32 PM, nathan binkert n...@binkert.org wrote:
#1 sounds pretty good to me... 2 3 seem like overkill. I don't
think the overhead of the null pointer is that bad.
Ok, cool. I'll cook up a diff.
I'm partial to doing 1, 3, or
Steve Reinhardt wrote:
On Sat, Mar 27, 2010 at 12:20 AM, Gabe Black gbl...@eecs.umich.edu wrote:
What about one way packets that don't collapse back to the sender? Do we
have any of those? Or do we always collapse back at least with the ack?
I'm not sure what you're referring
X86 support is enabled for M5, although isn't 100% complete or debugged.
There are no x86 checkpoints or ways to generate them currently, but we
do have a number of x86 regression tests. Those check the statistics of
the simple atomic CPU, so if you were to use them directly you'd need to
fake
It's been a while since I've looked at this, but I want to make sure I
remember to respond so I don't want to wait until I have a chance to
re-research all this. Isn't the problem that initiateAcc ends up calling
completeAcc mid-function, that cleans up after the access, then
initateAcc gets
:
Hi Gabe,
On Sun, Mar 21, 2010 at 5:22 PM, Gabe Black gbl...@eecs.umich.edu wrote:
It's been a while since I've looked at this, but I want to make sure I
remember to respond so I don't want to wait until I have a chance to
re-research all this. Isn't the problem that initiateAcc ends up
I wanted to fix it, but we never really found a way to do that, at least
that everybody could agree on. In my opinion, the timing simple CPU
needs a subtle but fundamental rework to avoid this class of bugs. Also,
that'll take more time than I personally have available these days, so
I'm not going
I've thought about these sorts of hard to reproduce failures before, and
thought maybe we should have the regressions periodically dump stats?
That way we could tell roughly when something diverged. I don't know if
that would actually tell us much, but it would tell us more and sounds
to my naive
(Practically speaking, do we
support anything other than linux on any other ISA?)
Only supporting Linux doesn't mean the OS never changes. It would be
nice to be able to test both 32 and 64 bits of Linux in both FS and SE,
or even different configurations of each. This is especially true
I asked the same question a while ago. I don't remember the reason but
there is one.
Gabe
Korey Sewell wrote:
Okay great, thanks Lisa.
So the follow-up question for anyone inclined to answer is: Is there
ever a reason to have a counter variable and a stat variable? Is
there something with
changeset f2b4d8bea5d3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f2b4d8bea5d3
description:
Config: Fix fs.py's call to CacheConfig.config_cache.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
configs/example/fs.py |4 ++--
diffs (15 lines):
diff
verbatim probably more than they're used as
examples, so it would be a good idea to actually test them.
My fourth reaction was that these scripts seem overly complicated to me,
and that probably makes mistakes like this a lot easier to make than is
really necessary.
Gabe
Gabe Black wrote:
changeset
As I mentioned before, ARM has an IT instruction which choses a
condition to predicate up to the next 4 instructions on. The particular
condition and the number of instructions left to predicate are available
in a control register and are set/saved/loaded to save context on
interrupts and
The original email and my own vague memories suggest these patches were
sent out once, there was some feedback, and you fixed them up and sent
them out again. Is that right? I looked through them fairly quickly and
didn't see anything that seemed wrong. The majority of the changes are
in O3, I
Hi Matt. Sorry no one has taken a look at this yet, at least that I'm
aware of. We haven't forgotten you, but it might take a little while
before we can get this taken care of.
Gabe
Matt DeVuyst wrote:
I fixed the problem. See the attached patch.
For the case of writing 3 bytes to memory,
I don't really know anything about the situation here, but is it
possible to just call a function to take care of the thread activation
at the end of the tick event? I'm making the assumption that every time
a thread is activated a tick should have already happened for that instant.
Gabe
Korey
This change seems to have broken the build for everything except Alpha
(no regressions?). I don't like that #if THE_ISA. What is it doing, and
why can't it be done in some Alpha specific body of code?
Gabe
Hsu, Lisa wrote:
This is the last one.
Lisa
-Original Message-
From:
Unless I'm missing something, those aren't available in the interface
instructions use to talk to the CPU (see exec_context.hh).
Gabe
nathan binkert wrote:
Why not use readBlob and writeBlob?
Nate
On Wed, Jan 20, 2010 at 2:48 AM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
A
changeset cdf3b0523858 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cdf3b0523858
description:
SCons: Make --help reflect the arguments to scons.
The arguments were added to the global_sticky_vars Variables object
after the
basic help text was
It looks like I forgot to update the Ruby version of the MIPS
regressions after changing the process initialization code. I'll try to
take care of that at some point today, but if anyone's in a hurry (or
bored) it should be fine to just update them.
Gabe
Cron Daemon wrote:
*
changeset 9e14a8c76257 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9e14a8c76257
description:
MIPS: Update the stats of the RUBY version of the regressions.
diffstat:
16 files changed, 71 insertions(+), 67 deletions(-)
changeset 45879b0e3240 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=45879b0e3240
description:
MIPS: Extract CPU pointer from the thread context in scheduleCP0
setMiscReg.
The MIPS ISA object expects to be constructed with a CPU pointer it
uses to
changeset 14fbdb0f9585 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=14fbdb0f9585
description:
MIPS: Create an artificial control register to hold the thread pointer.
In Linux, the set_thread_area system call stores the address of the
thread
local
changeset baa5ec031980 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=baa5ec031980
description:
MIPS: Implement the set_thread_area system call.
diffstat:
1 file changed, 11 insertions(+), 1 deletion(-)
src/arch/mips/linux/process.cc | 12 +++-
diffs (29
changeset d99f7b0ac614 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d99f7b0ac614
description:
MIPS: Fix decoding of the rdhwr instruction.
diffstat:
1 file changed, 2 insertions(+), 4 deletions(-)
src/arch/mips/isa/decoder.isa |6 ++
diffs (16 lines):
diff
changeset 451ddd5d50d6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=451ddd5d50d6
description:
MIPS: Update stats for updated initial environment.
diffstat:
12 files changed, 582 insertions(+), 590 deletions(-)
I notice that you comment out some function calls in this patch, and
that's probably not the right thing to do. You wouldn't be the first,
but generally it's better to either fix the problem by fixing the
function, to get rid of the broken implementation entirely (probably too
drastic), add a
This looks right to me and good catch. Does this look right to you,
Korey? We should be able to get this in immediately by leaving off the
change to the filterDoubles function for now.
Gabe
Matt wrote:
I stumbled across another MIPS floating-point problem. This one has
to do with conversion
(if it cannot be configured to support
64-bit wide FP registers) instead of just silently doing something
unpredictable.
On Tue, Dec 29, 2009 at 5:27 AM, Gabe Black gbl...@eecs.umich.edu wrote:
I notice that you comment out some function calls in this patch, and
that's probably not the right thing
changeset aa9e72a7d8d3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aa9e72a7d8d3
description:
MIPS: Add missing syscall slots.
These are all after the existing ones, suggesting they were added after
the
original list was created.
diffstat:
1 file
changeset 335f8b406bb9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=335f8b406bb9
description:
X86: Create a common flag with a name to indicate high multiplies.
diffstat:
5 files changed, 30 insertions(+), 23 deletions(-)
src/arch/x86/insts/micromediaop.hh
changeset 36131e4dfb6e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=36131e4dfb6e
description:
X86: Create a common flag with a name to indicate scalar media
instructions.
diffstat:
16 files changed, 134 insertions(+), 115 deletions(-)
These changes to the media uops work towards cleaning up ext but don't
cover everything yet. This was to prevent what I had working from going
stale again.
Gabe
Gabe Black wrote:
changeset 335f8b406bb9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=335f8b406bb9
description
In the mean time, is there any way to get a binary that will work right
now so I can fix the floating point problem?
Gabe
Korey Sewell wrote:
I think the unsupported instruction is the rdhwr instruction.
Aaah, i see more than likely that instructions is impl. specific
so GDB may
Hi everybody. Rather than blowing out your inboxes with 90 patches,
please pull my patch queue from ssh://h...@m5sim.org/arm-patches.
Everything is included except the obviously labeled final patch. As far
as I know I haven't broken anything, but since we've only got one fairly
easy
program, it won't do anything your version of M5 doesn't yet
support.
On Sat, Dec 12, 2009 at 4:54 PM, Gabe Black gbl...@eecs.umich.edu wrote:
Matt wrote:
I'm having problems getting double-precision floating-point to work in
m5 for the MIPS isa.
The 32-bit MIPS isa has 32 32-bit
There are a few minor things I notice. First, you should have spaces
around your operators, ie. ab should be a b. Second, I don't
think you need to explicitly set IntAluOp in places you're using an
integer register like Ra. Steve wouldn't know for sure. Third, in ctpop,
you don't need to put Rb
is relatively minor, so you can go ahead and commit this and
I'll fix it up in my change, or you can wait and I can describe what
you'd need to do.
Gabe
Vince Weaver wrote:
On Fri, 6 Nov 2009, Gabe Black wrote:
You seem to be missing the majority of the PC relative version... Would
you like
Matt wrote:
I'm having problems getting double-precision floating-point to work in
m5 for the MIPS isa.
The 32-bit MIPS isa has 32 32-bit floating-point registers.
Double-precision floating-point numbers are stored in pairs of
floating-point registers. At least that's how I understand it.
Gabe Black wrote:
Gabriel Michael Black wrote:
Quoting Korey Sewell ksew...@umich.edu:
I haven't checked too carefully, but this same problem may be
affecting ARM as well (since I think it uses the same paired
floating-point register scheme). Also, other double-precision
Gabriel Michael Black wrote:
Quoting Korey Sewell ksew...@umich.edu:
I haven't checked too carefully, but this same problem may be
affecting ARM as well (since I think it uses the same paired
floating-point register scheme). Also, other double-precision things
like checking for NaNs may
Does anybody have any comments? I'd like to address any issues sooner
rather than later.
Gabe
Gabe Black wrote:
Hi everybody. I've been doing a bunch of work on our ARM support,
and I've run into a few issues unique (or at least especially present)
to that ISA. I have solutions that I've
Hi everybody. I've been doing a bunch of work on our ARM support,
and I've run into a few issues unique (or at least especially present)
to that ISA. I have solutions that I've partially implemented, but I
wanted to talk about them here so everyone will have a chance to comment.
1. Many
Generally this looks like a fairly straightforward port replacement of
the original code with something essentially equivalent which is fine.
One issue is the new virtual finishTranslation function. Since
translation will happen very frequently (at least once a fetch), it's
best to avoid a
/src/arch/arm/kernel_stats.hh
copy from src/arch/sparc/kernel_stats.hh
copy to src/arch/arm/kernel_stats.hh
--- a/src/arch/sparc/kernel_stats.hh
+++ b/src/arch/arm/kernel_stats.hh
@@ -28,8 +28,8 @@
* Authors: Gabe Black
*/
-#ifndef __ARCH_SPARC_KERNEL_STATS_HH__
-#define
Why did you change the namespaces from ArmISA to ArmISAInst? ArmISAInst
is supposed to be a private namespace for the isa_parser to dump into.
It avoids mixing generated and handcoded namespaces and all the problems
that can cause. Also, while I don't disagree with your indentation
changes,
changeset 72836109775f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=72836109775f
description:
ARM: Create a new type of load uop that restores spsr into cpsr.
diffstat:
1 file changed, 17 insertions(+)
src/arch/arm/isa/formats/macromem.isa | 17 +
changeset e9970c1bccdd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e9970c1bccdd
description:
ARM: Make the exception return form of ldm restore CPSR.
diffstat:
1 file changed, 10 insertions(+), 3 deletions(-)
src/arch/arm/isa/formats/macromem.isa | 13
This sort of question should be on the m5sim-users mailing list. Please
move it there.
Gabe
Sujay Phadke wrote:
Hello,
I am trying to use M5-dev (latest) in SE mode with multiple cpu's
(n=4) switching from atomic-timing-detailed. However, the assertion
in
Would you be able to use srcSizeBits instead of srcSignIndex? This is
defined as the number of bits in a source operand, so you might need to
subtract one to get the right index. If you substitute and simplify your
expression for srcSignIndex (which the compiler is hopefully doing
already), I
changeset cdc62b81747e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cdc62b81747e
description:
ARM: Hook up the moded versions of the SPSR.
These registers can be accessed directly, or through MISCREG_SPSR which
will
act as whichever SPSR is
changeset 7d2767d7896f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7d2767d7896f
description:
ARM: More accurately describe the effects of using the control operands.
diffstat:
1 file changed, 6 insertions(+), 6 deletions(-)
src/arch/arm/isa/operands.isa | 12
changeset dc2adb75 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=dc2adb75
description:
ARM: Write some functions to write to the CPSR and SPSR for
instructions.
diffstat:
1 file changed, 50 insertions(+)
src/arch/arm/insts/static_inst.hh | 50
changeset ad8698d92176 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ad8698d92176
description:
ARM: Fix up the implmentation of the mrs instruction.
diffstat:
1 file changed, 4 insertions(+), 2 deletions(-)
src/arch/arm/isa/decoder.isa |6 --
diffs (23
changeset ac658ad78659 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ac658ad78659
description:
ARM: Add a bitfield to indicate if an immediate should be used.
diffstat:
2 files changed, 2 insertions(+)
src/arch/arm/isa/bitfields.isa |1 +
src/arch/arm/types.hh
changeset 33ac9df63f3e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=33ac9df63f3e
description:
ARM: Define a mask to differentiate purely CPSR bits from CondCodes
bits.
diffstat:
1 file changed, 4 insertions(+)
src/arch/arm/miscregs.hh |4
diffs (14 lines):
changeset 065d296b929b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=065d296b929b
description:
ARM: Fix up the implmentation of the msr instruction.
diffstat:
1 file changed, 27 insertions(+), 10 deletions(-)
src/arch/arm/isa/decoder.isa | 37
changeset 097d0a64650f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=097d0a64650f
description:
ARM: Switch the immediate and register versions of msr.
These were accidently transposed. This change straightens them out.
diffstat:
0 files changed
changeset c2b6531c305c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c2b6531c305c
description:
ARM: Check in the actual change from the last commit.
The last commit was somehow empty. This was what was supposed to go in
it.
diffstat:
1 file changed, 12
changeset 4ac7bc30c482 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4ac7bc30c482
description:
ARM: Fix the integer register indexes.
The PC indexes in the various register sets was defined in the section
for
unaliased registers which was throwing off
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Gabe Black
- * Stephen Hines
+ * Authors: Ali Saidi
+ * Gabe Black
*/
#include arch/arm/faults.hh
#include cpu/thread_context.hh
#include cpu
changeset 530e457c88c7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=530e457c88c7
description:
X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/arch/x86/isa/microops/ldstop.isa |4 ++--
diffs (21
changeset b3ab661715ac in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b3ab661715ac
description:
X86: Explain what really didn't work with unmapped addresses in SE mode.
diffstat:
1 file changed, 13 insertions(+), 3 deletions(-)
src/arch/x86/tlb.cc | 16
changeset 44010fc924d4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=44010fc924d4
description:
X86: Don't panic on faults on prefetches in SE mode.
diffstat:
1 file changed, 15 insertions(+), 11 deletions(-)
src/arch/x86/tlb.cc | 26 +++---
changeset 48d10ba361c9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=48d10ba361c9
description:
Mem: Eliminate the NO_FAULT request flag.
diffstat:
8 files changed, 26 insertions(+), 10 deletions(-)
src/arch/alpha/faults.cc |2 +-
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Gabe Black
- * Stephen Hines
+ * Authors: Ali Saidi
+ * Gabe Black
*/
#include arch/arm/faults.hh
#include cpu
changeset 73d89772f409 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=73d89772f409
description:
ARM: Fix some bugs in the ISA desc and fill out some instructions.
diffstat:
5 files changed, 98 insertions(+), 41 deletions(-)
src/arch/arm/isa/bitfields.isa|1
nathan binkert wrote:
Gabe, can you send out your patches inline, not as attachments? Did
you switch intentionally? It makes it harder to comment on your
changes.
Nate
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changeset 0ad05775b549 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0ad05775b549
description:
ARM: Get rid of some unneeded register indexes.
diffstat:
1 file changed, 30 deletions(-)
src/arch/arm/registers.hh | 30 --
diffs (47 lines):
IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include assert.h
+
+#ifndef __ARCH_ARM_INTREGS_HH__
+#define __ARCH_ARM_INTREGS_HH__
+
+namespace ArmISA
+{
+
+enum IntRegIndex
+{
+/* All the unique register indices. */
+INTREG_R0,
+INTREG_R1
changeset 260676453f66 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=260676453f66
description:
ARM: Initialize processes in user mode.
I accidentally left in a change to test using int registers in system
mode.
This change reverts that.
diffstat:
1
changeset 36aa46630e62 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=36aa46630e62
description:
ARM: Get rid of the Raddr operand.
diffstat:
1 file changed, 1 deletion(-)
src/arch/arm/isa/operands.isa |1 -
diffs (11 lines):
diff -r 260676453f66 -r 36aa46630e62
801 - 900 of 1750 matches
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