I know that I wasn't good about this with Alpha, but a comment in the
code with a reference to documentation that explains the numbers
you've stuck in there would generally be very nice.
Nate
On Sun, Feb 1, 2009 at 5:18 PM, Gabe Black gbl...@eecs.umich.edu wrote:
changeset a2c317cefcf8 in
You're manually setting loops per jiffy?
On alpha at least, we have a hook for the function that calculates it
and programatically return the number based on the clock frequency
selected.
I guess I should respond via e-mail for the record.
See arch/alpha/linux/system.(cc|hh)
Sure. Does that work like warn once? It's in a position to be called a lot.
There's hack() and hack_once(). Though, you bring up a good point as
to whether it is worth ever printing a hack message more than once.
Nate
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Hi Korey,
I'm like to start looking at this now. Do you have any outstanding
changes? Is there a time when I can have a lock on the repository to
work with your patches on my own?
I did make one commit to the patch repository. I removed the status
file since that depends on each person's
You'll notice the 12345 part in the line. That means load that when
you're in one of those init levels. Thing is, I think that with the
way we boot, you may still be in S (single user). So, what ali says
is probably necessary (the console= line). Doing a higher value like
115200 means that it
Woo! Super awesome! We generally don't run init and do our own thing,
so it should be even easier to move forward.
What's next?
Nate
On Wed, Feb 4, 2009 at 1:08 AM, Gabe Black gbl...@eecs.umich.edu wrote:
A little over dramatic perhaps, and it's not quite right, but tada!
Again! It even
changeset 040d328ce5de in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=040d328ce5de
description:
ignore some stuff
diffstat:
1 file changed, 4 insertions(+)
.hgignore |4
diffs (8 lines):
diff -r cd969187e2d3 -r 040d328ce5de .hgignore
--- /dev/null Thu
: Nathan L. Binkert
++# Authors: Nathan Binkert
+
+import sys
+
@@ -312,47 +287,49 @@
+ Source('thread_context.cc')
+ Source('cpu.cc')
+
-diff -r db1653549204 src/cpu/mixie/SConsopts
/dev/null Thu Jan 01 00:00:00 1970 +
-+++ b/src/cpu/mixie/SConsopts Mon Nov 24 18:03:46 2008
changeset d33c963656cb in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=d33c963656cb
description:
organize patches
diffstat:
10 files changed, 3446 insertions(+), 10152 deletions(-)
fix_compile.diff| 94
fix_mdu_latency_bug | 533 ---
changeset 40721d032036 in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=40721d032036
description:
Make sure everything compiles just fine
diffstat:
2 files changed, 15 insertions(+), 11 deletions(-)
import_mixie |4 +---
prepare_cpus.diff | 22
changeset d3fea0b4646c in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=d3fea0b4646c
description:
Rename mixie to inorder
diffstat:
3 files changed, 1185 insertions(+), 1185 deletions(-)
import_mixie| 2364 +--
changeset 8c1aa74572e4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8c1aa74572e4
description:
Quell g++ 4.3 warning about operator ambiguity
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |2 +-
diffs (12 lines):
We don't have it because we haven't implemented an ISA that supports
it, so I see no reason not to add it. (It's pretty odd to put a fence
in for reads and not want writes to be fenced too.)
Nate
On Fri, Feb 6, 2009 at 9:06 PM, Gabe Black gbl...@eecs.umich.edu wrote:
I notice that we
I want to move the minimum SCons version forward. Currently, the
minimum is 0.96.91 which has a bunch of warts which are annoying.
Does anyone have a reason for me not to move to 0.98.0? Should I move
it even further forward?
There's always scons-local if people don't have local
What are the specific warts and in what version are they fixed?
Sigh. Alright, here goes.
I'm trying to significantly improve the build framework and there is a
lot that has improved in scons with respect to our minimum version.
More specifically, I've figured out how to reduce both the null
Thank you. To me that sounds worth it. Although a page describing
scons-local perhaps linked to the EnusreScons() check would be a
necessity.
That's exactly what I'd do.
Nate
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Are you talking about just x86?
Nate
On Mon, Feb 9, 2009 at 1:19 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
I have a patch in my queue which, for reasons I can get into if people
are interested, prevents fetching in the simple CPU while in the
middle of a macroop. A side effect
changeset 50fb2cb40609 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=50fb2cb40609
description:
scons: Don't build the intermediate static library unless explicitly
requested.
This means that similar to libm5_fast.so, you need to explicitly build
Feb 09 20:10:14 2009 -0800
@@ -27,6 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
+# Nathan Binkert
###
#
@@ -63,25 +64,55
changeset 780dd1bead5c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=780dd1bead5c
description:
copyright: This file need not have had the more restrictive copyright.
diffstat:
1 file changed, 9 insertions(+), 36 deletions(-)
src/arch/x86/SConsopts | 45
Hi Developers,
I just wanted to let everyone know that I pushed a change that will
move the minimum version of SCons forward to 0.98.1. This release is
less than a year old, but it prepares us for upcoming fatal errors for
removed features while also allowing me to work on some significant
changeset 09ab46bfa914 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=09ab46bfa914
description:
InOrder: Import new inorder CPU model from MIPS.
This model currently only works in MIPS_SE mode, so it will take some
effort
to clean it up and make it
Just one little nit to pick: this function definition here should be in
static_inst.cc and not static_inst.hh. It certainly doesn't need to be
inlined for performance reasons, and since it's virtual it won't get inlined
anyway, so there's no point in cluttering the header file with it.
That
I'll give the short version here: MIPS was implemented ot use the MT ISA
extension
which requires the ability to read/write registers from other threads. I
designed the register file
to be on size fits all. It can be instantiated multiple times as a
per-thread register file (Simple-CPU) OR
changeset 5645632d594c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5645632d594c
description:
style
diffstat:
2 files changed, 63 insertions(+), 47 deletions(-)
src/cpu/static_inst.cc | 43 --
src/cpu/static_inst.hh | 67
, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+import os
+import sys
+
+from os.path import expanduser, isdir, isfile, join as joinpath
+
+homedir = os.environ
.
- Clint
On Jan 6, 2009, at 6:02 PM, nathan binkert wrote:
I feel like I'm missing some context with this patch (though I will
admit to not following the mailing list very closely after the last
few months. Was this the solution to us not being able to switch back
to timing from detailed
I don't get a holiday Monday... bummer. I'm free pretty much all day
though. I'm also free Tue afternoon and Wed afternoon exc. 2:30-3.
Tue/Wed evenings are bad for me.
Tuesday and Wednesday afternoons wouldn't be great for me since I'd
probably have to leave work to attend, but a phone
I'll look at it, but it does raise the concern that everything but the
latest releases of OSes will need a custom package to get to Scons .
98.1
I thought that was clear from my e-mails. It is honestly very easy to
get a compliant SCons.
Nate
I really appreciate the help!
As far as location, I agree src is the wrong place... how about under util,
like util/scons or util/sconshelp?
That also doesn't seem to fit for me, but if a top level directory is
the wrong place, util is the best. I still think I like buildlib at
the top better,
My toy example of this is say I want to read a integer register from an
instruction. I could either go:
(1) inst-threadContext-readIntReg()
or
(2) inst-cpu-readIntReg()
In the threadContext object, there is just some redundant call to
cpu-readIntReg() anyway. So you end up calling (1) and
changeset 98f6215dffce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=98f6215dffce
description:
SCons: Fix read_command so it can properly deal with command strings
diffstat:
1 file changed, 3 insertions(+)
SConstruct |3 +++
diffs (13 lines):
diff -r
changeset 67a6ea624776 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=67a6ea624776
description:
traceflags: fix --trace-help
diffstat:
3 files changed, 19 insertions(+), 18 deletions(-)
src/python/m5/main.py | 13 -
src/python/m5/trace.py
In x86 there are at least three different ways to call a system
call, int $0x80, sysenter, and syscall. In 64 bit mode I think syscall
is pretty much guaranteed to be there so glibc uses it directly, or at
least that's been my experience. For 32 bit x86, though, sysenter, the
preferred of
If #2 didnt exist, then that would make more sense to me. That would make an
instruction HAVE to use the threadContext interface to access any CPU
facilities. That would also remove the CPU pointer from the instruction
object as well.
If that were the solution, I would be OK with it, because
It's only a few instructions to push three registers on the stack, use
the appropriate instruction, pop those three, and return. All together
it's 11 bytes.
I don't think one can claim copyright on 11 bytes.
Nate
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m5-dev mailing list
I'm not sure I all the way understand why the register file shouldnt be
defined in the ISA...
I could see maybe there being one standard integer and floating point
register file thats totally generic however, the system/miscellaneous
registers are pretty ISA dependent so those register
there?
2009/2/17 Korey Sewell ksew...@umich.edu
Hmmm...Dont know what's going on here.. I just reinstalled mercurial with
no luck...
Can someone post the contents of their build/ALPHA_SE/python/m5/defines.py
file so I can see the differences going on?
On Mon, Feb 16, 2009 at 4:19 PM, nathan
]
hgext.mq =
patchbomb =
style = /home/ksewell/m5/util/style.py
So for some reason, adding patch-queue to the repo just kills the
build for me...
On Tue, Feb 17, 2009 at 3:18 PM, nathan binkert n...@binkert.org wrote:
I think that the problem is that you've got stuff in your hgrc
changeset e9f9c0f7e5f0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e9f9c0f7e5f0
description:
events: Make trace events happen at the right priority.
Also, while we're at it, remember that priorities are in the Event class
and add a disable method to
Hi Steve/everyone,
right now, we have code in src/python/swig. I'm thinking that for the
swig stuff, we should distribute the .i files along with the code they
wrap. Mostly this means that swig code goes in sim. I'm thinking
about this because I was going to add a .i file or two and wanted to
What a coincidence... I've never really looked at this code before about 4
hours ago. Brad and I were wondering where Stats::dump() gets called, and I
poked around and found src/python/swig/stats.i, and the first thing I thought
was shouldn't this really go in src/base/stats? I was going
1) not sure why the mt.hh file didnt get added to the patch, but it
should be there
I think the real problem is that you're adding an mt.hh, but only for
mips. That doesn't work so well with the switching directory code.
___
m5-dev mailing list
changeset 1db89432381b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1db89432381b
description:
stats: clean up the statistics unittest
diffstat:
1 file changed, 55 insertions(+), 50 deletions(-)
src/unittest/stattest.cc | 105
changeset 9775f70fbe66 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9775f70fbe66
description:
stats: move the limits stuff into the types.hh file
diffstat:
2 files changed, 3 insertions(+), 3 deletions(-)
src/base/statistics.hh |3 ---
src/base/stats/types.hh |
changeset 02e5bc7ca9ba in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=02e5bc7ca9ba
description:
stats: reorganize how parameters are stored and accessed.
diffstat:
4 files changed, 209 insertions(+), 197 deletions(-)
src/base/statistics.cc | 24 ++-
-0800
@@ -26,7 +26,6 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
- * Erik Hallnor
*/
/** @file
@@ -60,6 +59,7 @@
#include string
#include vector
+#include base/cast.hh
#include base/cprintf.hh
#include base
changeset c810b7d4383d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c810b7d4383d
description:
stats: cleanup static stats to make startup work.
This is mainly to allow the unit test to run without requiring the
standard
M5 stats from being initialized
I've noticed that that command runs frequently when unnecessary, but
I'm surprised that it causes a problem. Are you pushing and popping
patches? Now that we're putting the repository version into the
binary, when you push and pop, this changes. I have noticed that this
runs sometimes even if
[Polina- We should really have these conversations on the list so
everyone can benefit from them and to give others the chance to
respond]
Hi Nate,
I am trying to get SPARC_FS to run. I am trying to run two processors
and what I have so far is the following:
Processor 0 gets activated and
(most recent call last):
File string, line 1, in module
File /tmp/m5/src/python/m5/main.py, line 315, in main
e = event.create(trace.enable, Event.Trace_Enable_Pri)
NameError: name 'Event' is not defined
Ali
On Feb 18, 2009, at 2:37 PM, Nathan Binkert wrote:
changeset
Can you commit?
Thanks,
Nate
On Wed, Feb 25, 2009 at 8:59 AM, Ali Saidi sa...@umich.edu wrote:
That fixed it.
Ali
On Feb 25, 2009, at 1:37 AM, nathan binkert wrote:
Sorry. It should be event.Event... Does that fix it?
On Tue, Feb 24, 2009 at 10:27 PM, Ali Saidi sa...@umich.edu wrote
again.
Gabe
nathan binkert wrote:
Can you commit?
Thanks,
Nate
On Wed, Feb 25, 2009 at 8:59 AM, Ali Saidi sa...@umich.edu wrote:
That fixed it.
Ali
On Feb 25, 2009, at 1:37 AM, nathan binkert wrote:
Sorry. It should be event.Event... Does that fix it?
On Tue, Feb 24, 2009 at 10
changeset 0ea37baabfb0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0ea37baabfb0
description:
quell gcc 4.3 warning
diffstat:
1 file changed, 4 insertions(+), 4 deletions(-)
src/arch/x86/tlb.cc |8
diffs (25 lines):
diff -r d4cb6394049b -r 0ea37baabfb0
I agree that this stuff is all messed up. There's threads and cpus
each which have various states that don't necessarily work with each
other. Some of the states have to do with indicating that a CPU has
nothing to do at the moment so we don't need to schedule a tick, and
some indicate the type
things for FS breaks SE and vice-versa.
Needless to say, we should probably get this straightened out and
documented in the near future...
On Sat, Feb 28, 2009 at 9:30 PM, nathan binkert n...@binkert.org wrote:
I agree that this stuff is all messed up. There's threads and cpus
each which have
I think that Steve is the only one who both pays attention to the list
and might understand what's going on here.
Nate
On Mon, Feb 23, 2009 at 2:30 AM, Gabe Black gbl...@eecs.umich.edu wrote:
I was working on getting the X86_FS working with the timing simple
CPU as well as it does with
@@ -53,6 +53,15 @@ struct InterStageStruct {
uint64_t nextPC;
InstSeqNum squashedSeqNum;
bool includeSquashInst;
+
+ InterStageStruct()
+ {
+ size = 0;
+ mispredPC = nextPC = 0;
+ squash = branchMispredict = branchTaken = false;
+
The m5 binary on the disk image that we distribute doesn't support the
pin command. You'll need to compile it yourself. Additionally, I don't
believe libc on the disk image supports sched_setaffinity (needed by
pin). This is something we need to fix, but it unfortunately involves
distributing
+ int id()
+ {
+ return _id;
+ }
+
This one should be declared const. int id() const ...
Please try to use const properly.
Nate
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http://m5sim.org/mailman/listinfo/m5-dev
If you want to get going quickly, you can download the scons-local
package and just stick it somewhere.
Nate
2009/3/5 Polina Dudnik pdud...@gmail.com:
Yes, I am trying to figure it out right now by running it withing gdb. It is
pretty interesting that my output only differs from yours by one
There are multiple benchmarks that can be run in FS mode (like
ValStream). Where can I find a precise description of what those
benchmarks do exactly? The reason I ask is because I would like to
verify their behavior on SPARC_FS.
I don't know if much has been written down other than in papers
changeset 9c04119e93af in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9c04119e93af
description:
serialize: Allow floats and doubles to be serialized
diffstat:
1 file changed, 2 insertions(+)
src/sim/serialize.cc |2 ++
diffs (12 lines):
diff -r 3ca926101a5c -r
changeset 71e56052768f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=71e56052768f
description:
stats: miscellaneous cleanup
diffstat:
1 file changed, 7 insertions(+), 9 deletions(-)
src/base/statistics.hh | 16 +++-
diffs (82 lines):
diff -r
changeset 19131d568007 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19131d568007
description:
stats: get rid of meaningless uses of virtual
diffstat:
1 file changed, 79 insertions(+), 79 deletions(-)
src/base/statistics.hh | 158
changeset 2c9823c60c8c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2c9823c60c8c
description:
stats: better naming of template parameters for the wrapper stuff
Parent and Child are bad names. Derived and Base are better.
diffstat:
1 file changed, 25
changeset 7674070ccc92 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7674070ccc92
description:
stats: Add a wrapper class for the information side of things.
This provides an easy way to provide the callbacks into the data side
of things from the info
changeset 471090ec173e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=471090ec173e
description:
stats: stick the distribution's fancy parameter into the parameters
structure.
diffstat:
3 files changed, 22 insertions(+), 26 deletions(-)
src/base/statistics.hh | 23
changeset a4c935e9cf99 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a4c935e9cf99
description:
stats: remove the template wart left over from the ancient binning stuff
diffstat:
1 file changed, 14 insertions(+), 28 deletions(-)
src/base/statistics.hh | 42
changeset 3cf8e71257e0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3cf8e71257e0
description:
stats: Fix all stats usages to deal with template fixes
diffstat:
50 files changed, 486 insertions(+), 486 deletions(-)
src/arch/alpha/kernel_stats.hh| 12
changeset 4f887be9e1b6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4f887be9e1b6
description:
stats: clean up how templates are used on the data side.
This basically works by taking advantage of the curiously recurring
template
pattern in an
changeset 00251eb95de7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=00251eb95de7
description:
stats: create an enable phase, and a prepare phase.
Enable more or less takes the place of check, but also allows stats to
do some other configuration.
Stats::Vector
These should now just be:
Stats::Scalar
Stats::Vector
You're simply removing the which was totally useless anyway.
Nate
On Thu, Mar 5, 2009 at 7:11 PM, Nathan Binkert n...@binkert.org wrote:
changeset a4c935e9cf99 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node
Here's another option: make the CPU model smart and when it sees a
lock access have it keep running until it sees an unlock access.
This might not be too bad if keep running could be implemented
simply by doing something like a recursive tail call to tick().
There's already a big loop in the
How different are ITBs and DTBs anyway? It seems like for a UTB you'd
want a single object that handles both ifetch and data translations
using a common translate() method, not something that inherits from
two different classes. E.g., why not just derive it from TLB?
The two translation
I'll keep both pointers then. I have all the non-ISA bits and X86
converted and I'm trying to test it, but I'm running into a compile
error in the stats stuff. Nate?
cc1plus: warnings being treated as errors
build/X86_SE/base/statistics.hh: In member function
'Stats::VectorDistribution
That's odd... if it doesn't work that way, I'd consider that a bug.
On Fri, Mar 6, 2009 at 10:18 AM, Gabe Black gbl...@eecs.umich.edu wrote:
I tried something like this before, and I don't think it works because
self.dtb is a paramdesc, not a SparcTLB. What Nate told me to do was to
::init(Stats::size_type, Stats::Counter,
Stats::Counter, Stats::Counter)':
build/X86_SE/base/statistics.hh:2498: warning: converting to
'Stats::size_type' from 'double'
Steve Reinhardt wrote:
On Fri, Mar 6, 2009 at 10:19 AM, Gabe Black gbl...@eecs.umich.edu wrote:
nathan binkert wrote:
You
1. Diff the outputs and set the pass/fail status based on the result.
2. Declare the test's status as failed regardless of the outputs but
consider the job of running the test as completed successfully. The
test will not be re-run unless some dependence changes (like one that
causes the m5
changeset 7d75f1a525db in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7d75f1a525db
description:
build: fix errors for compilers other than g++ 4.3
diffstat:
2 files changed, 2 insertions(+), 2 deletions(-)
src/base/cp_annotate.hh |2 +-
src/base/statistics.hh |
changeset 8f374fd9a348 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8f374fd9a348
description:
scons: fix the library path stuff
diffstat:
1 file changed, 3 insertions(+), 3 deletions(-)
SConstruct |6 +++---
diffs (30 lines):
diff -r 7d75f1a525db -r
changeset 97660425ff39 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=97660425ff39
description:
stats: cleanup text output stuff and fix mysql output
diffstat:
4 files changed, 105 insertions(+), 123 deletions(-)
src/base/statistics.hh | 37 +-
changeset 1dc178e53487 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1dc178e53487
description:
stats: fix duplicate statistics names.
This generally requires providing a more meaningful name() function for
a
class.
diffstat:
4 files changed, 29
changeset 5437d5f54973 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5437d5f54973
description:
tests: update tests because of changes in stat names and in the stats
package
diffstat:
26 files changed, 663 insertions(+), 619 deletions(-)
OK, well I just unintentionally found that scons doesn't reliably
terminate on ^C even outside of the regressions (like when compiling
or doing the autoconf stuff) so sticking with the current plan is at
least no worse than that.
Really? I don't recall ever really having that problem.
Nate
@@ -29,10 +29,18 @@
import os
from os.path import isdir, isfile, join as joinpath
-homedir = os.environ['HOME']
-confdir = os.environ.get('M5_CONFIG', joinpath(homedir, '.m5'))
+
+confdir = os.environ.get('M5_CONFIG')
+
+if not confdir:
+ # HOME is not set when running regressions,
changeset 74bc713c71ce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=74bc713c71ce
description:
build: fix compiler warnings in g++ 3.4
diffstat:
1 file changed, 11 insertions(+), 11 deletions(-)
src/arch/x86/faults.hh | 22 +++---
diffs (60 lines):
Seems like it would be worth setting up a slew of g++ revs on zizzer
and running regressions under all of them, maybe on a rotating
basis...
Yeah, I agree. Multiple revs of swig and maybe scons would be good
too. I think we should set up a separate compile everything
regression actually. It
Please don't do anything with the TLBs yet. I'm hoping to send out a
patch tonight.
No problem.
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changeset 4df1c7698e52 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4df1c7698e52
description:
stats: fix compiler error
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/base/statistics.hh |4 ++--
diffs (19 lines):
diff -r 77bf0b8db2c5 -r
changeset 9116be67b6d8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9116be67b6d8
description:
ply: put the absolute path to ply in the environment, not a relative one
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
SConstruct |2 +-
diffs (12 lines):
changeset 7e310503019e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7e310503019e
description:
includes: add ext to the includes path.
move dnet to the correct place so that we use this
diffstat:
30 files changed, 1738 insertions(+), 1738 deletions(-)
+class SimObjectCollection(SimObject):
+ type = 'SimObjectCollection'
SimObjectCollection Seems like a pretty long name. Is there something
ambiguous about calling it Collection or Container?
Nate
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I have run this through gdb in with m5.debug and see the same errors, the
problem is the stack trace showing the cause of the seg fault or assert
changes depending on the inputs to the simulator. So, I have not been able
to pin point this bug which appears to be a subtle memory corruption
Does this problem really have anything to do with tracing, or is it
just more apparent with it?
On Sat, Apr 4, 2009 at 1:49 PM, Gabe Black gbl...@eecs.umich.edu wrote:
Oooh. I see what's broken. This is a result of my changes to
allow delaying translation. What happens is that Stl_c
changeset 6df0633d883b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6df0633d883b
description:
style: fix style hook for some newer versions of mercurial.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
util/style.py |4 ++--
diffs (21 lines):
diff -r
changeset 47b4fcb10c11 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=47b4fcb10c11
description:
tlb: More fixing of unified TLB
diffstat:
20 files changed, 130 insertions(+), 129 deletions(-)
src/arch/alpha/AlphaTLB.py |8 +-
src/arch/alpha/tlb.cc
changeset 0555121b5c5f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0555121b5c5f
description:
tests: update tests for TLB unification
diffstat:
197 files changed, 1885 insertions(+), 1171 deletions(-)
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
can someone elaborate on what the 3 modes mean {Read, Write, Execute}?
They correspond to the access types that come from the CPU.
I ask because in the translateAtomic function it seems as if the only modes
that matter are Write and Execute. Why does Read not matter?
It does. Which
The file I'm referring to is arch/alpha/tlb.cc and specifically the
translateAtomic() function implemented there.
Basically, having the Read mode is irrelevant there since it's given a
default type of write when it calls translateData(). Then in the
translateData() function it goes ahead and
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