Re: [m5-dev] changeset in m5: X86: Configure the first PCI interrupt.
I know that I wasn't good about this with Alpha, but a comment in the code with a reference to documentation that explains the numbers you've stuck in there would generally be very nice. Nate On Sun, Feb 1, 2009 at 5:18 PM, Gabe Black gbl...@eecs.umich.edu wrote: changeset a2c317cefcf8 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=a2c317cefcf8 description: X86: Configure the first PCI interrupt. diffstat: 3 files changed, 39 insertions(+), 1 deletion(-) configs/common/FSConfig.py | 31 +++ src/dev/x86/SouthBridge.py |3 ++- src/dev/x86/pc.cc |6 ++ diffs (77 lines): diff -r 1349786dd9a7 -r a2c317cefcf8 configs/common/FSConfig.py --- a/configs/common/FSConfig.pySun Feb 01 00:25:15 2009 -0800 +++ b/configs/common/FSConfig.pySun Feb 01 00:26:10 2009 -0800 @@ -212,6 +212,19 @@ self.intel_mp_table.add_entry(io_apic) isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') self.intel_mp_table.add_entry(isa_bus) +pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') +self.intel_mp_table.add_entry(pci_bus) +connect_busses = X86IntelMPBusHierarchy(bus_id=0, +subtractive_decode=True, parent_bus=1) +self.intel_mp_table.add_entry(connect_busses) +pci_dev4_inta = X86IntelMPIOIntAssignment( +interrupt_type = 'INT', +polarity = 'ConformPolarity', +trigger = 'ConformTrigger', +source_bus_id = 1, +source_bus_irq = 0 + (4 2), +dest_io_apic_id = 1, +dest_io_apic_intin = 16) assign_8259_0_to_apic = X86IntelMPIOIntAssignment( interrupt_type = 'ExtInt', polarity = 'ConformPolarity', @@ -266,6 +279,24 @@ dest_io_apic_id = 1, dest_io_apic_intin = 12) self.intel_mp_table.add_entry(assign_12_to_apic) +assign_8259_14_to_apic = X86IntelMPIOIntAssignment( +interrupt_type = 'ExtInt', +polarity = 'ConformPolarity', +trigger = 'ConformTrigger', +source_bus_id = 0, +source_bus_irq = 14, +dest_io_apic_id = 1, +dest_io_apic_intin = 0) +self.intel_mp_table.add_entry(assign_8259_14_to_apic) +assign_14_to_apic = X86IntelMPIOIntAssignment( +interrupt_type = 'INT', +polarity = 'ConformPolarity', +trigger = 'ConformTrigger', +source_bus_id = 0, +source_bus_irq = 14, +dest_io_apic_id = 1, +dest_io_apic_intin = 14) +self.intel_mp_table.add_entry(assign_14_to_apic) def makeLinuxX86System(mem_mode, mdesc = None): diff -r 1349786dd9a7 -r a2c317cefcf8 src/dev/x86/SouthBridge.py --- a/src/dev/x86/SouthBridge.pySun Feb 01 00:25:15 2009 -0800 +++ b/src/dev/x86/SouthBridge.pySun Feb 01 00:26:10 2009 -0800 @@ -87,7 +87,8 @@ ide.BAR3LegacyIO = True ide.BAR4 = 1 ide.Command = 1 -ide.InterruptLine = 20 +ide.InterruptLine = 14 +ide.InterruptPin = 1 def attachIO(self, bus): # Route interupt signals diff -r 1349786dd9a7 -r a2c317cefcf8 src/dev/x86/pc.cc --- a/src/dev/x86/pc.cc Sun Feb 01 00:25:15 2009 -0800 +++ b/src/dev/x86/pc.cc Sun Feb 01 00:26:10 2009 -0800 @@ -101,6 +101,12 @@ entry.vector = 0x2C; ioApic.writeReg(0x28, entry.bottomDW); ioApic.writeReg(0x29, entry.topDW); +entry.vector = 0x2E; +ioApic.writeReg(0x2C, entry.bottomDW); +ioApic.writeReg(0x2D, entry.topDW); +entry.vector = 0x30; +ioApic.writeReg(0x30, entry.bottomDW); +ioApic.writeReg(0x31, entry.topDW); } Tick ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: X86: Find the natural lpj for this configuration.
You're manually setting loops per jiffy? On alpha at least, we have a hook for the function that calculates it and programatically return the number based on the clock frequency selected. I guess I should respond via e-mail for the record. See arch/alpha/linux/system.(cc|hh) ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: X86: Rework interrupt pins to allow one to many...
Sure. Does that work like warn once? It's in a position to be called a lot. There's hack() and hack_once(). Though, you bring up a good point as to whether it is worth ever printing a hack message more than once. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] In-Order patches available on m5sim.org
Hi Korey, I'm like to start looking at this now. Do you have any outstanding changes? Is there a time when I can have a lock on the repository to work with your patches on my own? I did make one commit to the patch repository. I removed the status file since that depends on each person's status. Make sure you qpop -a before you pull in case it causes a conflict with your own status file. Also, I want to set up an e-mail hook so people are notified when patches change. Merging is pretty impossible with a patch repository, so it's pretty important that people work with the most up to date stuff, and they don't work on the same patch at the same time. Can I just send notifications to m5-dev? (They shouldn't be all that frequent) Nate On Thu, Jan 22, 2009 at 8:59 AM, Korey Sewell ksew...@umich.edu wrote: I put the in-order mixie patches on m5sim.org so that if any wants, they can assist in the effort of cleaning things and officially integrating the CPU model. You should be able to clone the patch repo at: daystrom.m5sim.org//repo/inorder-patches Using the patches and the series file, people should be able to use the mercurial patchqueue methods to patch their M5 directory and test what the model does so far. There are a few things that prevent it from official M5 introduction which include: - passing standard SPEC M5 regressions - moving the parameterization of the model into Python - make sure all licenses are fixed (again) I believe now that there is a repository for these patches I can just update the most current patches there instead of constantly sending out patches whenever something *new* happens. If anybody has any questions, let me know... -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] configuring inittab for a serial console login
You'll notice the 12345 part in the line. That means load that when you're in one of those init levels. Thing is, I think that with the way we boot, you may still be in S (single user). So, what ali says is probably necessary (the console= line). Doing a higher value like 115200 means that it will print at that baud rate which means that characters will appear faster. Nate On Tue, Feb 3, 2009 at 7:31 AM, Ali Saidi sa...@umich.edu wrote: On Feb 3, 2009, at 4:34 AM, Gabe Black wrote: I fixed the segfaults I was getting and now init (or libc or the linker) ends up waiting forever for the UART. I'm not sure what's happening there, but I think the kernel is waiting for either an interrupt or a particular register value that never shows up. I'm betting it's an interrupt. It could be a serial interrupt, it could be an interrupt from another device. In any case, I want to make sure that once things are working I'll actually see a login prompt and not get stuck by some dumb configuration issue. I notice in the Alpha inittab there's a line which says: console::respawn:/sbin/getty -L 115200 /dev/tts/0 vt100 Is that materially different from the one in the Gentoo image which has the following? s0:12345:respawn:/sbin/agetty 9600 ttyS0 vt100 That line was commented out so I uncommented it. I'm guessing it's effectively the same thing, but I'm not very familiar with how this stuff works so I'm not sure. There are a lot of other lines as well which I'm trusting (hoping) aren't interfering with this one somehow. I'm pretty sure they're effectively the same thing. Passing a console= parameter on the command line (like we do for alpha) will make sure you get a login on that port. Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MWAHAHAHAHAHAHAHAHAHA
Woo! Super awesome! We generally don't run init and do our own thing, so it should be even easier to move forward. What's next? Nate On Wed, Feb 4, 2009 at 1:08 AM, Gabe Black gbl...@eecs.umich.edu wrote: A little over dramatic perhaps, and it's not quite right, but tada! Again! It even echoed when I typed! Freeing unused kernel memory: 232k freed INIT: version 2.86 booting /bin/bash: /sbin/rccùü¢+: No such file or directory /bin/baahh: /sbinnrr: No such file or directory INIT: Entering runlevel: 3 /bin/bash: /sbin/rccyðLý*: No such file or directory This is (none).unknown_domain (Linux x86_64 2.6.22.9) 00:00:05 (none) login: ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in inorder-patches: ignore some stuff
changeset 040d328ce5de in /z/repo/inorder-patches details: inorder-patches?cmd=changeset;node=040d328ce5de description: ignore some stuff diffstat: 1 file changed, 4 insertions(+) .hgignore |4 diffs (8 lines): diff -r cd969187e2d3 -r 040d328ce5de .hgignore --- /dev/null Thu Jan 01 00:00:00 1970 + +++ b/.hgignore Wed Feb 04 16:32:10 2009 -0800 @@ -0,0 +1,4 @@ +syntax: glob +guards +status +*~ ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in inorder-patches: Fix some copyrights
and the following disclaimer in the
++# documentation and/or other materials provided with the distribution;
++# neither the name of the copyright holders nor the names of its
++# contributors may be used to endorse or promote products derived from
++# this software without specific prior written permission.
+#
-+# Permission is granted to use, copy, create derivative works and
-+# redistribute this software and such derivative works for any
-+# purpose, so long as the copyright notice above, this grant of
-+# permission, and the disclaimer below appear in all copies made; and
-+# so long as the name of The University of Michigan is not used in any
-+# advertising or publicity pertaining to the use or distribution of
-+# this software without specific, written prior authorization.
++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++# AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
-+# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-+# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
-+# WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
-+# EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
-+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-+# PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
-+# LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
-+# INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
-+# ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
-+# IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
-+# DAMAGES.
-+#
-+# Authors: Nathan L. Binkert
++# Authors: Nathan Binkert
+
+import sys
+
@@ -312,47 +287,49 @@
+ Source('thread_context.cc')
+ Source('cpu.cc')
+
-diff -r db1653549204 src/cpu/mixie/SConsopts
/dev/null Thu Jan 01 00:00:00 1970 +
-+++ b/src/cpu/mixie/SConsopts Mon Nov 24 18:03:46 2008 -0500
+diff --git a/src/cpu/mixie/SConsopts b/src/cpu/mixie/SConsopts
+new file mode 100644
+--- /dev/null
b/src/cpu/mixie/SConsopts
@@ -0,0 +1,34 @@
+# -*- mode:python -*-
+
-+# Copyright (c) 2006
-+# The Regents of The University of Michigan
-+# All Rights Reserved
++# Copyright (c) 2006 The Regents of The University of Michigan
++# All rights reserved.
+#
-+# This code is part of the M5 simulator.
++# Redistribution and use in source and binary forms, with or without
++# modification, are permitted provided that the following conditions are
++# met: redistributions of source code must retain the above copyright
++# notice, this list of conditions and the following disclaimer;
++# redistributions in binary form must reproduce the above copyright
++# notice, this list of conditions and the following disclaimer in the
++# documentation and/or other materials provided with the distribution;
++# neither the name of the copyright holders nor the names of its
++# contributors may be used to endorse or promote products derived from
++# this software without specific prior written permission.
+#
-+# Permission is granted to use, copy, create derivative works and
-+# redistribute this software and such derivative works for any
-+# purpose, so long as the copyright notice above, this grant of
-+# permission, and the disclaimer below appear in all copies made; and
-+# so long as the name of The University of Michigan is not used in any
-+# advertising or publicity pertaining to the use or distribution of
-+# this software without specific, written prior authorization.
++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++# AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in inorder-patches: organize patches
changeset d33c963656cb in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=d33c963656cb
description:
organize patches
diffstat:
10 files changed, 3446 insertions(+), 10152 deletions(-)
fix_compile.diff| 94
fix_mdu_latency_bug | 533 ---
fix_mixie_per_stage_tracing | 205 -
import_mixie| 5782
make_mixie_cmdline_runnable | 37
mixie_hello_world | 6729 ---
prepare_cpus.diff | 65
prepare_exetrace.diff | 34
prepare_mips.diff | 110
series |9
diffs (truncated from 15803 to 300 lines):
diff -r d8514fbac071 -r d33c963656cb fix_compile.diff
--- a/fix_compile.diff Fri Feb 06 16:28:10 2009 -0800
+++ /dev/null Thu Jan 01 00:00:00 1970 +
@@ -1,94 +0,0 @@
-diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
a/src/cpu/mixie/cpu.cc
-+++ b/src/cpu/mixie/cpu.cc
-@@ -152,7 +152,7 @@
- miscRegFile(this),
- timeBuffer(2 , 2),
- removeInstsThisCycle(false),
-- activityRec(NumStages, 10, params-activity),
-+ activityRec(params-name, NumStages, 10, params-activity),
- switchCount(0),
- deferRegistration(false/*params-deferRegistration*/),
- stageTracing(params-stageTracing),
-@@ -250,10 +250,10 @@
- pipelineStage[stNum]-setTimeBuffer(timeBuffer);
-
- // Take Care of 1st/Nth stages
--if (stNum != 0)
-+if (stNum 0)
- pipelineStage[stNum]-setPrevStageQueue(stageQueue[stNum - 1]);
--if (stNum != NumStages - 1)
--pipelineStage[stNum]-setNextStageQueue(stageQueue[stNum]);
-+if (stNum NumStages - 2)
-+pipelineStage[stNum]-setNextStageQueue(stageQueue[stNum + 1]);
- }
-
- // Initialize thread specific variables
-diff --git a/src/cpu/mixie/first_stage.cc b/src/cpu/mixie/first_stage.cc
a/src/cpu/mixie/first_stage.cc
-+++ b/src/cpu/mixie/first_stage.cc
-@@ -144,7 +144,10 @@
-
- #if TRACING_ON
- inst-traceData =
--tracer-getInstRecord(ThePipeline::NumStages,
cpu-stageTracing);
-+tracer-getInstRecord(ThePipeline::NumStages,
-+ cpu-stageTracing,
-+ cpu-thread[tid]-getTC());
-+
- #endif // TRACING_ON
-
- DPRINTF(RefCount, creation: [tid:%i]: [sn:%i]: Refcount = %i.\n,
-diff --git a/src/cpu/mixie/mixie_trace.cc b/src/cpu/mixie/mixie_trace.cc
a/src/cpu/mixie/mixie_trace.cc
-+++ b/src/cpu/mixie/mixie_trace.cc
-@@ -74,7 +74,8 @@
-
- MixieTraceRecord *
- MixieTrace::getInstRecord(Tick when, ThreadContext *tc,
-- const StaticInstPtr staticInst, Addr pc)
-+const StaticInstPtr staticInst, Addr pc,
-+const StaticInstPtr macroStaticInst, MicroPC upc)
- {
- return new MixieTraceRecord(ThePipeline::NumStages, true, tc);
- }
-diff --git a/src/cpu/mixie/mixie_trace.hh b/src/cpu/mixie/mixie_trace.hh
a/src/cpu/mixie/mixie_trace.hh
-+++ b/src/cpu/mixie/mixie_trace.hh
-@@ -89,7 +89,8 @@
- getInstRecord(unsigned num_stages, bool stage_tracing, ThreadContext *tc);
-
- virtual MixieTraceRecord *getInstRecord(Tick when, ThreadContext *tc,
--const StaticInstPtr staticInst, Addr pc);
-+const StaticInstPtr staticInst, Addr pc,
-+const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0);
- };
-
- /* namespace Trace */ }
-diff --git a/src/cpu/mixie/resources/cache_unit.cc
b/src/cpu/mixie/resources/cache_unit.cc
a/src/cpu/mixie/resources/cache_unit.cc
-+++ b/src/cpu/mixie/resources/cache_unit.cc
-@@ -450,8 +450,11 @@
- findRequest(cache_pkt-cacheReq-getInst()));
- assert(cache_req);
-
-+#if TRACING_ON
- // Get resource request info
- unsigned tid = 0;
-+#endif
-+
- //tid = pkt-req-getThreadNum();
- unsigned stage_num = cache_req-getStageNum();
- DynInstPtr inst = cache_req-inst;
-diff --git a/src/cpu/mixie/thread_context.hh b/src/cpu/mixie/thread_context.hh
a/src/cpu/mixie/thread_context.hh
-+++ b/src/cpu/mixie/thread_context.hh
-@@ -69,6 +69,8 @@
-
- /** Returns a pointer to the DTB. */
- TheISA::DTB *getDTBPtr() { return cpu-dtb; }
-+
-+System *getSystemPtr() { return cpu-system; }
-
- /** Returns a pointer to this CPU. */
- virtual BaseCPU *getCpuPtr() { return cpu; }
diff -r d8514fbac071 -r d33c963656cb fix_mdu_latency_bug
--- a/fix_mdu_latency_bug Fri Feb 06 16:28:10 2009 -0800
+++ /dev/null Thu Jan 01 00:00:00 1970 +
@@ -1,533 +0,0 @@
-diff --git a/src/cpu/mixie/cpu.cc b/src/cpu/mixie/cpu.cc
a/src/cpu/mixie/cpu.cc
-+++ b/src/cpu/mixie/cpu.cc
-@@ -162,6 +162,7 @@
- cpu_params = params;
-
- resPool = new ResourcePool(this, params);
-+//resPool-init();
-
- coreType = default; // eventually get this from params
-
-diff --git a/src/cpu/mixie/pipeline_traits.cc
[m5-dev] changeset in inorder-patches: Make sure everything compiles just...
changeset 40721d032036 in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=40721d032036
description:
Make sure everything compiles just fine
diffstat:
2 files changed, 15 insertions(+), 11 deletions(-)
import_mixie |4 +---
prepare_cpus.diff | 22 ++
diffs (66 lines):
diff -r 71012a6974ed -r 40721d032036 import_mixie
--- a/import_mixie Fri Feb 06 17:32:54 2009 -0800
+++ b/import_mixie Fri Feb 06 17:53:25 2009 -0800
@@ -231,11 +231,10 @@
new file mode 100644
--- /dev/null
+++ b/src/cpu/mixie/SConsopts
-@@ -0,0 +1,35 @@
+@@ -0,0 +1,33 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2007 MIPS Technologies, Inc.
-+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
@@ -266,7 +265,6 @@
+Import('*')
+
+all_cpu_list.append('MixieCPU')
-+default_cpus.append('MixieCPU')
diff --git a/src/cpu/mixie/comm.hh b/src/cpu/mixie/comm.hh
new file mode 100644
--- /dev/null
diff -r 71012a6974ed -r 40721d032036 prepare_cpus.diff
--- a/prepare_cpus.diff Fri Feb 06 17:32:54 2009 -0800
+++ b/prepare_cpus.diff Fri Feb 06 17:53:25 2009 -0800
@@ -6,24 +6,30 @@
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
-@@ -54,6 +54,8 @@
- virtual Fault completeAcc(Packet *pkt, %s *xc,
+@@ -48,12 +48,14 @@
+
+ # Template for execute() signature.
+ exec_sig_template = '''
+-virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0;
+-virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const
++virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
++virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
+ { panic(initiateAcc not defined!); M5_DUMMY_RETURN };
+-virtual Fault completeAcc(Packet *pkt, %s *xc,
++virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
Trace::InstRecord *traceData) const
{ panic(completeAcc not defined!); M5_DUMMY_RETURN };
-+virtual int memAccSize(%s *xc)
++virtual int memAccSize(%(type)s *xc)
+{ panic(memAccSize not defined!); M5_DUMMY_RETURN };
'''
mem_ini_sig_template = '''
-@@ -82,7 +84,10 @@
+@@ -82,7 +84,7 @@
'''
for cpu in temp_cpu_list:
xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
-print f, exec_sig_template % (xc_type, xc_type, xc_type)
-+#print f, exec_sig_template % (xc_type, xc_type, xc_type)
-+
-+# Needed for Mixie CPU Model
-+print f, exec_sig_template % (xc_type, xc_type, xc_type, xc_type)
++print f, exec_sig_template % { 'type' : xc_type }
print f, '''
#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
'''
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in inorder-patches: Rename mixie to inorder
changeset d3fea0b4646c in /z/repo/inorder-patches
details: inorder-patches?cmd=changeset;node=d3fea0b4646c
description:
Rename mixie to inorder
diffstat:
3 files changed, 1185 insertions(+), 1185 deletions(-)
import_mixie| 2364 +--
make_mixie_cmdline_runnable |4
prepare_cpus.diff |2
diffs (truncated from 5891 to 300 lines):
diff -r 40721d032036 -r d3fea0b4646c import_mixie
--- a/import_mixie Fri Feb 06 17:53:25 2009 -0800
+++ b/import_mixie Fri Feb 06 17:58:45 2009 -0800
@@ -12,13 +12,13 @@
CpuModel('O3CPU', 'o3_cpu_exec.cc',
'#include cpu/o3/isa_specific.hh',
{ 'CPU_exec_context': 'O3DynInst' })
-+CpuModel('MixieCPU', 'mixie_cpu_exec.cc',
-+ '#include cpu/mixie/mixie_dyn_inst.hh',
-+ { 'CPU_exec_context': 'MixieDynInst' })
-diff --git a/src/cpu/mixie/MixieCPU.py b/src/cpu/mixie/MixieCPU.py
-new file mode 100644
/dev/null
-+++ b/src/cpu/mixie/MixieCPU.py
++CpuModel('InOrderCPU', 'inorder_cpu_exec.cc',
++ '#include cpu/inorder/inorder_dyn_inst.hh',
++ { 'CPU_exec_context': 'InOrderDynInst' })
+diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
+new file mode 100644
+--- /dev/null
b/src/cpu/inorder/InOrderCPU.py
@@ -0,0 +1,80 @@
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
@@ -53,8 +53,8 @@
+from m5 import build_env
+from BaseCPU import BaseCPU
+
-+class MixieCPU(BaseCPU):
-+type = 'MixieCPU'
++class InOrderCPU(BaseCPU):
++type = 'InOrderCPU'
+activity = Param.Unsigned(0, Initial count)
+numThreads = Param.Unsigned(1, number of HW thread contexts)
+
@@ -100,10 +100,10 @@
+div24RepeatRate = Param.Unsigned(1, Repeat Rate for 24-bit Divide
Operations)
+div32Latency = Param.Unsigned(1, Latency for 32-bit Divide Operations)
+div32RepeatRate = Param.Unsigned(1, Repeat Rate for 32-bit Divide
Operations)
-diff --git a/src/cpu/mixie/MixieTrace.py b/src/cpu/mixie/MixieTrace.py
-new file mode 100644
/dev/null
-+++ b/src/cpu/mixie/MixieTrace.py
+diff --git a/src/cpu/inorder/InOrderTrace.py b/src/cpu/inorder/InOrderTrace.py
+new file mode 100644
+--- /dev/null
b/src/cpu/inorder/InOrderTrace.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2007 MIPS Technologies, Inc.
+# All rights reserved.
@@ -137,13 +137,13 @@
+from m5.params import *
+from InstTracer import InstTracer
+
-+class MixieTrace(InstTracer):
-+type = 'MixieTrace'
-+cxx_class = 'Trace::MixieTrace'
-diff --git a/src/cpu/mixie/SConscript b/src/cpu/mixie/SConscript
-new file mode 100644
/dev/null
-+++ b/src/cpu/mixie/SConscript
++class InOrderTrace(InstTracer):
++type = 'InOrderTrace'
++cxx_class = 'Trace::InOrderTrace'
+diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript
+new file mode 100644
+--- /dev/null
b/src/cpu/inorder/SConscript
@@ -0,0 +1,82 @@
+# -*- mode:python -*-
+
@@ -177,30 +177,30 @@
+
+Import('*')
+
-+if 'MixieCPU' in env['CPU_MODELS']:
-+ SimObject('MixieCPU.py')
-+ SimObject('MixieTrace.py')
++if 'InOrderCPU' in env['CPU_MODELS']:
++ SimObject('InOrderCPU.py')
++ SimObject('InOrderTrace.py')
+
+ TraceFlag('ResReqCount')
+ TraceFlag('FreeList')
-+ TraceFlag('MixieCachePort')
-+ TraceFlag('MixieStage')
-+ TraceFlag('MixieStall')
-+ TraceFlag('MixieCPU')
-+ TraceFlag('MixieMDU')
++ TraceFlag('InOrderCachePort')
++ TraceFlag('InOrderStage')
++ TraceFlag('InOrderStall')
++ TraceFlag('InOrderCPU')
++ TraceFlag('InOrderMDU')
+ TraceFlag('RegDepMap')
+ TraceFlag('Rename')
-+ TraceFlag('MixieDynInst')
++ TraceFlag('InOrderDynInst')
+ TraceFlag('Resource')
+ TraceFlag('RefCount')
+
-+ CompoundFlag('MixieCPUAll', [ 'MixieStage', 'MixieStall', 'MixieCPU',
-+ 'MixieMDU', 'RegDepMap', 'Resource', 'Rename'])
++ CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall',
'InOrderCPU',
++ 'InOrderMDU', 'RegDepMap', 'Resource', 'Rename'])
+
+ Source('pipeline_traits.cc')
-+ Source('mixie_dyn_inst.cc')
-+ Source('mixie_cpu_builder.cc')
-+ Source('mixie_trace.cc')
++ Source('inorder_dyn_inst.cc')
++ Source('inorder_cpu_builder.cc')
++ Source('inorder_trace.cc')
+ Source('pipeline_stage.cc')
+ Source('first_stage.cc')
+ Source('resource.cc')
@@ -227,10 +227,10 @@
+ Source('thread_context.cc')
+ Source('cpu.cc')
+
-diff --git a/src/cpu/mixie/SConsopts b/src/cpu/mixie/SConsopts
-new file mode 100644
/dev/null
-+++ b/src/cpu/mixie/SConsopts
+diff --git a/src/cpu/inorder/SConsopts b/src/cpu/inorder/SConsopts
+new file mode 100644
+--- /dev/null
b/src/cpu/inorder/SConsopts
@@ -0,0 +1,33 @@
+# -*- mode:python -*-
+
@@ -264,11 +264,11 @@
+
+Import('*')
+
-+all_cpu_list.append('MixieCPU')
-diff --git a/src/cpu/mixie/comm.hh
[m5-dev] changeset in m5: Quell g++ 4.3 warning about operator ambiguity
changeset 8c1aa74572e4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8c1aa74572e4
description:
Quell g++ 4.3 warning about operator ambiguity
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/isa/microops/regop.isa |2 +-
diffs (12 lines):
diff -r 68c52fee5a53 -r 8c1aa74572e4 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Wed Feb 04 16:26:15 2009 -0800
+++ b/src/arch/x86/isa/microops/regop.isa Fri Feb 06 20:55:50 2009 -0800
@@ -1074,7 +1074,7 @@
// Fall through on purpose
case SegIntGateCheck:
// Make sure the gate's the right type.
-if (m5reg.mode == LongMode ((desc.type 0xe) != 0xe) ||
+if ((m5reg.mode == LongMode (desc.type 0xe) != 0xe) ||
((desc.type 0x6) != 0x6)) {
fault = new GeneralProtection(0);
}
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] IsReadBarrier instruction flag
We don't have it because we haven't implemented an ISA that supports it, so I see no reason not to add it. (It's pretty odd to put a fence in for reads and not want writes to be fenced too.) Nate On Fri, Feb 6, 2009 at 9:06 PM, Gabe Black gbl...@eecs.umich.edu wrote: I notice that we have static inst flags called IsMemBarrier and IsWriteBarrier, but no IsReadBarrier or equivalent. Should we? I need something like that to implement the lfence instruction. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] SCons version
I want to move the minimum SCons version forward. Currently, the minimum is 0.96.91 which has a bunch of warts which are annoying. Does anyone have a reason for me not to move to 0.98.0? Should I move it even further forward? There's always scons-local if people don't have local administration. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] SCons version
What are the specific warts and in what version are they fixed? Sigh. Alright, here goes. I'm trying to significantly improve the build framework and there is a lot that has improved in scons with respect to our minimum version. More specifically, I've figured out how to reduce both the null build time and the total build time when building all variants (ALPHA_FS, ALPHA_SE, etc.) by a significant factor. I'm hoping for 5x. This comes from two things. First, SConscripts are read and parsed only once, this helps null build time. Second, I don't build things multiple times if they don't need to be. For example, almost all files in base don't depend on variant and could therefore just be compiled once. Files in sim, mem (with an annoying exception that I can fix), and python also don't care. These changes should help both null build and full build. The former because the dependency graph will be much smaller, the latter because there's just a lot less to compile. - The major issue is that VariantDir is more sane in 0.98. I *might* be able to workaround the issues with great pain, but I'd really rather not have to waste my time doing so. - Things that we use have been deprecated in 0.98 and will fail in scons 2.0 (BuildDir, env.Copy, TargetSignatures) SCons 0.98 was released just under one year ago. Of course this is the bigger issue. There are several systems that will not have this installed by default, but scons-local makes life easy for these people. I can provide instructions for people to set this up if they fail the scons minimum version test when trying to build. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] SCons version
Thank you. To me that sounds worth it. Although a page describing scons-local perhaps linked to the EnusreScons() check would be a necessity. That's exactly what I'd do. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] X86 SE timing speed up
Are you talking about just x86? Nate On Mon, Feb 9, 2009 at 1:19 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: I have a patch in my queue which, for reasons I can get into if people are interested, prevents fetching in the simple CPU while in the middle of a macroop. A side effect of this is that benchmarks on the timing simple CPU have ~25% faster simulated execution time. Real time isn't any faster, I don't think, but this was such a big difference I thought you might want to know. The patch is like any of my others in that it won't get to the head until the tlb miss mechanism is hammered out, so don't worry about it in the short term. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: scons: Don't build the intermediate static libr...
changeset 50fb2cb40609 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=50fb2cb40609 description: scons: Don't build the intermediate static library unless explicitly requested. This means that similar to libm5_fast.so, you need to explicitly build build/ALPHA_SE/libm5_fast.a if you want it. diffstat: 1 file changed, 2 insertions(+), 2 deletions(-) src/SConscript |4 ++-- diffs (16 lines): diff -r 8c1aa74572e4 -r 50fb2cb40609 src/SConscript --- a/src/SConscriptFri Feb 06 20:55:50 2009 -0800 +++ b/src/SConscriptMon Feb 09 20:10:12 2009 -0800 @@ -992,10 +992,10 @@ for target, sources in unit_tests: objs = [ new_env.StaticObject(s) for s in sources ] -new_env.Program(unittest/%s.%s % (target, label), objs + static_lib) +new_env.Program(unittest/%s.%s % (target, label), objs + static_objs) # Now link a stub with main() and the static library. -objects = [new_env.Object(s) for s in cc_bin_sources] + static_lib +objects = [new_env.Object(s) for s in cc_bin_sources] + static_objs if strip: unstripped_exe = exename + '.unstripped' new_env.Program(unstripped_exe, objects) ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: scons: Require SCons version 0.98.1
changeset f73e06bc8765 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f73e06bc8765
description:
scons: Require SCons version 0.98.1
This allows me to clean things up so we are up to date with respect to
deprecated features. There are many features scheduled for permanent
failure
in scons 2.0 and 0.98.1 provides the most compatability for that. It
also paves the way for some nice new features that I will add soon
diffstat:
4 files changed, 250 insertions(+), 284 deletions(-)
SConstruct | 501 ++
ext/libelf/SConscript|2
src/SConscript | 29 --
src/arch/alpha/SConsopts |2
diffs (truncated from 905 to 300 lines):
diff -r 50fb2cb40609 -r f73e06bc8765 SConstruct
--- a/SConstructMon Feb 09 20:10:12 2009 -0800
+++ b/SConstructMon Feb 09 20:10:14 2009 -0800
@@ -27,6 +27,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
+# Nathan Binkert
###
#
@@ -63,25 +64,55 @@
#
###
-import sys
+# Check for recent-enough Python and SCons versions.
+try:
+# Really old versions of scons only take two options for the
+# function, so check once without the revision and once with the
+# revision, the first instance will fail for stuff other than
+# 0.98, and the second will fail for 0.98.0
+EnsureSConsVersion(0, 98)
+EnsureSConsVersion(0, 98, 1)
+except SystemExit, e:
+print
+For more details, see:
+http://m5sim.org/wiki/index.php/Compiling_M5
+
+raise
+
+# We ensure the python version early because we have stuff that
+# requires python 2.4
+try:
+EnsurePythonVersion(2, 4)
+except SystemExit, e:
+print
+You can use a non-default installation of the Python interpreter by
+either (1) rearranging your PATH so that scons finds the non-default
+'python' first or (2) explicitly invoking an alternative interpreter
+on the scons script.
+
+For more details, see:
+http://m5sim.org/wiki/index.php/Using_a_non-default_Python_installation
+
+raise
+
import os
import re
+import subprocess
+import sys
-from os.path import isdir, isfile, join as joinpath
+from os import mkdir, environ
+from os.path import abspath, basename, dirname, expanduser, normpath
+from os.path import exists, isdir, isfile
+from os.path import join as joinpath, split as splitpath
import SCons
-# Check for recent-enough Python and SCons versions. If your system's
-# default installation of Python is not recent enough, you can use a
-# non-default installation of the Python interpreter by either (1)
-# rearranging your PATH so that scons finds the non-default 'python'
-# first or (2) explicitly invoking an alternative interpreter on the
-# scons script, e.g., /usr/local/bin/python2.4 `which scons` [args].
-EnsurePythonVersion(2,4)
-
-# Import subprocess after we check the version since it doesn't exist in
-# Python 2.4.
-import subprocess
+def read_command(cmd):
+run the command cmd, read the results and return them
+this is sorta like `cmd` in shell
+from subprocess import Popen, PIPE, STDOUT
+subp = Popen(cmd, shell=True, stdout=PIPE, stderr=STDOUT, close_fds=True)
+return subp.communicate()[0]
# helper function: compare arrays or strings of version numbers.
# E.g., compare_version((1,3,25), (1,4,1)')
@@ -106,46 +137,6 @@
if len(v1) len(v2): return 1
return 0
-# SCons version numbers need special processing because they can have
-# charecters and an release date embedded in them. This function does
-# the magic to extract them in a similar way to the SCons internal function
-# function does and then checks that the current version is not contained in
-# a list of version tuples (bad_ver_strs)
-def CheckSCons(bad_ver_strs):
-def scons_ver(v):
-num_parts = v.split(' ')[0].split('.')
-major = int(num_parts[0])
-minor = int(re.match('\d+', num_parts[1]).group())
-rev = 0
-rdate = 0
-if len(num_parts) 2:
-try: rev = int(re.match('\d+', num_parts[2]).group())
-except: pass
-rev_parts = num_parts[2].split('d')
-if len(rev_parts) 1:
-rdate = int(re.match('\d+', rev_parts[1]).group())
-
-return (major, minor, rev, rdate)
-
-sc_ver = scons_ver(SCons.__version__)
-for bad_ver in bad_ver_strs:
-bv = (scons_ver(bad_ver[0]), scons_ver(bad_ver[1]))
-if compare_versions(sc_ver, bv[0]) != -1 and\
-compare_versions(sc_ver, bv[1]) != 1:
-print The version of SCons that you have installed: ,
SCons.__version__
-print has a bug that prevents it from working correctly with M5.
-print Please install a version NOT contained within the
following,
-print ranges
[m5-dev] changeset in m5: copyright: This file need not have had the more...
changeset 780dd1bead5c in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=780dd1bead5c description: copyright: This file need not have had the more restrictive copyright. diffstat: 1 file changed, 9 insertions(+), 36 deletions(-) src/arch/x86/SConsopts | 45 + diffs (56 lines): diff -r f73e06bc8765 -r 780dd1bead5c src/arch/x86/SConsopts --- a/src/arch/x86/SConsoptsMon Feb 09 20:10:14 2009 -0800 +++ b/src/arch/x86/SConsoptsMon Feb 09 20:10:15 2009 -0800 @@ -3,43 +3,16 @@ # Copyright (c) 2007 The Hewlett-Packard Development Company # All rights reserved. # -# Redistribution and use of this software in source and binary forms, -# with or without modification, are permitted provided that the -# following conditions are met: -# -# The software must be used only for Non-Commercial Use which means any -# use which is NOT directed to receiving any direct monetary -# compensation for, or commercial advantage from such use. Illustrative -# examples of non-commercial use are academic research, personal study, -# teaching, education and corporate research development. -# Illustrative examples of commercial use are distributing products for -# commercial advantage and providing services using the software for -# commercial advantage. -# -# If you wish to use this software or functionality therein that may be -# covered by patents for commercial use, please contact: -# Director of Intellectual Property Licensing -# Office of Strategy and Technology -# Hewlett-Packard Company -# 1501 Page Mill Road -# Palo Alto, California 94304 -# -# Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. Redistributions -# in binary form must reproduce the above copyright notice, this list of -# conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. Neither the name of -# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its # contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. No right of -# sublicense is granted herewith. Derivatives of the software and -# output created using the software may be prepared, but only for -# Non-Commercial Uses. Derivatives of the software may be shared with -# others provided: (i) the others agree to abide by the list of -# conditions herein which includes the Non-Commercial Use restrictions; -# and (ii) such Derivatives of the software include the above copyright -# notice to acknowledge the contribution from this software where -# applicable, this list of conditions and the disclaimer below. +# this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS # AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] SCons minimum version now 0.98.1
Hi Developers, I just wanted to let everyone know that I pushed a change that will move the minimum version of SCons forward to 0.98.1. This release is less than a year old, but it prepares us for upcoming fatal errors for removed features while also allowing me to work on some significant improvements to the build framework. Check out http://www.m5sim.org/wiki/index.php/Compiling_M5 for a little bit more info on SCons. If this causes major headaches for anyone, please let us know and we can see what we can do to help people through this. The biggest side effect is that it could cause some people to have to install their own local copy of scons. This is unfortunate, but should hopefully be relatively painless. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: InOrder: Import new inorder CPU model from MIPS.
changeset 09ab46bfa914 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=09ab46bfa914 description: InOrder: Import new inorder CPU model from MIPS. This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen! Awesome! I've looked at this code quite a bit, and it's a great start, but I do think we need to put some effort into it to make it work well along with the other CPU models. My biggest concern is how registers, thread ids, and thread contexts are handled. This is different from other models. I'd really love it if we could have a call among people that really understand the CPU models so we can discuss what needs to be done to get things working. Unfortunately, I can't write huge amounts of code in this area because HP lawyers won't let me, but I can review patches, help tweak things, and in general give advice. My first inclination is that the InOrder model and MIPS should do threads the way the other ISAs and O3 do them, in that each hardware thread has a separate register file (as opposed to the unified register file done for MIPS), but we should certainly discuss the pros and cons of this. In general, I think our thread support is probably lacking, so coming up with a coordinated vision is a good thing. Anyone interested? Gabe? Kevin? Korey? Steve? I know that Daniel is interested in using the model. Anyone else out there want to pitch in? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: CPU: Prepare CPU models for the new in-order CP...
Just one little nit to pick: this function definition here should be in static_inst.cc and not static_inst.hh. It certainly doesn't need to be inlined for performance reasons, and since it's virtual it won't get inlined anyway, so there's no point in cluttering the header file with it. That was totally my bad. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: InOrder: Import new inorder CPU model from MIPS.
I'll give the short version here: MIPS was implemented ot use the MT ISA extension which requires the ability to read/write registers from other threads. I designed the register file to be on size fits all. It can be instantiated multiple times as a per-thread register file (Simple-CPU) OR it could be used as one big physical register file to allow threads communicate with each other (InOrder model). This differs since O3 defines it's own physical register file instead of the pre-defined one in the src/arch folder. There is one patch that I need to send out that merges the two solutions together where I add a thread-ID to all the thread-context functions cpu/thread_context.* and then defaulted that value to 0. This in effect allowed the other ISAs (ALPHA/SPARC/etc.) to compile and run unaffected by the changes I made. I'm not sure the other ISAs will ever care about communicating between register files so I though that was an OK solution. Instead of this, couldn't you do the cross thread thing by looking up the appropriate thread context in the cpu object and then calling the register access function for that thread context? This would work more in line with the other CPU models. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: style
changeset 5645632d594c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5645632d594c
description:
style
diffstat:
2 files changed, 63 insertions(+), 47 deletions(-)
src/cpu/static_inst.cc | 43 --
src/cpu/static_inst.hh | 67
diffs (228 lines):
diff -r acbe11bbfe68 -r 5645632d594c src/cpu/static_inst.cc
--- a/src/cpu/static_inst.ccTue Feb 10 15:49:29 2009 -0800
+++ b/src/cpu/static_inst.ccTue Feb 10 22:19:27 2009 -0800
@@ -40,11 +40,17 @@
StaticInst::AddrDecodeCache StaticInst::addrDecodeCache;
StaticInst::cacheElement StaticInst::recentDecodes[2];
+using namespace std;
+
+StaticInst::~StaticInst()
+{
+if (cachedDisassembly)
+delete cachedDisassembly;
+}
+
void
StaticInst::dumpDecodeCacheStats()
{
-using namespace std;
-
cerr Decode hash table stats @ curTick : endl;
cerr \tnum entries = decodeCache.size() endl;
cerr \tnum buckets = decodeCache.bucket_count() endl;
@@ -81,6 +87,37 @@
StaticInst::fetchMicroop(MicroPC micropc)
{
panic(StaticInst::fetchMicroop() called on instruction
-that is not microcoded.);
+ that is not microcoded.);
}
+Addr
+StaticInst::branchTarget(Addr branchPC) const
+{
+panic(StaticInst::branchTarget() called on instruction
+ that is not a PC-relative branch.);
+M5_DUMMY_RETURN;
+}
+
+Addr
+StaticInst::branchTarget(ThreadContext *tc) const
+{
+panic(StaticInst::branchTarget() called on instruction
+ that is not an indirect branch.);
+M5_DUMMY_RETURN;
+}
+
+Request::Flags
+StaticInst::memAccFlags()
+{
+panic(StaticInst::memAccFlags called on non-memory instruction);
+return 0;
+}
+
+const string
+StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const
+{
+if (!cachedDisassembly)
+cachedDisassembly = new string(generateDisassembly(pc, symtab));
+
+return *cachedDisassembly;
+}
diff -r acbe11bbfe68 -r 5645632d594c src/cpu/static_inst.hh
--- a/src/cpu/static_inst.hhTue Feb 10 15:49:29 2009 -0800
+++ b/src/cpu/static_inst.hhTue Feb 10 22:19:27 2009 -0800
@@ -382,12 +382,7 @@
{ }
public:
-
-virtual ~StaticInst()
-{
-if (cachedDisassembly)
-delete cachedDisassembly;
-}
+virtual ~StaticInst();
/**
* The execute() signatures are auto-generated by scons based on the
@@ -406,12 +401,7 @@
* Invalid if not a PC-relative branch (i.e. isDirectCtrl()
* should be true).
*/
-virtual Addr branchTarget(Addr branchPC) const
-{
-panic(StaticInst::branchTarget() called on instruction
- that is not a PC-relative branch.);
-M5_DUMMY_RETURN
-}
+virtual Addr branchTarget(Addr branchPC) const;
/**
* Return the target address for an indirect branch (jump). The
@@ -420,12 +410,7 @@
* execute the branch in question. Invalid if not an indirect
* branch (i.e. isIndirectCtrl() should be true).
*/
-virtual Addr branchTarget(ThreadContext *tc) const
-{
-panic(StaticInst::branchTarget() called on instruction
- that is not an indirect branch.);
-M5_DUMMY_RETURN
-}
+virtual Addr branchTarget(ThreadContext *tc) const;
/**
* Return true if the instruction is a control transfer, and if so,
@@ -433,11 +418,7 @@
*/
bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr tgt) const;
-virtual Request::Flags memAccFlags()
-{
-panic(StaticInst::memAccFlags called on non-memory instruction);
-return 0;
-};
+virtual Request::Flags memAccFlags();
/**
* Return string representation of disassembled instruction.
@@ -447,14 +428,7 @@
* should not be cached, this function should be overridden directly.
*/
virtual const std::string disassemble(Addr pc,
- const SymbolTable *symtab = 0) const
-{
-if (!cachedDisassembly)
-cachedDisassembly =
-new std::string(generateDisassembly(pc, symtab));
-
-return *cachedDisassembly;
-}
+const SymbolTable *symtab = 0) const;
/// Decoded instruction cache type.
/// For now we're using a generic hash_map; this seems to work
@@ -486,13 +460,13 @@
/// A cache of decoded instruction objects from addresses.
static AddrDecodeCache addrDecodeCache;
-struct cacheElement {
+struct cacheElement
+{
Addr page_addr;
AddrDecodePage *decodePage;
-cacheElement()
- :decodePage(NULL) { }
-} ;
+cacheElement() : decodePage(NULL) { }
+};
/// An array of recently decoded instructions.
// might not use an array if there is only two elements
@@ -521,7 +495,7 @@
/// @retval A pointer to the corresponding StaticInst object.
//This is defined as inlined below.
static
[m5-dev] SCons issues
in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+import os
+import sys
+
+from os.path import expanduser, isdir, isfile, join as joinpath
+
+homedir = os.environ['HOME']
+confdir = os.environ.get('M5_CONFIG', joinpath(homedir, '.m5'))
+confdir = expanduser(confdir)
+if not isdir(confdir):
+raise ImportError, \
+ could not find M5 configuration directory at %s % confdir
+
+def find(filename):
+path = joinpath(confdir, filename)
+if not isfile(path):
+raise AttributeError, \
+ could not find %s in config directory: %s % (filename, confdir)
+return path
+
+__all__ = [ 'homedir', 'confdir', 'find' ]
diff -r 5645632d594c util/build/dotm5_build.py
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/util/build/dotm5_build.py Wed Feb 11 12:51:40 2009 -0800
@@ -0,0 +1,184 @@
+# Copyright (c) 2006-2009 The Hewlett-Packard Development Company
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+import os
+import sys
+
+from os.path import expanduser, isdir, isfile, join as joinpath
+
+help = \
+%prog assumes that the user has a ~/.m5/build.py (the directory
+~/.m5 is configurable with the M5_CONFIG environment variable) file
+describing the various versions of M5 that have been built.
+
+the config directory describes where in the filesystem source
+directories and potentially build directories live. Source
+directories must be specified, but build directories are optional.
+
+For example, one could keep sources in a shared filesystem (like nfs),
+say in ~/m5 and keep build output on local disks for each machine
+e.g. /home/username/build. This separation easily allows different
+os configurations to be used while at the same time significantly
+improving build time because output files don't go over the network.
+
+example .m5/build.py:
+
+# This file is actually -*- mode:python -*-
+
+default['binaries'] = [ 'opt' ]
+default['isas'] = [ 'alpha' ]
+default['emulations'] = [ 'fullsys' ]
+
+# arm build
+arm = M5Build('~/m5/work', '~/build/arm')
+arm.scons.append('EXTRAS=~/m5/arm_extras')
+
+# work build
+work
Re: [m5-dev] [PATCH] [mq]: switchtotimingsimplecpu.diff
I'm cleaning out my inbox and I was wondering if this ever got resolved. David?
It would be nice to see this whole interface cleaned up (across all
CPUs), so if anyone understands what's going on here, I'd appreciate
some info.
Nate
On Wed, Jan 7, 2009 at 8:09 AM, Clint Smullen cw...@cs.virginia.edu wrote:
This patch is unrelated to switching back from detailedd. I have still
not finished fixing everything (and, when I get a chance, I need to
post some questions about it).
I'm not sure why this patch is needed, since in takeOverFrom, at that
point, _status is set to Running. Then, later on, when resume is
called, since _status is Running, schedule is called. The only thing I
could think of that would mess up that process would be if the status
changed again before resume got called. If that was occurring, then
that should probably be fixed instead of calling the schedule early.
I could not locate any discussion context related to this patch, but I
did ask a related question some time back (see Switching back to
already used CPUs). I was able to work around the problem by using
fresh processors every time, but that is, of course, not a general
solution.
- Clint
On Jan 6, 2009, at 6:02 PM, nathan binkert wrote:
I feel like I'm missing some context with this patch (though I will
admit to not following the mailing list very closely after the last
few months. Was this the solution to us not being able to switch back
to timing from detailed? Can you write up a commit message?
At first glance, it seems correct. I'll just double check, and when I
get your commit message, I'll apply it.
Thanks for the patch!
Nate
On Mon, Jan 5, 2009 at 12:16 AM, David A. Ramos dtrum...@umich.edu
wrote:
# HG changeset patch
# User David Ramos dtrum...@umich.edu
# Date 1231142438 18000
# Node ID 122cc03013a106e722593bee490d4b8210c623a4
# Parent 50c9d48de3caa629a27408bf5f3423656ae15da1
[mq]: switchtotimingsimplecpu.diff
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -194,6 +194,7 @@
ThreadContext *tc = threadContexts[i];
if (tc-status() == ThreadContext::Active _status !=
Running) {
_status = Running;
+schedule(fetchEvent, nextCycle());
break;
}
}
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] I can't contribute to x86 M5 right now
I don't get a holiday Monday... bummer. I'm free pretty much all day though. I'm also free Tue afternoon and Wed afternoon exc. 2:30-3. Tue/Wed evenings are bad for me. Tuesday and Wednesday afternoons wouldn't be great for me since I'd probably have to leave work to attend, but a phone meeting any time on Monday sounds good. My kids nap around 1:00. Can we do it at 1:00 on Monday then? I can also do Monday evening after my kids go to sleep at 7PM. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
I'll look at it, but it does raise the concern that everything but the latest releases of OSes will need a custom package to get to Scons . 98.1 I thought that was clear from my e-mails. It is honestly very easy to get a compliant SCons. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] SCons issues
I really appreciate the help! As far as location, I agree src is the wrong place... how about under util, like util/scons or util/sconshelp? That also doesn't seem to fit for me, but if a top level directory is the wrong place, util is the best. I still think I like buildlib at the top better, Your use of build dir for the latter confused me a bit. I suggest we call the latter the build root and not the build dir.) Ok, I agree. I will start using that term. The -D option that I proposed would be the build root I think the key issue is that we have canonical names of ISA_FS|SE for default configs, but no naming scheme for anything else. Note that from the build_opts perspective, these names are totally arbitrary and are just the names of settings files in the build_opts directory. If you wanted to configure the X86_SE directory to build with the Alpha ISA in FS mode you could easily do that just by editing one file. Not that we need that flexibility, but it seems odd to me that with your m5build scheme you end up having to map --isa=alpha --emulation=syscall to this arbitrary string ALPHA_SE and then use build_opts to map that back to the corresponding compile-time settings. My m5build scheme works the way it does just because I was wrapping the existing stuff. It's also why I haven't really pushed it out there much. That said, my goal with a new framework would be to get rid of build_opts, and fix the names, so it wouldn't be this bizarre mapping. This brings up the related question, do we want to preserve the existing names ALPHA_SE, etc. or do we want to make them lower case, or something else? I ask because this would be the time to change things. (BTW, this is really minor, but using the singular instead of the plural for the m5build args seems much more natural to me. What specifically are you referring to? You mean that it should be --isa or --binary instead of --isas or --binaries? Though IIRC optparse will work with the minimum unique prefix of the arg--is that true?--in which case maybe it's moot.) I don't know if it can or not. I could certainly support either, but I have no problem switching to the singluar form. So my overall feedback is (1) the m5build script looks nice in concept and I'd be glad to see something like that integrated with our scons scripts but (2) I'd much prefer to have whatever it does be general enough to replace build_opts without losing functionality (I do on occasion use FAST_ALLOC_DEBUG) as opposed to just adding a layer of indirection on top of it. I completely agree. More on this below. One option would be to have all the compile-time options other than ISA and emulation mode be set at the build root level... then I could still have two versions of ALPHA_SE but I'd have to create a new build root for that. Perhaps that makes sense if most of the non-ISA options impact most of the ISA-independent code; you'd need someplace separate to store the rebuilt common files anyway. OK, so now I see why you might want to move to two classes of compile-time options: those that affect all of the common base code and those that only impact predetermined subsets of code that get built independently. Right. Getting rid of build-dir-specific compile-time options that are set via sticky scons options pretty much does eliminate the point of build_opts, I think... which would be the case if everything other than the ISA and emulation mode (which can be derived directly from the build dir name) is a global sticky option instead. Right, and since it is a global sticky option, you have to create another build root if you want to have two options available at once. This is fundamentally easy to do. Another option (probably instead of using global sticky scons opts) would be to leverage the config/*.hh files more... currently these are generated by scons to reflect the settings of the internal scons options, but never read back in (by scons). We could have our SConstruct read the config files directly if it needs to know what the settings for an existing build dir are. The whole rigmarole of saving sticky options in build/options/* is only useful for preserving non-default options settings in the face of blowing away entire build dirs, which does not seem critical to me (can't recall the last time I used that). Well, by saving sticky options, you will not regenerate the config/*.hh files if you only specify the sticky option the first time. So, let's say you create a build root for FAST_ALLOC_DEBUG, you'd only have to define it once if you use the sticky option. Otherwise, if in a subsequent build you forgot to include the FAST_ALLOC_DEBUG, SCons would generate a new config/*.hh file and would do a rebuild. So, I do think these have value. (Am I making sense, or do I misunderstand something?) As far as parsing the target path, the key thing is figuring out which default options to use, particularly if I
Re: [m5-dev] changeset in m5: InOrder: Import new inorder CPU model from MIPS.
My toy example of this is say I want to read a integer register from an instruction. I could either go: (1) inst-threadContext-readIntReg() or (2) inst-cpu-readIntReg() In the threadContext object, there is just some redundant call to cpu-readIntReg() anyway. So you end up calling (1) and (2) instead of just directly calling (2). I think that's a holdover from before we had thread support. I'd argue that #2 shouldn't exist. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: SCons: Fix read_command so it can properly deal...
changeset 98f6215dffce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=98f6215dffce
description:
SCons: Fix read_command so it can properly deal with command strings
diffstat:
1 file changed, 3 insertions(+)
SConstruct |3 +++
diffs (13 lines):
diff -r 8007803be77a -r 98f6215dffce SConstruct
--- a/SConstructWed Feb 11 16:58:51 2009 -0800
+++ b/SConstructSun Feb 15 20:38:49 2009 -0800
@@ -114,6 +114,9 @@
this is sorta like `cmd` in shell
from subprocess import Popen, PIPE, STDOUT
+if isinstance(cmd, str):
+cmd = cmd.split()
+
no_exception = 'exception' in kwargs
exception = kwargs.pop('exception', None)
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: traceflags: fix --trace-help
changeset 67a6ea624776 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=67a6ea624776 description: traceflags: fix --trace-help diffstat: 3 files changed, 19 insertions(+), 18 deletions(-) src/python/m5/main.py | 13 - src/python/m5/trace.py | 11 ++- src/python/m5/util/__init__.py | 13 + diffs (73 lines): diff -r 98f6215dffce -r 67a6ea624776 src/python/m5/main.py --- a/src/python/m5/main.py Sun Feb 15 20:38:49 2009 -0800 +++ b/src/python/m5/main.py Sun Feb 15 20:39:12 2009 -0800 @@ -38,19 +38,6 @@ __all__ = [ 'options', 'arguments', 'main' ] -def print_list(items, indent=4): -line = ' ' * indent -for i,item in enumerate(items): -if len(line) + len(item) 76: -print line -line = ' ' * indent - -if i len(items) - 1: -line += '%s, ' % item -else: -line += item -print line - usage=%prog [m5 options] script.py [script options] version=%prog 2.0 brief_copyright=''' diff -r 98f6215dffce -r 67a6ea624776 src/python/m5/trace.py --- a/src/python/m5/trace.pySun Feb 15 20:38:49 2009 -0800 +++ b/src/python/m5/trace.pySun Feb 15 20:39:12 2009 -0800 @@ -28,6 +28,7 @@ import internal import traceflags as flags +import util from internal.trace import clear, output, set, ignore @@ -36,13 +37,13 @@ def help(): print Base Flags: -for flag in trace.flags.basic: -print %s: %s % (flag, trace.flags.descriptions[flag]) +for flag in flags.basic: +print %s: %s % (flag, flags.descriptions[flag]) print print Compound Flags: -for flag in trace.flags.compound: +for flag in flags.compound: if flag == 'All': continue -print %s: %s % (flag, trace.flags.descriptions[flag]) -print_list(trace.flags.compoundMap[flag], indent=8) +print %s: %s % (flag, flags.descriptions[flag]) +util.print_list(flags.compoundMap[flag], indent=8) print diff -r 98f6215dffce -r 67a6ea624776 src/python/m5/util/__init__.py --- a/src/python/m5/util/__init__.pySun Feb 15 20:38:49 2009 -0800 +++ b/src/python/m5/util/__init__.pySun Feb 15 20:39:12 2009 -0800 @@ -30,3 +30,16 @@ from misc import * from multidict import multidict import jobfile + +def print_list(items, indent=4): +line = ' ' * indent +for i,item in enumerate(items): +if len(line) + len(item) 76: +print line +line = ' ' * indent + +if i len(items) - 1: +line += '%s, ' % item +else: +line += item +print line ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] vsyscall page and license issues
In x86 there are at least three different ways to call a system call, int $0x80, sysenter, and syscall. In 64 bit mode I think syscall is pretty much guaranteed to be there so glibc uses it directly, or at least that's been my experience. For 32 bit x86, though, sysenter, the preferred of the two remaining instructions, is not necessarily present or enabled. What Linux does to handle this situation is that there's a vsyscall page which the kernel defines and which is mapped into the user level process at an address the kernel provides through an auxiliary vector on the initial stack frame. When it wants to do a system call, it jumps to the right location on the vsyscall page and the right instruction is there. Otherwise, system calls happen through the relatively slow int $0x80 interface. This is generally fine and it's not hard to put that page in place and put something useful on it, but in order to exactly match native execution in M5 I need to put the exact same instructions on my vsyscall page as appears in Linux. I don't know how this all works as far as licensing goes. Do we have to use GPL if I copy the bytes that implement a portion of that page into M5 for compatibility? How many instructions are we talking about? If it's only a handful and there is only one way you can do things, I think it should be ok. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: InOrder: Import new inorder CPU model from MIPS.
If #2 didnt exist, then that would make more sense to me. That would make an instruction HAVE to use the threadContext interface to access any CPU facilities. That would also remove the CPU pointer from the instruction object as well. If that were the solution, I would be OK with it, because then the CPU would be appropriately encapsulated away from an instruction's commands... It turns out that I had forgotten about the relationship between ThreadContext, ExecContext, and registers. I had a chance to discuss this with Steve and Gabe today and Gabe has agreed to write something up to describe how to solve this problem cleanly across the CPU models. I think that part of the problem is that the register file shouldn't really be defined in the ISA, and the ExecContext needs a consistent way for accessing registers. We'll probably end up with new functions for accessing registers from other threads instead of modifying the existing ones. Hopefully one of the things that will fall out of this work is consistent, working thread support across the various CPU models. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] vsyscall page and license issues
It's only a few instructions to push three registers on the stack, use the appropriate instruction, pop those three, and return. All together it's 11 bytes. I don't think one can claim copyright on 11 bytes. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: InOrder: Import new inorder CPU model from MIPS.
I'm not sure I all the way understand why the register file shouldnt be defined in the ISA... I could see maybe there being one standard integer and floating point register file thats totally generic however, the system/miscellaneous registers are pretty ISA dependent so those register probably need to be defined in some custom manner. Anyway, I was just about to rearrange everything so that all accesses to registers use the ThreadContext instead of directly going through the CPU (for the InOrder model at least). I'll assume that I should hold off on that for now? I think at this point, we need more discussion and less action. If you think you know how to make the ThreadContext stuff work right, please write up a description of how it will work. I think I was mistaken in saying that we could do it that way. Please also make sure that whatever you propose is consistent across the CPU models. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Scons 0.98 build problems...
I think that the problem is that you've got stuff in your hgrc that is
causing problems. What happens when you do
hg id from the command line? I'm guessing that it will complain.
Nate
2009/2/17 Steve Reinhardt ste...@gmail.com:
Have you tried cloning a fresh repo and seeing if it works there?
2009/2/17 Korey Sewell ksew...@umich.edu
Hmmm...Dont know what's going on here.. I just reinstalled mercurial with
no luck...
Can someone post the contents of their build/ALPHA_SE/python/m5/defines.py
file so I can see the differences going on?
On Mon, Feb 16, 2009 at 4:19 PM, nathan binkert n...@binkert.org wrote:
Just looking at the output seems to indicate that you've done
something funny with your mercurial setup. Do you have mq in both
your .hgrc file and in /etc/mercurial?
Nate
2009/2/16 Korey Sewell ksew...@umich.edu:
Hey all,
I am currently unable to build any CPU Model successfully after the
scons
update...0
Other people seem to be doing just fine, so am I missing something?
My error message has something to do with generating a defines.py file:
makeDefinesPyFile([build/ALPHA_SE/python/m5/defines.py],
[{'ALPHA_TLASER':
False, 'FAST_ALLOC_STATS': False, 'FAST_ALLOC_DEBUG': False,
'USE_CHECKER':
False, 'SS_COMPATIBLE_FP': True, 'NO_FAST_ALLOC': False, 'USE_FENV':
True,
'TARGET_ISA': 'alpha', 'FULL_SYSTEM': False, 'USE_MYSQL': False},
extension
'hgext/mq' overrides commands: qheader qnew ^qpop qrestore qapplied
qguard
qclone ^strip qgoto qprev qunapplied ^qrefresh qtop ^qdiff qseries
qcommit|qci qfold qnext qdelete|qremove|qrm ^qimport qselect ^qpush
^qinit
qrename|qmv qsave\nextension 'patchbomb' overrides commands: email\nTag
inorder-thread-context-updates.diff overrides mq patch of the same
name\nTag
qtip overrides mq patch of the same name\nTag qbase overrides mq patch
of
the same name\nTag qparent overrides mq patch of the same
name\nec076c266464
5875 default qtip tip inorder-thread-context-updates.diff qbase])
objectifyPyFile([build/ALPHA_SE/python/m5/defines.py.s],
[build/ALPHA_SE/python/m5/defines.py])
scons: *** [build/ALPHA_SE/python/m5/defines.py.s] Exception
Traceback (most recent call last):
File /usr/lib/scons/SCons/Taskmaster.py, line 222, in execute
self.targets[0].build()
File /usr/lib/scons/SCons/Node/__init__.py, line 372, in build
apply(self.get_executor(), (self,), kw)
File /usr/lib/scons/SCons/Executor.py, line 145, in __call__
return self.do_execute(target, kw)
File /usr/lib/scons/SCons/Executor.py, line 131, in do_execute
status = apply(act, (self.targets, self.get_sources(), env), kw)
File /usr/lib/scons/SCons/Action.py, line 468, in __call__
stat = self.execute(target, source, env)
File /usr/lib/scons/SCons/Action.py, line 846, in execute
result = self.execfunction(target=target, source=rsources, env=env)
File /home/ksewell/m5-fresh/build/ALPHA_SE/SConscript, line 843, in
objectifyPyFile
compiled = compile(src, pysource.debugname, 'exec')
File /home/ksewell/m5-fresh/build/ALPHA_SE/python/m5/defines.py,
line 2
hgRev = 'extension 'hgext/mq' overrides commands: qheader qnew
^qpop
qrestore qapplied qguard qclone ^strip qgoto qprev qunapplied ^qrefresh
qtop
^qdiff qseries qcommit|qci qfold qnext qdelete|qremove|qrm ^qimport
qselect
^qpush ^qinit qrename|qmv qsave
--
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science Engineering
University of Michigan
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
--
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science Engineering
University of Michigan
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Scons 0.98 build problems...
If you read the error message it was the hgext.mq line, not the
others. You should leave the style hook enabled.
Nate
On Tue, Feb 17, 2009 at 7:10 PM, Korey Sewell ksew...@umich.edu wrote:
So I finally got M5 to build with scons 0.98 but I had to remove the
patch-queue lines:
[extensions]
hgext.mq =
patchbomb =
style = /home/ksewell/m5/util/style.py
So for some reason, adding patch-queue to the repo just kills the
build for me...
On Tue, Feb 17, 2009 at 3:18 PM, nathan binkert n...@binkert.org wrote:
I think that the problem is that you've got stuff in your hgrc that is
causing problems. What happens when you do
hg id from the command line? I'm guessing that it will complain.
Nate
2009/2/17 Steve Reinhardt ste...@gmail.com:
Have you tried cloning a fresh repo and seeing if it works there?
2009/2/17 Korey Sewell ksew...@umich.edu
Hmmm...Dont know what's going on here.. I just reinstalled mercurial with
no luck...
Can someone post the contents of their build/ALPHA_SE/python/m5/defines.py
file so I can see the differences going on?
On Mon, Feb 16, 2009 at 4:19 PM, nathan binkert n...@binkert.org wrote:
Just looking at the output seems to indicate that you've done
something funny with your mercurial setup. Do you have mq in both
your .hgrc file and in /etc/mercurial?
Nate
2009/2/16 Korey Sewell ksew...@umich.edu:
Hey all,
I am currently unable to build any CPU Model successfully after the
scons
update...0
Other people seem to be doing just fine, so am I missing something?
My error message has something to do with generating a defines.py file:
makeDefinesPyFile([build/ALPHA_SE/python/m5/defines.py],
[{'ALPHA_TLASER':
False, 'FAST_ALLOC_STATS': False, 'FAST_ALLOC_DEBUG': False,
'USE_CHECKER':
False, 'SS_COMPATIBLE_FP': True, 'NO_FAST_ALLOC': False, 'USE_FENV':
True,
'TARGET_ISA': 'alpha', 'FULL_SYSTEM': False, 'USE_MYSQL': False},
extension
'hgext/mq' overrides commands: qheader qnew ^qpop qrestore qapplied
qguard
qclone ^strip qgoto qprev qunapplied ^qrefresh qtop ^qdiff qseries
qcommit|qci qfold qnext qdelete|qremove|qrm ^qimport qselect ^qpush
^qinit
qrename|qmv qsave\nextension 'patchbomb' overrides commands: email\nTag
inorder-thread-context-updates.diff overrides mq patch of the same
name\nTag
qtip overrides mq patch of the same name\nTag qbase overrides mq patch
of
the same name\nTag qparent overrides mq patch of the same
name\nec076c266464
5875 default qtip tip inorder-thread-context-updates.diff qbase])
objectifyPyFile([build/ALPHA_SE/python/m5/defines.py.s],
[build/ALPHA_SE/python/m5/defines.py])
scons: *** [build/ALPHA_SE/python/m5/defines.py.s] Exception
Traceback (most recent call last):
File /usr/lib/scons/SCons/Taskmaster.py, line 222, in execute
self.targets[0].build()
File /usr/lib/scons/SCons/Node/__init__.py, line 372, in build
apply(self.get_executor(), (self,), kw)
File /usr/lib/scons/SCons/Executor.py, line 145, in __call__
return self.do_execute(target, kw)
File /usr/lib/scons/SCons/Executor.py, line 131, in do_execute
status = apply(act, (self.targets, self.get_sources(), env), kw)
File /usr/lib/scons/SCons/Action.py, line 468, in __call__
stat = self.execute(target, source, env)
File /usr/lib/scons/SCons/Action.py, line 846, in execute
result = self.execfunction(target=target, source=rsources, env=env)
File /home/ksewell/m5-fresh/build/ALPHA_SE/SConscript, line 843, in
objectifyPyFile
compiled = compile(src, pysource.debugname, 'exec')
File /home/ksewell/m5-fresh/build/ALPHA_SE/python/m5/defines.py,
line 2
hgRev = 'extension 'hgext/mq' overrides commands: qheader qnew
^qpop
qrestore qapplied qguard qclone ^strip qgoto qprev qunapplied ^qrefresh
qtop
^qdiff qseries qcommit|qci qfold qnext qdelete|qremove|qrm ^qimport
qselect
^qpush ^qinit qrename|qmv qsave
--
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science Engineering
University of Michigan
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
--
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science Engineering
University of Michigan
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
--
--
Korey L Sewell
Graduate Student - PhD Candidate
Computer Science Engineering
University of Michigan
[m5-dev] changeset in m5: events: Make trace events happen at the right p...
changeset e9f9c0f7e5f0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=e9f9c0f7e5f0 description: events: Make trace events happen at the right priority. Also, while we're at it, remember that priorities are in the Event class and add a disable method to disable tracing. diffstat: 3 files changed, 9 insertions(+), 3 deletions(-) src/python/m5/event.py |7 +-- src/python/m5/main.py |2 +- src/python/m5/trace.py |3 +++ diffs (47 lines): diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/event.py --- a/src/python/m5/event.pyTue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/event.pyWed Feb 18 10:00:15 2009 -0800 @@ -35,13 +35,16 @@ def create(obj, priority=None): if priority is None: -priority = internal.event.Event.Default_Pri +priority = Event.Default_Pri return PythonEvent(obj, priority) + +# As a reminder, priorities found in sim/eventq.hh are stuck into the +# Event class by swig class Event(PythonEvent): def __init__(self, priority=None): if priority is None: -priority = internal.event.Event.Default_Pri +priority = Event.Default_Pri super(Event, self).__init__(self, priority) class ProgressEvent(Event): diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/main.py --- a/src/python/m5/main.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/main.py Wed Feb 18 10:00:15 2009 -0800 @@ -312,7 +312,7 @@ if options.trace_start: check_tracing() -e = event.create(trace.enable) +e = event.create(trace.enable, Event.Trace_Enable_Pri) event.mainq.schedule(e, options.trace_start) else: trace.enable() diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/trace.py --- a/src/python/m5/trace.pyTue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/trace.pyWed Feb 18 10:00:15 2009 -0800 @@ -32,6 +32,9 @@ from internal.trace import clear, output, set, ignore +def disable(): +internal.trace.cvar.enabled = False + def enable(): internal.trace.cvar.enabled = True ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Python Swig
Hi Steve/everyone, right now, we have code in src/python/swig. I'm thinking that for the swig stuff, we should distribute the .i files along with the code they wrap. Mostly this means that swig code goes in sim. I'm thinking about this because I was going to add a .i file or two and wanted to do the right thing. Along these lines, should I rename .i files to .ii to indicate C++? Additionally, there's a question about src/python/m5. I'm inclined to leave it alone because it is actually a python package that we build. Arguably, we might want to rename python to lib, but I could be convinced that this is a bad idea. I guess it just feels odd to have a directory called python. Finally, right now, SimObjects are compiled into a flat namespace called m5.objects. It seems that we should have some package hierarchy here to potentially mirror the C++ file hierarchy (and to get rid of the practice of prepending the ISA to the name of many objects). It would also help prevent name clashes with any EXTRAS people might create. These things come up because I'm actively working on the build system which would touch many of these things. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Python Swig
What a coincidence... I've never really looked at this code before about 4 hours ago. Brad and I were wondering where Stats::dump() gets called, and I poked around and found src/python/swig/stats.i, and the first thing I thought was shouldn't this really go in src/base/stats? I was going to send an email to you about it later this evening. heh. I guess it's not so striking since I'm working on cleaning up stats as we speak. I hope you haven't done too much hacking. I have a tested diff that I could push soon if you want, but this diff mostly finishes off a lot of cleanup that I was in the middle of that should also make things a little bit clearer, though there is still work to be done. Along these lines, should I rename .i files to .ii to indicate C++? Does it really matter? Is that a swig convention? If not, I'd say don't bother. It's not like there's any plain C code that we wrap. No, it oesn't matter, but if I'm doing a rename anyway, now would be the time to change this. Then again, I thought that scons would know .ii, but it doesn't so I guess it's not worth it. I think it's fine the way it is... it is a little asymmetric since we don't have a c++ directory, but I can deal with that. lib is a little too generic I think. ok. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] [PATCH] imported patch inorder-alpha-port
1) not sure why the mt.hh file didnt get added to the patch, but it should be there I think the real problem is that you're adding an mt.hh, but only for mips. That doesn't work so well with the switching directory code. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: clean up the statistics unittest
changeset 1db89432381b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1db89432381b
description:
stats: clean up the statistics unittest
diffstat:
1 file changed, 55 insertions(+), 50 deletions(-)
src/unittest/stattest.cc | 105 --
diffs (205 lines):
diff -r cba4b5495d7b -r 1db89432381b src/unittest/stattest.cc
--- a/src/unittest/stattest.cc Mon Feb 23 12:04:50 2009 -0800
+++ b/src/unittest/stattest.cc Mon Feb 23 12:04:52 2009 -0800
@@ -42,31 +42,6 @@
using namespace std;
using namespace Stats;
-Scalar s1;
-Scalar s2;
-Average s3;
-Scalar s4;
-Vector s5;
-Distribution s6;
-Vector s7;
-AverageVector s8;
-StandardDeviation s9;
-AverageDeviation s10;
-Scalar s11;
-Distribution s12;
-VectorDistribution s13;
-VectorStandardDeviation s14;
-VectorAverageDeviation s15;
-Vector2d s16;
-
-Formula f1;
-Formula f2;
-Formula f3;
-Value f4;
-Value f5;
-Formula f6;
-Formula f7;
-
double
testfunc()
{
@@ -141,15 +116,34 @@
if (!text (compat || descriptions))
usage();
-s5.init(5);
-s6.init(1, 100, 13);
-s7.init(7);
-s8.init(10);
-s12.init(1, 100, 13);
-s13.init(4, 0, 99, 10);
-s14.init(9);
-s15.init(10);
-s16.init(2, 9);
+Scalar s1;
+Scalar s2;
+Average s3;
+Scalar s4;
+Vector s5;
+Distribution s6;
+Vector s7;
+AverageVector s8;
+StandardDeviation s9;
+AverageDeviation s10;
+Scalar s11;
+Distribution s12;
+VectorDistribution s13;
+VectorStandardDeviation s14;
+VectorAverageDeviation s15;
+Vector2d s16;
+Value s17;
+Value s18;
+
+Formula f1;
+Formula f2;
+Formula f3;
+Formula f4;
+Formula f5;
+
+cprintf(sizeof(Scalar) = %d\n, sizeof(Scalar));
+cprintf(sizeof(Vector) = %d\n, sizeof(Vector));
+cprintf(sizeof(Distribution) = %d\n, sizeof(Distribution));
s1
.name(Stat01)
@@ -165,7 +159,7 @@
s3
.name(Stat03)
.desc(this is statistic 3)
-.prereq(f7)
+.prereq(f5)
;
s4
@@ -175,6 +169,7 @@
;
s5
+.init(5)
.name(Stat05)
.desc(this is statistic 5)
.prereq(s11)
@@ -186,12 +181,14 @@
;
s6
+.init(1, 100, 13)
.name(Stat06)
.desc(this is statistic 6)
.prereq(s11)
;
s7
+.init(7)
.name(Stat07)
.desc(this is statistic 7)
.precision(1)
@@ -200,6 +197,7 @@
;
s8
+.init(10)
.name(Stat08)
.desc(this is statistic 8)
.precision(2)
@@ -221,26 +219,31 @@
;
s12
+.init(1, 100, 13)
.name(Stat12)
.desc(this is statistic 12)
;
s13
+.init(4, 0, 99, 10)
.name(Stat13)
.desc(this is statistic 13)
;
s14
+.init(9)
.name(Stat14)
.desc(this is statistic 14)
;
s15
+.init(10)
.name(Stat15)
.desc(this is statistic 15)
;
s16
+.init(2, 9)
.name(Stat16)
.desc(this is statistic 16)
.flags(total)
@@ -250,6 +253,20 @@
.ysubname(1, y1)
;
+s17
+.functor(testfunc)
+.name(Stat17)
+.desc(this is stat 17)
+;
+
+TestClass testclass;
+s18
+.functor(testclass)
+.name(Stat18)
+.desc(this is stat 18)
+;
+
+
f1
.name(Formula1)
.desc(this is formula 1)
@@ -275,29 +292,17 @@
;
f4
-.functor(testfunc)
.name(Formula4)
.desc(this is formula 4)
;
-TestClass testclass;
-f5
-.functor(testclass)
-.name(Formula5)
-.desc(this is formula 5)
-;
-
-f6
-.name(Formula6)
-.desc(this is formula 6)
-;
f1 = s1 + s2;
f2 = (-s1) / (-s2) * (-s3 + ULL(100) + s4);
f3 = sum(s5) * s7;
-f6 += constant(10.0);
-f6 += s5[3];
-f7 = constant(1);
+f4 += constant(10.0);
+f4 += s5[3];
+f5 = constant(1);
check();
reset();
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: move the limits stuff into the types.hh ...
changeset 9775f70fbe66 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9775f70fbe66
description:
stats: move the limits stuff into the types.hh file
diffstat:
2 files changed, 3 insertions(+), 3 deletions(-)
src/base/statistics.hh |3 ---
src/base/stats/types.hh |3 +++
diffs (41 lines):
diff -r 6b312cafaa59 -r 9775f70fbe66 src/base/statistics.hh
--- a/src/base/statistics.hhMon Feb 23 12:22:17 2009 -0800
+++ b/src/base/statistics.hhMon Feb 23 12:22:18 2009 -0800
@@ -55,7 +55,6 @@
#include cmath
#include functional
#include iosfwd
-#include limits
#include list
#include string
#include vector
@@ -78,9 +77,7 @@
/* A namespace for all of the Statistics */
namespace Stats {
-typedef std::numeric_limitsCounter CounterLimits;
-/* Contains the statistic implementation details */
//
//
// Statistics Framework Base classes
diff -r 6b312cafaa59 -r 9775f70fbe66 src/base/stats/types.hh
--- a/src/base/stats/types.hh Mon Feb 23 12:22:17 2009 -0800
+++ b/src/base/stats/types.hh Mon Feb 23 12:22:18 2009 -0800
@@ -31,6 +31,7 @@
#ifndef __BASE_STATS_TYPES_HH__
#define __BASE_STATS_TYPES_HH__
+#include limits
#include vector
#include sim/host.hh
@@ -42,6 +43,8 @@
/** vector of counters. */
typedef std::vectorCounter VCounter;
+typedef std::numeric_limitsCounter CounterLimits;
+
/** All results are doubles. */
typedef double Result;
/** vector of results. */
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: reorganize how parameters are stored and...
changeset 02e5bc7ca9ba in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=02e5bc7ca9ba
description:
stats: reorganize how parameters are stored and accessed.
diffstat:
4 files changed, 209 insertions(+), 197 deletions(-)
src/base/statistics.cc | 24 ++-
src/base/statistics.hh | 337 ++-
src/base/stats/mysql.cc | 18 +-
src/base/stats/text.cc | 27 ++-
diffs (truncated from 1139 to 300 lines):
diff -r 9775f70fbe66 -r 02e5bc7ca9ba src/base/statistics.cc
--- a/src/base/statistics.ccMon Feb 23 12:22:18 2009 -0800
+++ b/src/base/statistics.ccMon Feb 23 12:22:19 2009 -0800
@@ -36,6 +36,7 @@
#include base/callback.hh
#include base/cprintf.hh
+#include base/debug.hh
#include base/hostinfo.hh
#include base/misc.hh
#include base/statistics.hh
@@ -81,6 +82,12 @@
}
void
+InfoAccess::setParams(const StorageParams *params)
+{
+info()-storageParams = params;
+}
+
+void
InfoAccess::setInit()
{
info()-flags |= init;
@@ -102,11 +109,20 @@
return (*i).second;
}
+StorageParams::~StorageParams()
+{
+}
+
+int Info::id_count = 0;
+
+int debug_break_id = -1;
+
Info::Info()
-: flags(none), precision(-1), prereq(0)
+: flags(none), precision(-1), prereq(0), storageParams(NULL)
{
-static int count = 0;
-id = count++;
+id = id_count++;
+if (debug_break_id = 0 and debug_break_id == id)
+debug_break();
}
Info::~Info()
@@ -249,7 +265,7 @@
Info *info = *i;
assert(info);
if (!info-check() || !info-baseCheck())
-panic(stat check failed for %s\n, info-name);
+panic(stat check failed for '%s' %d\n, info-name, info-id);
}
off_t j = 0;
diff -r 9775f70fbe66 -r 02e5bc7ca9ba src/base/statistics.hh
--- a/src/base/statistics.hhMon Feb 23 12:22:18 2009 -0800
+++ b/src/base/statistics.hhMon Feb 23 12:22:19 2009 -0800
@@ -77,6 +77,10 @@
/* A namespace for all of the Statistics */
namespace Stats {
+struct StorageParams
+{
+virtual ~StorageParams();
+};
//
//
@@ -100,9 +104,13 @@
* A unique stat ID for each stat in the simulator.
* Can be used externally for lookups as well as for debugging.
*/
+static int id_count;
int id;
public:
+const StorageParams *storageParams;
+
+ public:
Info();
virtual ~Info();
@@ -247,10 +255,6 @@
Counter squares;
Counter samples;
-Counter min;
-Counter max;
-Counter bucket_size;
-size_type size;
bool fancy;
};
@@ -383,9 +387,13 @@
/** Set up an info class for this statistic */
void setInfo(Info *info);
/** Save Storage class parameters if any */
+void setParams(const StorageParams *params);
+/** Save Storage class parameters if any */
void setInit();
+/** Grab the information class for this statistic */
Info *info();
+/** Grab the information class for this statistic */
const Info *info() const;
};
@@ -591,55 +599,51 @@
*/
class StatStor
{
- public:
-/** The paramaters for this storage type, none for a scalar. */
-struct Params { };
-
private:
/** The statistic value. */
Counter data;
public:
+struct Params : public StorageParams {};
+
+ public:
/**
* Builds this storage element and calls the base constructor of the
* datatype.
*/
-StatStor(const Params ) : data(Counter()) {}
+StatStor(Info *info)
+: data(Counter())
+{ }
/**
* The the stat to the given value.
* @param val The new value.
- * @param p The paramters of this storage type.
*/
-void set(Counter val, const Params p) { data = val; }
+void set(Counter val) { data = val; }
/**
* Increment the stat by the given value.
* @param val The new value.
- * @param p The paramters of this storage type.
*/
-void inc(Counter val, const Params p) { data += val; }
+void inc(Counter val) { data += val; }
/**
* Decrement the stat by the given value.
* @param val The new value.
- * @param p The paramters of this storage type.
*/
-void dec(Counter val, const Params p) { data -= val; }
+void dec(Counter val) { data -= val; }
/**
* Return the value of this stat as its base type.
- * @param p The params of this storage type.
* @return The value of this stat.
*/
-Counter value(const Params p) const { return data; }
+Counter value() const { return data; }
/**
* Return the value of this stat as a result type.
- * @param p The parameters of this storage type.
* @return The value of this stat.
*/
-Result result(const Params p) const { return (Result)data; }
+Result result() const { return (Result)data; }
/**
* Reset stat value to default
*/
-void reset() { data = Counter(); }
+void
[m5-dev] changeset in m5: stats: Try to make the names of things more int...
changeset 12431dc9a30a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=12431dc9a30a
description:
stats: Try to make the names of things more intuitive.
Basically, this means renaming several things called data to info, which
is information about the statistics. Things that are named data now are
actual data stored for the statistic.
diffstat:
9 files changed, 424 insertions(+), 410 deletions(-)
src/base/statistics.cc | 78 ++---
src/base/statistics.hh | 263 --
src/base/stats/mysql.cc | 211 ++--
src/base/stats/mysql.hh | 42 +++
src/base/stats/statdb.cc |6 -
src/base/stats/statdb.hh | 10 -
src/base/stats/text.cc | 182 ---
src/base/stats/text.hh | 14 +-
src/base/stats/visit.hh | 28 ++--
diffs (truncated from 1988 to 300 lines):
diff -r 1db89432381b -r 12431dc9a30a src/base/statistics.cc
--- a/src/base/statistics.ccMon Feb 23 12:04:52 2009 -0800
+++ b/src/base/statistics.ccMon Feb 23 12:22:15 2009 -0800
@@ -48,65 +48,59 @@
namespace Stats {
-StatData *
-DataAccess::find() const
+Info *
+InfoAccess::find() const
{
return Database::find(const_castvoid *((const void *)this));
}
-const StatData *
-getStatData(const void *stat)
+const Info *
+getInfo(const void *stat)
{
return Database::find(const_castvoid *(stat));
}
void
-DataAccess::map(StatData *data)
+InfoAccess::setInfo(Info *info)
{
-Database::regStat(this, data);
-}
-
-StatData *
-DataAccess::statData()
-{
-StatData *ptr = find();
-assert(ptr);
-return ptr;
-}
-
-const StatData *
-DataAccess::statData() const
-{
-const StatData *ptr = find();
-assert(ptr);
-return ptr;
+Database::regStat(this, info);
}
void
-DataAccess::setInit()
+InfoAccess::setInit()
{
-statData()-flags |= init;
+info()-flags |= init;
}
-void
-DataAccess::setPrint()
+Info *
+InfoAccess::info()
{
-Database::regPrint(this);
+Info *info = find();
+assert(info);
+return info;
}
-StatData::StatData()
+const Info *
+InfoAccess::info() const
+{
+const Info *info = find();
+assert(info);
+return info;
+}
+
+Info::Info()
: flags(none), precision(-1), prereq(0)
{
static int count = 0;
id = count++;
}
-StatData::~StatData()
+Info::~Info()
{
}
bool
-StatData::less(StatData *stat1, StatData *stat2)
+Info::less(Info *stat1, Info *stat2)
{
const string name1 = stat1-name;
const string name2 = stat2-name;
@@ -132,7 +126,7 @@
}
bool
-StatData::baseCheck() const
+Info::baseCheck() const
{
if (!(flags init)) {
#ifdef DEBUG
@@ -190,7 +184,7 @@
}
void
-FormulaBase::update(StatData *)
+FormulaBase::update(Info *)
{
}
@@ -238,20 +232,20 @@
iter_t i, end = Database::stats().end();
for (i = Database::stats().begin(); i != end; ++i) {
-StatData *data = *i;
-assert(data);
-if (!data-check() || !data-baseCheck())
-panic(stat check failed for %s\n, data-name);
+Info *info = *i;
+assert(info);
+if (!info-check() || !info-baseCheck())
+panic(stat check failed for %s\n, info-name);
}
off_t j = 0;
for (i = Database::stats().begin(); i != end; ++i) {
-StatData *data = *i;
-if (!(data-flags print))
-data-name = __Stat + to_string(j++);
+Info *info = *i;
+if (!(info-flags print))
+info-name = __Stat + to_string(j++);
}
-Database::stats().sort(StatData::less);
+Database::stats().sort(Info::less);
if (i == end)
return;
@@ -275,8 +269,8 @@
Database::stat_list_t::iterator i = Database::stats().begin();
Database::stat_list_t::iterator end = Database::stats().end();
while (i != end) {
-StatData *data = *i;
-data-reset();
+Info *info = *i;
+info-reset();
++i;
}
diff -r 1db89432381b -r 12431dc9a30a src/base/statistics.hh
--- a/src/base/statistics.hhMon Feb 23 12:04:52 2009 -0800
+++ b/src/base/statistics.hhMon Feb 23 12:22:15 2009 -0800
@@ -26,7 +26,6 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
- * Erik Hallnor
*/
/** @file
@@ -60,6 +59,7 @@
#include string
#include vector
+#include base/cast.hh
#include base/cprintf.hh
#include base/intmath.hh
#include base/refcnt.hh
@@ -85,8 +85,9 @@
// Statistics Framework Base classes
//
//
-struct StatData
+class Info
{
+ public:
/** The name of the stat. */
std::string name;
/** The description of the stat. */
@@ -96,15 +97,16 @@
/** The display precision. */
int precision;
/** A pointer to a prerequisite Stat. */
-const StatData *prereq;
+const Info *prereq
[m5-dev] changeset in m5: stats: cleanup static stats to make startup work.
changeset c810b7d4383d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c810b7d4383d
description:
stats: cleanup static stats to make startup work.
This is mainly to allow the unit test to run without requiring the
standard
M5 stats from being initialized (e.g. sim_seconds, sim_ticks,
host_seconds)
diffstat:
2 files changed, 21 insertions(+), 11 deletions(-)
src/sim/stat_control.cc | 31 +--
src/sim/stats.hh|1 -
diffs (65 lines):
diff -r 5a047c3f3795 -r c810b7d4383d src/sim/stat_control.cc
--- a/src/sim/stat_control.cc Mon Feb 23 11:48:40 2009 -0800
+++ b/src/sim/stat_control.cc Mon Feb 23 12:03:06 2009 -0800
@@ -44,14 +44,6 @@
using namespace std;
-Stats::Formula hostInstRate;
-Stats::Formula hostTickRate;
-Stats::Value hostMemory;
-Stats::Value hostSeconds;
-
-Stats::Value simTicks;
-Stats::Value simInsts;
-Stats::Value simFreq;
Stats::Formula simSeconds;
namespace Stats {
@@ -84,8 +76,21 @@
SimTicksReset simTicksReset;
-void
-initSimStats()
+struct Global
+{
+Stats::Formula hostInstRate;
+Stats::Formula hostTickRate;
+Stats::Value hostMemory;
+Stats::Value hostSeconds;
+
+Stats::Value simTicks;
+Stats::Value simInsts;
+Stats::Value simFreq;
+
+Global();
+};
+
+Global::Global()
{
simInsts
.functor(BaseCPU::numSimulatedInstructions)
@@ -146,6 +151,12 @@
registerResetCallback(simTicksReset);
}
+void
+initSimStats()
+{
+static Global global;
+}
+
class _StatEvent : public Event
{
private:
diff -r 5a047c3f3795 -r c810b7d4383d src/sim/stats.hh
--- a/src/sim/stats.hh Mon Feb 23 11:48:40 2009 -0800
+++ b/src/sim/stats.hh Mon Feb 23 12:03:06 2009 -0800
@@ -34,6 +34,5 @@
#include base/statistics.hh
extern Stats::Formula simSeconds;
-extern Stats::Value simTicks;
#endif // __SIM_SIM_STATS_HH__
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] scons weirdness
I've noticed that that command runs frequently when unnecessary, but
I'm surprised that it causes a problem. Are you pushing and popping
patches? Now that we're putting the repository version into the
binary, when you push and pop, this changes. I have noticed that this
runs sometimes even if you change nothing in the repository. Are you
pushing/popping or anythign like that?
Nate
This is what scons is doing when it's recompiling unnecessarily:
makeDefinesPyFile([build/X86_SE/python/m5/defines.py],
[{'ALPHA_TLASER': False, 'FAST_ALLOC_STATS': False, 'FAST_ALLOC_DEBUG':
False, 'USE_CHECKER': False, 'SS_COMPATIBLE_FP': False, 'NO_FAST_ALLOC':
False, 'USE_FENV': True, 'TARGET_ISA': 'x86', 'FULL_SYSTEM': False,
'USE_MYSQL': False}, '652016638b82+ 5907+ default qtip tip
nofetchonmicrostats.patch'])
Gabe Black wrote:
I mentioned this earlier, but scons and regressions are misbehaving,
and it's making updating the regressions very annoying. If a run is
canceled halfway, scons now assumes it actually finished and was just
wrong. I have to go and manually delete the old, incomplete run before
it's willing to try again. Also, it seems really anxious to rebuild and
rerun tests when it -doesn't- need to. This makes it really annoying to,
for instance, see which tests fail, look at the differences, update the
results, and verify that they took. If I don't make any mistakes like
loosing track of which tests failed, that takes three runs through all
of the regressions I'm interested in which takes three times as long as
it needs to. Unfortunately I haven't yet managed this minimum, so I've
resorted to just updating the stats the first time around and looking at
the patch post mortem which is not ideal. If somebody could look at this
I'd really appreciate it. If it seems like a local problem, like from
when I recently upgraded scons for example, that would be useful
information.
Gabe
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Multiprocessor SPARC_FS
[Polina- We should really have these conversations on the list so everyone can benefit from them and to give others the chance to respond] Hi Nate, I am trying to get SPARC_FS to run. I am trying to run two processors and what I have so far is the following: Processor 0 gets activated and runs. I found in utility.hh the following comment: Other CPUs will get activated by IPIs. So, then several generateIpi calls are made but they are not doing anything because the cpu number is out of range. Finally, the cpu number is inside the range and it turns out that it is a halt instruction for processor 1 which was never activated. So assertion (status == Running) fails. I am worried about how the cpu number for Iob write is generated; specifically, I think it's troublesome that cpu can be out of range. I think then a couple things could be happening: 1. This is a halt, but it should be for processor 0 2. This Iob is wrong altogether Would you mind looking at the output? Thanks. output: command line: build/SPARC_FS/m5.debug --trace-flags=SimpleCPU configs/example/fs.py -n 2 Global frequency set at 1 ticks per second warn: No kernel set for full system simulation. Assuming you know what you're doing... Listening for t1000 connection on port 3456 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.t1000.htod: Real-time clock set to 1230768000 Listening for t1000 connection on port 3457 0: global: Started instantiating 0: global: Done instantiating 0: global: Started instantiating 0: global: Done instantiating 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7000 REAL SIMULATION **SimStartup*** starting up 0 0: global: Activation record 0: system.cpu0: ActivateContext 0 (0 cycles) starting up 1 warn: Entering event queue @ 0. Starting simulation... 0: system.cpu0: Tick 500: system.cpu0: Tick 1000: system.cpu0: Tick 1500: system.cpu0: Tick 2000: system.cpu0: Tick 2500: system.cpu0: Tick 3000: system.cpu0: Tick 3500: system.cpu0: Tick 4000: system.cpu0: Tick 4500: system.cpu0: Tick 5000: system.cpu0: Tick 5500: system.cpu0: Tick 6000: system.cpu0: Tick 6500: system.cpu0: Tick 7000: system.cpu0: Tick 7500: system.cpu0: Tick 8000: system.cpu0: Tick 8500: system.cpu0: Tick 9000: system.cpu0: Tick 9500: system.cpu0: Tick 1: system.cpu0: Tick 10500: system.cpu0: Tick 11000: system.cpu0: Tick 11500: system.cpu0: Tick 12000: system.cpu0: Tick 12500: system.cpu0: Tick 13000: system.cpu0: Tick 13500: system.cpu0: Tick 14000: system.cpu0: Tick 14500: system.cpu0: Tick 15000: system.cpu0: Tick 15500: system.cpu0: Tick 16000: system.cpu0: Tick 16500: system.cpu0: Tick 17000: system.cpu0: Tick 17500: system.cpu0: Tick 18000: system.cpu0: Tick 18500: system.cpu0: Tick 19000: system.cpu0: Tick 19500: system.cpu0: Tick 2: system.cpu0: Tick 20500: system.cpu0: Tick 21000: system.cpu0: Tick 21500: system.cpu0: Tick 22000: system.cpu0: Tick 22500: system.cpu0: Tick 23000: system.cpu0: Tick 23500: system.cpu0: Tick generateIpi? CPU number is out of range 24000: system.cpu0: Tick 24500: system.cpu0: Tick 25000: system.cpu0: Tick 25500: system.cpu0: Tick 26000: system.cpu0: Tick 26500: system.cpu0: Tick 27000: system.cpu0: Tick 27500: system.cpu0: Tick 28000: system.cpu0: Tick 28500: system.cpu0: Tick 29000: system.cpu0: Tick generateIpi? CPU number is out of range 29500: system.cpu0: Tick 3: system.cpu0: Tick 30500: system.cpu0: Tick 31000: system.cpu0: Tick 31500: system.cpu0: Tick 32000: system.cpu0: Tick 32500: system.cpu0: Tick 33000: system.cpu0: Tick 33500: system.cpu0: Tick 34000: system.cpu0: Tick 34500: system.cpu0: Tick generateIpi? CPU number is out of range 35000: system.cpu0: Tick 35500: system.cpu0: Tick 36000: system.cpu0: Tick 36500: system.cpu0: Tick 37000: system.cpu0: Tick 37500: system.cpu0: Tick 38000: system.cpu0: Tick 38500: system.cpu0: Tick 39000: system.cpu0: Tick 39500: system.cpu0: Tick 4: system.cpu0: Tick generateIpi? CPU number is out of range 40500: system.cpu0: Tick 41000: system.cpu0: Tick 41500: system.cpu0: Tick 42000: system.cpu0: Tick 42500: system.cpu0: Tick 43000: system.cpu0: Tick 43500: system.cpu0: Tick 44000: system.cpu0: Tick 44500: system.cpu0: Tick 45000: system.cpu0: Tick 45500: system.cpu0: Tick generateIpi? CPU number is out of range 46000: system.cpu0: Tick 46500: system.cpu0: Tick 47000: system.cpu0: Tick 47500: system.cpu0: Tick 48000: system.cpu0: Tick 48500: system.cpu0: Tick 49000: system.cpu0: Tick 49500: system.cpu0: Tick 5: system.cpu0: Tick 50500: system.cpu0: Tick 51000: system.cpu0: Tick generateIpi? CPU number is out of range
Re: [m5-dev] changeset in m5: events: Make trace events happen at the right p...
Sorry. It should be event.Event... Does that fix it? On Tue, Feb 24, 2009 at 10:27 PM, Ali Saidi sa...@umich.edu wrote: This changeset broke tracing that starts at a tick other than 0. command line: ./build/ALPHA_FS/m5.opt --trace-flags=Exec --trace- start=4 configs/example/fs.py Traceback (most recent call last): File string, line 1, in module File /tmp/m5/src/python/m5/main.py, line 315, in main e = event.create(trace.enable, Event.Trace_Enable_Pri) NameError: name 'Event' is not defined Ali On Feb 18, 2009, at 2:37 PM, Nathan Binkert wrote: changeset e9f9c0f7e5f0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=e9f9c0f7e5f0 description: events: Make trace events happen at the right priority. Also, while we're at it, remember that priorities are in the Event class and add a disable method to disable tracing. diffstat: 3 files changed, 9 insertions(+), 3 deletions(-) src/python/m5/event.py | 7 +-- src/python/m5/main.py | 2 +- src/python/m5/trace.py | 3 +++ diffs (47 lines): diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/event.py --- a/src/python/m5/event.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/event.py Wed Feb 18 10:00:15 2009 -0800 @@ -35,13 +35,16 @@ def create(obj, priority=None): if priority is None: - priority = internal.event.Event.Default_Pri + priority = Event.Default_Pri return PythonEvent(obj, priority) + +# As a reminder, priorities found in sim/eventq.hh are stuck into the +# Event class by swig class Event(PythonEvent): def __init__(self, priority=None): if priority is None: - priority = internal.event.Event.Default_Pri + priority = Event.Default_Pri super(Event, self).__init__(self, priority) class ProgressEvent(Event): diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/main.py --- a/src/python/m5/main.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/main.py Wed Feb 18 10:00:15 2009 -0800 @@ -312,7 +312,7 @@ if options.trace_start: check_tracing() - e = event.create(trace.enable) + e = event.create(trace.enable, Event.Trace_Enable_Pri) event.mainq.schedule(e, options.trace_start) else: trace.enable() diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/trace.py --- a/src/python/m5/trace.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/trace.py Wed Feb 18 10:00:15 2009 -0800 @@ -32,6 +32,9 @@ from internal.trace import clear, output, set, ignore +def disable(): + internal.trace.cvar.enabled = False + def enable(): internal.trace.cvar.enabled = True ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: events: Make trace events happen at the right p...
Can you commit? Thanks, Nate On Wed, Feb 25, 2009 at 8:59 AM, Ali Saidi sa...@umich.edu wrote: That fixed it. Ali On Feb 25, 2009, at 1:37 AM, nathan binkert wrote: Sorry. It should be event.Event... Does that fix it? On Tue, Feb 24, 2009 at 10:27 PM, Ali Saidi sa...@umich.edu wrote: This changeset broke tracing that starts at a tick other than 0. command line: ./build/ALPHA_FS/m5.opt --trace-flags=Exec --trace- start=4 configs/example/fs.py Traceback (most recent call last): File string, line 1, in module File /tmp/m5/src/python/m5/main.py, line 315, in main e = event.create(trace.enable, Event.Trace_Enable_Pri) NameError: name 'Event' is not defined Ali On Feb 18, 2009, at 2:37 PM, Nathan Binkert wrote: changeset e9f9c0f7e5f0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=e9f9c0f7e5f0 description: events: Make trace events happen at the right priority. Also, while we're at it, remember that priorities are in the Event class and add a disable method to disable tracing. diffstat: 3 files changed, 9 insertions(+), 3 deletions(-) src/python/m5/event.py | 7 +-- src/python/m5/main.py | 2 +- src/python/m5/trace.py | 3 +++ diffs (47 lines): diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/event.py --- a/src/python/m5/event.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/event.py Wed Feb 18 10:00:15 2009 -0800 @@ -35,13 +35,16 @@ def create(obj, priority=None): if priority is None: - priority = internal.event.Event.Default_Pri + priority = Event.Default_Pri return PythonEvent(obj, priority) + +# As a reminder, priorities found in sim/eventq.hh are stuck into the +# Event class by swig class Event(PythonEvent): def __init__(self, priority=None): if priority is None: - priority = internal.event.Event.Default_Pri + priority = Event.Default_Pri super(Event, self).__init__(self, priority) class ProgressEvent(Event): diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/main.py --- a/src/python/m5/main.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/main.py Wed Feb 18 10:00:15 2009 -0800 @@ -312,7 +312,7 @@ if options.trace_start: check_tracing() - e = event.create(trace.enable) + e = event.create(trace.enable, Event.Trace_Enable_Pri) event.mainq.schedule(e, options.trace_start) else: trace.enable() diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/trace.py --- a/src/python/m5/trace.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/trace.py Wed Feb 18 10:00:15 2009 -0800 @@ -32,6 +32,9 @@ from internal.trace import clear, output, set, ignore +def disable(): + internal.trace.cvar.enabled = False + def enable(): internal.trace.cvar.enabled = True ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: events: Make trace events happen at the right p...
This change won't affect the regressions. It's only when you use the --trace-start command line option. On Wed, Feb 25, 2009 at 9:29 AM, Gabe Black gbl...@eecs.umich.edu wrote: Please run all the regressions before you do. I'm almost ready to push and I'd hate to start checking everything again. Gabe nathan binkert wrote: Can you commit? Thanks, Nate On Wed, Feb 25, 2009 at 8:59 AM, Ali Saidi sa...@umich.edu wrote: That fixed it. Ali On Feb 25, 2009, at 1:37 AM, nathan binkert wrote: Sorry. It should be event.Event... Does that fix it? On Tue, Feb 24, 2009 at 10:27 PM, Ali Saidi sa...@umich.edu wrote: This changeset broke tracing that starts at a tick other than 0. command line: ./build/ALPHA_FS/m5.opt --trace-flags=Exec --trace- start=4 configs/example/fs.py Traceback (most recent call last): File string, line 1, in module File /tmp/m5/src/python/m5/main.py, line 315, in main e = event.create(trace.enable, Event.Trace_Enable_Pri) NameError: name 'Event' is not defined Ali On Feb 18, 2009, at 2:37 PM, Nathan Binkert wrote: changeset e9f9c0f7e5f0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=e9f9c0f7e5f0 description: events: Make trace events happen at the right priority. Also, while we're at it, remember that priorities are in the Event class and add a disable method to disable tracing. diffstat: 3 files changed, 9 insertions(+), 3 deletions(-) src/python/m5/event.py | 7 +-- src/python/m5/main.py | 2 +- src/python/m5/trace.py | 3 +++ diffs (47 lines): diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/event.py --- a/src/python/m5/event.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/event.py Wed Feb 18 10:00:15 2009 -0800 @@ -35,13 +35,16 @@ def create(obj, priority=None): if priority is None: - priority = internal.event.Event.Default_Pri + priority = Event.Default_Pri return PythonEvent(obj, priority) + +# As a reminder, priorities found in sim/eventq.hh are stuck into the +# Event class by swig class Event(PythonEvent): def __init__(self, priority=None): if priority is None: - priority = internal.event.Event.Default_Pri + priority = Event.Default_Pri super(Event, self).__init__(self, priority) class ProgressEvent(Event): diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/main.py --- a/src/python/m5/main.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/main.py Wed Feb 18 10:00:15 2009 -0800 @@ -312,7 +312,7 @@ if options.trace_start: check_tracing() - e = event.create(trace.enable) + e = event.create(trace.enable, Event.Trace_Enable_Pri) event.mainq.schedule(e, options.trace_start) else: trace.enable() diff -r ce12f1cf978c -r e9f9c0f7e5f0 src/python/m5/trace.py --- a/src/python/m5/trace.py Tue Feb 17 19:24:46 2009 -0800 +++ b/src/python/m5/trace.py Wed Feb 18 10:00:15 2009 -0800 @@ -32,6 +32,9 @@ from internal.trace import clear, output, set, ignore +def disable(): + internal.trace.cvar.enabled = False + def enable(): internal.trace.cvar.enabled = True ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: quell gcc 4.3 warning
changeset 0ea37baabfb0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0ea37baabfb0
description:
quell gcc 4.3 warning
diffstat:
1 file changed, 4 insertions(+), 4 deletions(-)
src/arch/x86/tlb.cc |8
diffs (25 lines):
diff -r d4cb6394049b -r 0ea37baabfb0 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Fri Feb 27 09:26:41 2009 -0800
+++ b/src/arch/x86/tlb.cc Fri Feb 27 17:29:58 2009 -0800
@@ -590,8 +590,8 @@
// address size is 64 bits, overridable to 32.
int size = 32;
bool sizeOverride = (flags (AddrSizeFlagBit FlagShift));
-if (csAttr.defaultSize sizeOverride ||
-!csAttr.defaultSize !sizeOverride)
+if ((csAttr.defaultSize sizeOverride) ||
+(!csAttr.defaultSize !sizeOverride))
size = 16;
Addr offset = bits(vaddr - base, size-1, 0);
Addr endOffset = offset + req-getSize() - 1;
@@ -647,8 +647,8 @@
// Do paging protection checks.
bool inUser = (csAttr.dpl == 3
!(flags (CPL0FlagBit FlagShift)));
-if (inUser !entry-user ||
-write !entry-writable) {
+if ((inUser !entry-user) ||
+(write !entry-writable)) {
// The page must have been present to get into the TLB in
// the first place. We'll assume the reserved bits are
// fine even though we're not checking them.
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] suspending unallocated context
I agree that this stuff is all messed up. There's threads and cpus each which have various states that don't necessarily work with each other. Some of the states have to do with indicating that a CPU has nothing to do at the moment so we don't need to schedule a tick, and some indicate the type of stuff that Gabe is discussing. Nate On Sat, Feb 28, 2009 at 1:08 PM, Steve Reinhardt ste...@gmail.com wrote: Recalling from some of the issues with getting O3 MT to work, I believe there's a general confusion and inconsistency with respect to the meanings of suspended, unallocated, and perhaps other states. It's possible (maybe even likely) that the code that does SE-mode MT apps like SPLASH has requirements that are inconsistent with FS mode. So there's no right answer short of figuring out how it ought to be and fixing the half of the code that assumes something different. Can you tell how it works in Alpha FS? Seems like x86 shouldn't be any different. Steve On Sat, Feb 28, 2009 at 12:48 PM, Gabe Black gbl...@eecs.umich.edu wrote: I'm trying to bring up SMP under x86 FS, and I'm not able to wake up any AP because the wakeup function gives up if the CPU isn't suspended. The CPUs I'm working with are actually unallocated, so nothing happens. I had startupCPU set up to suspend the APs as the came up, but that causes a problem with the simple CPUs which insist the thread is Running, and again it's Unallocated. How is this supposed to work? Do I have to activate and then suspend a context? Or did somebody just leave a possible option out of an assert someplace? Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] suspending unallocated context
Yep. On Sat, Feb 28, 2009 at 6:40 PM, Korey Sewell ksew...@umich.edu wrote: Nate, are you referring to the CPU's state vs. the actual thread-object's state? That connection between the two in my opinion has been ad-hoc for awhile or at least beyond my complete understanding. Changing things for FS breaks SE and vice-versa. Needless to say, we should probably get this straightened out and documented in the near future... On Sat, Feb 28, 2009 at 9:30 PM, nathan binkert n...@binkert.org wrote: I agree that this stuff is all messed up. There's threads and cpus each which have various states that don't necessarily work with each other. Some of the states have to do with indicating that a CPU has nothing to do at the moment so we don't need to schedule a tick, and some indicate the type of stuff that Gabe is discussing. Nate On Sat, Feb 28, 2009 at 1:08 PM, Steve Reinhardt ste...@gmail.com wrote: Recalling from some of the issues with getting O3 MT to work, I believe there's a general confusion and inconsistency with respect to the meanings of suspended, unallocated, and perhaps other states. It's possible (maybe even likely) that the code that does SE-mode MT apps like SPLASH has requirements that are inconsistent with FS mode. So there's no right answer short of figuring out how it ought to be and fixing the half of the code that assumes something different. Can you tell how it works in Alpha FS? Seems like x86 shouldn't be any different. Steve On Sat, Feb 28, 2009 at 12:48 PM, Gabe Black gbl...@eecs.umich.edu wrote: I'm trying to bring up SMP under x86 FS, and I'm not able to wake up any AP because the wakeup function gives up if the CPU isn't suspended. The CPUs I'm working with are actually unallocated, so nothing happens. I had startupCPU set up to suspend the APs as the came up, but that causes a problem with the simple CPUs which insist the thread is Running, and again it's Unallocated. How is this supposed to work? Do I have to activate and then suspend a context? Or did somebody just leave a possible option out of an assert someplace? Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] wrong answer from getMemoryMode
I think that Steve is the only one who both pays attention to the list and might understand what's going on here. Nate On Mon, Feb 23, 2009 at 2:30 AM, Gabe Black gbl...@eecs.umich.edu wrote: I was working on getting the X86_FS working with the timing simple CPU as well as it does with atomic, and found that when called in my page table walker, sys-getMemoryMode() is very definitely giving the wrong answer. I suspect there's something I didn't do quite right when setting up the system object, but since part of that is in python I wasn't sure how it all went together. Why might my system object think it's in atomic mode when it's actually in timing? How does it end up assuming one mode or the other? Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] [PATCH 3 of 5] InOrder didnt have all it's params set to a default value, which is now required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before
@@ -53,6 +53,15 @@ struct InterStageStruct {
uint64_t nextPC;
InstSeqNum squashedSeqNum;
bool includeSquashInst;
+
+ InterStageStruct()
+ {
+ size = 0;
+ mispredPC = nextPC = 0;
+ squash = branchMispredict = branchTaken = false;
+ squashedSeqNum = 0;
+ }
+
This is a constructor, right? Can you use proper C++ initialization? e.g.
InterStateStruct()
: size(0), mispredPC(0), nextPC(0),
{}
The compiler can do better things when you do this.
InOrderDynInst::InOrderDynInst()
: traceData(NULL), cpu(cpu)
-{ initVars(); }
+{
+ seqNum = 0;
+ initVars();
+}
Same proper initialization for seqNum
Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] [m5-users] Using the pin command to bin programs to cores
The m5 binary on the disk image that we distribute doesn't support the pin command. You'll need to compile it yourself. Additionally, I don't believe libc on the disk image supports sched_setaffinity (needed by pin). This is something we need to fix, but it unfortunately involves distributing a new disk image to everyone and updating a bunch of regressions. You can easily make a new disk image by starting with a gentoo image or you can copy the libc* and libstdc++* from one of the cross compilers on the m5sim.org website onto the disk image (you might need to make the actual image bigger to do this). Maybe we should just bite the bullet and do this. If we do, I think we should probably deprecate any stuff we don't like in the m5ops stuff. My inclination is to just generate a new disk image with gentoo 2008.0, recompile the binaries and move them over. Does anyone have a problem if we do this? Does anyone know if/when a 2009.0 is supposed to come out? Should we wait for it? I will probably be a many weeks before I could have time to do this, but it may at least be good to have a plan of attack so we can do the right thing when the time comes. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: Give TimeBuffer an ID that can be set. Necessar...
+ int id()
+ {
+ return _id;
+ }
+
This one should be declared const. int id() const ...
Please try to use const properly.
Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] sparc_fs follow-up
If you want to get going quickly, you can download the scons-local package and just stick it somewhere. Nate 2009/3/5 Polina Dudnik pdud...@gmail.com: Yes, I am trying to figure it out right now by running it withing gdb. It is pretty interesting that my output only differs from yours by one line which is segfault. It will be a little bit before I can install the most recent m5-dev because the scons was upgraded to 0.98 and we are still on 0.97 and I need to wait for the lab to upgrade scons. Polina On Thu, Mar 5, 2009 at 2:26 PM, Ali Saidi sa...@umich.edu wrote: My output looks like this: M5 compiled Mar 5 2009 13:51:37 M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff qbase M5 started Mar 5 2009 14:03:22 M5 executing on zeep command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2 Global frequency set at 1 ticks per second info: No kernel set for full system simulation. Assuming you know what you're doing... Listening for t1000 connection on port 3456 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009 0: system.t1000.htod: Real-time clock set to 1230768000 Listening for t1000 connection on port 3457 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7000 REAL SIMULATION info: Entering event queue @ 0. Starting simulation... hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) hack: Processor 2 is virtual processor 4. Swizzle the numbers(this will only work for = 2 processors) info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. For more information see: http://www.m5sim.org/warn/7fe1004f info: Ignoring write to SPARC ERROR regsiter info: Ignoring write to SPARC ERROR regsiter and the console output looks like: cpu cpu Sun Fire T2000, No Keyboard Copyright 2006 Sun Microsystems, Inc. All rights reserved. OpenBoot 4.23.0, 256 MB memory available, Serial #1122867. [saidi obp #30] Ethernet address 0:80:3:de:ad:3, Host ID: 80112233. Boot device: /virtual-devices/d...@0 File and args: -vV Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. FCode UFS Reader 1.12 00/07/17 15:48:16. Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot Loading: /platform/sun4v/ufsboot device path '/virtual-devi...@100/d...@0:a' The boot filesystem is logging. The ufs log is empty and will not be used. standalone = `kernel/sparcv9/unix', args = `-v' Elf64 client Size: 0x76e40+0x1c872+0x3123a Bytes modpath: /platform/sun4v/kernel /kernel /usr/kernel module /platform/sun4v/kernel/sparcv9/unix: text at [0x100, 0x1076e3f] data at 0x180 module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0 module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0 module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0 module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300 SunOS Release 5.10 Version Generic_118822-23 64-bit Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Ethernet address = 0:80:3:de:ad:3 mem = 262144K (0x1000) avail mem = 237879296 root nexus = Sun Fire T2000 pseudo0 at root pseudo0 is /pseudo scsi_vhci0 at root scsi_vhci0 is /scsi_vhci virtual-device: hsimd0 hsimd0 is /virtual-devi...@100/d...@0 root on /virtual-devi...@100/d...@0:a fstype ufs pseudo-device: dld0 dld0 is /pseudo/d...@0 cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz) cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz) At this point there is no futher output. I imagine that one cpu is waiting for another one or something and whatever condition it's waiting for is not being reached. It is still interesting to know why it's crashing for you, since it might shed some light on the reason. The thing to do now is look through the solaris source to see what is going on right after the cpuX: ... lines are printed and look at an exec trace and try to debug the problem. Ali On Mar 5, 2009, at 2:30 PM, Polina Dudnik wrote: It is m5-stable. Maybe I should change to m5. I can do that. Also, are any of the binaries dependent on 1g2p-md.bin or 1g2p- hv.bin by any chance? Polina On Thu, Mar 5, 2009 at 1:24 PM, Steve Reinhardt ste...@gmail.com wrote: m5 or m5-stable? The contextId change is in the former but not the latter. 2009/3/5 Polina Dudnik pdud...@gmail.com: I am doing it in m5. Polina - Show quoted text - On Thu, Mar 5, 2009 at 1:04 PM, Steve Reinhardt ste...@gmail.com wrote: - Show quoted text - 2009/3/5 Polina Dudnik pdud...@gmail.com: I am not sure why our code base would be different and
Re: [m5-dev] FS benchmark description
There are multiple benchmarks that can be run in FS mode (like ValStream). Where can I find a precise description of what those benchmarks do exactly? The reason I ask is because I would like to verify their behavior on SPARC_FS. I don't know if much has been written down other than in papers that people have written using M5. (I'm not sure what ValStream even is.) Also a lot of those benchmarks use tsunami, so they are inherently only benchmarking Alpha. Are there equivalents for SPARC? I'm not sure why you think any of the benchmarks we've used are inherently only for alpha. If you're talking about how the binaries are compiled for alpha, that's true, but most things can be compiled for whichever architecture you want. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: serialize: Allow floats and doubles to be seria...
changeset 9c04119e93af in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=9c04119e93af description: serialize: Allow floats and doubles to be serialized diffstat: 1 file changed, 2 insertions(+) src/sim/serialize.cc |2 ++ diffs (12 lines): diff -r 3ca926101a5c -r 9c04119e93af src/sim/serialize.cc --- a/src/sim/serialize.cc Thu Mar 05 17:15:31 2009 -0800 +++ b/src/sim/serialize.cc Thu Mar 05 19:09:53 2009 -0800 @@ -351,6 +351,8 @@ INSTANTIATE_PARAM_TEMPLATES(signed long long) INSTANTIATE_PARAM_TEMPLATES(unsigned long long) INSTANTIATE_PARAM_TEMPLATES(bool) +INSTANTIATE_PARAM_TEMPLATES(float) +INSTANTIATE_PARAM_TEMPLATES(double) INSTANTIATE_PARAM_TEMPLATES(string) ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: miscellaneous cleanup
changeset 71e56052768f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=71e56052768f
description:
stats: miscellaneous cleanup
diffstat:
1 file changed, 7 insertions(+), 9 deletions(-)
src/base/statistics.hh | 16 +++-
diffs (82 lines):
diff -r 9c04119e93af -r 71e56052768f src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -468,7 +468,7 @@
/**
* Set the precision and marks this stat to print at the end of simulation.
- * @param p The new precision
+ * @param _precision The new precision
* @return A reference to this stat.
*/
Parent
@@ -728,7 +728,7 @@
void
reset(Info *info)
{
-total = 0;
+total = 0.0;
last = curTick;
}
@@ -1253,7 +1253,7 @@
Result
total() const
{
-Result total = 0;
+Result total = 0.0;
for (off_type i = 0; i size(); ++i)
total += data(i)-result();
return total;
@@ -1471,7 +1471,6 @@
* Add a value to the distribution for the given number of times.
* @param val The value to add.
* @param number The number of times to add the value.
- * @param params The paramters of the distribution.
*/
void
sample(Counter val, int number)
@@ -1595,7 +1594,6 @@
* values seen by the given number.
* @param val The value to add.
* @param number The number of times to add the value.
- * @param p The parameters of this stat.
*/
void
sample(Counter val, int number)
@@ -1973,7 +1971,7 @@
Result
VectorDistBaseStorage::total(off_type index) const
{
-Result total = 0;
+Result total = 0.0;
for (off_type i = 0; i x_size(); ++i)
total += data(i)-result();
}
@@ -2215,7 +2213,7 @@
total() const
{
const VResult vec = this-result();
-Result total = 0;
+Result total = 0.0;
for (off_type i = 0; i size(); i++)
total += vec[i];
return total;
@@ -2277,7 +2275,7 @@
total() const
{
const VResult vec = this-result();
-Result total = 0;
+Result total = 0.0;
for (off_type i = 0; i size(); i++)
total += vec[i];
return total;
@@ -2853,7 +2851,7 @@
* Return the node pointer.
* @return the node pointer.
*/
-operator NodePtr() { return node;}
+operator NodePtr() { return node; }
public:
/**
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: get rid of meaningless uses of virtual
changeset 19131d568007 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=19131d568007
description:
stats: get rid of meaningless uses of virtual
diffstat:
1 file changed, 79 insertions(+), 79 deletions(-)
src/base/statistics.hh | 158
diffs (truncated from 391 to 300 lines):
diff -r 71e56052768f -r 19131d568007 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -155,7 +155,7 @@
virtual Counter value() const = 0;
virtual Result result() const = 0;
virtual Result total() const = 0;
-virtual void visit(Visit visitor) { visitor.visit(*this); }
+void visit(Visit visitor) { visitor.visit(*this); }
};
template class Stat
@@ -167,12 +167,12 @@
public:
ScalarInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual Counter value() const { return s.value(); }
-virtual Result result() const { return s.result(); }
-virtual Result total() const { return s.total(); }
-virtual void reset() { s.reset(); }
-virtual bool zero() const { return s.zero(); }
+bool check() const { return s.check(); }
+Counter value() const { return s.value(); }
+Result result() const { return s.result(); }
+Result total() const { return s.total(); }
+void reset() { s.reset(); }
+bool zero() const { return s.zero(); }
};
class VectorInfoBase : public Info
@@ -183,10 +183,10 @@
mutable std::vectorstd::string subdescs;
public:
-virtual size_type size() const = 0;
+virtual size_type size() const = 0;
virtual const VCounter value() const = 0;
virtual const VResult result() const = 0;
-virtual Result total() const = 0;
+virtual Result total() const = 0;
void
update()
@@ -213,29 +213,29 @@
public:
VectorInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual bool zero() const { return s.zero(); }
-virtual void reset() { s.reset(); }
+bool check() const { return s.check(); }
+bool zero() const { return s.zero(); }
+void reset() { s.reset(); }
-virtual size_type size() const { return s.size(); }
+size_type size() const { return s.size(); }
-virtual VCounter
+VCounter
value() const
{
s.value(cvec);
return cvec;
}
-virtual const VResult
+const VResult
result() const
{
s.result(rvec);
return rvec;
}
-virtual Result total() const { return s.total(); }
+Result total() const { return s.total(); }
-virtual void
+void
visit(Visit visitor)
{
update();
@@ -274,11 +274,11 @@
public:
DistInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual void reset() { s.reset(); }
-virtual bool zero() const { return s.zero(); }
+bool check() const { return s.check(); }
+void reset() { s.reset(); }
+bool zero() const { return s.zero(); }
-virtual void
+void
visit(Visit visitor)
{
s.update(this);
@@ -323,12 +323,12 @@
public:
VectorDistInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual void reset() { s.reset(); }
-virtual size_type size() const { return s.size(); }
-virtual bool zero() const { return s.zero(); }
+bool check() const { return s.check(); }
+void reset() { s.reset(); }
+size_type size() const { return s.size(); }
+bool zero() const { return s.zero(); }
-virtual void
+void
visit(Visit visitor)
{
update();
@@ -368,11 +368,11 @@
public:
Vector2dInfo(Stat stat) : s(stat) {}
-virtual bool check() const { return s.check(); }
-virtual void reset() { s.reset(); }
-virtual bool zero() const { return s.zero(); }
+bool check() const { return s.check(); }
+void reset() { s.reset(); }
+bool zero() const { return s.zero(); }
-virtual void
+void
visit(Visit visitor)
{
update();
@@ -862,12 +862,12 @@
class ProxyInfo : public ScalarInfoBase
{
public:
-virtual void visit(Visit visitor) { visitor.visit(*this); }
-virtual std::string str() const { return to_string(value()); }
-virtual size_type size() const { return 1; }
-virtual bool zero() const { return value() == 0; }
-virtual bool check() const { return true; }
-virtual void reset() { }
+void visit(Visit visitor) { visitor.visit(*this); }
+std::string str() const { return to_string(value()); }
+size_type size() const { return 1; }
+bool zero() const { return value() == 0; }
+bool check() const { return true; }
+void reset() { }
};
template class T
@@ -878,9 +878,9 @@
public:
ValueProxy(T val) : scalar(val) {}
-virtual Counter value() const { return *scalar;
[m5-dev] changeset in m5: stats: better naming of template parameters for...
changeset 2c9823c60c8c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2c9823c60c8c
description:
stats: better naming of template parameters for the wrapper stuff
Parent and Child are bad names. Derived and Base are better.
diffstat:
1 file changed, 25 insertions(+), 25 deletions(-)
src/base/statistics.hh | 50
diffs (144 lines):
diff -r 19131d568007 -r 2c9823c60c8c src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -397,16 +397,16 @@
const Info *info() const;
};
-template class Parent, class Child, template class class Info
-class Wrap : public Child
+template class Derived, class Base, template class class Info
+class Wrap : public Base
{
public:
-typedef Parent ParentType;
-typedef Child ChildType;
-typedef InfoChild InfoType;
+typedef Derived DerivedType;
+typedef Base BaseType;
+typedef InfoBase InfoType;
protected:
-Parent self() { return *reinterpret_castParent *(this); }
+Derived self() { return *reinterpret_castDerived *(this); }
protected:
InfoType *
@@ -444,7 +444,7 @@
* @param name The new name.
* @return A reference to this stat.
*/
-Parent
+Derived
name(const std::string _name)
{
InfoType *info = this-info();
@@ -459,7 +459,7 @@
* @param desc The new description.
* @return A reference to this stat.
*/
-Parent
+Derived
desc(const std::string _desc)
{
this-info()-desc = _desc;
@@ -471,7 +471,7 @@
* @param _precision The new precision
* @return A reference to this stat.
*/
-Parent
+Derived
precision(int _precision)
{
this-info()-precision = _precision;
@@ -483,7 +483,7 @@
* @param f The new flags.
* @return A reference to this stat.
*/
-Parent
+Derived
flags(StatFlags _flags)
{
this-info()-flags |= _flags;
@@ -497,7 +497,7 @@
* @return A reference to this stat.
*/
template class Stat
-Parent
+Derived
prereq(const Stat prereq)
{
this-info()-prereq = prereq.info();
@@ -505,13 +505,13 @@
}
};
-template class Parent, class Child, template class Child class Info
-class WrapVec : public WrapParent, Child, Info
+template class Derived, class Base, template class Base class Info
+class WrapVec : public WrapDerived, Base, Info
{
public:
-typedef Parent ParentType;
-typedef Child ChildType;
-typedef InfoChild InfoType;
+typedef Derived DerivedType;
+typedef Base BaseType;
+typedef InfoBase InfoType;
public:
// The following functions are specific to vectors. If you use them
@@ -524,7 +524,7 @@
* @param name The new name of the subfield.
* @return A reference to this stat.
*/
-Parent
+Derived
subname(off_type index, const std::string name)
{
std::vectorstd::string subn = this-info()-subnames;
@@ -541,7 +541,7 @@
* @param desc The new description of the subfield
* @return A reference to this stat.
*/
-Parent
+Derived
subdesc(off_type index, const std::string desc)
{
std::vectorstd::string subd = this-info()-subdescs;
@@ -554,20 +554,20 @@
};
-template class Parent, class Child, template class Child class Info
-class WrapVec2d : public WrapVecParent, Child, Info
+template class Derived, class Base, template class Base class Info
+class WrapVec2d : public WrapVecDerived, Base, Info
{
public:
-typedef Parent ParentType;
-typedef Child ChildType;
-typedef InfoChild InfoType;
+typedef Derived DerivedType;
+typedef Base BaseType;
+typedef InfoBase InfoType;
public:
/**
* @warning This makes the assumption that if you're gonna subnames a 2d
* vector, you're subnaming across all y
*/
-Parent
+Derived
ysubnames(const char **names)
{
InfoType *info = this-info();
@@ -577,7 +577,7 @@
return this-self();
}
-Parent
+Derived
ysubname(off_type index, const std::string subname)
{
InfoType *info = this-info();
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: Add a wrapper class for the information ...
changeset 7674070ccc92 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7674070ccc92
description:
stats: Add a wrapper class for the information side of things.
This provides an easy way to provide the callbacks into the data side
of things from the info side of things. Rename Wrap to DataWrap so it
is more easily distinguishable from InfoWrap
diffstat:
1 file changed, 98 insertions(+), 125 deletions(-)
src/base/statistics.hh | 223 +---
diffs (truncated from 538 to 300 lines):
diff -r 2c9823c60c8c -r 7674070ccc92 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -115,7 +115,7 @@
virtual ~Info();
/**
- * Reset the corresponding stat to the default state.
+ * Reset the stat to the default state.
*/
virtual void reset() = 0;
@@ -149,6 +149,20 @@
static bool less(Info *stat1, Info *stat2);
};
+template class Stat, class Base
+class InfoWrap : public Base
+{
+ protected:
+Stat s;
+
+ public:
+InfoWrap(Stat stat) : s(stat) {}
+
+bool check() const { return s.check(); }
+void reset() { s.reset(); }
+bool zero() const { return s.zero(); }
+};
+
class ScalarInfoBase : public Info
{
public:
@@ -159,20 +173,14 @@
};
template class Stat
-class ScalarInfo : public ScalarInfoBase
+class ScalarInfo : public InfoWrapStat, ScalarInfoBase
{
- protected:
-Stat s;
+ public:
+ScalarInfo(Stat stat) : InfoWrapStat, ScalarInfoBase(stat) {}
- public:
-ScalarInfo(Stat stat) : s(stat) {}
-
-bool check() const { return s.check(); }
-Counter value() const { return s.value(); }
-Result result() const { return s.result(); }
-Result total() const { return s.total(); }
-void reset() { s.reset(); }
-bool zero() const { return s.zero(); }
+Counter value() const { return this-s.value(); }
+Result result() const { return this-s.result(); }
+Result total() const { return this-s.total(); }
};
class VectorInfoBase : public Info
@@ -203,43 +211,38 @@
};
template class Stat
-class VectorInfo : public VectorInfoBase
+class VectorInfo : public InfoWrapStat, VectorInfoBase
{
protected:
-Stat s;
mutable VCounter cvec;
mutable VResult rvec;
public:
-VectorInfo(Stat stat) : s(stat) {}
+VectorInfo(Stat stat) : InfoWrapStat, VectorInfoBase(stat) {}
-bool check() const { return s.check(); }
-bool zero() const { return s.zero(); }
-void reset() { s.reset(); }
-
-size_type size() const { return s.size(); }
+size_type size() const { return this-s.size(); }
VCounter
value() const
{
-s.value(cvec);
+this-s.value(cvec);
return cvec;
}
const VResult
result() const
{
-s.result(rvec);
+this-s.result(rvec);
return rvec;
}
-Result total() const { return s.total(); }
+Result total() const { return this-s.total(); }
void
visit(Visit visitor)
{
-update();
-s.update(this);
+this-update();
+this-s.update(this);
visitor.visit(*this);
}
};
@@ -266,22 +269,15 @@
};
template class Stat
-class DistInfo : public DistInfoBase
+class DistInfo : public InfoWrapStat, DistInfoBase
{
- protected:
-Stat s;
-
public:
-DistInfo(Stat stat) : s(stat) {}
-
-bool check() const { return s.check(); }
-void reset() { s.reset(); }
-bool zero() const { return s.zero(); }
+DistInfo(Stat stat) : InfoWrapStat, DistInfoBase(stat) {}
void
visit(Visit visitor)
{
-s.update(this);
+this-s.update(this);
visitor.visit(*this);
}
};
@@ -315,24 +311,18 @@
};
template class Stat
-class VectorDistInfo : public VectorDistInfoBase
+class VectorDistInfo : public InfoWrapStat, VectorDistInfoBase
{
- protected:
-Stat s;
+ public:
+VectorDistInfo(Stat stat) : InfoWrapStat, VectorDistInfoBase(stat) {}
- public:
-VectorDistInfo(Stat stat) : s(stat) {}
-
-bool check() const { return s.check(); }
-void reset() { s.reset(); }
-size_type size() const { return s.size(); }
-bool zero() const { return s.zero(); }
+size_type size() const { return this-s.size(); }
void
visit(Visit visitor)
{
-update();
-s.update(this);
+this-update();
+this-s.update(this);
visitor.visit(*this);
}
};
@@ -360,23 +350,16 @@
};
template class Stat
-class Vector2dInfo : public Vector2dInfoBase
+class Vector2dInfo : public InfoWrapStat, Vector2dInfoBase
{
- protected:
-Stat s;
-
public:
-Vector2dInfo(Stat stat) : s(stat) {}
-
-bool check() const { return s.check(); }
-void reset() { s.reset(); }
-bool zero() const { return s.zero(); }
+Vector2dInfo(Stat stat) : InfoWrapStat,
[m5-dev] changeset in m5: stats: stick the distribution's fancy parameter...
changeset 471090ec173e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=471090ec173e
description:
stats: stick the distribution's fancy parameter into the parameters
structure.
diffstat:
3 files changed, 22 insertions(+), 26 deletions(-)
src/base/statistics.hh | 23 ++-
src/base/stats/mysql.cc |8
src/base/stats/text.cc | 17 -
diffs (130 lines):
diff -r 7674070ccc92 -r 471090ec173e src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -257,8 +257,6 @@
Counter sum;
Counter squares;
Counter samples;
-
-bool fancy;
};
class DistInfoBase : public Info
@@ -1419,8 +1417,9 @@
Counter bucket_size;
/** The number of buckets. Equal to (max-min)/bucket_size. */
size_type buckets;
+
+enum { fancy = false };
};
-enum { fancy = false };
private:
/** The minimum value to track. */
@@ -1556,10 +1555,10 @@
class FancyStor
{
public:
-struct Params : public StorageParams {};
-
- public:
-enum { fancy = true };
+struct Params : public StorageParams
+{
+enum { fancy = true };
+};
private:
/** The current sum. */
@@ -1632,10 +1631,10 @@
class AvgFancy
{
public:
-struct Params : public StorageParams {};
-
- public:
-enum { fancy = true };
+struct Params : public StorageParams
+{
+enum { fancy = true };
+};
private:
/** Current total. */
@@ -1765,7 +1764,6 @@
void
update(DistInfoBase *base)
{
-base-data.fancy = Storage::fancy;
data()-update(info(), base-data);
}
@@ -1881,7 +1879,6 @@
size_type size = this-size();
base-data.resize(size);
for (off_type i = 0; i size; ++i) {
-base-data[i].fancy = Storage::fancy;
data(i)-update(info(), base-data[i]);
}
}
diff -r 7674070ccc92 -r 471090ec173e src/base/stats/mysql.cc
--- a/src/base/stats/mysql.cc Thu Mar 05 19:09:53 2009 -0800
+++ b/src/base/stats/mysql.cc Thu Mar 05 19:09:53 2009 -0800
@@ -583,8 +583,8 @@
if (!configure(info, DIST))
return;
-if (!info.data.fancy) {
-const Params *params = safe_castconst Params *(info.storageParams);
+const Params *params = safe_castconst Params *(info.storageParams);
+if (!params-fancy) {
stat.size = params-buckets;
stat.min = params-min;
stat.max = params-max;
@@ -599,8 +599,8 @@
if (!configure(info, VECTORDIST))
return;
-if (!info.data[0].fancy) {
-const Params *params = safe_castconst Params *(info.storageParams);
+const Params *params = safe_castconst Params *(info.storageParams);
+if (!params-fancy) {
stat.size = params-buckets;
stat.min = params-min;
stat.max = params-max;
diff -r 7674070ccc92 -r 471090ec173e src/base/stats/text.cc
--- a/src/base/stats/text.ccThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/stats/text.ccThu Mar 05 19:09:53 2009 -0800
@@ -673,12 +673,11 @@
print.squares = data.squares;
print.samples = data.samples;
-print.fancy = data.fancy;
+const DistStor::Params *params =
+safe_castconst DistStor::Params *(info.storageParams);
-if (!data.fancy) {
-const DistStor::Params *params =
-safe_castconst DistStor::Params *(info.storageParams);
-
+print.fancy = params-fancy;
+if (!params-fancy) {
print.min = params-min;
print.max = params-max;
print.bucket_size = params-bucket_size;
@@ -716,11 +715,11 @@
print.squares = info.data[i].squares;
print.samples = info.data[i].samples;
-print.fancy = info.data[i].fancy;
-if (!print.fancy) {
-const DistStor::Params *params =
-safe_castconst DistStor::Params *(info.storageParams);
+const DistStor::Params *params =
+safe_castconst DistStor::Params *(info.storageParams);
+print.fancy = params-fancy;
+if (!params-fancy) {
print.min = params-min;
print.max = params-max;
print.bucket_size = params-bucket_size;
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: remove the template wart left over from ...
changeset a4c935e9cf99 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a4c935e9cf99
description:
stats: remove the template wart left over from the ancient binning stuff
diffstat:
1 file changed, 14 insertions(+), 28 deletions(-)
src/base/statistics.hh | 42 ++
diffs (151 lines):
diff -r 471090ec173e -r a4c935e9cf99 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -2350,8 +2350,7 @@
* This is a simple scalar statistic, like a counter.
* @sa Stat, ScalarBase, StatStor
*/
-templateint N = 0
-class Scalar : public DataWrapScalarN, ScalarBaseStatStor, ScalarInfo
+class Scalar : public DataWrapScalar, ScalarBaseStatStor, ScalarInfo
{
public:
/** The base implementation. */
@@ -2398,8 +2397,7 @@
* A stat that calculates the per tick average of a value.
* @sa Stat, ScalarBase, AvgStor
*/
-templateint N = 0
-class Average : public DataWrapAverageN, ScalarBaseAvgStor, ScalarInfo
+class Average : public DataWrapAverage, ScalarBaseAvgStor, ScalarInfo
{
public:
/** The base implementation. */
@@ -2427,8 +2425,7 @@
* A vector of scalar stats.
* @sa Stat, VectorBase, StatStor
*/
-templateint N = 0
-class Vector : public DataWrapVecVectorN, VectorBaseStatStor, VectorInfo
+class Vector : public DataWrapVecVector, VectorBaseStatStor, VectorInfo
{
public:
/** The base implementation. */
@@ -2451,9 +2448,8 @@
* A vector of Average stats.
* @sa Stat, VectorBase, AvgStor
*/
-templateint N = 0
class AverageVector
-: public DataWrapVecAverageVectorN, VectorBaseAvgStor, VectorInfo
+: public DataWrapVecAverageVector, VectorBaseAvgStor, VectorInfo
{
public:
/**
@@ -2473,9 +2469,8 @@
* A 2-Dimensional vecto of scalar stats.
* @sa Stat, Vector2dBase, StatStor
*/
-templateint N = 0
class Vector2d
-: public DataWrapVec2dVector2dN, Vector2dBaseStatStor, Vector2dInfo
+: public DataWrapVec2dVector2d, Vector2dBaseStatStor, Vector2dInfo
{
public:
Vector2d
@@ -2490,9 +2485,8 @@
* A simple distribution stat.
* @sa Stat, DistBase, DistStor
*/
-templateint N = 0
class Distribution
-: public DataWrapDistributionN, DistBaseDistStor, DistInfo
+: public DataWrapDistribution, DistBaseDistStor, DistInfo
{
public:
/** Base implementation. */
@@ -2524,9 +2518,8 @@
* Calculates the mean and variance of all the samples.
* @sa Stat, DistBase, FancyStor
*/
-templateint N = 0
class StandardDeviation
-: public DataWrapStandardDeviationN, DistBaseFancyStor, DistInfo
+: public DataWrapStandardDeviation, DistBaseFancyStor, DistInfo
{
public:
/** The base implementation */
@@ -2546,9 +2539,8 @@
* Calculates the per tick mean and variance of the samples.
* @sa Stat, DistBase, AvgFancy
*/
-templateint N = 0
class AverageDeviation
-: public DataWrapAverageDeviationN, DistBaseAvgFancy, DistInfo
+: public DataWrapAverageDeviation, DistBaseAvgFancy, DistInfo
{
public:
/** The base implementation */
@@ -2568,9 +2560,8 @@
* A vector of distributions.
* @sa Stat, VectorDistBase, DistStor
*/
-templateint N = 0
class VectorDistribution
-: public DataWrapVecVectorDistributionN,
+: public DataWrapVecVectorDistribution,
VectorDistBaseDistStor,
VectorDistInfo
{
@@ -2605,9 +2596,8 @@
* This is a vector of StandardDeviation stats.
* @sa Stat, VectorDistBase, FancyStor
*/
-templateint N = 0
class VectorStandardDeviation
-: public DataWrapVecVectorStandardDeviationN,
+: public DataWrapVecVectorStandardDeviation,
VectorDistBaseFancyStor,
VectorDistInfo
{
@@ -2633,9 +2623,8 @@
* This is a vector of AverageDeviation stats.
* @sa Stat, VectorDistBase, AvgFancy
*/
-templateint N = 0
class VectorAverageDeviation
-: public DataWrapVecVectorAverageDeviationN,
+: public DataWrapVecVectorAverageDeviation,
VectorDistBaseAvgFancy,
VectorDistInfo
{
@@ -2828,8 +2817,7 @@
* Create a new ScalarStatNode.
* @param s The ScalarStat to place in a node.
*/
-template int N
-Temp(const ScalarN s)
+Temp(const Scalar s)
: node(new ScalarStatNode(s.info()))
{ }
@@ -2845,8 +2833,7 @@
* Create a new ScalarStatNode.
* @param s The ScalarStat to place in a node.
*/
-template int N
-Temp(const AverageN s)
+Temp(const Average s)
: node(new ScalarStatNode(s.info()))
{ }
@@ -2854,8 +2841,7 @@
* Create a new VectorStatNode.
* @param s The VectorStat to place in a node.
*/
-template int N
-Temp(const VectorN s)
+Temp(const Vector s)
: node(new VectorStatNode(s.info()))
{ }
___
m5-dev mailing list
[m5-dev] changeset in m5: stats: Fix all stats usages to deal with templa...
changeset 3cf8e71257e0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3cf8e71257e0
description:
stats: Fix all stats usages to deal with template fixes
diffstat:
50 files changed, 486 insertions(+), 486 deletions(-)
src/arch/alpha/kernel_stats.hh| 12 +--
src/arch/alpha/tlb.hh | 22 ++---
src/arch/mips/tlb.hh | 16 ++--
src/base/hybrid_pred.hh | 12 +--
src/base/sat_counter.hh | 12 +--
src/cpu/base.hh |2
src/cpu/inorder/cpu.hh| 14 +--
src/cpu/inorder/pipeline_stage.hh | 14 +--
src/cpu/inorder/resource.hh |2
src/cpu/inorder/resources/bpred_unit.hh | 16 ++--
src/cpu/inorder/resources/branch_predictor.hh |4 -
src/cpu/inorder/resources/execution_unit.hh |4 -
src/cpu/inorder/resources/inst_buffer.hh |2
src/cpu/inorder/resources/mult_div_unit.hh|4 -
src/cpu/memtest/memtest.hh|6 -
src/cpu/o3/bpred_unit.hh | 16 ++--
src/cpu/o3/commit.hh | 28 +++
src/cpu/o3/cpu.hh |8 +-
src/cpu/o3/decode.hh | 20 ++---
src/cpu/o3/fetch.hh | 24 +++---
src/cpu/o3/iew.hh | 54 +++---
src/cpu/o3/inst_queue.hh | 38 +-
src/cpu/o3/lsq_unit.hh| 20 ++---
src/cpu/o3/mem_dep_unit.hh|8 +-
src/cpu/o3/rename.hh | 38 +-
src/cpu/ozone/back_end.hh | 92 -
src/cpu/ozone/cpu.hh |4 -
src/cpu/ozone/front_end.hh| 40 +-
src/cpu/ozone/inorder_back_end.hh |2
src/cpu/ozone/inst_queue.hh | 32
src/cpu/ozone/lsq_unit.hh |2
src/cpu/ozone/lw_back_end.hh | 84 +++---
src/cpu/ozone/lw_lsq.hh |4 -
src/cpu/simple/base.hh| 14 +--
src/cpu/thread_state.hh |4 -
src/dev/copy_engine.hh|4 -
src/dev/etherdevice.hh| 64 -
src/dev/ide_disk.hh | 12 +--
src/dev/sinic.hh | 38 +-
src/kern/kernel_stats.hh | 16 ++--
src/mem/cache/base.hh | 32
src/mem/cache/prefetch/base.hh| 18 ++--
src/mem/cache/tags/base.hh| 10 +-
src/mem/cache/tags/fa_lru.hh |6 -
src/mem/cache/tags/iic.hh | 14 +--
src/mem/cache/tags/iic_repl/gen.hh|6 -
src/mem/dram.hh | 36 -
src/sim/faults.hh |2
src/sim/process.hh|2
src/unittest/stattest.cc | 38 +-
diffs (truncated from 1953 to 300 lines):
diff -r a4c935e9cf99 -r 3cf8e71257e0 src/arch/alpha/kernel_stats.hh
--- a/src/arch/alpha/kernel_stats.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/arch/alpha/kernel_stats.hhThu Mar 05 19:09:53 2009 -0800
@@ -62,15 +62,15 @@
void changeMode(cpu_mode newmode, ThreadContext *tc);
private:
-Stats::Vector _callpal;
-//Stats::Vector _faults;
+Stats::Vector _callpal;
+//Stats::Vector _faults;
-Stats::Vector _mode;
-Stats::Vector _modeGood;
+Stats::Vector _mode;
+Stats::Vector _modeGood;
Stats::Formula _modeFraction;
-Stats::Vector _modeTicks;
+Stats::Vector _modeTicks;
-Stats::Scalar _swap_context;
+Stats::Scalar _swap_context;
public:
Statistics(System *system);
diff -r a4c935e9cf99 -r 3cf8e71257e0 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Thu Mar 05 19:09:53 2009 -0800
+++ b/src/arch/alpha/tlb.hh Thu Mar 05 19:09:53 2009 -0800
@@ -121,9 +121,9 @@
class ITB : public TLB
{
protected:
-mutable Stats::Scalar hits;
-mutable Stats::Scalar misses;
-mutable Stats::Scalar acv;
+mutable Stats::Scalar hits;
+mutable Stats::Scalar misses;
+mutable Stats::Scalar acv;
mutable Stats::Formula accesses;
public:
@@ -139,14 +139,14 @@
class DTB : public TLB
{
protected:
-mutable Stats::Scalar read_hits;
-mutable Stats::Scalar read_misses;
-mutable Stats::Scalar read_acv;
-mutable Stats::Scalar read_accesses;
-mutable Stats::Scalar write_hits;
-mutable Stats::Scalar write_misses;
-mutable Stats::Scalar write_acv;
-mutable Stats::Scalar write_accesses;
+mutable Stats::Scalar read_hits;
+mutable Stats::Scalar read_misses;
+mutable Stats::Scalar read_acv;
+mutable Stats::Scalar
[m5-dev] changeset in m5: stats: clean up how templates are used on the d...
changeset 4f887be9e1b6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4f887be9e1b6
description:
stats: clean up how templates are used on the data side.
This basically works by taking advantage of the curiously recurring
template
pattern in an intelligent way so as to reduce the number of lines of
code
and hopefully make things a little bit clearer.
diffstat:
2 files changed, 326 insertions(+), 413 deletions(-)
src/base/statistics.cc | 100 +++
src/base/statistics.hh | 639
diffs (truncated from 1375 to 300 lines):
diff -r 3cf8e71257e0 -r 4f887be9e1b6 src/base/statistics.cc
--- a/src/base/statistics.ccThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.ccThu Mar 05 19:09:53 2009 -0800
@@ -158,7 +158,7 @@
bool
Info::baseCheck() const
{
-if (!(flags init)) {
+if (!(flags Stats::init)) {
#ifdef DEBUG
cprintf(this is stat number %d\n, id);
#endif
@@ -175,55 +175,6 @@
}
-void
-FormulaBase::result(VResult vec) const
-{
-if (root)
-vec = root-result();
-}
-
-Result
-FormulaBase::total() const
-{
-return root ? root-total() : 0.0;
-}
-
-size_type
-FormulaBase::size() const
-{
-if (!root)
-return 0;
-else
-return root-size();
-}
-
-void
-FormulaBase::reset()
-{
-}
-
-bool
-FormulaBase::zero() const
-{
-VResult vec;
-result(vec);
-for (off_t i = 0; i vec.size(); ++i)
-if (vec[i] != 0.0)
-return false;
-return true;
-}
-
-void
-FormulaBase::update(Info *)
-{
-}
-
-string
-FormulaBase::str() const
-{
-return root ? root-str() : ;
-}
-
Formula::Formula()
{
setInit();
@@ -256,6 +207,55 @@
}
void
+Formula::result(VResult vec) const
+{
+if (root)
+vec = root-result();
+}
+
+Result
+Formula::total() const
+{
+return root ? root-total() : 0.0;
+}
+
+size_type
+Formula::size() const
+{
+if (!root)
+return 0;
+else
+return root-size();
+}
+
+void
+Formula::reset()
+{
+}
+
+bool
+Formula::zero() const
+{
+VResult vec;
+result(vec);
+for (off_t i = 0; i vec.size(); ++i)
+if (vec[i] != 0.0)
+return false;
+return true;
+}
+
+void
+Formula::update()
+{
+}
+
+string
+Formula::str() const
+{
+return root ? root-str() : ;
+}
+
+void
check()
{
typedef listInfo *::iterator iter_t;
diff -r 3cf8e71257e0 -r 4f887be9e1b6 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -115,6 +115,14 @@
virtual ~Info();
/**
+ * Check that this stat has been set up properly and is ready for
+ * use
+ * @return true for success
+ */
+virtual bool check() const = 0;
+bool baseCheck() const;
+
+/**
* Reset the stat to the default state.
*/
virtual void reset() = 0;
@@ -126,14 +134,6 @@
virtual bool zero() const = 0;
/**
- * Check that this stat has been set up properly and is ready for
- * use
- * @return true for success
- */
-virtual bool check() const = 0;
-bool baseCheck() const;
-
-/**
* Visitor entry for outputing statistics data
*/
virtual void visit(Visit visitor) = 0;
@@ -187,8 +187,8 @@
{
public:
/** Names and descriptions of subfields. */
-mutable std::vectorstd::string subnames;
-mutable std::vectorstd::string subdescs;
+std::vectorstd::string subnames;
+std::vectorstd::string subdescs;
public:
virtual size_type size() const = 0;
@@ -242,7 +242,7 @@
visit(Visit visitor)
{
this-update();
-this-s.update(this);
+this-s.update();
visitor.visit(*this);
}
};
@@ -275,7 +275,7 @@
void
visit(Visit visitor)
{
-this-s.update(this);
+this-s.update();
visitor.visit(*this);
}
};
@@ -285,9 +285,9 @@
public:
std::vectorDistData data;
- /** Names and descriptions of subfields. */
-mutable std::vectorstd::string subnames;
-mutable std::vectorstd::string subdescs;
+/** Names and descriptions of subfields. */
+std::vectorstd::string subnames;
+std::vectorstd::string subdescs;
protected:
/** Local storage for the entry values, used for printing. */
@@ -320,7 +320,7 @@
visit(Visit visitor)
{
this-update();
-this-s.update(this);
+this-s.update();
visitor.visit(*this);
}
};
@@ -333,10 +333,11 @@
std::vectorstd::string subdescs;
std::vectorstd::string y_subnames;
+size_type x;
+size_type y;
+
/** Local storage for the entry values, used for printing. */
mutable VCounter cvec;
-mutable size_type x;
-mutable size_type y;
public:
void
@@ -357,7 +358,7 @@
visit(Visit visitor)
{
this-update();
-this-s.update(this);
+this-s.update();
[m5-dev] changeset in m5: stats: create an enable phase, and a prepare ph...
changeset 00251eb95de7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=00251eb95de7
description:
stats: create an enable phase, and a prepare phase.
Enable more or less takes the place of check, but also allows stats to
do some other configuration. Prepare moves all of the code that readies
a stat for dumping into a separate function in preparation for
supporting
serialization of certain pieces of statistics data.
While we're at it, clean up the visitor code and some of the python
code.
diffstat:
7 files changed, 215 insertions(+), 162 deletions(-)
src/base/statistics.cc| 67 ---
src/base/statistics.hh| 264 +
src/base/stats/output.cc |3
src/python/m5/core.py |7 +
src/python/m5/simulate.py | 14 +-
src/python/m5/stats.py| 19 ++-
src/python/swig/stats.i |3
diffs (truncated from 758 to 300 lines):
diff -r 4f887be9e1b6 -r 00251eb95de7 src/base/statistics.cc
--- a/src/base/statistics.ccThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.ccThu Mar 05 19:09:53 2009 -0800
@@ -32,6 +32,7 @@
#include fstream
#include list
#include map
+#include set
#include string
#include base/callback.hh
@@ -174,6 +175,41 @@
return true;
}
+void
+Info::enable()
+{
+}
+
+void
+VectorInfoBase::enable()
+{
+size_type s = size();
+if (subnames.size() s)
+subnames.resize(s);
+if (subdescs.size() s)
+subdescs.resize(s);
+}
+
+void
+VectorDistInfoBase::enable()
+{
+size_type s = size();
+if (subnames.size() s)
+subnames.resize(s);
+if (subdescs.size() s)
+subdescs.resize(s);
+}
+
+void
+Vector2dInfoBase::enable()
+{
+if (subnames.size() x)
+subnames.resize(x);
+if (subdescs.size() x)
+subdescs.resize(x);
+if (y_subnames.size() y)
+y_subnames.resize(y);
+}
Formula::Formula()
{
@@ -244,11 +280,6 @@
return true;
}
-void
-Formula::update()
-{
-}
-
string
Formula::str() const
{
@@ -256,7 +287,7 @@
}
void
-check()
+enable()
{
typedef listInfo *::iterator iter_t;
@@ -277,17 +308,21 @@
statsList().sort(Info::less);
-if (i == end)
-return;
+for (i = statsList().begin(); i != end; ++i) {
+Info *info = *i;
+info-enable();
+}
+}
-iter_t last = i;
-++i;
-
-for (i = statsList().begin(); i != end; ++i) {
-if ((*i)-name == (*last)-name)
-panic(same name used twice! name=%s\n, (*i)-name);
-
-last = i;
+void
+prepare()
+{
+listInfo *::iterator i = statsList().begin();
+listInfo *::iterator end = statsList().end();
+while (i != end) {
+Info *info = *i;
+info-prepare();
+++i;
}
}
diff -r 4f887be9e1b6 -r 00251eb95de7 src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
@@ -123,6 +123,16 @@
bool baseCheck() const;
/**
+ * Enable the stat for use
+ */
+virtual void enable();
+
+/**
+ * Prepare the stat for dumping.
+ */
+virtual void prepare() = 0;
+
+/**
* Reset the stat to the default state.
*/
virtual void reset() = 0;
@@ -159,7 +169,13 @@
InfoWrap(Stat stat) : s(stat) {}
bool check() const { return s.check(); }
+void prepare() { s.prepare(); }
void reset() { s.reset(); }
+void
+visit(Visit visitor)
+{
+visitor.visit(*static_castBase *(this));
+}
bool zero() const { return s.zero(); }
};
@@ -169,7 +185,6 @@
virtual Counter value() const = 0;
virtual Result result() const = 0;
virtual Result total() const = 0;
-void visit(Visit visitor) { visitor.visit(*this); }
};
template class Stat
@@ -191,23 +206,13 @@
std::vectorstd::string subdescs;
public:
+void enable();
+
+ public:
virtual size_type size() const = 0;
virtual const VCounter value() const = 0;
virtual const VResult result() const = 0;
virtual Result total() const = 0;
-
-void
-update()
-{
-if (!subnames.empty()) {
-size_type s = size();
-if (subnames.size() s)
-subnames.resize(s);
-
-if (subdescs.size() s)
-subdescs.resize(s);
-}
-}
};
template class Stat
@@ -237,14 +242,6 @@
}
Result total() const { return this-s.total(); }
-
-void
-visit(Visit visitor)
-{
-this-update();
-this-s.update();
-visitor.visit(*this);
-}
};
struct DistData
@@ -271,13 +268,6 @@
{
public:
DistInfo(Stat stat) : InfoWrapStat, DistInfoBase(stat) {}
-
-void
-visit(Visit visitor)
-{
-this-s.update();
-visitor.visit(*this);
-}
};
class VectorDistInfoBase : public Info
@@ -288,6 +278,7 @@
/** Names and descriptions of
Re: [m5-dev] changeset in m5: stats: remove the template wart left over from ...
Just so everyone knows, this change fixes an old problem with the
template stuff left over from the binning days (for those of you that
remember). The thing that changes for people as a result is that the
name of the stat Classes has slightly changed.
We used to say things like
Stats::Scalar
Stats::Vector
These should now just be:
Stats::Scalar
Stats::Vector
You're simply removing the which was totally useless anyway.
Nate
On Thu, Mar 5, 2009 at 7:11 PM, Nathan Binkert n...@binkert.org wrote:
changeset a4c935e9cf99 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a4c935e9cf99
description:
stats: remove the template wart left over from the ancient binning
stuff
diffstat:
1 file changed, 14 insertions(+), 28 deletions(-)
src/base/statistics.hh | 42 ++
diffs (151 lines):
diff -r 471090ec173e -r a4c935e9cf99 src/base/statistics.hh
--- a/src/base/statistics.hh Thu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hh Thu Mar 05 19:09:53 2009 -0800
@@ -2350,8 +2350,7 @@
* This is a simple scalar statistic, like a counter.
* @sa Stat, ScalarBase, StatStor
*/
-templateint N = 0
-class Scalar : public DataWrapScalarN, ScalarBaseStatStor, ScalarInfo
+class Scalar : public DataWrapScalar, ScalarBaseStatStor, ScalarInfo
{
public:
/** The base implementation. */
@@ -2398,8 +2397,7 @@
* A stat that calculates the per tick average of a value.
* @sa Stat, ScalarBase, AvgStor
*/
-templateint N = 0
-class Average : public DataWrapAverageN, ScalarBaseAvgStor, ScalarInfo
+class Average : public DataWrapAverage, ScalarBaseAvgStor, ScalarInfo
{
public:
/** The base implementation. */
@@ -2427,8 +2425,7 @@
* A vector of scalar stats.
* @sa Stat, VectorBase, StatStor
*/
-templateint N = 0
-class Vector : public DataWrapVecVectorN, VectorBaseStatStor,
VectorInfo
+class Vector : public DataWrapVecVector, VectorBaseStatStor, VectorInfo
{
public:
/** The base implementation. */
@@ -2451,9 +2448,8 @@
* A vector of Average stats.
* @sa Stat, VectorBase, AvgStor
*/
-templateint N = 0
class AverageVector
- : public DataWrapVecAverageVectorN, VectorBaseAvgStor, VectorInfo
+ : public DataWrapVecAverageVector, VectorBaseAvgStor, VectorInfo
{
public:
/**
@@ -2473,9 +2469,8 @@
* A 2-Dimensional vecto of scalar stats.
* @sa Stat, Vector2dBase, StatStor
*/
-templateint N = 0
class Vector2d
- : public DataWrapVec2dVector2dN, Vector2dBaseStatStor, Vector2dInfo
+ : public DataWrapVec2dVector2d, Vector2dBaseStatStor, Vector2dInfo
{
public:
Vector2d
@@ -2490,9 +2485,8 @@
* A simple distribution stat.
* @sa Stat, DistBase, DistStor
*/
-templateint N = 0
class Distribution
- : public DataWrapDistributionN, DistBaseDistStor, DistInfo
+ : public DataWrapDistribution, DistBaseDistStor, DistInfo
{
public:
/** Base implementation. */
@@ -2524,9 +2518,8 @@
* Calculates the mean and variance of all the samples.
* @sa Stat, DistBase, FancyStor
*/
-templateint N = 0
class StandardDeviation
- : public DataWrapStandardDeviationN, DistBaseFancyStor, DistInfo
+ : public DataWrapStandardDeviation, DistBaseFancyStor, DistInfo
{
public:
/** The base implementation */
@@ -2546,9 +2539,8 @@
* Calculates the per tick mean and variance of the samples.
* @sa Stat, DistBase, AvgFancy
*/
-templateint N = 0
class AverageDeviation
- : public DataWrapAverageDeviationN, DistBaseAvgFancy, DistInfo
+ : public DataWrapAverageDeviation, DistBaseAvgFancy, DistInfo
{
public:
/** The base implementation */
@@ -2568,9 +2560,8 @@
* A vector of distributions.
* @sa Stat, VectorDistBase, DistStor
*/
-templateint N = 0
class VectorDistribution
- : public DataWrapVecVectorDistributionN,
+ : public DataWrapVecVectorDistribution,
VectorDistBaseDistStor,
VectorDistInfo
{
@@ -2605,9 +2596,8 @@
* This is a vector of StandardDeviation stats.
* @sa Stat, VectorDistBase, FancyStor
*/
-templateint N = 0
class VectorStandardDeviation
- : public DataWrapVecVectorStandardDeviationN,
+ : public DataWrapVecVectorStandardDeviation,
VectorDistBaseFancyStor,
VectorDistInfo
{
@@ -2633,9 +2623,8 @@
* This is a vector of AverageDeviation stats.
* @sa Stat, VectorDistBase, AvgFancy
*/
-templateint N = 0
class VectorAverageDeviation
- : public DataWrapVecVectorAverageDeviationN,
+ : public DataWrapVecVectorAverageDeviation,
VectorDistBaseAvgFancy,
VectorDistInfo
{
@@ -2828,8 +2817,7 @@
* Create a new ScalarStatNode.
* @param s The ScalarStat to place in a node.
*/
- template int N
- Temp(const ScalarN s)
+ Temp(const Scalar s)
: node(new ScalarStatNode(s.info
Re: [m5-dev] locked memory accesses
Here's another option: make the CPU model smart and when it sees a lock access have it keep running until it sees an unlock access. This might not be too bad if keep running could be implemented simply by doing something like a recursive tail call to tick(). There's already a big loop in the tick() function to simulate a cpu width (so we can set a low CPU frequency, but get a high instruction rate for rate matching). I'd rather see something like the for loop being changed into a while loop, and do a i++ or something like that to keep it going. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
How different are ITBs and DTBs anyway? It seems like for a UTB you'd want a single object that handles both ifetch and data translations using a common translate() method, not something that inherits from two different classes. E.g., why not just derive it from TLB? The two translation functions are different because every ISA does some different things for instructions vs data. Think about something like the executable bit. Philosophically, I agree... let's avoid virtual inheritance if at all possible. It's just not a good idea. Ok, so the question is, which of the other alternatives should we do? Gabe (mister TLB expert)? Korey (since this is mips code)? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
I'll keep both pointers then. I have all the non-ISA bits and X86 converted and I'm trying to test it, but I'm running into a compile error in the stats stuff. Nate? cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' You have a VectorDistribution stat somewhere, and you're calling its init() function with the first parameter as a float instead of an integer. Nothing magic here, just apply normal debugging techniques. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
That's odd... if it doesn't work that way, I'd consider that a bug. On Fri, Mar 6, 2009 at 10:18 AM, Gabe Black gbl...@eecs.umich.edu wrote: I tried something like this before, and I don't think it works because self.dtb is a paramdesc, not a SparcTLB. What Nate told me to do was to instantiate those objects as regular members first I believe. This was the SouthBridge stuff. I can't remember your specific situation, but I believe that it was special. If you can remind us (or just dig up the title on the e-mail thread), we can see if we can fix it. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
I'll try to figure this out, but I don't get it yet. I'll get an older compiler going... Nate On Fri, Mar 6, 2009 at 10:48 AM, Gabe Black gbl...@eecs.umich.edu wrote: I'm heading out the door, but I just tried building X86_SE on the head and it gave me the errors. I didn't think my changes caused them. I have similar problems with ALPHA_SE, and I haven't tried any other targets. gbl...@tater ~/m5/repos/m5.x86fs $ gcc -v Using built-in specs. Target: x86_64-pc-linux-gnu Configured with: /var/tmp/portage/sys-devel/gcc-4.1.2/work/gcc-4.1.2/configure --prefix=/usr --bindir=/usr/x86_64-pc-linux-gnu/gcc-bin/4.1.2 --includedir=/usr/lib/gcc/x86_64-pc-linux-gnu/4.1.2/include --datadir=/usr/share/gcc-data/x86_64-pc-linux-gnu/4.1.2 --mandir=/usr/share/gcc-data/x86_64-pc-linux-gnu/4.1.2/man --infodir=/usr/share/gcc-data/x86_64-pc-linux-gnu/4.1.2/info --with-gxx-include-dir=/usr/lib/gcc/x86_64-pc-linux-gnu/4.1.2/include/g++-v4 --host=x86_64-pc-linux-gnu --build=x86_64-pc-linux-gnu --disable-altivec --enable-nls --without-included-gettext --with-system-zlib --disable-checking --disable-werror --enable-secureplt --enable-multilib --enable-libmudflap --disable-libssp --enable-java-awt=gtk --enable-languages=c,c++,java,treelang,fortran --enable-shared --enable-threads=posix --enable-__cxa_atexit --enable-clocale=gnu Thread model: posix gcc version 4.1.2 (Gentoo 4.1.2 p1.1) gbl...@tater ~/m5/repos/m5.x86fs $ python -V Python 2.5.2 gbl...@tater ~/m5/repos/m5.x86fs $ swig -version SWIG Version 1.3.36 Compiled with x86_64-pc-linux-gnu-g++ [x86_64-pc-linux-gnu] Please see http://www.swig.org for reporting bugs and further information gbl...@tater ~/m5/repos/m5.x86fs $ scons -v SCons by Steven Knight et al.: script: v1.0.0.r3266, 2008/08/12 07:31:01, by knight on bangkok engine: v1.0.0.r3266, 2008/08/12 07:31:01, by knight on bangkok Copyright (c) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 The SCons Foundation cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' scons: *** [build/X86_SE/cpu/pc_event.o] Error 1 cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' scons: *** [build/X86_SE/cpu/thread_context.o] Error 1 cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' Steve Reinhardt wrote: On Fri, Mar 6, 2009 at 10:19 AM, Gabe Black gbl...@eecs.umich.edu wrote: nathan binkert wrote: You have a VectorDistribution stat somewhere, and you're calling its init() function with the first parameter as a float instead of an integer. Nothing magic here, just apply normal debugging
Re: [m5-dev] scons weirdness
1. Diff the outputs and set the pass/fail status based on the result. 2. Declare the test's status as failed regardless of the outputs but consider the job of running the test as completed successfully. The test will not be re-run unless some dependence changes (like one that causes the m5 binary to get rebuilt). 3. Consider the job of running the test as unsuccessful and don't generate a pass/fail status. This will cause scons to terminate unless you've used -k, and the test to be re-run if your re-run scons. 4. Terminate scons unconditionally by calling scons's Exit() function. Here's my current plan: 1. Only when m5's exit status is 0. 2. When m5 has a normal (non-signal) but non-zero exit, or is terminated by a signal other than the ones listed in #3. 3. When m5 is terminated by SIGTERM, SIGINT, SIGKILL, SIGHUP, or SIGQUIT. 4. Never. This all sounds great. I've got some test framework stuff in the works that should make adding tests and picking subsets of tests to run a lot easier. Questions: - Do I have the right list of signals in #3 to distinguish premature termination from m5 program errors? I think so. - Is there any reason for SIGTERM et al (or some subset of them) to cause #4 instead of #3? Hard to say. I never use -k with tests (only when trying to get through compiler stuff), but I generally hate when programs don't terminate on SIGINT (Ctrl-C). Of course, I could just not ask for any tests to run when using -k and it wouldn't be a problem. Then again, a quick succession of SIGINTs will probably still terminate the program since SCons itself might catch one of them. Then again, if SCons forks a subprocess, but you send a CTRL-C to the terminal, who gets it? I honestly don't remember. In the shell, it would go to whatever process is currently running, but I think that in that case, the shell might actually be forwarding the signal. So, would python (scons) get it, or m5? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: build: fix errors for compilers other than g++ 4.3
changeset 7d75f1a525db in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7d75f1a525db
description:
build: fix errors for compilers other than g++ 4.3
diffstat:
2 files changed, 2 insertions(+), 2 deletions(-)
src/base/cp_annotate.hh |2 +-
src/base/statistics.hh |2 +-
diffs (24 lines):
diff -r 00251eb95de7 -r 7d75f1a525db src/base/cp_annotate.hh
--- a/src/base/cp_annotate.hh Thu Mar 05 19:09:53 2009 -0800
+++ b/src/base/cp_annotate.hh Sat Mar 07 14:30:52 2009 -0800
@@ -53,7 +53,7 @@
#if !CP_ANNOTATE
-class CPA : SimObject
+class CPA
{
public:
enum flags {
diff -r 00251eb95de7 -r 7d75f1a525db src/base/statistics.hh
--- a/src/base/statistics.hhThu Mar 05 19:09:53 2009 -0800
+++ b/src/base/statistics.hhSat Mar 07 14:30:52 2009 -0800
@@ -2495,7 +2495,7 @@
params-min = min;
params-max = max;
params-bucket_size = bkt;
-params-buckets = rint((max - min) / bkt + 1.0);
+params-buckets = (size_type)rint((max - min) / bkt + 1.0);
this-setParams(params);
this-doInit(size);
return this-self();
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: scons: fix the library path stuff
changeset 8f374fd9a348 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8f374fd9a348
description:
scons: fix the library path stuff
diffstat:
1 file changed, 3 insertions(+), 3 deletions(-)
SConstruct |6 +++---
diffs (30 lines):
diff -r 7d75f1a525db -r 8f374fd9a348 SConstruct
--- a/SConstructSat Mar 07 14:30:52 2009 -0800
+++ b/SConstructSat Mar 07 14:30:52 2009 -0800
@@ -161,7 +161,8 @@
# Set up the base build environment.
#
-use_vars = set([ 'AS', 'AR', 'CC', 'CXX', 'HOME', 'PATH', 'RANLIB' ])
+use_vars = set([ 'AS', 'AR', 'CC', 'CXX', 'HOME', 'LD_LIBRARY_PATH', 'PATH',
+ 'RANLIB' ])
use_env = {}
for key,val in os.environ.iteritems():
@@ -550,7 +551,7 @@
if py_platform_include != py_general_include:
py_includes.append(py_platform_include)
-py_lib_path = []
+py_lib_path = [ py_getvar('LIBDIR') ]
# add the prefix/lib/pythonX.Y/config dir, but only if there is no
# shared library in prefix/lib/.
if not py_getvar('Py_ENABLE_SHARED'):
@@ -564,7 +565,6 @@
env.Append(CPPPATH=py_includes)
env.Append(LIBPATH=py_lib_path)
-#env.Append(LIBS=py_libs)
# verify that this stuff works
if not conf.CheckHeader('Python.h', ''):
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: cleanup text output stuff and fix mysql ...
changeset 97660425ff39 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=97660425ff39
description:
stats: cleanup text output stuff and fix mysql output
diffstat:
4 files changed, 105 insertions(+), 123 deletions(-)
src/base/statistics.hh | 37 +-
src/base/stats/mysql.cc | 15 ++--
src/base/stats/mysql.hh |3
src/base/stats/text.cc | 173 +++
diffs (truncated from 439 to 300 lines):
diff -r 8f374fd9a348 -r 97660425ff39 src/base/statistics.hh
--- a/src/base/statistics.hhSat Mar 07 14:30:52 2009 -0800
+++ b/src/base/statistics.hhSat Mar 07 14:30:53 2009 -0800
@@ -1423,6 +1423,22 @@
//
//
+struct DistParams : public StorageParams
+{
+const bool fancy;
+
+/** The minimum value to track. */
+Counter min;
+/** The maximum value to track. */
+Counter max;
+/** The number of entries in each bucket. */
+Counter bucket_size;
+/** The number of buckets. Equal to (max-min)/bucket_size. */
+size_type buckets;
+
+explicit DistParams(bool f) : fancy(f) {}
+};
+
/**
* Templatized storage and interface for a distrbution stat.
*/
@@ -1430,18 +1446,9 @@
{
public:
/** The parameters for a distribution stat. */
-struct Params : public StorageParams
+struct Params : public DistParams
{
-/** The minimum value to track. */
-Counter min;
-/** The maximum value to track. */
-Counter max;
-/** The number of entries in each bucket. */
-Counter bucket_size;
-/** The number of buckets. Equal to (max-min)/bucket_size. */
-size_type buckets;
-
-enum { fancy = false };
+Params() : DistParams(false) {}
};
private:
@@ -1578,9 +1585,9 @@
class FancyStor
{
public:
-struct Params : public StorageParams
+struct Params : public DistParams
{
-enum { fancy = true };
+Params() : DistParams(true) {}
};
private:
@@ -1654,9 +1661,9 @@
class AvgFancy
{
public:
-struct Params : public StorageParams
+struct Params : public DistParams
{
-enum { fancy = true };
+Params() : DistParams(true) {}
};
private:
diff -r 8f374fd9a348 -r 97660425ff39 src/base/stats/mysql.cc
--- a/src/base/stats/mysql.cc Sat Mar 07 14:30:52 2009 -0800
+++ b/src/base/stats/mysql.cc Sat Mar 07 14:30:53 2009 -0800
@@ -583,7 +583,8 @@
if (!configure(info, DIST))
return;
-const Params *params = safe_castconst Params *(info.storageParams);
+const DistParams *params =
+safe_castconst DistParams *(info.storageParams);
if (!params-fancy) {
stat.size = params-buckets;
stat.min = params-min;
@@ -599,7 +600,8 @@
if (!configure(info, VECTORDIST))
return;
-const Params *params = safe_castconst Params *(info.storageParams);
+const DistParams *params =
+safe_castconst DistParams *(info.storageParams);
if (!params-fancy) {
stat.size = params-buckets;
stat.min = params-min;
@@ -765,7 +767,7 @@
}
void
-MySql::output(const DistData data)
+MySql::output(const DistData data, const DistParams *params)
{
const int db_sum = -1;
const int db_squares = -2;
@@ -787,7 +789,7 @@
newdata.data = data.samples;
newdata.insert();
-if (data.samples !data.fancy) {
+if (data.samples !params-fancy) {
newdata.x = db_min_val;
newdata.data = data.min_val;
newdata.insert();
@@ -821,7 +823,7 @@
newdata.stat = find(info.id);
newdata.y = 0;
-output(info.data);
+output(info.data, safe_castconst DistParams *(info.storageParams));
}
void
@@ -835,7 +837,8 @@
size_type size = info.data.size();
for (off_type y = 0; y size; ++y) {
newdata.y = y;
-output(info.data[y]);
+output(info.data[y],
+ safe_castconst DistParams *(info.storageParams));
}
}
diff -r 8f374fd9a348 -r 97660425ff39 src/base/stats/mysql.hh
--- a/src/base/stats/mysql.hh Sat Mar 07 14:30:52 2009 -0800
+++ b/src/base/stats/mysql.hh Sat Mar 07 14:30:53 2009 -0800
@@ -56,6 +56,7 @@
bool total;
bool pdf;
bool cdf;
+
double min;
double max;
double bktsize;
@@ -177,7 +178,7 @@
void output(const VectorDistInfoBase info);
void output(const Vector2dInfoBase info);
void output(const FormulaInfoBase info);
-void output(const DistData data);
+void output(const DistData data, const DistParams *params);
void configure();
bool configure(const Info info, std::string type);
diff -r 8f374fd9a348 -r 97660425ff39 src/base/stats/text.cc
--- a/src/base/stats/text.ccSat Mar 07 14:30:52 2009 -0800
+++ b/src/base/stats/text.ccSat Mar 07 14:30:53 2009 -0800
@@ -351,27 +351,63 @@
bool descriptions;
int precision;
-Result min_val;
-Result
[m5-dev] changeset in m5: stats: fix duplicate statistics names.
changeset 1dc178e53487 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1dc178e53487
description:
stats: fix duplicate statistics names.
This generally requires providing a more meaningful name() function for
a
class.
diffstat:
4 files changed, 29 insertions(+), 25 deletions(-)
src/cpu/o3/bpred_unit.hh|4
src/cpu/o3/bpred_unit_impl.hh | 23 ---
src/cpu/o3/mem_dep_unit.hh |8 ++--
src/cpu/o3/mem_dep_unit_impl.hh | 19 +++
diffs (172 lines):
diff -r 97660425ff39 -r 1dc178e53487 src/cpu/o3/bpred_unit.hh
--- a/src/cpu/o3/bpred_unit.hh Sat Mar 07 14:30:53 2009 -0800
+++ b/src/cpu/o3/bpred_unit.hh Sat Mar 07 14:30:54 2009 -0800
@@ -62,6 +62,8 @@
PredType predictor;
+const std::string _name;
+
public:
/**
@@ -69,6 +71,8 @@
*/
BPredUnit(DerivO3CPUParams *params);
+const std::string name() const { return _name; }
+
/**
* Registers statistics.
*/
diff -r 97660425ff39 -r 1dc178e53487 src/cpu/o3/bpred_unit_impl.hh
--- a/src/cpu/o3/bpred_unit_impl.hh Sat Mar 07 14:30:53 2009 -0800
+++ b/src/cpu/o3/bpred_unit_impl.hh Sat Mar 07 14:30:54 2009 -0800
@@ -38,9 +38,10 @@
templateclass Impl
BPredUnitImpl::BPredUnit(DerivO3CPUParams *params)
- : BTB(params-BTBEntries,
-params-BTBTagSize,
-params-instShiftAmt)
+: _name(params-name + .BPredUnit),
+ BTB(params-BTBEntries,
+ params-BTBTagSize,
+ params-instShiftAmt)
{
// Setup the selected predictor.
if (params-predType == local) {
@@ -73,43 +74,43 @@
BPredUnitImpl::regStats()
{
lookups
-.name(name() + .BPredUnit.lookups)
+.name(name() + .lookups)
.desc(Number of BP lookups)
;
condPredicted
-.name(name() + .BPredUnit.condPredicted)
+.name(name() + .condPredicted)
.desc(Number of conditional branches predicted)
;
condIncorrect
-.name(name() + .BPredUnit.condIncorrect)
+.name(name() + .condIncorrect)
.desc(Number of conditional branches incorrect)
;
BTBLookups
-.name(name() + .BPredUnit.BTBLookups)
+.name(name() + .BTBLookups)
.desc(Number of BTB lookups)
;
BTBHits
-.name(name() + .BPredUnit.BTBHits)
+.name(name() + .BTBHits)
.desc(Number of BTB hits)
;
BTBCorrect
-.name(name() + .BPredUnit.BTBCorrect)
+.name(name() + .BTBCorrect)
.desc(Number of correct BTB predictions (this stat may not
work properly.)
;
usedRAS
-.name(name() + .BPredUnit.usedRAS)
+.name(name() + .usedRAS)
.desc(Number of times the RAS was used to get a target.)
;
RASIncorrect
-.name(name() + .BPredUnit.RASInCorrect)
+.name(name() + .RASInCorrect)
.desc(Number of incorrect RAS predictions.)
;
}
diff -r 97660425ff39 -r 1dc178e53487 src/cpu/o3/mem_dep_unit.hh
--- a/src/cpu/o3/mem_dep_unit.hhSat Mar 07 14:30:53 2009 -0800
+++ b/src/cpu/o3/mem_dep_unit.hhSat Mar 07 14:30:54 2009 -0800
@@ -65,7 +65,11 @@
* dependence prediction schemes.
*/
template class MemDepPred, class Impl
-class MemDepUnit {
+class MemDepUnit
+{
+ protected:
+std::string _name;
+
public:
typedef typename Impl::DynInstPtr DynInstPtr;
@@ -79,7 +83,7 @@
~MemDepUnit();
/** Returns the name of the memory dependence unit. */
-std::string name() const;
+std::string name() const { return _name; }
/** Initializes the unit with parameters and a thread id. */
void init(DerivO3CPUParams *params, int tid);
diff -r 97660425ff39 -r 1dc178e53487 src/cpu/o3/mem_dep_unit_impl.hh
--- a/src/cpu/o3/mem_dep_unit_impl.hh Sat Mar 07 14:30:53 2009 -0800
+++ b/src/cpu/o3/mem_dep_unit_impl.hh Sat Mar 07 14:30:54 2009 -0800
@@ -44,7 +44,8 @@
template class MemDepPred, class Impl
MemDepUnitMemDepPred, Impl::MemDepUnit(DerivO3CPUParams *params)
-: depPred(params-SSITSize, params-LFSTSize), loadBarrier(false),
+: _name(params-name + .memdepunit),
+ depPred(params-SSITSize, params-LFSTSize), loadBarrier(false),
loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
{
DPRINTF(MemDepUnit, Creating MemDepUnit object.\n);
@@ -76,18 +77,12 @@
}
template class MemDepPred, class Impl
-std::string
-MemDepUnitMemDepPred, Impl::name() const
-{
-return memdepunit;
-}
-
-template class MemDepPred, class Impl
void
MemDepUnitMemDepPred, Impl::init(DerivO3CPUParams *params, int tid)
{
DPRINTF(MemDepUnit, Creating MemDepUnit %i object.\n,tid);
+_name = csprintf(%s.memDep%d, params-name, tid);
id = tid;
depPred.init(params-SSITSize, params-LFSTSize);
@@ -98,19 +93,19 @@
MemDepUnitMemDepPred, Impl::regStats()
{
insertedLoads
-.name(name() +
[m5-dev] changeset in m5: tests: update tests because of changes in stat ...
changeset 5437d5f54973 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=5437d5f54973 description: tests: update tests because of changes in stat names and in the stats package diffstat: 26 files changed, 663 insertions(+), 619 deletions(-) tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout| 10 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 64 ++-- tests/long/00.gzip/ref/sparc/linux/o3-timing/simout| 10 tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 64 ++-- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout| 10 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 120 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 10 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 64 ++-- tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 10 tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 64 ++-- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout | 10 tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 64 ++-- tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 10 tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 64 ++-- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 10 tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt| 64 ++-- tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout | 10 tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt| 64 ++-- tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 10 tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 128 - tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout | 10 tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 128 - tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout | 10 tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt| 136 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout | 10 tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt| 128 - diffs (truncated from 1828 to 300 lines): diff -r 1dc178e53487 -r 5437d5f54973 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Sat Mar 07 14:30:54 2009 -0800 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Sat Mar 07 14:30:55 2009 -0800 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Feb 16 2009 00:22:05 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:27:51 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing +M5 compiled Mar 6 2009 18:15:46 +M5 revision c619bb0f8f4f 6005 default qtip stats_duplicates.diff tip +M5 started Mar 6 2009 18:15:58 +M5 executing on maize +command line: /n/blue/z/binkert/build/work/build/ALPHA_SE/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 1dc178e53487 -r 5437d5f54973 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txtSat Mar 07 14:30:54 2009 -0800 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txtSat Mar 07 14:30:55 2009 -0800 @@ -1,25 +1,21 @@ -- Begin Simulation Statistics -- -global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 65718859 # Number of BTB hits -global.BPredUnit.BTBLookups 73181368 # Number of BTB lookups -global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect4206850 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted -global.BPredUnit.lookups 76039018 # Number of BP lookups -global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. -host_inst_rate 244512 # Simulator instruction rate (inst/s) -host_mem_usage 204148 #
Re: [m5-dev] scons weirdness
OK, well I just unintentionally found that scons doesn't reliably terminate on ^C even outside of the regressions (like when compiling or doing the autoconf stuff) so sticking with the current plan is at least no worse than that. Really? I don't recall ever really having that problem. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: Fix up regression execution to better handle te...
@@ -29,10 +29,18 @@
import os
from os.path import isdir, isfile, join as joinpath
-homedir = os.environ['HOME']
-confdir = os.environ.get('M5_CONFIG', joinpath(homedir, '.m5'))
+
+confdir = os.environ.get('M5_CONFIG')
+
+if not confdir:
+ # HOME is not set when running regressions, due to use of scons
+ # Execute() function.
Can you explain this a little bit better? Who is not setting HOME?
Is it actually SCons, or is it util/regress, or is it cron?
If it is actually SCons, is there not some way that you can pass in
the home directory? does env.Execute do the right thing?
+ homedir = os.environ.get('HOME')
+ if homedir and isdir(joinpath(homedir, '.m5')):
+ confdir = joinpath(homedir, '.m5')
+
def get(name):
- if not isdir(confdir):
+ if not confdir:
return None
conffile = joinpath(confdir, name)
if not isfile(conffile):
+# List of signals that indicate that we should retry the test rather
+# than consider it failed.
+retry_signals = (signal.SIGTERM, signal.SIGKILL, signal.SIGINT,
+ signal.SIGQUIT, signal.SIGHUP)
No big deal here, but don't forget that we can use frozenset() since
we have a floor of python2.4.
diff -r 5437d5f54973 -r e0344c15e73b tests/run.py
--- a/tests/run.py Sat Mar 07 14:30:55 2009 -0800
+++ b/tests/run.py Sat Mar 07 16:58:51 2009 -0800
@@ -34,7 +34,7 @@
m5.disableAllListeners()
# single path arg encodes everything we need to know about test
-(category, name, isa, opsys, config) = sys.argv[1].split('/')
+(category, name, isa, opsys, config) = sys.argv[1].split('/')[-5:]
What's the deal here? What was getting prepended?
Nate
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: build: fix compiler warnings in g++ 3.4
changeset 74bc713c71ce in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=74bc713c71ce
description:
build: fix compiler warnings in g++ 3.4
diffstat:
1 file changed, 11 insertions(+), 11 deletions(-)
src/arch/x86/faults.hh | 22 +++---
diffs (60 lines):
diff -r fb50ea61a226 -r 74bc713c71ce src/arch/x86/faults.hh
--- a/src/arch/x86/faults.hhSat Mar 07 17:24:13 2009 -0800
+++ b/src/arch/x86/faults.hhSat Mar 07 21:34:50 2009 -0800
@@ -76,9 +76,9 @@
uint64_t errorCode;
X86FaultBase(const char * _faultName, const char * _mnem,
-const uint8_t _vector, uint64_t _errorCode = -1) :
-faultName(_faultName), mnem(_mnem),
-vector(_vector), errorCode(_errorCode)
+ const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
+: faultName(_faultName), mnem(_mnem),
+ vector(_vector), errorCode(_errorCode)
{
}
@@ -115,8 +115,8 @@
{
protected:
X86Fault(const char * name, const char * mnem,
-const uint8_t vector, uint64_t _errorCode = -1) :
-X86FaultBase(name, mnem, vector, _errorCode)
+ const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
+: X86FaultBase(name, mnem, vector, _errorCode)
{}
};
@@ -126,8 +126,8 @@
{
protected:
X86Trap(const char * name, const char * mnem,
-const uint8_t vector, uint64_t _errorCode = -1) :
-X86FaultBase(name, mnem, vector, _errorCode)
+const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
+: X86FaultBase(name, mnem, vector, _errorCode)
{}
#if FULL_SYSTEM
@@ -140,8 +140,8 @@
{
protected:
X86Abort(const char * name, const char * mnem,
-const uint8_t vector, uint64_t _errorCode = -1) :
-X86FaultBase(name, mnem, vector, _errorCode)
+const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
+: X86FaultBase(name, mnem, vector, _errorCode)
{}
#if FULL_SYSTEM
@@ -154,8 +154,8 @@
{
protected:
X86Interrupt(const char * name, const char * mnem,
-const uint8_t _vector, uint64_t _errorCode = -1) :
-X86FaultBase(name, mnem, _vector, _errorCode)
+const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
+: X86FaultBase(name, mnem, _vector, _errorCode)
{}
};
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: build: fix compiler warnings in g++ 3.4
Seems like it would be worth setting up a slew of g++ revs on zizzer and running regressions under all of them, maybe on a rotating basis... Yeah, I agree. Multiple revs of swig and maybe scons would be good too. I think we should set up a separate compile everything regression actually. It doesn't take that long to compile the tree, and with the pool being available, we could just compile a bunch of combinations. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] old code
Please don't do anything with the TLBs yet. I'm hoping to send out a patch tonight. No problem. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: stats: fix compiler error
changeset 4df1c7698e52 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4df1c7698e52
description:
stats: fix compiler error
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/base/statistics.hh |4 ++--
diffs (19 lines):
diff -r 77bf0b8db2c5 -r 4df1c7698e52 src/base/statistics.hh
--- a/src/base/statistics.hhMon Mar 16 11:01:23 2009 -0400
+++ b/src/base/statistics.hhMon Mar 16 15:16:58 2009 -0700
@@ -961,13 +961,13 @@
* Return the current value of this stat as its base type.
* @return The current value.
*/
-Counter value() const { return stat-data(index)-value(); }
+Counter value() const { return stat.data(index)-value(); }
/**
* Return the current value of this statas a result type.
* @return The current value.
*/
-Result result() const { return stat-data(index)-result(); }
+Result result() const { return stat.data(index)-result(); }
public:
/**
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: ply: put the absolute path to ply in the enviro...
changeset 9116be67b6d8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9116be67b6d8
description:
ply: put the absolute path to ply in the environment, not a relative one
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
SConstruct |2 +-
diffs (12 lines):
diff -r 4df1c7698e52 -r 9116be67b6d8 SConstruct
--- a/SConstructMon Mar 16 15:16:58 2009 -0700
+++ b/SConstructTue Mar 17 12:45:41 2009 -0700
@@ -374,7 +374,7 @@
Export('extras_dir_list')
# M5_PLY is used by isa_parser.py to find the PLY package.
-env.Append(ENV = { 'M5_PLY' : str(Dir('ext/ply')) })
+env.Append(ENV = { 'M5_PLY' : Dir('ext/ply').abspath })
CXX_version = read_command([env['CXX'],'--version'], exception=False)
CXX_V = read_command([env['CXX'],'-V'], exception=False)
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: includes: add ext to the includes path.
changeset 7e310503019e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7e310503019e
description:
includes: add ext to the includes path.
move dnet to the correct place so that we use this
diffstat:
30 files changed, 1738 insertions(+), 1738 deletions(-)
SConstruct |4
ext/dnet/addr.h | 67 ++
ext/dnet/arp.h | 103 +
ext/dnet/blob.h | 56 +
ext/dnet/dnet/addr.h| 67 --
ext/dnet/dnet/arp.h | 103 -
ext/dnet/dnet/blob.h| 56 -
ext/dnet/dnet/eth.h | 77 ---
ext/dnet/dnet/fw.h | 54 -
ext/dnet/dnet/icmp.h| 265 -
ext/dnet/dnet/intf.h| 68 --
ext/dnet/dnet/ip.h | 487 ---
ext/dnet/dnet/ip6.h | 183 -
ext/dnet/dnet/os.h | 117 ---
ext/dnet/dnet/rand.h| 33 ---
ext/dnet/dnet/route.h | 35 ---
ext/dnet/dnet/tcp.h | 158 ---
ext/dnet/dnet/udp.h | 32 ---
ext/dnet/eth.h | 77 +++
ext/dnet/fw.h | 54 +
ext/dnet/icmp.h | 265 +
ext/dnet/intf.h | 68 ++
ext/dnet/ip.h | 487 +++
ext/dnet/ip6.h | 183 +
ext/dnet/os.h | 117 +++
ext/dnet/rand.h | 33 +++
ext/dnet/route.h| 35 +++
ext/dnet/tcp.h | 158 +++
ext/dnet/udp.h | 32 +++
ext/gzstream/SConscript |2
diffs (truncated from 3615 to 300 lines):
diff -r 9116be67b6d8 -r 7e310503019e SConstruct
--- a/SConstructTue Mar 17 12:45:41 2009 -0700
+++ b/SConstructTue Mar 17 12:49:03 2009 -0700
@@ -373,6 +373,9 @@
Export('base_dir')
Export('extras_dir_list')
+# the ext directory should be on the #includes path
+env.Append(CPPPATH=[Dir('ext')])
+
# M5_PLY is used by isa_parser.py to find the PLY package.
env.Append(ENV = { 'M5_PLY' : Dir('ext/ply').abspath })
@@ -418,7 +421,6 @@
if sys.platform == 'cygwin':
# cygwin has some header file issues...
env.Append(CCFLAGS=Split(-Wno-uninitialized))
-env.Append(CPPPATH=[Dir('ext/dnet')])
# Check for SWIG
if not env.has_key('SWIG'):
diff -r 9116be67b6d8 -r 7e310503019e ext/dnet/addr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/ext/dnet/addr.h Tue Mar 17 12:49:03 2009 -0700
@@ -0,0 +1,67 @@
+/*
+ * addr.h
+ *
+ * Network address operations.
+ *
+ * Copyright (c) 2000 Dug Song dugs...@monkey.org
+ *
+ * $Id: addr.h,v 1.12 2003/02/27 03:44:55 dugsong Exp $
+ */
+
+#ifndef DNET_ADDR_H
+#define DNET_ADDR_H
+
+#define ADDR_TYPE_NONE 0 /* No address set */
+#defineADDR_TYPE_ETH 1 /* Ethernet */
+#defineADDR_TYPE_IP2 /* Internet Protocol v4 */
+#defineADDR_TYPE_IP6 3 /* Internet Protocol v6 */
+
+struct addr {
+uint16_t addr_type;
+uint16_t addr_bits;
+union {
+eth_addr_t __eth;
+ip_addr_t __ip;
+ip6_addr_t __ip6;
+
+uint8_t__data8[16];
+uint16_t __data16[8];
+uint32_t __data32[4];
+} __addr_u;
+};
+#define addr_eth __addr_u.__eth
+#define addr_ip__addr_u.__ip
+#define addr_ip6 __addr_u.__ip6
+#define addr_data8 __addr_u.__data8
+#define addr_data16__addr_u.__data16
+#define addr_data32__addr_u.__data32
+
+#define addr_pack(addr, type, bits, data, len) do {\
+(addr)-addr_type = type; \
+(addr)-addr_bits = bits; \
+memmove((addr)-addr_data8, (char *)data, len);\
+} while (0)
+
+__BEGIN_DECLS
+int addr_cmp(const struct addr *a, const struct addr *b);
+
+int addr_bcast(const struct addr *a, struct addr *b);
+int addr_net(const struct addr *a, struct addr *b);
+
+char *addr_ntop(const struct addr *src, char *dst, size_t size);
+int addr_pton(const char *src, struct addr *dst);
+
+char *addr_ntoa(const struct addr *a);
+#define addr_aton addr_pton
+
+int addr_ntos(const struct addr *a, struct sockaddr *sa);
+int addr_ston(const struct sockaddr *sa, struct addr *a);
+
+int addr_btos(uint16_t bits, struct sockaddr *sa);
+int addr_stob(const struct sockaddr *sa, uint16_t *bits);
+
+int addr_btom(uint16_t bits, void *mask, size_t size);
+int addr_mtob(const void *mask, size_t size, uint16_t *bits);
+__END_DECLS
+
+#endif /* DNET_ADDR_H */
diff -r 9116be67b6d8 -r 7e310503019e ext/dnet/arp.h
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/ext/dnet/arp.hTue Mar 17 12:49:03 2009 -0700
@@ -0,0 +1,103 @@
+/*
+ * arp.h
+ *
+ * Address Resolution Protocol.
+ * RFC 826
+ *
+ * Copyright (c) 2000 Dug Song dugs...@monkey.org
+ *
+ * $Id: arp.h,v
Re: [m5-dev] SimObjectCollection patch
+class SimObjectCollection(SimObject): + type = 'SimObjectCollection' SimObjectCollection Seems like a pretty long name. Is there something ambiguous about calling it Collection or Container? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Memory corruption in m5 dev repository when using --trace-flags=ExecEnable
I have run this through gdb in with m5.debug and see the same errors, the problem is the stack trace showing the cause of the seg fault or assert changes depending on the inputs to the simulator. So, I have not been able to pin point this bug which appears to be a subtle memory corruption somewhere in the code. This error does not happen for other trace flags such as the “Cache” trace flag. It appears linked solely to the instruction tracing mechanism. Has anybody else seen this bug? Regressions have been passing and I haven't heard anything about this, so we'll need more info. (Or better yet, I'd like to give you moral support to continue debugging :) Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Memory corruption in m5 dev repository when using --trace-flags=ExecEnable
Does this problem really have anything to do with tracing, or is it just more apparent with it? On Sat, Apr 4, 2009 at 1:49 PM, Gabe Black gbl...@eecs.umich.edu wrote: Oooh. I see what's broken. This is a result of my changes to allow delaying translation. What happens is that Stl_c goes into initiateAcc. That function calls write on the CPU which calls into the TLB which calls the translation callback which recognizes a failed store conditional which completes the instruction execution with completeAcc and cleans up. The call stack then collapses back to the initiateAcc which is still waiting to finish and which then tries to call a member function on traceData which was deleted during the cleanup. The problem here is not fundamentally complicated, but the mechanisms involved are. One solution would be to record the fact that we're still in initiateAcc, and if we are wait for the call stack to collapse back down to initiateAcc's caller before calling into completeAcc. That matches the semantics an instruction would expect more, I think, where the initiateAcc/completeAcc pair are called sequentially. One other concern this raises is that the code in the simple timing CPU is not very simple. One thing that would help would be to try to relocate some of the special cases, like failed store conditionals or memory mapped registers, into different bodies of code or at least out of the midst of everything else going on. I haven't thought about this in any depth, but I'll try to put together a flow chart sort of thing to explain what happens to memory instructions as they execute. That would be good for the sake of documentation and also so we have something concrete to talk about. Gabe Gabe Black wrote: The segfault for me happens in malloc called by the new operator in exetrace.hh on line 84. That says to me that the most likely culprit is heap corruption which will be very obnoxious to track down. I've started up a run of valgrind just in case it can catch something bad happening sometime in the next n hours. Gabe Gabe Black wrote: Oh wow. It did happen eventually. I'll see if I can figure out what's going on. Gabe Gabe Black wrote: I tried that command line and I haven't seen any segfault yet. I'll let it run and see if anything happens. What version of the code are you using? Gabe Geoffrey Blake wrote: I’ve added a couple edits, but nothing major, ie: added statistics to the bus model, and some extra latency randomization to cache misses to get better averages of parallel code runs. None of this is tied to the trace-flags mechanism that I can determine. I did run the code through valgrind, but ridiculously enough, the segfault disappears. I’ll keep digging in my spare time. The “Exec” trace flags work fine (billions of instructions, no problems) with an old version of m5 that is somewhere between beta4 and beta5 of the stable releases. Now I can trace maybe a few thousand instructions before M5 seg faults. Here is a stripped command line that does expose the bug with the least number of variables to consider in case someone out there wants to try and duplicate the segfaults I’m seeing (it could be a product of my build setup, so I’d appreciate it if someone could verify independently): % m5.opt –trace-flags=”ExecEnable” fs.py –b MutexTest –t –n 1 /dev/null Geoff *From:* m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] *On Behalf Of *Korey Sewell *Sent:* Friday, April 03, 2009 9:56 AM *To:* M5 Developer List *Subject:* Re: [m5-dev] Memory corruption in m5 dev repository when using --trace-flags=ExecEnable I would echo Gabe sentiments. I've been suspicious of the trace-flags causing memory corruption for awhile now, but every time I dig into it there's some small error that I'm propagating through that finally surfaces. In the big picture, I suspect that the trace-flags just exacerbate any kind of memory-corruption issues since you are accessing things at such a heavy-rate. In terms of debugging, is there any code that you edited that is tagged when you use ExecEnable rather than just Exec? Also, if you can turn valgrind on for maybe the 1st thousand/million cycles with ExecEnable you'll probably find something. On Thu, Apr 2, 2009 at 7:28 PM, Gabriel Michael Black gbl...@eecs.umich.edu mailto:gbl...@eecs.umich.edu wrote: Does this happen when you start tracing sooner? I'd suggest valgrind, especially if you can make the segfault happen quickly. If you wait for your simulation to get to 14000 ticks in valgrind, you may die before you see the result. There's a suppression file in util which should cut down on the noise. Gabe Quoting Geoffrey Blake bla...@umich.edu mailto:bla...@umich.edu: I stumbled upon what appears to be a memory corruption bug in the current M5 repository. If on the command line I enter: % ./build/ALPHA_FS/m5.opt
[m5-dev] changeset in m5: style: fix style hook for some newer versions o...
changeset 6df0633d883b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6df0633d883b
description:
style: fix style hook for some newer versions of mercurial.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
util/style.py |4 ++--
diffs (21 lines):
diff -r 0647c8b31a99 -r 6df0633d883b util/style.py
--- a/util/style.py Mon Apr 06 10:19:36 2009 -0700
+++ b/util/style.py Wed Apr 08 22:21:25 2009 -0700
@@ -347,7 +347,7 @@
if prompt(fname, fixonly):
return True
-def check_whitespace(ui, repo, hooktype, node, parent1, parent2):
+def check_whitespace(ui, repo, hooktype, node, parent1, parent2, **kwargs):
if hooktype != 'pretxncommit':
raise AttributeError, \
This hook is only meant for pretxncommit, not %s % hooktype
@@ -355,7 +355,7 @@
args = { 'tabsize' : 8 }
do_check_whitespace(ui, repo, **args)
-def check_format(ui, repo, hooktype, node, parent1, parent2):
+def check_format(ui, repo, hooktype, node, parent1, parent2, **kwargs):
if hooktype != 'pretxncommit':
raise AttributeError, \
This hook is only meant for pretxncommit, not %s % hooktype
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] changeset in m5: tlb: More fixing of unified TLB
changeset 47b4fcb10c11 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=47b4fcb10c11
description:
tlb: More fixing of unified TLB
diffstat:
20 files changed, 130 insertions(+), 129 deletions(-)
src/arch/alpha/AlphaTLB.py |8 +-
src/arch/alpha/tlb.cc| 13 --
src/arch/alpha/tlb.hh|6 +
src/arch/mips/tlb.cc | 12 --
src/arch/mips/tlb.hh |5 +---
src/arch/sparc/tlb.cc| 12 --
src/arch/sparc/tlb.hh|5 +---
src/arch/x86/faults.hh |9 ---
src/arch/x86/pagetable_walker.cc | 18 +++
src/arch/x86/pagetable_walker.hh |5 ++--
src/arch/x86/tlb.cc | 33 +++
src/arch/x86/tlb.hh |8 ++
src/cpu/BaseCPU.py | 13 +-
src/cpu/base_dyn_inst.hh |5 ++--
src/cpu/o3/fetch_impl.hh |2 -
src/cpu/simple/atomic.cc |7 +++--
src/cpu/simple/timing.cc | 28 +++
src/cpu/simple/timing.hh | 45 +-
src/sim/tlb.cc |7 ++---
src/sim/tlb.hh | 18 +--
diffs (truncated from 738 to 300 lines):
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/alpha/AlphaTLB.py
--- a/src/arch/alpha/AlphaTLB.pyWed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/alpha/AlphaTLB.pyWed Apr 08 22:21:27 2009 -0700
@@ -34,4 +34,10 @@
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
cxx_class = 'AlphaISA::TLB'
-size = Param.Int(64, TLB size)
+size = Param.Int(TLB size)
+
+class AlphaDTB(AlphaTLB):
+size = 64
+
+class AlphaITB(AlphaTLB):
+size = 48
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/alpha/tlb.cc Wed Apr 08 22:21:27 2009 -0700
@@ -607,23 +607,20 @@
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
-bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
-if (execute)
+if (mode == Execute)
return translateInst(req, tc);
else
-return translateData(req, tc, write);
+return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
-Translation *translation,
-bool write, bool execute)
+Translation *translation, Mode mode)
{
assert(translation);
-translation-finish(translateAtomic(req, tc, write, execute),
-req, tc, write, execute);
+translation-finish(translateAtomic(req, tc, mode), req, tc, mode);
}
/* end namespace AlphaISA */ }
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/alpha/tlb.hh Wed Apr 08 22:21:27 2009 -0700
@@ -141,11 +141,9 @@
Fault translateInst(RequestPtr req, ThreadContext *tc);
public:
-Fault translateAtomic(RequestPtr req, ThreadContext *tc,
-bool write = false, bool execute = false);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
-Translation *translation,
-bool write = false, bool execute = false);
+ Translation *translation, Mode mode);
};
} // namespace AlphaISA
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/mips/tlb.cc Wed Apr 08 22:21:27 2009 -0700
@@ -562,22 +562,20 @@
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
-bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
-if (execute)
+if (mode == Execute)
return translateInst(req, tc);
else
-return translateData(req, tc, write);
+return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
-Translation *translation, bool write, bool execute)
+Translation *translation, Mode mode)
{
assert(translation);
-translation-finish(translateAtomic(req, tc, write, execute),
-req, tc, write, execute);
+translation-finish(translateAtomic(req, tc, mode), req, tc, mode);
}
diff -r 410194bb3049 -r 47b4fcb10c11 src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh Wed Apr 08 22:21:27 2009 -0700
+++ b/src/arch/mips/tlb.hh Wed Apr 08 22:21:27 2009 -0700
@@ -138,10 +138,9 @@
void regStats();
-Fault translateAtomic(RequestPtr req, ThreadContext *tc,
-bool write=false, bool execute=false);
+Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
-Translation *translation, bool write=false, bool
[m5-dev] changeset in m5: tests: update tests for TLB unification
changeset 0555121b5c5f in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=0555121b5c5f description: tests: update tests for TLB unification diffstat: 197 files changed, 1885 insertions(+), 1171 deletions(-) tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini |4 tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout |8 tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 40 +- tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini |4 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout | 10 tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt | 40 +- tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini |4 tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout | 10 tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt | 40 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini |4 tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |8 tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt |8 tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini |4 tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout | 10 tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt |8 tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini |4 tests/long/00.gzip/ref/sparc/linux/simple-timing/simout |8 tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt |8 tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini |4 tests/long/00.gzip/ref/x86/linux/simple-atomic/simout | 10 tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt |8 tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini |4 tests/long/00.gzip/ref/x86/linux/simple-timing/simout | 10 tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt |8 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |8 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |8 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 72 +++-- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini |4 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout |8 tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 40 +- tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini |4 tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout | 10 tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt |8 tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini |4 tests/long/10.mcf/ref/sparc/linux/simple-timing/simout |8 tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt |8 tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini |4 tests/long/10.mcf/ref/x86/linux/simple-atomic/simout | 10 tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt |8 tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini |4 tests/long/10.mcf/ref/x86/linux/simple-timing/simout | 10 tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt |8 tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini |4 tests/long/20.parser/ref/x86/linux/simple-atomic/simout | 10 tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt |8 tests/long/20.parser/ref/x86/linux/simple-timing/config.ini |4 tests/long/20.parser/ref/x86/linux/simple-timing/simout | 10 tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt |8 tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini |4 tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |8
Re: [m5-dev] changeset in m5: tlb: Don't separate the TLB classes into an ins...
can someone elaborate on what the 3 modes mean {Read, Write, Execute}?
They correspond to the access types that come from the CPU.
I ask because in the translateAtomic function it seems as if the only modes
that matter are Write and Execute. Why does Read not matter?
It does. Which translateAtomic function do you think it doesn't matter for?
I might be missing something simple, but it seems as if there are only 2
necessary modes (Inst/Data) and for the data portion we read the alpha
system register to figure out if it's a read/write access.
You don't read a register to find out if its a read or a write, the
instruction itself tells you that.
Thus, the 3rd argument to that function looks unnecessary since it is always
the value Write. If it is unneccessary, then does that not mess up the
stats in that function who play off the write variable instead of maybe
more appropriately the mode variable?
Which file exactly are you liking in. There are multiple
implementations of this function.
Again, I might just be overlooking something. Can someone give me some
insight into what's going on here?
___
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] changeset in m5: tlb: Don't separate the TLB classes into an ins...
The file I'm referring to is arch/alpha/tlb.cc and specifically the translateAtomic() function implemented there. Basically, having the Read mode is irrelevant there since it's given a default type of write when it calls translateData(). Then in the translateData() function it goes ahead and gets the mode from a system register. So either I'm mixing up what mode means or that extra mode (at least for translateAtomic()) is just extra there. It's not given write. There's a check to see if the mode is write. the code is mode == Write not Write, so a true is passed in if it's a write and a false if it's a read. Or is this not the issue? ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
