[PEDA] (PEDA] PCB: place track
I dont know if this topic has been covered before but. in 99SE, I set up a hotkey (W) to PCB: PlaceTrack.I disabled W so that Windows menu does not interfere. When I place track using my W key it always places an invisble trace which has NO NET assigned to it.I tried the same thing on my laptop several months ago and dismissed it as something I didnt want to troubleshoot at the time. Can anyone give me some insite to why I am getting an invisible traee . Yes, my layers are turned on and all display is final, and no I am not in single layer mode. Any help ? Thanks in advance Mike Reagan * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] (PEDA] PCB: place track
Very very nice Dennis, You hit the nail on the head. Muchas Gracias, Amigo it was ManRoute:RunExternalManualRouter that fixed my problem Mike Reagan - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, October 25, 2002 5:07 PM Subject: Re: [PEDA] (PEDA] PCB: place track i think what you want is to assign instead: ManRoute:RunExternalManualRouter whereas PCB:Placetrack is from 98 and doesn't work right anymore BTW the Place track will allow tab settings before the first click, but it is not as smart for setting the right net and width etc Dennis Saputelli Michael Reagan (EDSI) wrote: I dont know if this topic has been covered before but. in 99SE, I set up a hotkey (W) to PCB: PlaceTrack.I disabled W so that Windows menu does not interfere. When I place track using my W key it always places an invisble trace which has NO NET assigned to it.I tried the same thing on my laptop several months ago and dismissed it as something I didnt want to troubleshoot at the time. Can anyone give me some insite to why I am getting an invisible traee . Yes, my layers are turned on and all display is final, and no I am not in single layer mode. Any help ? Thanks in advance Mike Reagan -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] (PEDA] PCB: place track
and thanks to you too Harry for the right answer Mike - Original Message - From: Harry Selfridge [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, October 25, 2002 4:56 PM Subject: Re: [PEDA] (PEDA] PCB: place track Well, the first thing that comes to mind is that you are calling the wrong process for Protel99SE. If you look at the existing menu item for '(P)lace (T)rack', it is really (P)lace Interac(t)ive Routing. The process is ManRoute:RunExternalManualRouter and the parameter string is $Description=Interactively route connections. I suspect that PCB: PlaceTrack is a carryover from Protel98 that is no longer functional. Regards - Harry At 02:44 PM 10/25/02 -0400, you wrote: I dont know if this topic has been covered before but. in 99SE, I set up a hotkey (W) to PCB: PlaceTrack.I disabled W so that Windows menu does not interfere. When I place track using my W key it always places an invisble trace which has NO NET assigned to it.I tried the same thing on my laptop several months ago and dismissed it as something I didnt want to troubleshoot at the time. Can anyone give me some insite to why I am getting an invisible traee . Yes, my layers are turned on and all display is final, and no I am not in single layer mode. Any help ? Thanks in advance Mike Reagan * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:proteledaforum;techservinc.com * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:ForumAdministrator;TechServInc.com * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum;techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] flipping board
The only thing left now is Jun is now producing a design counter to IPC guidelines for documentation, Primary side is on the bottom. - Original Message - From: Rick Wilson (Protta) [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Thursday, October 10, 2002 11:03 AM Subject: Re: [PEDA] flipping board Ian, I must apologies. When I ran the process I mentioned in my e-mail, I would have sworn the Component pads were in the correct positions when the components were flipped onto the back of the board. I went back and tried to recreate the process I mentioned, and you are absolutely correct. It can't be done. So I apologize to Jun as well, for giving him false information. I tried Jami's method and it seems to flip the comp's correctly to the bottom layer, With the pins in the correct orientation, but there seemed to be a few crazy things Still happening with this method as well, such as the silkscreen staying on the top Overlay, even though the parts are now on the bottom layer. Anyway, it sound like you have solved this with your server and I hope this server Will be a solution to Jun and many others. Again, sorry for the incorrect information. Best Regards, == Richard Rick J. Wilson - Owner PROTTA Professional Technical Training Associates (916) 941-1185 - Office/Fax (916) 955-0083 - Mobile visit our web site at www.protta.com == -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: Wednesday, October 09, 2002 10:20 PM To: Protel EDA Forum Subject: Re: [PEDA] flipping board On 02:35 PM 10/10/2002 +0930, Terry Creer said: Heh! sorry 'bout that - I couldn't help it :) But seriously - Most of the boards we deal with here are only double sided, with the occasional 4 layer, so the server that Ian co-wrote, sounds ok to me. I seem to remember seeing a server a while ago, that brought up a window which allowed you to view the other side of the PCB in the correct orientation. I can't remember where it came from (could have been a commercial website). TC That is one of mine as well. You can download and use if you wish. I ask for payment of some small amount if you think it is useful. The amount of money I have made from server development does not come close to covering the time I spend. It is more of a hobby. I have released some freeware as well. http://www.considered.com.au/ProtelFiles/CSFlipView_1_2.zip This was written as a work around to the problems we were having with the inverter. It is most useful for positioning bottom side designators. Ian Considered Solutions Pty Ltd mailto:[EMAIL PROTECTED] ABN: 96 088 410 002 5 The Crescent CHATSWOOD 2067 Ph: +61 2 9411 4248 Fax: +61 2 9411 4249 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] PADS conversion
Hello all I have two very old PADS files dating back to 1996 not even sure what PADS versions these are in , either Perform or Works. I only have PADS from 2.0 up which will not read these PADS job files. I need to get the ASCII conversion for these files so that I can then read them into 99Se, any help out there to convert these to ASCII? Mike Reagan Cornet Technology Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] flipping board
Yea Jami and how do you propose to get pin 1 not reversed then populating all of the components on the board all backwards? We call that smoke then fire. Mike - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Wednesday, October 09, 2002 5:39 PM Subject: Re: [PEDA] flipping board Jun, I am not quite sure what you are asking here, but I think you want to take the components and circuitry on the top and flip it on the bottom, and that what was on the bottom then becomes flipped to the top. Try this with a copy of your database, so that you do not loose anything if it does not work. Make sure you have a large area to the right or above you original board to work with. It will be much easier to do this if you set your grid to .100 and make a reference point at the lower left of the original board, and another one at the lower right of the new board location.on this grid. Turn off all layers except the top layer. Select everything on the top layer (including all traces and components, etc.). Use E C (Edit Copy) and click on your reference point to set the reference point of the copy. Turn the bottom layer back on. Make the bottom layer the active layer. Use E A (Edit Paste Special) to copy the array, and check off the boxes in the Paste Special Dialogue for Paste on current layer, Keep net name, and Duplicate designator, and then click on the Paste button. Hit x on your keyboard to flip the array. You will get a warning message that says Warning: you are attempting to flip a component to the same side of the board . . . , but remember, we changed from the top layer of the board to the bottom layer of the board, so we really are not on the same layer anymore, so where it says Do you want to continue?, click on the Yes button. Position your new array to the right or above the original board, at your new reference point, and then place it with a mouse click. Use E E A (or X A ) to deselect everything. You should now have a mirror image if your top layer on the bottom layer in a new location. You will also have a bunch of rats nest connections going between the two boards since you have duplicated all of the components and all of the traces. Inspect everything to make sure this is what you want, and if so, then continue. Turn off everything except the bottom layer. Select everything on the bottom layer of your original board, and do an E C and select your reference point for your original board. Turn the top layer back on, and make it the current layer. Go thru the E A (Paste Special) Dialogue again, flip it by hitting x, click Yes, and place your new top layer where it belongs with respect to your new bottom layer. You will have to go thru this same scenario for other signal layers of the board, but should not have to worry about flipping plane layers unless you have split planes, in which case you will have to flip them also, although you do have to copy any boundries on your planes,into your new board (although it may be easier just to fix the planes in the Layer Stack Manager after you are done with everything else). Once you have copied or transferred everything to your new flipped board, make sure all of your layers are turned on, and that you have copied everything that you need to copy into your new mirrior image board, and if everything looks OK, then it is time do delete the original. Simply select everything in the original board, and delete it. You may now want to move your new board into the place formerly occupied with the old one. Needless to say, you will have to juggle your mechanical layers to your new configuration, and possibly other things such as the board outline and keepout layers, etc., etc., but other than that I think that you will have what you are looking for. Hope this works for you, JaMi Smith - Original Message - From: Jun Gong [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED]; Protel Developers Forum [EMAIL PROTECTED]; Open Topic Forum [EMAIL PROTECTED] Sent: Wednesday, October 09, 2002 12:23 PM Subject: [PEDA] flipping board Hi, Any one knows how to flip a board in Protel? I want to turn the direction of a pre-routed PCB ( the left side will be at right side and right side will be at the left, just like I hold a piece of PCB board in hand and turn it ). I selected the PCB board, then press X key, Protel prompts that it will flip the board in the same layer, so wires are kept in the original layer and compoent footprints are flipped but keep in the original layer. I can not use L key, because a lot of wires and components are selected. Anyone has a solution? Thanks a lot. Jun * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: *
Re: [PEDA] Database maxed: Update
MikeR You are doing something very wrong (somewhere) if your DDB is a 1GB. I m working on a design with 2500 components, 4500 nets, 21000 nodes and the ddb is only 18 meg. Yes it is slow as molasses but still only 18 meg. MikeR if you want to send one of us your ddb , zip it , and I will be glad to look at it for you . Maybe giving us a breakdown Sch files xxxKB, pcb, xKB etc. might help Mike Reagan EDSI - Original Message - From: Robison Michael R CNIN [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, October 08, 2002 11:45 AM Subject: Re: [PEDA] Database maxed: Update Just a quick update: 1. I have emptied the recycle bin. It only had 84KB in it. 2. I deleted about 4 earlier versions of the PCB in the DDB. My feeling now is that if it would save the DDB, it would now be down to less than 200MB. I am still getting the error. I have 64GB left on my drive. I'm not certain yet about limits on backup sizes. I will be back soon. I want to say that I REALLY APPRECIATE ALL YOU PEOPLE HELPING ME OUT. You are all very kind. Thanks, Michael Robison * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Changing Ratsnest Colors in PCB 99SE
you can also globally change all of the nets colors using the same method listed below then hit global. it will change all of the colors Mike Reagan - Original Message - From: Brad Velander [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Wednesday, October 02, 2002 9:22 PM Subject: Re: [PEDA] Changing Ratsnest Colors in PCB 99SE Terry, the color chip in the normal layers color page does not work to change ratsnests. Confirmed across the board by many users, many years ago now. However, you can change rats nest connection colors individually. Not realistic for the whole works but can be used to high light some nets. Go the list of nets in the left explorer pane, highlight and edit or double click a net from the list. Within the edit dialogue you can change the color for that individual net. Good luck. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Norsat's Microwave Products Division has now achieved ISO 9001:2000 certification -Original Message- From: Terry Creer [mailto:[EMAIL PROTECTED]] Sent: Wednesday, October 02, 2002 6:03 PM To: Protel EDA Forum (E-mail) Subject: [PEDA] Changing Ratsnest Colors in PCB 99SE Has anyone ever noticed if you change the color for the ratsnest (Connections) in OptionsColors, it makes no difference whatsoever to the ratsnest displayed in the PCB editor? It just stays that Greenish-blue color - Or am I crazy? Terry Creer Electronic Design Technician Clipsal Integrated Systems Pty. Ltd. Phone: (08) 8269 0560 Fax: (08) 8346 0380 Email: [EMAIL PROTECTED] Disclaimer: The information contained in this email is intended only for the use of the person(s) to whom it is addressed and may be confidential or contain legally privileged information. If you are not the intended recipient you are hereby notified that any perusal, use, distribution, copying or disclosure is strictly prohibited. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Inner pad feature
Mark After I thought about it a little, the inner pad actually may serve as barrier to prevent a trace to close to the drill. Regardless, This issue is not about removing or changing annular ring , this is about removing unwanted pads. Annular ring is and unwanted pads are two different objects on a via or pads .I'm not sure by your reply below if I'm presenting this well enough to understand Mike - Original Message - From: Forum Member [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 17, 2002 3:51 PM Subject: Re: [PEDA] Inner pad feature Mike, I believe I did understand. I'm very familiar with fabrication methods/limitations and we do a substantial number of fine line COB/wirebond designs so I also know the difficulties of high density layout. Yet I just don't see any advantage to having a new rule or smart via pad stack. The reason is that on really tight layouts, the area made available by that removing the annular ring on an unused via is still needed for the hole wall of the plated via and the tolerance in hole position. Yes, on designs that have generous annular rings on the vias, removing the ring can make available some room (but not all of it). So a new rule might be useful in that situation, but I find it just as easy or easier to reduce the annular ring on some or all the vias as needed. Is my logic flawed? Mark Koitmaa TechServ At 11:41 AM 9/17/2002, you wrote: Mark and Dennis thanks for the reply: Actually Dennis hit the nail on the head : smarter DRC would cover the problem. I not sure Mark understood the issue ,On inner layers where there is no trace , there is actually no pad if you generate gerbers with unconnected pads on inner layers removed This is the setting that board manufacturers prefer, since they remove floating pads anyway. Unconnected pads, float, causing shorts, and also cause premature drill bit wear. Every board house removes these whether you include them or not. In 99SE is assumed that the pad is present for the DRCs whether the connection is there or not. Thus on inner layers clearance should actually be allowed from trace edge to hole edge ( as allowed by manufacturing). Mark, vias are padless internally on all designs unless they connect to a trace. Removal of these pads only helps manufacturing . A via consists of top pad with min annular ring, bottom pad with min annular ring and a barrel with no pads unless it is connected a signal layer inwhich case it has one pad on that layer.The internal and external annular rings are independent of the floating pads. A smart DRC rule ieunconnected pads on inner layers removed would solve the problem. Can that be done in DXP? can we see it SP7 which by the way I would also pay for. Mike Reagan EDSI Frederick - Original Message - From: Mark Koitmaa [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 17, 2002 1:49 PM Subject: Re: [PEDA] Inner pad feature Mike, since you are talking about high density connectors I assume you are using minimum via sizes. If so, given todays minimum hole sizes and annular rings, is it advisable to route this close to a hole? In my experience, taking into account hole position tolerance and over drilling to compensate for hole wall thickness, routing this close to 'padless' via might result in a short. Maybe your fab house can do better, but the ones I've used need at least 5.5 mils around a via hole to prevent break out of the hole wall. This is what we use as minimum annular ring. For a decent fab yield we need at least 3 mils air gap to the nearest trace. Removing the unused via pad during layout doesn't buy us any extra routing room so I don't see any advantage in removing the unused via pad. If you are using vias with a greater than minimum annular ring, wouldn't you get the same by just reducing the annular rings on the affected vias? Mark Koitmaa TechServ At 10:15 AM 9/17/2002, Mike Reagan wrote: One feature I would like to see in future releases or service packs is removal of inner pads before processing gerber data. In other terms inner pads would not be added to a via until a connection is made to that via. The reason for this is for high density connectors where I am trying to route between pad, I often get violations, when in fact the real gerber data will have no clearance violations after gerbers are processed with removed inner pads. This would allow proper routing in high density connectors. The padstack for a via would automatically represent the a via the way it really looks to the fabricator not to the designer. An no ,I dont want to go the way Accel did with their complicated padstacks because then I have to spend time creating a complex stack library with silly names.
Re: [PEDA] Inner pad feature
Exactly JAMI A BGA application is ideal for dumping the pad. It might make the difference between using twice as many layers to route a BGA Mike - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Tuesday, September 17, 2002 5:07 PM Subject: Re: [PEDA] Inner pad feature Mike, I too would like th see the ability to control the removal of the inner pad propr to the gerber file generation stage, but for a different reason. Polygon fills around a pad on a signal layer, are based on the pad being there, and since I use these fills on internal signal layers for planes, in many instances, it can mean the difference on whether I get a good fill and hence a good plane or not. There are also some BGA routing issues where it it would be nice do dump the pad early (so to speak) so that you can get as much other stuf fin there as you can, and still really see what tou are doinf as well as have the coverage of DRC. JaMi - Original Message - From: Michael Reagan (EDSI) [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 17, 2002 10:15 AM Subject: [PEDA] Inner pad feature One feature I would like to see in future releases or service packs is removal of inner pads before processing gerber data. In other terms inner pads would not be added to a via until a connection is made to that via. The reason for this is for high density connectors where I am trying to route between pad, I often get violations, when in fact the real gerber data will have no clearance violations after gerbers are processed with removed inner pads. This would allow proper routing in high density connectors. The padstack for a via would automatically represent the a via the way it really looks to the fabricator not to the designer. An no ,I dont want to go the way Accel did with their complicated padstacks because then I have to spend time creating a complex stack library with silly names. Editing vias in either PADS or Accel is time consuming, I like being able to double click and everything about that object appears. Anybody is welcome to add to this. Mike Reagan EDSI Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Inner pad feature
Ian This could be not a pad stack feature since you can not create a pad stack for every combination of via or pad layer used. Remember the internal pad is only used when a trace is connected to it. I have used Accel to create complex pad stacks but again this feature has nothing to do with internal annular ring size which is all you are controlling with complex pad stacks. Also you could not use a padstack feature for the hundred variations of which pads are connected and not connected on a lets say a 14 - 16 layer design. The permutations are maybe 96 or more different padstacks you would have to create, then picking a via or pad would be impossible. I doubt if the complex pad stack feature in DXP is any difference than Accel. It wouldn't suffice. Minimal annular ring rules would have to be applied internally , along with additional clearance rules for internal layers , drill to trace clearance rule , and even a mfg drill tolerance might be required. Then I might be able to cut my BGA designsnumber of layers by half. Mike Reagan - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 17, 2002 6:57 PM Subject: Re: [PEDA] Inner pad feature On 05:49 PM 17/09/2002 -0400, Michael Reagan (EDSI) said: Exactly JAMI A BGA application is ideal for dumping the pad. It might make the difference between using twice as many layers to route a BGA Mike The padstack feature has been extended in DXP to allow control on all the inner layers individually (full padstack mode) - so you would be able to manually control what pads and what layers have annuli. This helps but does not completely solve the problem. The problem being you may make a connection on a layer and forget to increase the annulus on that layer. I am trying to think if the query system would allow a rule to be applied that would catch this - but as powerful as they are I can't think how one would construct a query that allowed you to determine that a specific layer of a pad had a connection, and how one would be able to selectively apply that to each layer without having to have a rule for all layers. (Vias don't have the full padstack option.) This would be a powerful extension - I think I will propose this and see what the response is. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Inner pad feature
Mr. Lomax wrote: But it does not make the gained space safe for routing, because we can assume that, if routing density is an issue, via pads have been already been reduced in size to the minimum annular ring necessary to avoid breakout, as Mr. Koitmaa notes. And thus it is possible for the hole wall outer edge to be at the same position as the pad would have been. No no no there is huge misunderstanding here, this has nothing to do with flirting with either internal or external annular rings. I can achieve this goal with annular rings of 1000 mils and never see break out on my 12 mil hole. It would give me the other 988 mils back on layers not connected only.My suggested feature has nothing to do with modifying the padstack. the more I think about it It is a DRC issue. . One might gain as much as a few mils of routing space. You are correct but on many occasions all I needed was a few mils. Mike Reagan * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Inner pad feature
Mr. Lomax wrote: But it does not make the gained space safe for routing, because we can assume that, if routing density is an issue, via pads have been already been reduced in size to the minimum annular ring necessary to avoid breakout, as Mr. Koitmaa notes. And thus it is possible for the hole wall outer edge to be at the same position as the pad would have been. No no no there is huge misunderstanding here, this has nothing to do with flirting with either internal or external annular rings. I can achieve this goal with annular rings of 1000 mils and never see break out on my 12 mil hole. It would give me the clearance on other 988 mils back on layers not connected only.My suggested feature has nothing to do with modifying the padstack. the more I think about it It is a DRC issue. . One might gain as much as a few mils of routing space. You are correct but on many occasions all I needed was a few mils. Mike Reagan - Original Message - From: Abd ul-Rahman Lomax [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 17, 2002 5:49 PM Subject: Re: [PEDA] Inner pad feature At 10:49 AM 9/17/2002 -0700, Mark Koitmaa wrote: Maybe your fab house can do better, but the ones I've used need at least 5.5 mils around a via hole to prevent break out of the hole wall. This is what we use as minimum annular ring. For a decent fab yield we need at least 3 mils air gap to the nearest trace. Removing the unused via pad during layout doesn't buy us any extra routing room so I don't see any advantage in removing the unused via pad. It is quite clear that removing unused internal pads improves yield, the only question is *how much* it improves yield. But it does not make the gained space safe for routing, because we can assume that, if routing density is an issue, via pads have been already been reduced in size to the minimum annular ring necessary to avoid breakout, as Mr. Koitmaa notes. And thus it is possible for the hole wall outer edge to be at the same position as the pad would have been. Nevertheless, this only takes place at extreme drill wander in just the wrong direction, and it is possible that a few mils of space could be gained for routing by becoming dead-pad aware in DRC. Essentially, at some value for the variables, the gain in yield from dropping the dead pads could be balanced by the loss in yield due to extreme drill wander. One might gain as much as a few mils of routing space. To determine without experiment the exact values that one could attain would be difficult, I think, but the problem could be approached by a statistical analysis assuming that drill wander is random; the results might vary with the number of holes, i.e., what you might get away with if there are a few hundred holes might be unsupportable with a few thousand. In any case, DRC for dead pads is not a simple matter of dropping the pads and taking the holes at nominal value!!! (By the way, there is a similar issue with inner planes, which for many users actually have a few mils less clearance than might appear! -- since Protel uses the hole size to determine inner plane clearance. For normal conditions, the blowouts should be 3 mils larger diametrically to make the real clearances on the inner plane layers the same as on positive layers. I don't think DRC is aware of this at all.) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] GTC - Guaranteed To Crash
Yea Ive had noticed that about a year ago and might have reported it, It happens if when turn off all of the signal/plane layers. I just figured if I never use it that mode it never crashes. Also if you turn off of all the clearance rules it will cause a crash. There are a few other weird modes Protel crashes in but they aren't anything that prevents the job from being completed. - Original Message - From: Terry Creer [EMAIL PROTECTED] To: Protel EDA Forum (E-mail) [EMAIL PROTECTED] Sent: Tuesday, September 10, 2002 10:21 PM Subject: [PEDA] GTC - Guaranteed To Crash I just discovered this. I had all copper layers turned off, and only 2 Mechanical Layers and the Multilayer turned on. Then I hit 'Asterisk' not thinking that all my copper layers were off.. Protel just froze and I had to Ctrl+Alt+Del End Task to 'fix' it... TC Disclaimer: The information contained in this email is intended only for the use of the person(s) to whom it is addressed and may be confidential or contain legally privileged information. If you are not the intended recipient you are hereby notified that any perusal, use, distribution, copying or disclosure is strictly prohibited. * Tracking #: 2C815BCD3319AD4D9E05C68FB9315927394BFA14 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] So sue me ...(was:Crunch time?)
Jami wrote: When I pointed this out to Roger on the first day of a three day international Design Aids DS1Users Group Meeting hosted by Boeing in Seattle Washington in the fall of 1983 (84?), he immediately left the conference early and flew back to Southern California so that he could immediately file for Federal Bankruptcy protection Jami, I think the bankruptcy filing was already in his adgenda that dark Seattle afternoon regardless of your input. I am also confident Altium will make good on DXP even if it takes them another year.SP6 was a long time in the making.Altium may not file for bankuptcy, if anything they would be aquired by any of the big three. Mike Reagan EDSI * Tracking #: 39772F96C2D6394BA34B3D529FD9173E0123DD56 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] So sue me ...(was:Crunch time?)
Jami wrote That is why I have floated several different proposals here in this forum, ranging from SP7, to free upgrades to DXP (without ATS) for all who bought into Protel 99 SE at its current level due to the fact that it actually does have problems and these people have never received any support at all. These proposals have met with a lot of support, even from you. What the hell are you talking about . I read every one your proposals.you arent an Altium employee and certainly not top level management at Altium so I doubt if the chances for SP7 are any better today than they were a year ago. I really hate to say this but I am sure Altium's marketing knew ( or should have have known) the risks with current users releasing DXP. Legal enforcement of buggy software is probably impossible, because all software has bugs now. It is an accepted practice as shameful as it is. You choices are like mine, dont purchase or recommend a purchase. That hits Nick's parachute where it hurts the most, by depreciating stock value.It hurts my investment also, because Im a stock holder. Mike Reagan * Tracking #: 33DBFDF400025843AE7127D596716418D8797A87 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] So sue me ...(was:Crunch time?)
Jami, Don't get me wrong I like a rebel with an attitude! March on troops but I think we are going to be left in the dust holding our breath waiting for SP7 even if we pay wish a premium on it.Protel would then be supporting 3 products, 99SE, DXP and Accel Pee Pee cad.I don think were going to see that. As steamed as most of us are, The Borgs were right resistance is futile Mike Reagan - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Tuesday, September 10, 2002 5:36 PM Subject: Re: [PEDA] So sue me ...(was:Crunch time?) Michael, See below, JaMi - Original Message - From: Michael Reagan (EDSI) [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, September 10, 2002 5:44 AM Subject: Re: [PEDA] So sue me ...(was:Crunch time?) Jami wrote That is why I have floated several different proposals here in this forum, ranging from SP7, to free upgrades to DXP (without ATS) for all who bought into Protel 99 SE at its current level due to the fact that it actually does have problems and these people have never received any support at all. These proposals have met with a lot of support, even from you. What the hell are you talking about . I read every one your proposals.you arent an Altium employee and certainly not top level management at Altium so I doubt if the chances for SP7 are any better today than they were a year ago.. . . I have absolutely no doubt whatsoever that the current level of customer dissatisfaction both with ATS and DXP, not to mention Protel 99 SE, weighs very very heavily right now on all of Protel / Altiums top executives and employees, and further, I have absolutely no doubt whatsoever that every word of every thread that has passed thru this forum in the past few weeks has been very carefully read and is in fact being very carefully considered by all of Protel / Altiums top executives and employees as we speak. Protel / Altium is in trouble. That is obvious. They are racing against time with DXP for many reason already discussed here. That is obvious. They are on the verge of loosing not only a lot of current and also future customers. That is obvious You don't think that Protel / Altium is looking to pull a rabbit out of a hat, and looking for some real magic answers and real magic solutions to some of these problems? (rhetorical) . . . I really hate to say this but I am sure Altium's marketing knew ( or should have have known) the risks with current users releasing DXP. Legal enforcement of buggy software is probably impossible, because all software has bugs now. It is an accepted practice as shameful as it is. You choices are like mine, dont purchase or recommend a purchase. That hits Nick's parachute where it hurts the most, by depreciating stock value.It hurts my investment also, because Im a stock holder. I am sure that they knew some of it, and I am sure that the were willing to take a certain amount of risk. But I think that they may have misjudged what they were getting in for. I also think that they never thought it would get this far out of hand and get this bad. Thanks for your input and participation, JaMi * Tracking #: CBDE12417A445D4580167346B41F13009A4AC982 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Hard Look at other Programms
Bob Wolfe wrote I do feel the VeriBest router still beats Specctra though. If you really look at this program it runs circles around anything else for interactive routing. Not just interactive routing , there is more to interactive routing than placing traces. Mentor understands dedign rules with High speed, delay, capacitance, parrallel rules, timing etc. It follows all the rules. These are the tools I need. I find it hard to believe you can't take in a netlist though?? Hard to believe its true. I even went to a full day workshop for Mentor, The reps choked when I asked them if it supported an external netlist. I would have purchased the product two months ago if it did. You are right about pricing Purchase Protel for 10K ( or whatever) then add 45 K for a real router. I wish Protel would just stop what ever they are trying to do with this router project. Start from scratch.. First line of code should read.. Once upon a time. Develop the router as a separate product Then market it as a separate product.Reason, it would support new useres, old users, even other programs that still rely on Spectra, ie Accel. Dont think for a minute that Altium didnt redesign DXP without hooks into Accel .They have two products, they wouldnt dream of developing two product lines at this point. So the router has to be compatible with product B. I have preferences to use a seperate computer to do routing. It allows me to contunue with other projects while routing.Integrated routers sound good in theory but for me it doesnt work well. . I may be part of a small exception. Does anyone out there know of a conversion program that can take the 99SE rules text file and can convert it to a spectra.do file with net classes included?Right now this may be my best alternative to routing. Mike Reagan EDSI * Tracking #: 2BF2659CF555FB40B9CA488995DC136E0BEC3CE4 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] SV: Hard Look at other Programms
The guy said there had been a rush of demo downloads today from American Protel users - you know who you are :) Geez did that make me laugh I don't doubt it Their site is probably overloaded today Mike Reagan EDSI * Tracking #: FF5458687241DF4685D58A7B3A6D729A3D3C8E47 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Re[2]: Hard Look at other Programms
Colin, My apologies if I am wrong about the netlist. I was unable to do anything with it nor were any Mentor reps able to help me at the time. (JUN-July of this year) I might attend another workshop later this month and am going to work outside of their canned demo and get some factory engineers to help. From my comments you can see that I am leaning towards Expedition anyway. Its price/ performance is unparralled. Mike Reagan - Original Message - From: Colin Earl [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, September 04, 2002 9:02 PM Subject: [PEDA] Re[2]: Hard Look at other Programms Mike Will you please stop saying that Expedition can't import netlists from other packages. I am currently working on three boards that had their schematics and netlists generated in OrCAD, and am frequently doing the same with designs originating in Protel. Did you work through the example (using a Keyin netlist as the source) that I emailed to you on June 8th? The process (essentially) in OrCAD is to generate a netlist in Integra format, with a package(footprint) specific part value as the Combined property string. Then in Expedition, have a PDB (Parts DataBase) entry for each of the footprints used in the design, and you're ready to start placement. Best regards, Colinmailto:[EMAIL PROTECTED] I find it hard to believe you can't take in a netlist though?? MRE Hard to believe its true. I even went to a full day workshop for Mentor, MRE The reps choked when I asked them if it supported an external netlist. I MRE would have purchased the product two months ago if it did. MRE Mike Reagan MRE EDSI * Tracking #: C66CB6917C45FA499803550577FC602C9F62B4EE * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Service Pack 7 vs DXP issues
What Rob Young stated is what I have been saying for since Accel was acquired. Just Like some of you, I am taking a very hard look at other programs. A very hard lookMy future depends on having the right software for my requirements not someone dictating what my requirements are. Mike Reagan - Original Message - From: Rob Young [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, August 31, 2002 10:56 AM Subject: Re: [PEDA] Service Pack 7 vs DXP issues Speaking of the Beta program, I asked to be part of the Beta program for DXP and was not selected. I have been using Protel since version 1.12 back in 1993 I believe, so I would have thought that my input would have been worth something to them. For whatever reason, they chose not to include me. That was fine as I have too much work to do anyway. The reason I have recently stepped up and began using the DXP demo, is that I have a great interest in seeing that our beloved Protel continues as it has. While Protel has never been perfect, in my opinion, it has been the best value on the market for manual PCB layout and schematic capture. But now, just as they have been gaining ground they decide to make this ATS policy along with a repeat of the P99 release. I nearly severed my Protel relationship over the bugs in P99 and continued to use P98 until P99SE came out. I was encouraged in that the P99SE release directly addressed many of the concerns on this group. It is quite upsetting to see them repeat that mistake again, but this time, they expect us to pay for it as well. Also it just occurred to me as why I am not getting any responses from Altium on the many issues I asked about in the demo I am not a current ATS subscriber! So I am now being shunned for previewing their new release. Not a great way to treat a long time user and supporter of Protel in my opinion. As a consultant, I have been responsible for many more seats of Protel than just my seat. With Altium's current attitude, I will recommend to all of my clients that they wait to see what the outcome of the ATS policy will really be and until DXP has matured enough to be a usable package. Unless Altium intends to be more aggressive with service packs on ATS, that will be at least a year and maybe more based upon past experience. As much as I would like to see SP7, I don't think Altium will provide one as it is not in their new company model to continue with P99SE. They want to move everyone over to DXP and start to collect ATS fees for what is currently an inferior product. Perhaps if they would provide SP7 under the ATS program, it would make the ATS worth something. Then a user could continue to use P99SE with new features and bug fixes and feel like they got something for their money while DXP was getting refined. Plus the user would be able to test DXP and provide valuable feedback to Altium. I just don't agree with paying ATS for bug fixes. New features, yes... telephone tech support for those that need it, yes... fixing buggy software, absolutely not! Is it just me or does it seem like Accel was the one who bought Protel? Ever since Protel purchased Accel and changed their name to Atium, it seems that most people at Altium are former Accel people and the new policies seem to be old Accel policies. I fear that the Protel us long time users have come to know and respect is no longer in existence. Rob - Original Message - From: John A. Ross [Design] [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, August 31, 2002 10:09 AM Subject: Re: [PEDA] Service Pack 7 vs DXP issues From: Brad Velander [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Friday, August 30, 2002 4:58 PM Subject: Re: [PEDA] Service Pack 7 vs DXP issues Rob, could you explain your comments about the Cam Manager in DXP a little better. Do you mean to say that every time you want to generate Gerber/Drill output, you have to reconfigure your output formats manually each time? If what I think you are saying is true, who is the rocket scientist at Protel that blew that one. You know how many mistakes are made generating gerber/drill formats on an initial configuration, saving and tweaking those configurations is only the minimal acceptable feature for the past 10 years (some packages longer than that). Aaaarghhh, Protel/Altium just don't know what the f#$% they are doing, incompetent, completely incompetent. Brad You have to generate the ouptuts in the individual groups (gerber, drill etc). Pre Cam-Manager style. So we have ANOTHER step backwards, productivity wise. Pay more (ATS) do less! Dont figure with me. The features in DXP that I would have welcomed (productivity increase) might not have been so easy to get into a SP7 in 99SE as a database change was needed to accomodate them. BUT, a
Re: [PEDA] Service Pack 7 vs DXP issues
Dennis wrote: now such arrogance can actually be ok if they are truly visionary and much smarter than we are (which is something i would hope to be the case) Well I thought they were prophets until they decided to drop ddb format after cramming it down my throat in the first place. I was the first on this forum to condemn it using very a harsh language several years ago. OK I got used to it, and it has some advantages, ie I can keep all of my files together. But now the winds of Microsoft have changed the direction of the sails of Protel and they embark on another path. Am I to believe the hype two years ago in favor of ddb or is someone pulling my leg this time because they really don't know what direction they are headed. That is not the sight of a visionary. This is hindsight. Mike Reagan EDSI * Tracking #: 86C2B3D325C5DD429CDEB6D65ACA3CED8A3A54D7 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Service Pack 7 - or free DXP
Not only did I pay for it . They will take my ATS money to future develop things I don't want... then charge me for them again when they sell it to me. OH my! I hear voices from graveyard disgruntled ACCEL users saying the same thing before ACCEL died while under their last management team. Mike - Original Message - From: Andrew Jenkins [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Friday, August 30, 2002 5:12 AM Subject: Re: [PEDA] Service Pack 7 - or free DXP -Original Message- From: Michael Reagan (EDSI) [mailto:[EMAIL PROTECTED]] snippity-doo-dah I use 1/5 of the Protel tool set but paid for all of itI don't want their autorouter, their PLD tools etc. So why should I have to pay for them? Most likely, I will have to pay for the full suite again. You can thank their shiny new wall-street corporate management team for that. One used to be able to purchase the components, until the corporation decided that they could force additional profit by coercive methodology. Have you never wondered why there are five separate license code entry points? aj * Tracking #: B85474D7949B1449B359F8E3DCC3867B8DF6AB8B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Service Pack 7 - or free DXP
Mattias Ericson wrote Often a customer wanted to get for example 5 schematics and 1 pcb. Eventually they changed and it was possible to sell and upgrade individual packages. Not only is that, there are still customers and small companies out there that want only schematic capture tools at a low cost.If I am not mistaken you can only purchase Schematic tools from Orcad and Eagle software. Cadence reluctantly sold me the sch tools because I am such a small 1 seat user. It was a pain the a..z dealing with them. They weren't interested in my $ 200 upgrade anymore. It will also interesting to see what market share Cadence looses with OrCad. Orcad had 70 % market share of users two years ago. This does nt translate to 70% in dollar terms. Mike Reagan * Tracking #: 0987A9416DAB9E48A65D75C3E3D124C18EC2A595 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Service Pack 7 vs DXP issues
I probably would pay for SP7 with as long as they met the long list of our requirements also. Mike Reagan - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, August 30, 2002 3:00 PM Subject: Re: [PEDA] Service Pack 7 vs DXP issues i hope that my skepticism is misplaced regarding this development Dennis Saputelli Terry Harris wrote: On Fri, 30 Aug 2002 10:26:22 -0700, Daniel wrote: Dennis Saputelli wrote: i am very skeptical about the fading thing which i think is driving the performance degradation It is unfortunate, but seems to be the consistent testimony of many Protel users that the new DXP software is not improving the ability of pcb designs to do their work better and more effeciently. I don't (yet) agree about the 'fading thing'. A mechanism to let you see what you are currently interested in amongst the confusing mess of a modern high density PCB would be a great productivity aid. I don't think I have heard any existing user praising the DXP user interface, it seems to be more a case of reluctantly learning and putting up with the gratuitious changes to take advantage of new and improved features. At least this 'fading thing' is a genuinely new feature. I am hopeful it will be a very useful but haven't used DXP enough to know. Cheers, Terry. * Tracking #: BD27DB0D336FB942B798DB161CB2D1D5B163DFE1 * -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Dxp forum
Thanks to all that posted the DXP link. I'm going to monitor DXP forum until all of the OS bugs are worked out. The DXP release looks like it was released too early and with too many bugs to be a useful tool, much like 99 was released then a year later 99SE was released. So Ill monitor activity there without my two cents See you guys there Mike Reagan - Original Message - From: Tony Karavidas [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, August 27, 2002 7:45 PM Subject: Re: [PEDA] Dxp forum Nah, we're just all so smart with 99SE that we now don't have much to say about it. (other than the I forgot if it does this...can someone tell me? or the newbie questions which have been answered pretty darn fast. You take it easy Mike. Maybe we'll see ya on the DXP forum someday. -Original Message- From: Michael Reagan (EDSI) [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 27, 2002 7:51 PM To: Protel EDA Forum Subject: Re: [PEDA] Dxp forum This forum has really gone downhill I think its time to bail this forum and see what is happening in the DXP forum. Can anyone post the link for the DXP forum Frankly Im tired of hearing , My protel doesnt work with SCSI, or cd rom , or doesnt run nwhen I listen to nSync in the backround on my Linux system Probahly my last posting on here because there are no new issues here Mike Reagan EDSI ** ** * Tracking #: B613DACD1BAE614C8AAB58EC8200A129BD127FBC * ** ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] AW: DXP Variants / version control
Georg wrote I bought the upgrade and estimate to run it parallel to 99SE until the begin of next year. Georg, Some of us cant afford to run in parrallel and certainly cant afford any more Altium Frankenstein experiments. Mike Reagan EDSI * Tracking #: 50E71B857A6C8043A5CF661956DF9590A4CCC9AB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Dxp forum
This forum has really gone downhill I think its time to bail this forum and see what is happening in the DXP forum. Can anyone post the link for the DXP forum Frankly Im tired of hearing , My protel doesnt work with SCSI, or cd rom , or doesnt run nwhen I listen to nSync in the backround on my Linux system Probahly my last posting on here because there are no new issues here Mike Reagan EDSI * Tracking #: B613DACD1BAE614C8AAB58EC8200A129BD127FBC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Revision problems
Dennis The reason you want to use update afterwards is because you want to update relative to the latest netlist. Mike - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, August 25, 2002 11:52 AM Subject: Re: [PEDA] Revision problems shouldn't you load the netlist AFTER the update? else stray tracks could pick up connectivity? i haven't found clearing nets necessary, although i do it sometime Dennis Saputelli Michael Reagan (EDSI) wrote: Robert, Update free primitives is a very good command to use. I use flawlessly on every design. If you are getting drc errors when invoking the command then you must have traces shorted from one pad to another. The exact process I use is different than most others recommended practice, here is what I do 1 clear all nets from the design 2. load a new netlist 3 update free primitives 4 run drcs The reason I follow this procedure is because it can save hours of Protel crunching the netlist over and over again. If the pcb still has drc errors then there is a problem in the pcb file. I have used this process for hundreds of designs, and hundreds of thousands connections. It has never failed me Mike Reagan EDSI Frederick MD - Original Message - From: Robert M. Wolfe [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, August 25, 2002 9:04 AM Subject: Re: [PEDA] Revision problems To All on this one, I have also been in this situation with a board I had to use the update free primitive to connected copper. IMHO this is a VERY VERY dangerous command unless you are ABSOLUTELY sure there is nothing touching any pads that it should not be. I have used fottprints of pads touching to tie A D GND's etc together and if that has been done it will pick one of those nets and make that one net. NOT just the fact that trace touched this was clearly only pads touching but it made both ends one net. Also if there were footprint changes and traces just happen to be touching things that really don't want to be you are also in trouble. Yes DRC should flag all of these but IMHO this is a very dangerous and time consuming way to deal with this. I had to use this function because I did a board with contact patterns for switches I built into the footprint, and this is the only way Protel deals with making those tracks in the footprint become proper net. Again don't like it at all this way. It also seems to me that Protel is not consistant with respect to update, I have seen in some cases what is described in this thread, and also times where it actually updated the nets properly to new connections. Also it does not seem consistant with update footprints either, sometimes it does it and sometimes I have had to update them manually as I knew I changed one and it was not updated during PCB update with that option checked. Also on this board I did see that Online DRC did not actually update in real time, only after moving aound the board, and if I remember correctly, and maybe closing and going back in did I in fact see the green come up to inform me I had the shorts. I have not dealt with that phone board in awhile and my changes to boards has been pretty minimal so I have not seen this in awhile, but I would say Protels PCB update is a little flaky, and a word of caution be very careful with the update free primitives command Bob Wolfe - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, August 23, 2002 9:25 PM Subject: Re: [PEDA] Revision problems i am on the same page as you about this and yes almost all of our bds have polygon pours, so that is probably at the root of the 'false DRCs' i always reload the netlist after a copper update, just a sanity check and now for a confession i STILL don't use the synchronizer i have been told i am missing something there and i don't doubt it i just never seem to have the time to learn anything and a lot of our netlists are from orcad with all the wrong footprints Dennis Saputelli Brad Velander wrote: I get those not really a DRC problem highlighing all the time. Drives me nuts. I can change the size of a pad that is connected to a pour (legally) and the whole pour lights up as a DRC. I usually repour the polygon because it is faster than running the DRC and the highlight goes away. When I see it, it is usually on a polygon pour. Yeah, I would expect that your check would work with the reloading of the netlist as well. I don't think that you mentioned the reload of the netlist in the first reply so he might have had a real
Re: [PEDA] Revision problems
Robert, Update free primitives is a very good command to use. I use flawlessly on every design. If you are getting drc errors when invoking the command then you must have traces shorted from one pad to another. The exact process I use is different than most others recommended practice, here is what I do 1 clear all nets from the design 2. load a new netlist 3 update free primitives 4 run drcs The reason I follow this procedure is because it can save hours of Protel crunching the netlist over and over again. If the pcb still has drc errors then there is a problem in the pcb file. I have used this process for hundreds of designs, and hundreds of thousands connections. It has never failed me Mike Reagan EDSI Frederick MD - Original Message - From: Robert M. Wolfe [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Sunday, August 25, 2002 9:04 AM Subject: Re: [PEDA] Revision problems To All on this one, I have also been in this situation with a board I had to use the update free primitive to connected copper. IMHO this is a VERY VERY dangerous command unless you are ABSOLUTELY sure there is nothing touching any pads that it should not be. I have used fottprints of pads touching to tie A D GND's etc together and if that has been done it will pick one of those nets and make that one net. NOT just the fact that trace touched this was clearly only pads touching but it made both ends one net. Also if there were footprint changes and traces just happen to be touching things that really don't want to be you are also in trouble. Yes DRC should flag all of these but IMHO this is a very dangerous and time consuming way to deal with this. I had to use this function because I did a board with contact patterns for switches I built into the footprint, and this is the only way Protel deals with making those tracks in the footprint become proper net. Again don't like it at all this way. It also seems to me that Protel is not consistant with respect to update, I have seen in some cases what is described in this thread, and also times where it actually updated the nets properly to new connections. Also it does not seem consistant with update footprints either, sometimes it does it and sometimes I have had to update them manually as I knew I changed one and it was not updated during PCB update with that option checked. Also on this board I did see that Online DRC did not actually update in real time, only after moving aound the board, and if I remember correctly, and maybe closing and going back in did I in fact see the green come up to inform me I had the shorts. I have not dealt with that phone board in awhile and my changes to boards has been pretty minimal so I have not seen this in awhile, but I would say Protels PCB update is a little flaky, and a word of caution be very careful with the update free primitives command Bob Wolfe - Original Message - From: Dennis Saputelli [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, August 23, 2002 9:25 PM Subject: Re: [PEDA] Revision problems i am on the same page as you about this and yes almost all of our bds have polygon pours, so that is probably at the root of the 'false DRCs' i always reload the netlist after a copper update, just a sanity check and now for a confession i STILL don't use the synchronizer i have been told i am missing something there and i don't doubt it i just never seem to have the time to learn anything and a lot of our netlists are from orcad with all the wrong footprints Dennis Saputelli Brad Velander wrote: I get those not really a DRC problem highlighing all the time. Drives me nuts. I can change the size of a pad that is connected to a pour (legally) and the whole pour lights up as a DRC. I usually repour the polygon because it is faster than running the DRC and the highlight goes away. When I see it, it is usually on a polygon pour. Yeah, I would expect that your check would work with the reloading of the netlist as well. I don't think that you mentioned the reload of the netlist in the first reply so he might have had a real jumble for a while. Using the connected copper with an update really frightens me sometimes because with the changes I may have a connection that is made to ground and then it renames almost of the GND net except for the component pads. This can take me a while to untangle sometimes because of our extensive use of polygons in our microwave boards. Then it take even longer before I feel really comvfortable about the integrity of the board again. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com Norsat's Microwave Products Division has now
Re: [PEDA] Find and Set Testpoints
I agree with Ian, the testpoint feature is pretty much useless. I also found the testpoint report to be incomplete and inaccurate. For those reasons, I have my customers generate a separate schematic page with nothing but testpoints. The clear advantages are you can control clearances, top or bottom sides, and have much better control over size and location. There is no easy method to do some tasks, this is one of them. Even the testpont generator in other programs like spectra doesn't work well either. It generates top test points under components which is not desirable.Using Ians method doesn't take long .I will complete a design, then add the testpoints after importing a netlist for the final time.Move component (testpoint) manually to desired locations is a cinch. Afterwards I use the pick and place output to generate their locations, merge is with a netlist report and it works everytime on all machines. Mike Reagan EDSI Frederick MD - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, August 21, 2002 6:25 PM Subject: Re: [PEDA] Find and Set Testpoints On 03:07 PM 21/08/2002 -0500, Michael Biggs said: What issues prevent Find and Set Testpoints - from converting connector pads or vias to be testpoints if your Testpoit style and Testpoit usage are all ok. I have to manually go and set the pads for testpoints and they are through holes. The design rules clear ok but why doesnt it pick up on all the vias and pads needed? Protel's testpoint finder is not really all that useful for current technology tester. It assumes that the points must be on a grid - most modern testers only require a certain separation (100mils preferred, 75 mils OK). I have had poor results with the Testpoint finder. The testpoint rule is great - it will alert my to any net without a testpoint. There is/was, I think an third party testpoint finder - it may (not sure) have been at: http://www.eda.co.uk We often have quite dense boards. We usually try to achieve 100% testpoint coverage. Although we prefer not to use a via as a test point, due to possible barrel damage, we do sometimes. Since the boards are dense we like to tent the top of the via but expose the bottom of those that are set as testpoints. P99SE did not allow selective top and bottom tenting (DXP does). So we manually placed a testpoint component (a simple 1mm round pad) over the vias that we want to expose as test point. The Sch has all the testpoints marked for debugging. The testpoint components can be placed on vias if necessary or nearby a via and a track run, if possible. A simple rule can be set to check clearances between testpoint components (we normally name the single pad as something like TP, within the library footprint and then set a Pad to pad clearance rule with a suitable scope based on the pad name. The testpoint component can include a 5mil wide, 47.5mil radius arc on a mech layer to show (visually) the clearance required. Since the testpoints are components they have automatic text (designator) that can be hidden or shown as desired, which matches the Sch. There are lots of advantages in this over using existing pads and vias as testpoint. In fact, the ability to be able to set a rule checking the distance between testpoint pads is missing unless you use a separate pad, or you use other contrived methods. We use Footprint-Pad scope - only out TP component (with its single TP pad) is used as a testpoint so the rule is easy). Can any one else come up with a clearance rule that checks that any via or pad marked as a testpoint (either free or within a component) is at least xyz mils from its nearest neighbour? Is is there anyway to select all the pads you want as testpoints and do a global edit? Mine was'nt working for me. Any thoughts? http://www.considered.com.au/Protel01.htm There is a freeware server there to allow this. In the past I used to do it (set the testpoint status of selected pads/vias) by saving-as an ASCII format and then using a search and replace to change the testpoint status as required for records marked as selected. I got sick of doing this hence the server. For some very unknown and unfathomable reason Altium did not permit global operations on the testpoint status. No idea why. It may be that the global code in P99Se was getting quite complex and any change required significant changes elsewhere - I can't imagine that it would be deliberately left out if it was easy to do. Ian Wilson * Tracking #: C6DAC609AD84274D8D85C98F600DC9C9E842FAA2 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: *
Re: [PEDA] Netlist output to Protel from Orcad 9.1?
I am not sure if Protel will support the latest version of CIS 9.2 . I had some import problems with 9.1 only because one of my customers managed to create a hierarchy of virtual schematics that even I didn't understand. This customer is a high level math major with no design experience so I don't know what he did, but his schematic worked in Orcad 9.1 only but would not import reference numbers into Protel 99SE.Examination of his files in 9.1 indicated they were ok. Exporting them to Orcad 7.2 revealed the same problem Protel translated. CIS 9.1 must have a differenent hierarchy structure. That schematic has been the only exception I had with Orcad. Mike Reagan EDSI Frederick MD - Original Message - From: Robert M. Wolfe [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, August 21, 2002 7:55 PM Subject: Re: [PEDA] Netlist output to Protel from Orcad 9.1? Mike, Yes, only later 9.X versions of Orcad output a Protel and Protel2 netlist however the 9.1 should output a Tango netlist and Protel will use Tango. Interesting though I am is a situation where th eeng. just updated to Orcad ver 9.2.3 and the import by Protel claims it will import Orcad Ver 9.X well the schematic in this latest version of Orcad does not come across to Protel well at all. Bob Wolfe - Original Message - From: Michael Reagan (EDSI) [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, August 21, 2002 1:59 A Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) -- Chronological -- -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to Re: [PEDA] Netlist output to Protel from Orcad 9.1?, Michael Reagan (EDSI) Chronological -- Thread -- 000f01c249ef$096328a0$05cafea9@mike"> Reply via email to <!-- google_ad_client = "pub-7266757337600734"; google_alternate_ad_url = "http://www.mail-archive.com/blank.png"; google_ad_width = 160; google_ad_height = 600; google_ad_format = "160x600_as"; google_ad_channel = "3243237953"; google_color_borde
Re: [PEDA] Protel 99SE on Windows XP
Ivan wrote I hope that one Compaq is the only one you ever bought. I had one some years ago (PII-266) and it was absolute junk. Yes, Compaq does make proprietary version of Windows for their PCs. How smart is that - a proprietary version of a proprietary OS? Yea it is my only Compaq, and maybe my last. Compaq may be smarter than the rest of the industryThey have built hardware speciifially to run a specific OS. Sounds like an Apple Computer doesnt it? Mike * Tracking #: F5ACF8B6FC98264B848648C9676A74250B075B5E * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Matched Lenghth Constraint
Clive, I was waiting until all of the replies were in before responding about Protel's matched lengths. You are right it does not work, or does not work well. My reasons for it not working well are the following. In all of the cases that I have had to match length, my objective was to evaluate the longest length, This became my critical length or yardstick. My objective was to increase the shortest to match the longest. There is no reason to add more trace to the longest trace unless you are intentionally adding delay. The longest trace should be the yardstick for the other traces to match. If you use Protel's equalizer it will also readjust the longest trace. This feature has never worked on any version of Protel.I am not even sure it works in Spectra without adding length to the longest trace. Time will tell if it works on DXP. I think I need to join the DXP forum to see if this was fixed. Mike Reagan EDSI Frederick - Original Message - From: Robert M. Wolfe [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, August 17, 2002 11:20 AM Subject: Re: [PEDA] Matched Lenghth Constraint Clive, I gave up after about ten tries on the matched length, just figured it did not work. It did add some serpentine, but again after about ten tries the lenghts were still not even close to being matched. Seems kind of rediculous to have to run it multiple times? It should do it in one shot in my mind. Bob Wolfe - Original Message - From: [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, August 13, 2002 6:36 PM Subject: Re: [PEDA] Matched Lenghth Constraint Matched length works very well. To implement the equalize netlengths feature, you have to define a netclass with the nets you want to equalize. Then go to Design Rules/High Speed/Matched Length and set the attributes. Depending on how much room on the board you have, set the amplitude and gap for the largest that can be fitted. Then run Tools/Equalize Net Length a couple of times to progressivly add sections. Usually a couple of runs are required as Protel only 'adds' 1 section at a time. It works out which net in the netclass is the longest and adds sections to the other nets to bring them up. The amplitude and gap can be reduced in later runs to have a finer tolarence. You can then do a DRC to check the lengths. DRC takes the shortest track/net in the netclass and compares the other nets to it Robert M. Wolfe [EMAIL PROTECTED] on 08/13/2002 10:55:53 PM Please respond to Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] cc:(bcc: Clive Broome/sdc) Subject: Re: [PEDA] Matched Lenghth Constraint Well ADEEL, I am afraid that to actually have the system (99SE, don't know about DXP) match these leghts it will not do it, I was told any auto-router function, and this is one will not ahere to these rules. I tried it a few times where there was plenty of room to match the lengths of a delay loop and they were not even close so eneded up having to manually route these. I would also love to hear if there was a way in 99SE to get the system to match these lengths. Bob Wolfe - Original Message - From: Adeel Malik [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, August 13, 2002 9:36 AM Subject: [PEDA] Matched Lenghth Constraint Hi All, I want to apply a matched-length constraint to the signals connected to the bus. In the Protel Design Rule dialog, there are mainly 2 parameters to specify, one is Tolerance (whose purpose is obvious) and the other is Connection style. In connection style there are three options 1) 90 degree 2) 45 degree and 3) Rounded. Alongwith them there are also options of Amplitude and Gap.I couldn't understand these options so Can someone tell me how these options are utilized effectively while routing a bus running at 66MHz. Regards, ADEEL MALIK * Tracking #: 0E65D282D6969F409D601E4E0E422F8499FF2F09 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99SE on Windows XP
Charlie, I ran 99se on XP for a while. It really didn't run any better than running on W98. I eventually had to uninstall XP and reload W 98 after experiencing 3 fatal crashes.These weren't Protel related. XP did everything wrong, it crashed, banged my harddrive until I found out how to stop it, it would loose internet, and network connections, and lost my USP port three times, I'm convinced that my Compaq was molded to run a Compaq version of W98 and attempting to run any other operation system is fruitless, so I ll hold on to W98/ 99SE combo for another year since I'm not ready to buy a new computer every year.Next year I will re-evaluate all of the new design software out there Protel and competition included.I just got my stock statement today, my Protel stock has dropped to 70 cents US.That doesn't say much Mike Reagan EDSI - Original Message - From: Upton Charles R CNIN [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, August 15, 2002 3:10 PM Subject: [PEDA] Protel 99SE on Windows XP Has anyone tried to run 99SE on XP? Thanks, Charlie * Tracking #: 33027F7CB3F19443BFD86CBE7FBC2A7462EC61CE * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Changing default document settings
TC, Create a blank template for both schematic and pcb then start your design from the template. Mike Reagan EDSI Frederick MD Hi all, A few days ago there was a thread on setting up the default.tdb to set up my default database every time I start up a new database. Is there a way to change the default design rules, snap grids, layers etc every time I start a new PCB document (or schematic for that matter)? I'm sick of changing the default settings every time I create a new document... :( Cheers TC * Tracking #: 731DE2F4BBFABC46BF5310A2FC2D0A5FBE8CC400 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Gerber and Specctra bugs
Mattias, It s really not a bug,you also have to remove the layer from Design Rules, Routing layers and change it to Not Used Then you will get a clean Specta export Mike Reagan EDSI Frederick MD Hi, I can confirm the last of the bugs reported. I had a situation where Midlayer 14 had been used and I removed that layer from the layer stack manager to use an other layer. (I usually use Mid layer 1, 2 etc. but this design was don by somebody else before me). When I exported the design to Specctra the Layer 14 still was exported. I Opened the rules to fix it and it was greyed out. I had to add so I had 14 mid layers in the layer stack manager to be able to choose not used under rules. Then I could remove all unwanted midlayers and I was back to the design that I wanted. Really messy. So it is a bug that only the routing layer is used for the specctra export and no warning is issued that there is an difference between Layer Stack manager and Routing layers rule. Best Regards Mattias Ericson Mattias Ericson Omnisys Instruments AB Gruvgatan 8 SE-421 30 V stra Fr lunda, SWEDEN Phone: +46 31 734 34 08 Fax: +46 31 734 34 29 http://www.omnisys.se [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] 2002-08-14 14:29 cc: Please respond toSubject: Re: [PEDA] Gerber and Specctra bugs Protel EDA Forum Hi Ian, thank you for the quick response. Here are the details: snip What would be really really helpful would be you laying out the info in the following form so I can copy and paste. Date: 2002/01/28 sort of format (/mm/dd) Summary: PCB: Gerber gerneration of renamed layers is (wrong?) Details: P99SE SP6 PCB: a few sentences describing the problem and any workarounds... Reported by: yourself here Confirmed by: has anyone confirmed it? Do this for both of the bugs, if you could. I do not have Specctra so would not really know what I was writing anyway... I will do as you suggest. Here we go: Date: 2002/07/05 Summary: PCB: Gerber generation of renamed layers creates 2 layer files, one with old and one with new name Details: P99SE SP6 PCB: In the Layer Stack Manager, when you rename a layer, the Layer Stack Manager shows the new name, and so do all other PCB functions related to layers, but when you create Gerbers, there shows up a layer with the old name, plus a layer with the new name, but this one is empty apart from multi-layer elements. Reported by: Gisbert Auge Confirmed by: not until now to my knowledge Date: 2002/07/05 Summary: PCB: Autoroute/Specctra Interface/Export design file can generate a .DSN file with the wrong number of routing layers specified Details: P99SE SP6 PCB: There is a bug in the influence of Rules/Routing layers and the Autoroute/Specctra Interface/Export design file function. It is easy to reproduce. Do the following: Take a multilayer PCB (no matter how many layers, but at least one inner routing layer) and define the layers in Layer Stack Manager as usual. Go to Design/Rules/Routing Layers/Properties and define the layer directions as desired. Close with ok. Go back to the Layer Stack Manager and delete one inner routing layer. Check in Design/Rules/Routing Layers/Properties that the layer is not active (selected and editable) any more. Do an export to SPECCTRA. Check the resulting .DSN file, and you will see, that the deleted layer is exported to SPECCTRA as active routing layer, resulting in SPECCTRA routing the design with too many layers. A clear, reproducable bug. Workaround: Before deleting the layer in the Layer Stack Manager, go to Design/Rules/Routing Layers/Properties and reset the layer to not used. Then delete it in the Layer Stack Manager, and it is gone for good. Reported by: Gisbert Auge Confirmed by: not until now to my knowledge Still onward and upward. I gather there is lots of bad weather in Europe at the moment - are you very wet where you are? It is very dry in Eastern Australia at the moment and little chance of any significant rain till into next year apparently - full drought conditions in many parts. Not too bad in our part of the country, fortunately. But very bad in the southeast parts of Germany, Austria, and the Czech Republic. Most probably for the same reason why it's so dry in your place. And still the US refuse to sign the Kyoto agreement. They might get it next time. They will notice. No harm intended. Just my 2 Eurocents. Mit freundlichem Gru Kind regards Gisbert Auge N.A.T. GmbH www.nateurope.com * Tracking #: 610057760B0CD147AA97BEEE28250F60E375 *
Re: [PEDA] IPC Footprint Standards
Linden, Given the two footprint documents, IPC vs the manufacture's , I will always use the manufacture's first. The manufacture has generally allowed for tolerances specifically designed for their part. Under some circumstances, I have had large contract manufactures provide me with very specific design guidelines which altered footprints for their reflow process. One claimed since he was also responsible to his client to provide warranty, any percent of increased reliability = one percent of his profits. I would set the precedence to follow the manufacture's guidelines then IPC. (which by the way is very good) Mike Reagan - Original Message - From: Linden Doyle [EMAIL PROTECTED] To: PEDA [EMAIL PROTECTED] Sent: Sunday, August 11, 2002 10:36 PM Subject: [PEDA] IPC Footprint Standards Greetings all, I have a copy of IPC-SM-782. In it are described various recommended footprints for resistors, capacitors, discrete semis and ICs. I also have some documentation from Philips Semiconductors describing the same items. The problem is that the sizes represented in each publication are vastly different. What dangers are there in straying from the path prescribed by the IPC? If I work from the Philips documents I have smaller footprints for things like generic 0603 and 0805 thus allowing for tighter layouts. My copy of IPC-SM-782 is date 1993 - is it likely that the footprint recommendations would have changed in later revisions of the standard? My previous surface mount boards have not been overly tight but this is not the case with the latest job - I need all the space I can get. Any comments would be greatly appreciated. Thanks and Best Regards, Linden Doyle Product Development Engineer Zener Electric Pty Ltd. Ph: +61 2 9795 3600 Fax: +61 2 9795 3611 [EMAIL PROTECTED] mailto:[EMAIL PROTECTED] * Tracking #: 7AE998780E1AD14BA518CF969F9E79261307E4BB * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP Net lists
in the protel orcad universe i have yet to see EDIF do anything useful Dennis Saputelli I agree with you Dennis, Well said. Mike Reagan * Tracking #: AD3A7D6B966FBC4F856C8731401ED4EF18246992 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 'Global' button missing : replaced by fileter and inspect and more gripes
Ian, Read all of my comments about Accel graphics looking like Bitmapped Crayola for the past three years. Protel is cross migrating to Accel and vice-versa.What you describe is in my terms Bitmapped Crayola ( for ALTIUM programmers, Crayola (TM) is a cheap wax pencil wrapped in paper used by artist and children to draw stick figures. I have stated in the past that Protel graphics / color schemes were the best in the industry. Compare zoom in to the maximum resolutions with either PADS or Accel. ( I am comparing comperable products) Then compare a zoom board level with either PADS or Accel. Accel becomes crayola at both levels , PADs is good at zoom in level but round PADS change shape as you zoom out. It has nothing to do with the monitor or video card you use. I have seen it across multiple platforms. So now we have introduced bit mapped crayola to DXP I am surprised to see a negative comment from IANI was going to question his relationship with Protel Mike Reagan EDSI - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, August 01, 2002 5:02 PM Subject: Re: [PEDA] 'Global' button missing : replaced by fileter and inspect and more gripes On 03:11 PM 1/08/2002 -0400, vincent mail said: couple of problems. there is no longar a 'gobal' button when changing properties of objects , a solution given here is close but no sigar : Now we are really getting into my complaints about DXP. Gripe 1: scenario: open pcb select all components try changing all designator text heights to 45 mil for example. I can't do it . The moment you click on 'designator' in the inspector it snaps to the text of only one components and does not modify the proprties of all selected parts. Also the selection process is annoying since it pops up a 'list' window. you can't continue editing unless you hit the Clear button in this list window. I am sure I have done this. So it can be done. Just can't quite recall and do not have the software to test. May have to bear with me or wait for someone else to test. Gripe 2 Selecting a bunch of tracks. The tracks are highlighted by either: - a fine line drawn on top of the traces : - a kind of lattice thrown on top of them , (depending on your zoom level), instead of changing the color of the track. I am colorblind ! ( actually contrast blindness) it is very hard to see what is selected and what not. ( for certain layers that have close contrast levels to the white line. ) I am also a little R-G colour blind. I am not too happy with some of the changes in DXP. There is a reduction in the overall screen contrast - or at least that is my impression. Also when drawing a selection box, if the filter is still active ( see previous example ) the parts inside the box do not get selected. Gripe 3 when selecting a bunch of parts by drawing a selection window , the PCb viewer draws a colored recangle over each and every component this reduces the contrast even more and makes it completely bogu s for me to see anything I am not happy with selection in DXP. Gripe 4 The selection is not 'sticky' you select a bunch of stuff , as soon as you click somewhere the selection gets undone. how do you It is an option - to make selections sticky - check the Preferences you should be able to find it. But ... I think it is still broken even with sticky selections. The sticky selections make it confusing and difficult to operate IMO. P99SE is better in that focus and selection were different attributes. DXP merges them to be more standard Windows-like and I think we have lost something. Gripe 5 Select all : sometimes no longer selects all , only layers ( no components) this seems to be related to this list again . something triggers this list to contain stuff without you specifying it. you have to open the list , Clear it and then the commands behave normally. Dunno - you got more details? Report it as a bug maybe. This seems to affect a number of commands . Sometimes the click , hold and drag to move a track with rubberbanding doesn't behave correctly either Clarification : click is the proces of pushing mouse button and releaseing it without moving the mouce , hold drag is push the mouse button down without releaseing it and then start moving click is select something hold drag is move without rubberbanding click followed by hold and drag is move with rubberbanding of connected vertexes. been playing with DXP for 3 days now ( DEMO version , i'm waiting for my 3 version to come in the mail) . i like a lot of the new things but the above are very annoying for me. I can get used to some of these but the highlight is going to be hard unless someone can do an eye transplant for me. Does the blend slider help? Can you change the colours to help? Ian
Re: [PEDA] Re[2]: Re[2]: Not DXP or P99SE, but have you seen the Cadence offer!!!!
forget ATS, you don't require it. we'll see what happens with future service packs. Whether ther are available for free or not. ATS? When I bought my version 2.8 I think I had free ( was it lifetime or did it say unlimited support or neither ? ) Wish I could find a okl brochure, I don't think there was limitation on the support clause Mike Reagan EDSI * Tracking #: 11D8E272575047419FDCA9EEAD03ABC633C7C76A * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Upgrade Pricing Ethics WAS: Not DXP or P99SE, but have you seen the Cadence offer!!!!
the early days of Daisy, Mentor, Valid you would have to pay ten's of thousands of dollars just for schematic capture! The PCB layout tools cost $100k+. This was before PC's came along. In the IC industry, they have to pay $100k-1m+ for a single software seat! I think PCB is doing pretty well compared to that. Well not quite true yes Some schematics tools cost 100K in the early days, and one in particular cost $500 US. The first time I saw orcad on a pirated version, my jaw dropped. $500 I couldn't believe it! Orcad went on to capture 70 % of the entire Schmatic market with a product that now sells for 1500. and can still compete with any program out there Mike Reagan EDSI * Tracking #: 2A0C60D9AB04D1458ECF8A9F26EC02272586EFD3 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Bag it Discussion
Brian wrote InterestingIn my neck of the woods (NW US), to bag something is to abandon it as useless, but without extreme prejudice Yea that was the same meaning I have always understood. So in this case it meant abandoning Protel, which left me confused Mike Reagan * Tracking #: BD5CE9A9D23CEC48A22E3138057F29F54A05E6A7 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Copper pours on outer layers
Something I forgot to mention: If the parts are surface mount then the internal plane has no hog-outs at all for the pads. Thats why you might be interested in using the soldermask layer instead. Dave Lewis We looked at it today Dave the mask layer would work except we still need to tie the copper to gnd. I think the best solution offered might be using a few different pours. Divide the board into 4 quadrants then pour with overlaps. I just found out the cost of one these boards to mfg is around 10 K each.I hate to send these out relying on the fab house performing tricks on them that I cant verify. Thanks to all for responding Mike Reagan EDSI Frederick MD * Tracking #: FC40710B72761841951A517856DEDDC094996BDD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Copper pours on outer layers
Abdul wrote AND WELCOME BACK! Suppose the worst designer reading this list knows how to accomplish the task? Should he keep it to himself? No that automatically requalifies the worst designer as the best of the best .It is generally not necessary to pour in more than one direction. That we havent tried. I might have mentioned this is a backplane I saw it for the first time today, it has 42,000 pads If one desired pour track to pass between pins with a narrow width, it is not necessary to set the entire pour to that width. Instead. Make a pass-through pattern for a part and copy that pattern over the part with the pour already done. Protel will assign these copied tracks the proper net. That is too risky and cumbersome of a solution if we have to edit the design, but thanks First, route the ground (if that's the net being used) with track entirely ...etc Abdul, we decided to BAG ( our terms means Sh- can ) the merge system becuase the we can not control verification on a board that cost 10K a pop . POP means each for you down under.We will attempt dividing the design into 4 quadrants and pour separately. Thanks Mike Reagan EDSI * Tracking #: 5C18A182D0451645ABEFB0347B0181D5D3D3304E * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP Discussion
Ian wrote, Just a brief comment before the discussion really hots up. My comments: Ian,follow the context of the messages on this forum from release of 99 to present. The earlier tone from these discussions was nothing but frustration. Some of us were mad as hell at simple things not working like INSTALL. There is no reason for mature software to take a 3 year step backwards for simple tasks like copy, select, install, etc.I think the tone of the feedback to follow in the next few months will reflect the same tone that was discussed in 99 early years. Contructive input is years away Lets try to make the discussion constructive. Altium do watch this list and I would guess they would be watching this as one of their prime sources of feedback. I disagree,This is expensive software. I purchase $49.00 software and complain to store managers if my $49.00 package doesnt work, why shouldnt ALTIUM receive heat from us about not correcting bugs and not meeting our expectations. We are the paying customer. SIMPLE AS THAT If I take ALTIUMS attitude with my customers, I would be out of business. We can bag DXP - that is really easy. Can we do the harder stuff of being constructive? We can bag DXP? I too participated in the BETA program, but unlike some who choose to invest 100 hours debugging a program that wasn't ready for prime time, I looked at for the features I wanted and they weren't there. I evaluated the program for my requirements in less than 5 minutes. PROTEL programs no longer meets my design requirements, simple as that. I would expect the current program is finally ready for Beta testing by all the users who wish to pay for it. I just spent the last several years figuring out how 99SE works, what makes it crash, how not to make it crash and how to get around long compilations that send my computer to PLUTO. I wont spend the same time this time with a program that offers no clear advantage to upgrading. How is that for constructive? I will sit back and read all of the DXP input now Mike Reagan EDSI * Tracking #: 8F71C4C0EBD99A44A6DCA9CE6224F55C32D84C88 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP Discussion
Tony, Thank you for the reminder, I don't think I have disclosed anything other than reinforcing any commentary that I have posted here for the past year and long before dXP was a gleam in the Kangaroo's eye. I believe Andrew Jenkins past comments on here also reflect the poor response from Protel to fix bugs and make 99SE more usable.I wish they would sell me the old 99 code, let me hire some of their programmers to polish an already good program like 99SE. It is a very good program , it just could be better without having to write code from the floor up. Mike Reagan EDSI - Original Message - From: Tony Karavidas [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Tuesday, July 30, 2002 10:54 AM Subject: Re: [PEDA] DXP Discussion Part of the beta agreement was to not disclose things that transpired during the beta period. That would seem to imply good or bad. The comments made on this list should be 'freshly formed' from the released demo that everyone has access to right now, not from what beta people saw in the past. -Original Message- From: JaMi Smith [mailto:[EMAIL PROTECTED]] Sent: Tuesday, July 30, 2002 10:45 AM To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] DXP Discussion Ian, This is really scarey, you beta'd the thing and you cant say anything more constructive yourself? Talk about George Orwellean 1984 doublespeak . . . JaMi - Original Message - From: Ian Wilson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, July 29, 2002 11:26 PM Subject: [PEDA] DXP Discussion Hello all, Just a brief comment before the discussion really hots up. There is lots to like about DXP. There is lots to re-learn. There is lots that is the same. There is lots to dislike. Lets try to make the discussion constructive. Altium do watch this list and I would guess they would be watching this as one of their prime sources of feedback. We can bag DXP - that is really easy. Can we do the harder stuff of being constructive? All that said, I am ready to call something rubbish when I think it is. There are a number of us that will be somewhat circumspec as the NDA beta testers signed does cover some info we may have received. Also, IMO, I think it is well worthwhile letting fresh eyes pass comment without too much prompting. Ian Wilson * Tracking #: A153AA0099921341A1FD9A73CE937F13AA986D52 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP Discussion
This is really scarey, you beta'd the thing and you cant say anything more constructive yourself? Tony, I felt very strong that the platform (99SE) was and is superior to anything else in the price range. A few minor tweaks, a few lines of code taken out to optimize long compilations, and an autorouter, even if it meant a separate package to sell at additional costs would have done it for me. Maybe some enhancements to the high speed design rules , Protel...Sell us a separate autorotuing package with an interface that I can use other programs. Mike Reagan * Tracking #: D51E2786DF504A4D8B7B8807A501A22A946D0CE5 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Copper pours on outer layers
Question to smartest of smartest designers out there: Here is the delima, we have a board appox 24 x 30 ( a very large backplane) , many thousands of connections, every layer controlled impedance. The boards are used for high speed tele comminications switching and data monitoring. ( No the the tele com industry is not dead). The designs are as many as 28 layers, some approching .250 inch in thickness, a very expensive baord to design and manufacture. On the outer layers we avoid placing traces, since we embed the entire design, The outer layer are copper pours tied to gnd to reduce EMI and to maintain controlled Z on the next inner layer. The copper is poured on both the top and bottom layers. Copper pours of this size are poured last because they are time consuming. The pours can take 4 hours, and even longer if they are not right the first time. Question to any of the best out there.can we avoid a copper pour and merge a gnd layer to the top? Does anyone have a method or suggestion to merge copper to flood the top layer. Is there a quicker method? We are using 99SE on aa 1 gig cpu with 512 meg. Mike Reagan EDSI * Tracking #: C05FC4455FDD074E8E0D19C321C392CAC217810D * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Copper pours on outer layers
Thanks Vince, We do all of your mentioned tricks, it still takes hours. As a matter of fact anytime I layout a design I turn off DRCs when I a place parts, I turn on only clearance constraints and hide gnd and plane nets after I start to manually route critical lines. This allows my computer to work with me and not work the DRCs. Also I do not set up any rules until I need them. It really speeds things up, But large designs copper pours with a jillion pixels takes hours Mike - Original Message - From: vincent mail [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, July 31, 2002 2:23 PM Subject: Re: [PEDA] Copper pours on outer layers before pouring , switch off the online DRC , 'Pour over same net' and 'remove dead copper' since you have only that on thse layers no need to have the pouring algorithm look for this stuff. that should speed it up somewhat Michael Reagan (EDSI) wrote: Question to smartest of smartest designers out there: Here is the delima, we have a board appox 24 x 30 ( a very large backplane) , many thousands of connections, every layer controlled impedance. The boards are used for high speed tele comminications switching and data monitoring. ( No the the tele com industry is not dead). The designs are as many as 28 layers, some approching .250 inch in thickness, a very expensive baord to design and manufacture. On the outer layers we avoid placing traces, since we embed the entire design, The outer layer are copper pours tied to gnd to reduce EMI and to maintain controlled Z on the next inner layer. The copper is poured on both the top and bottom layers. Copper pours of this size are poured last because they are time consuming. The pours can take 4 hours, and even longer if they are not right the first time. Question to any of the best out there.can we avoid a copper pour and merge a gnd layer to the top? Does anyone have a method or suggestion to merge copper to flood the top layer. Is there a quicker method? We are using 99SE on aa 1 gig cpu with 512 meg. Mike Reagan EDSI * Tracking #: C05FC4455FDD074E8E0D19C321C392CAC217810D * -- -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- _ // Vincent Himpe // _ ___/ Lab Manager / \ \ / / /ST Microelectronics /___\ \ / / / 5510 Six Forks Road . Suite 200 /__//_/__/ Raleigh NC 27612 Tel : (919) 850 6070 Fax : (919) 850 6689 e-mail : [EMAIL PROTECTED] -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Copper pours on outer layers
Peter and All If an internal ground plane has an appropriate copper pattern for the outer layers, just tell the board shop to use that artwork for both the inner layer and outer layer - just because Protel thinks the *.gtl file is the top layer, doesn't mean you _must_ use that as the top layer. (Or if one of the existing planes isn't suitable, make another one that is!) Peter have you actually done it I think this is the answer I am looking for Mike * Tracking #: 190B5DF1C1EC844FA5AD2C7A7E0E1D1971E76167 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Best PCB Package to use?
Michael Wrote: P-CAD is about $10K for the full package, $6K for a 6 layer package, $1.5K for schematic only, with free viewers with cross probing and print capabilities Michael, I don't know how Altium is pricing PCAD these days. but the last I checked. A fully functional PCAD station was in the 20 K range. ( I read their website and it still reads $9995, or whatever )At 10K - 20K it is in the range of packages like PADS, CADENCE, and MENTOR. When these packages are in the same price range and I will opt for the package that has the best reputation, regardless of it being the best (layout) package. Only because I don't have to convince a customer that my package is as good as.(MENTOR) .I deal with allot of managers that are biased against low end packages and no matter how you try to convince them . Their perception is low end software = low end product, even if I am the best designer in the universe. As of claiming a full package is 6 layers, I don't know what you could possibly design with 6 layers. If I had to rely on business being limited to 6 layers, I would not have survived past the first 6 months. 6 layers does is not a full package for me so add some $$ to the base price. PCAD is now sold with PROTEL's infamous non functional auto router. To make PCAD work you still need another 35 K to by a real router like SPECTRA. Don't get me wrong, To make PROTEL work you also need to spend 35 K to purchase are real router like SPECTRA. So a real PROTEL seat is around 45 K. and a real PCAD Seat is 45- 55 K. I know some of you will blast me for saying a PROTEL seat is 45K, but until you use SPECTRA, see how fast it is, how efficient it is, how it works, don't even talk to me. Your poor lives have been in misery without a real autorouter. I have made some noises in for past 2 yeas that if Altium adopted PCAD menus, interface, and functionality into Protel , I would seriously start looking at other programs. I have also voiced for the past several years that PROTEL now Altiom's survival in this industry my hinge on the release of an auto router that trounces the competition. I cant hold my breath any longer. I have seen the next generation routers with MENTOR EXPEDITION software. The bar has been raised and ALTIUM is trying to play catch up to last years technology. They currently have two software packages with no router. That is unacceptable for today's designs.MENTOR just swallowed up PADS, Cadence swallowed Orcad, I think Altiom will be the next target. I have a 50/50 chance of picking the right company that will swallow Altiom Mentor or Cadence. This is my Saturday Morning Commentary Mike Reagan * Tracking #: 1CADDD8C06DDDB48A0461956AD1AAE7147ABE310 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] PEDA] Honeywell footprint
Re: [PEDA] PEDA] Honeywell footprint
Harry MANY THANKS Mike - Original Message - From: Harry Selfridge [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, July 18, 2002 1:53 PM Subject: Re: [PEDA] PEDA] Honeywell footprint Hi Mike, Page three of the data sheet at: http://www.ssec.honeywell.com/microwave/products/AT4610specsheet.pdf points to the mechanical data at: http://www.asat.com/library/drawings/mod/dgmj4i.pdf The mechanical data is quite detailed, and you should be able to develop a PCB footprint that will suit your application. Regards - Harry At 03:26 PM 7/18/02 -0700, you wrote: Sorry guys, I hate to post this here, but does anyone have a link for a Honeywell Attenuator HRF-AT4610 footprint?I tried every page on Honeywell's website and cant find mechanical data. Any help is appreciated by emailing me [EMAIL PROTECTED] snip * Tracking #: BFD844D37445634DAB5740D97FD1B7CA277835B7 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] ATS - don't do it! (was restore defaults...)
On Wed, 10 Jul 2002 09:28, you wrote: I've been told by my boss that for what Altium are offering with ATS it's just not going to happen here. DXP is way out of the question. It's a pity that more people wont jump on this bandwagon. They'll just keep forking out hard earned money for defective software. Kat, I am working for a Telcom company who has 6 seats of 99, 5 seats of 98. Most of the engineers struggle with using schematic in 98 . Even with shortcomings and bugs, the program is very usable. The PCB designers are using the 99 seats. They hae pretty much expressed the samewhy upgrade? Unless there is some clear advantage to upgrade. They also have made a major investment in Spectra, spending almost 100K between 3 seats, and training. Specta was charging them 15 K per year for support and very minor changes to the software. They dropped Spectra support and saved 30 K already. Specta runs fine without the 30K support, even though they are sevreal revisions behind. 30K is alot of money in these days of cutbacks , they were able to buy a network analyzer with the savings. I doubt if I could sell them on any reason why they should upgrade their CAE software for the next few years. It will be a tough sale Mike Reagan EDSI Frederick MD * Tracking #: 7225A5E5E601A2499EC4536D7810348EEC234F6B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
