On Wed, 10 Jul 2002 09:28, you wrote:
I've been told by my boss that for what Altium are offering with ATS
it's
just not going to happen here. DXP is way out of the question.
It's a pity that more people wont jump on this bandwagon. They'll
just keep forking out hard earned
Harry
MANY THANKS
Mike
- Original Message -
From: Harry Selfridge [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Thursday, July 18, 2002 1:53 PM
Subject: Re: [PEDA] PEDA] Honeywell footprint
Hi Mike,
Page three of the data sheet at:
Michael Wrote:
P-CAD is about $10K for the full package, $6K for a 6 layer
package, $1.5K for schematic only, with free viewers with cross probing and
print capabilities
Michael,
I don't know how Altium is pricing PCAD these days. but the last I checked.
A fully functional PCAD station was
Ian wrote,
Just a brief comment before the discussion really hots up.
My comments: Ian,follow the context of the messages on this forum from
release of 99 to present. The earlier tone from these discussions was
nothing but frustration. Some of us were mad as hell at simple things not
Tony,
Thank you for the reminder, I don't think I have disclosed anything other
than reinforcing any commentary that I have posted here for the past year
and long before dXP was a gleam in the Kangaroo's eye. I believe Andrew
Jenkins past comments on here also reflect the poor response from
This is really scarey, you beta'd the thing and you cant say anything
more
constructive yourself?
Tony,
I felt very strong that the platform (99SE) was and is superior to anything
else in the price range. A few minor tweaks, a few lines of code taken out
to optimize long compilations, and
Question to smartest of smartest designers out there:
Here is the delima, we have a board appox 24 x 30 ( a very large
backplane) , many thousands of connections, every layer controlled
impedance. The boards are used for high speed tele comminications
switching and data monitoring. ( No
speed it up somewhat
Michael Reagan (EDSI) wrote:
Question to smartest of smartest designers out there:
Here is the delima, we have a board appox 24 x 30 ( a very large
backplane) , many thousands of connections, every layer controlled
impedance. The boards are used for high speed
Peter and All
If an internal ground plane has an appropriate copper pattern for the
outer layers, just tell the board shop to use that artwork for both the
inner layer and outer layer - just because Protel thinks the *.gtl file
is the top layer, doesn't mean you _must_ use that as the top
Brian wrote
InterestingIn my neck of the woods (NW US), to bag something is to
abandon it
as useless, but without extreme prejudice
Yea that was the same meaning I have always understood. So in this case it
meant abandoning Protel, which left me confused
Mike Reagan
Something I forgot to mention:
If the parts are surface mount then the internal plane has no hog-outs at
all for the pads. Thats why you might be interested in using the
soldermask layer instead.
Dave Lewis
We looked at it today Dave the mask layer would work except we still need
to
Abdul wrote
AND WELCOME BACK!
Suppose the worst designer reading this list knows how to accomplish the
task? Should he keep it to himself?
No that automatically requalifies the worst designer as the best of the
best
.It is generally not necessary to pour in more than one
forget ATS, you don't require it.
we'll see what happens with future service packs.
Whether ther are available for free or not.
ATS? When I bought my version 2.8 I think I had free ( was it lifetime
or did it say unlimited support or neither ? ) Wish I could find a okl
brochure,
the early days of Daisy, Mentor, Valid you would have
to pay ten's of thousands of dollars just for
schematic capture! The PCB layout tools cost $100k+.
This was before PC's came along.
In the IC industry, they have to pay $100k-1m+ for a
single software seat! I think PCB is doing pretty
Ian,
Read all of my comments about Accel graphics looking like Bitmapped Crayola
for the past three years.
Protel is cross migrating to Accel and vice-versa.What you describe is
in my terms Bitmapped Crayola ( for ALTIUM programmers, Crayola (TM) is a
cheap wax pencil wrapped in paper
in the protel orcad universe i have yet to see EDIF do anything useful
Dennis Saputelli
I agree with you Dennis, Well said.
Mike Reagan
* Tracking #: AD3A7D6B966FBC4F856C8731401ED4EF18246992
*
Linden,
Given the two footprint documents, IPC vs the manufacture's , I will always
use the manufacture's first. The manufacture has generally allowed for
tolerances specifically designed for their part. Under some circumstances,
I have had large contract manufactures provide me with very
Mattias,
It s really not a bug,you also have to remove the layer from Design
Rules, Routing layers and change it to Not Used Then you will get a
clean Specta export
Mike Reagan
EDSI
Frederick MD
Hi,
I can confirm the last of the bugs reported.
I had a situation where Midlayer 14
Charlie,
I ran 99se on XP for a while. It really didn't run any better than running
on W98. I eventually had to uninstall XP and reload W 98 after experiencing
3 fatal crashes.These weren't Protel related. XP did everything wrong,
it crashed, banged my harddrive until I found out how to
TC,
Create a blank template for both schematic and pcb then start your design
from the template.
Mike Reagan
EDSI
Frederick MD
Hi all,
A few days ago there was a thread on setting up the default.tdb to
set up my default database every time I start up a new database. Is there
a
way to
Ivan wrote
I hope that one Compaq is the only one you ever bought. I had one some
years ago (PII-266) and it was absolute junk. Yes, Compaq does make
proprietary version of Windows for their PCs. How smart is that - a
proprietary version of a proprietary OS?
Yea it is my only
Clive,
I was waiting until all of the replies were in before responding about
Protel's matched lengths. You are right it does not work, or does not work
well. My reasons for it not working well are the following.
In all of the cases that I have had to match length, my objective was to
I agree with Ian, the testpoint feature is pretty much useless. I also
found the testpoint report to be incomplete and inaccurate. For those
reasons, I have my customers generate a separate schematic page with
nothing but testpoints. The clear advantages are you can control
clearances,
claims it will
import Orcad Ver 9.X well the schematic
in this latest version of Orcad does not
come across to Protel well at all.
Bob Wolfe
- Original Message -
From: Michael Reagan (EDSI) [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Wednesday, August 21, 2002 1:59
Robert,
Update free primitives is a very good command to use. I use flawlessly on
every design. If you are getting drc errors when invoking the command then
you must have traces shorted from one pad to another.
The exact process I use is different than most others recommended practice,
here
] Revision problems
shouldn't you load the netlist AFTER the update?
else stray tracks could pick up connectivity?
i haven't found clearing nets necessary, although i do it sometime
Dennis Saputelli
Michael Reagan (EDSI) wrote:
Robert,
Update free primitives is a very good command to use
Georg wrote
I bought the upgrade and estimate to run it parallel to 99SE until the
begin
of next year.
Georg,
Some of us cant afford to run in parrallel and certainly cant afford any
more Altium Frankenstein experiments.
Mike Reagan
EDSI
This forum has really gone downhill I think its time to bail this forum and
see what is happening in the DXP forum. Can anyone post the link for the
DXP forum
Frankly Im tired of hearing , My protel doesnt work with SCSI, or cd rom ,
or doesnt run nwhen I listen to nSync in the backround on
don't have much to
say about it. (other than the I forgot if it does this...can someone
tell me? or the newbie questions which have been answered pretty darn
fast.
You take it easy Mike. Maybe we'll see ya on the DXP forum someday.
-Original Message-
From: Michael Reagan (EDSI
.
Mike
- Original Message -
From: Andrew Jenkins [EMAIL PROTECTED]
To: 'Protel EDA Forum' [EMAIL PROTECTED]
Sent: Friday, August 30, 2002 5:12 AM
Subject: Re: [PEDA] Service Pack 7 - or free DXP
-Original Message-
From: Michael Reagan (EDSI) [mailto:[EMAIL PROTECTED
Mattias Ericson wrote
Often a customer wanted to get for example 5 schematics and 1 pcb.
Eventually they
changed and it was possible to sell and upgrade individual packages.
Not only is that, there are still customers and small companies out there
that want only schematic capture tools at a
I probably would pay for SP7 with as long as they met the long list of our
requirements also.
Mike Reagan
- Original Message -
From: Dennis Saputelli [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Friday, August 30, 2002 3:00 PM
Subject: Re: [PEDA] Service Pack 7 vs
What Rob Young stated is what I have been saying for since Accel was
acquired. Just Like some of you, I am taking a very hard look at other
programs. A very hard lookMy future depends on having the right
software for my requirements not someone dictating what my requirements are.
Dennis wrote:
now such arrogance can actually be ok if they are truly visionary and
much smarter than we are (which is something i would hope to be the
case)
Well I thought they were prophets until they decided to drop ddb format
after cramming it down my throat in the first place. I was
Bob Wolfe wrote
I do feel the VeriBest router still beats Specctra though.
If you really look at this program it runs circles around
anything else for interactive routing.
Not just interactive routing , there is more to interactive routing than
placing traces. Mentor understands dedign rules
The guy said there had been a rush of demo downloads today from American
Protel users - you know who you are :)
Geez did that make me laugh I don't doubt it Their site is probably
overloaded today
Mike Reagan
EDSI
Colin,
My apologies if I am wrong about the netlist. I was unable to do anything
with it nor were any Mentor reps able to help me at the time. (JUN-July of
this year) I might attend another workshop later this month and am going to
work outside of their canned demo and get some factory
Jami wrote:
When I pointed this out to Roger on the first day of a three day
international Design Aids DS1Users Group Meeting hosted by Boeing in
Seattle Washington in the fall of 1983 (84?), he immediately left the
conference early and flew back to Southern California so that he could
Jami wrote
That is why I have floated several different proposals here in this forum,
ranging from SP7, to free upgrades to DXP (without ATS) for all who bought
into Protel 99 SE at its current level due to the fact that it actually does
have problems and these people have never received any
Subject: Re: [PEDA] So sue me ...(was:Crunch time?)
Michael,
See below,
JaMi
- Original Message -
From: Michael Reagan (EDSI) [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Tuesday, September 10, 2002 5:44 AM
Subject: Re: [PEDA] So sue me ...(was:Crunch time?)
Jami
Yea Ive had noticed that about a year ago and might have reported it, It
happens if when turn off all of the signal/plane layers. I just figured
if I never use it that mode it never crashes. Also if you turn off of all
the clearance rules it will cause a crash. There are a few other
Mark
After I thought about it a little, the inner pad actually may serve as
barrier to prevent a trace to close to the drill. Regardless,
This issue is not about removing or changing annular ring , this is about
removing unwanted pads. Annular ring is and unwanted pads are two
different
can get as much other stuf fin
there as you can, and still really see what tou are doinf as well as have
the coverage of DRC.
JaMi
- Original Message -
From: Michael Reagan (EDSI) [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Tuesday, September 17, 2002 10:15 AM
: Tuesday, September 17, 2002 6:57 PM
Subject: Re: [PEDA] Inner pad feature
On 05:49 PM 17/09/2002 -0400, Michael Reagan (EDSI) said:
Exactly JAMI
A BGA application is ideal for dumping the pad. It might make the
difference between using twice as many layers to route a BGA
Mike
The padstack
Mr. Lomax wrote:
But it does not make the gained space safe for routing, because we can
assume that, if routing density is an issue, via pads have been already
been reduced in size to the minimum annular ring necessary to avoid
breakout, as Mr. Koitmaa notes. And thus it is possible for the
Mr. Lomax wrote:
But it does not make the gained space safe for routing, because we can
assume that, if routing density is an issue, via pads have been already
been reduced in size to the minimum annular ring necessary to avoid
breakout, as Mr. Koitmaa notes. And thus it is possible for the
you can also globally change all of the nets colors using the same method
listed below then hit global. it will change all of the colors
Mike Reagan
- Original Message -
From: Brad Velander [EMAIL PROTECTED]
To: 'Protel EDA Forum' [EMAIL PROTECTED]
Sent: Wednesday, October 02, 2002
MikeR
You are doing something very wrong (somewhere) if your DDB is a 1GB. I m
working on a design with 2500 components, 4500 nets, 21000 nodes and the ddb
is only 18 meg. Yes it is slow as molasses but still only 18 meg.
MikeR if you want to send one of us your ddb , zip it , and I will be
Hello all
I have two very old PADS files dating back to 1996 not even sure what PADS
versions these are in , either Perform or Works. I only have PADS from
2.0 up which will not read these PADS job files. I need to get the ASCII
conversion for these files so that I can then read them into
Yea Jami and how do you propose to get pin 1 not reversed then populating
all of the components on the board all backwards? We call that smoke then
fire.
Mike
- Original Message -
From: JaMi Smith [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Cc: JaMi Smith [EMAIL
The only thing left now is Jun is now producing a design counter to IPC
guidelines for documentation, Primary side is on the bottom.
- Original Message -
From: Rick Wilson (Protta) [EMAIL PROTECTED]
To: 'Protel EDA Forum' [EMAIL PROTECTED]
Sent: Thursday, October 10, 2002 11:03 AM
I dont know if this topic has been covered before but. in 99SE, I set up
a hotkey (W) to PCB: PlaceTrack.I disabled W so that Windows menu does
not interfere.
When I place track using my W key it always places an invisble trace which
has NO NET assigned to it.I tried the same thing on
, but
it is not as smart for setting the right net and width etc
Dennis Saputelli
Michael Reagan (EDSI) wrote:
I dont know if this topic has been covered before but. in 99SE, I
set up
a hotkey (W) to PCB: PlaceTrack.I disabled W so that Windows menu
does
not interfere.
When I place track using my W
and thanks to you too Harry for the right answer
Mike
- Original Message -
From: Harry Selfridge [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Friday, October 25, 2002 4:56 PM
Subject: Re: [PEDA] (PEDA] PCB: place track
Well, the first thing that comes to mind is that
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