Re: [PEDA] keepoutlayer and planes ??
At 02:04 PM 11/13/01 -0600, Mark E Witherite wrote: >I've been monitoring this thread and would like to know isn't any one > worried about delamination of the PCB? I've had at lease 3 board houses > flag me about extending the copper all the way to the board edge. I suppose the board material-copper bond might not be as strong as the board material bonded to itself. Since I have never made a board with copper to the very edge (I have done extra plating on an internal slot) I don't have any experience with such a board delaminating. Essentially, the idea would be that a crack could get started at the edge, particularly if the whole edge were weak. However, the process as I suggested it would leave a few areas of no-copper at the edges where the tabs were. One likely place for some of these tabs would be the corner of the board. So there would be no place for the crack to start. IPC- explicitly allows "ground and heat sink planes to extend to the edge when required by design." (p.20) [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Re: [PEDA] keepoutlayer and planes ??
At 02:28 PM 11/12/01 -0600, Jon Elson wrote: >Abd ul-Rahman Lomax wrote: > > > It should not have been much more expensive. In fact, as I recall, > > depending on the process, panel edges plate if you don't do something to > > prevent it! > >Yes, that is true. But, because of the way boards are made, the edge of the >panel is cut away in the routing step. Yes. This is why I said that the board would need to be fabricated as a breakaway board. > It would be possible for a fabricator >to make the panel equal to the board, but then there are problems with how >to hold the board without shadowing a spot during plating, not to mention >that most shops use large panels, with several boards per panel. Yes. That is not a practical solution. To plate the edges at the same time as the holes, the board *must* be fabricated breakaway. That increases cost for routing, which should be the only increased cost except maybe a little touchup if required where the tabs broke away. If one really wanted *no* gaps in the edge, those gaps where the tabs were could be manually plated with a plating pen, practical with a relatively small run. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Brad Velander wrote: > My 2 cents worth, since we do this regularily. > > The edge plating will make a significant difference in board > emmisions with GHz frequency signals depending on the board material used. > It gets worse the higher your frequencies go. The problem is that the board > material is a dielectric and thus will conduct high freq. signals between > the copper of the other outer layers. It is essentially a waveguide. The > vias will block some of the signal but the higher the frequency the closer > you have to space the vias until you are almost hole to hole and your board > has no structural strength along the line of vias. > The additional cost for the edge plating should be minimal. The only > operation or labor is to route the board edges before doing the intitial > electoless plating, instead of doing it after the board is processed. There > is no additional work or effort unless there is also still unplated routing > to do after the board is processed. Other than the small boards not being part of a larger panel anymore, the other problem is how do you hold the board for further processing (especially solder mask and legend)? You'd need to arrange alignment holes for the fab house to use that would be a permanent part of the board. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Brad Velander wrote: > My 2 cents worth, since we do this regularily. > > The edge plating will make a significant difference in board > emmisions with GHz frequency signals depending on the board material used. > It gets worse the higher your frequencies go. The problem is that the board > material is a dielectric and thus will conduct high freq. signals between > the copper of the other outer layers. It is essentially a waveguide. Yes, undoubtedly, but at what frequency? I'm not an RF engineer, so I don't know what effect the dielectric has on the usable frequency of the waveguide, but it must be very high, I'm sure in excess of 20 GHz! All PCB dielectrics are REAL lossy at that frequency, so not much signal will escape. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Abd ul-Rahman Lomax wrote: > It should not have been much more expensive. In fact, as I recall, > depending on the process, panel edges plate if you don't do something to > prevent it! Yes, that is true. But, because of the way boards are made, the edge of the panel is cut away in the routing step. It would be possible for a fabricator to make the panel equal to the board, but then there are problems with how to hold the board without shadowing a spot during plating, not to mention that most shops use large panels, with several boards per panel. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 11:26 AM 11/12/01 -0700, Bob Fearon wrote: >Guts > Sorry to mislead, the additional cost came from routing the boards out of >the panels > and then plating. Ah. *That's why it was so expensive.* A whole extra step to be performed on a bunch of small boards instead of on the panel. I'd really try to avoid doing it that way. It would not only be two additional plating steps but also the top and bottom surfaces would have to be masked. Instead, I'd determine a few places, if possible, where an opening in the edge plating would be tolerable and leave those as tabs. The internal routing would be done before electroless copper, so all the edges would be plated in the same step as the holes. > Mindful that edgr plating is not a "linear" or accurate as >standard > thru hole plating. That does not make sense to me. Plating of a copper-free board surface is done by first using electroless copper which chemically deposits a *very* thin film of copper on the surface, then it is electroplated up, typically to one ounce added copper in order to get about 1 mil of copper minimum in the holes. The rest of the board gets about 1.4 mils. The holes do not plate as easily or as reliably as the board surface, and this gets worse the smaller the holes. So edge plating should be pretty good, being more like board surface than like the interior of holes. But the accuracy of the plating would not be of much importance. Even small voids in the plating might be harmless. The largest difficulty in plating the edges would be the roughness of the edges, the smoother the edges before plating, the more uniform the plating. Still, I'd think that plating accuracy would be better than in the holes. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Guts Sorry to mislead, the additional cost came from routing the boards out of the panels and then plating. Mindful that edgr plating is not a "linear" or accurate as standard thru hole plating. Bob Fearon Brad Velander wrote: > My 2 cents worth, since we do this regularily. > > The edge plating will make a significant difference in board > emmisions with GHz frequency signals depending on the board material used. > It gets worse the higher your frequencies go. The problem is that the board > material is a dielectric and thus will conduct high freq. signals between > the copper of the other outer layers. It is essentially a waveguide. The > vias will block some of the signal but the higher the frequency the closer > you have to space the vias until you are almost hole to hole and your board > has no structural strength along the line of vias. > The additional cost for the edge plating should be minimal. The only > operation or labor is to route the board edges before doing the intitial > electoless plating, instead of doing it after the board is processed. There > is no additional work or effort unless there is also still unplated routing > to do after the board is processed. > > Sincerely, > Brad Velander. > > Lead PCB Designer > Norsat International Inc. > #300 - 4401 Still Creek Drive, > Burnaby, B.C., Canada, V5C 6G9. > Tel (604) 292-9089 (direct line) > Fax (604) 292-9010 > Website: www.norsat.com > > -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: Friday, November 09, 2001 12:22 PM > To: Protel EDA Forum > Subject: Re: [PEDA] keepoutlayer and planes ?? > > At 09:44 AM 11/9/01 -0700, Bob Fearon wrote: > >Abdul-Rahman > > Yes I have seen an inner plane layer come all the way out to an edge. > > The design was supposed to be "better for RF", but made no difference > > in board performance. The two outside layers were plated aound the > edge > > and shorted ( on purpose ) to the inner layer. This was a nightmare to > > build and cost "extra". > > The same performance was achieved by placing a row of vias 100 mils > > from the edge on a "regular" board, at a much lower cost. > > This is not an example of what I asked for. Instead, this was a board > deliberately fabricated without edge clearance. Yes, it was not a great > idea from the start, as anyone who knows HF design would have anticipated, > unless -- maybe -- one was trying to squeeze the last percent out of noise > emissions *and* board space was very limited. I could see doing this with > very small PCBs, where the via ring would take up an appreciable percentage > of the board space. > > It should not have been much more expensive. In fact, as I recall, > depending on the process, panel edges plate if you don't do something to > prevent it! (The same electroless copper used to plate the inside of holes > also plates the panel edge, I'd think, I don't remember actually seeing > this; however, that edge is normally routed away when all the processing is > done, leaving the unplated edges that we normally see. So to accomplish > this relatively inexpensively, one would route the boards as one routes a > breakaway board *before* going to the electroless copper; this would leave > some unplated tabs but one might hide the unplated tabs behind mounting > holes) > > Edge effect with regard to radiated noise is a controversial subject, but > actually plating the board edge I have never before seen suggested. > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
My experience with planes-to-the-edge has been this... to date, no one has ever sent me a board that has both power and ground all the way out to the edge whether I pulled the planes back in the gerbers or not. It appears to be pretty much SOP. However, I have received almost all the boards that have multiple ground planes only- no power plane at all- that came back with the planes out to the edge. I actually wanted them that way, but I didn't specify other than not pulling the planes back on the gerbers. I never really thought about it too much, but that is quite a decision on the board house's part. Luckily for me, they seem to be able to determine which designs are RF and which are Digital and such. One pet peeve of mine- I've had it happen twice on high-current designs- a board house adding thermal reliefs to all the through-hole components. A near disaster. Needless to say, we don't use those houses any more. Funny thing is, they acted very baffled as to why we would be angry about that. As for plating edges, I have had this done several times. I don't believe it's all that uncommon. In a case with RF components near an edge, and the board mounting surface being a chunk of aluminum that follows the perimeter underneath the board, the RF can flow right off the edge of the board and down to the aluminum case "ground plane" with very little inductance. This is especially effective with thicker boards, where proper GND via diameters can get pretty large. I have seen a few cases where edge plating seemed to really make a difference. A well placed set of stitching holes appears to be almost equally effective though in the majority of situations, and I generally get by with that. Funny you should mention this right now, I was kicking around the idea of plating an edge of our new receiver board and see if it accidentally had any effect. -Frank At 03:21 PM 11/9/2001 -0500, Abdulrahman Lomax wrote: At 09:44 AM 11/9/01 -0700, Bob Fearon wrote: Abdul-Rahman Yes I have seen an inner plane layer come all the way out to an edge. The design was supposed to be "better for RF", but made no difference in board performance. The two outside layers were plated aound the edge and shorted ( on purpose ) to the inner layer. This was a nightmare to build and cost "extra". The same performance was achieved by placing a row of vias 100 mils from the edge on a "regular" board, at a much lower cost. This is not an example of what I asked for. Instead, this was a board deliberately fabricated without edge clearance. Yes, it was not a great idea from the start, as anyone who knows HF design would have anticipated, unless -- maybe -- one was trying to squeeze the last percent out of noise emissions *and* board space was very limited. I could see doing this with very small PCBs, where the via ring would take up an appreciable percentage of the board space. It should not have been much more expensive. In fact, as I recall, depending on the process, panel edges plate if you don't do something to prevent it! (The same electroless copper used to plate the inside of holes also plates the panel edge, I'd think, I don't remember actually seeing this; however, that edge is normally routed away when all the processing is done, leaving the unplated edges that we normally see. So to accomplish this relatively inexpensively, one would route the boards as one routes a breakaway board *before* going to the electroless copper; this would leave some unplated tabs but one might hide the unplated tabs behind mounting holes) Edge effect with regard to radiated noise is a controversial subject, but actually plating the board edge I have never before seen suggested. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA Frank Gilley Dell-Star Technologies (918) 838-1973 Phone (918) 838-8814 Fax [EMAIL PROTECTED] http://www.dellstar.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
My 2 cents worth, since we do this regularily. The edge plating will make a significant difference in board emmisions with GHz frequency signals depending on the board material used. It gets worse the higher your frequencies go. The problem is that the board material is a dielectric and thus will conduct high freq. signals between the copper of the other outer layers. It is essentially a waveguide. The vias will block some of the signal but the higher the frequency the closer you have to space the vias until you are almost hole to hole and your board has no structural strength along the line of vias. The additional cost for the edge plating should be minimal. The only operation or labor is to route the board edges before doing the intitial electoless plating, instead of doing it after the board is processed. There is no additional work or effort unless there is also still unplated routing to do after the board is processed. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. #300 - 4401 Still Creek Drive, Burnaby, B.C., Canada, V5C 6G9. Tel (604) 292-9089 (direct line) Fax (604) 292-9010 Website: www.norsat.com -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Friday, November 09, 2001 12:22 PM To: Protel EDA Forum Subject: Re: [PEDA] keepoutlayer and planes ?? At 09:44 AM 11/9/01 -0700, Bob Fearon wrote: >Abdul-Rahman > Yes I have seen an inner plane layer come all the way out to an edge. > The design was supposed to be "better for RF", but made no difference > in board performance. The two outside layers were plated aound the edge > and shorted ( on purpose ) to the inner layer. This was a nightmare to > build and cost "extra". > The same performance was achieved by placing a row of vias 100 mils > from the edge on a "regular" board, at a much lower cost. This is not an example of what I asked for. Instead, this was a board deliberately fabricated without edge clearance. Yes, it was not a great idea from the start, as anyone who knows HF design would have anticipated, unless -- maybe -- one was trying to squeeze the last percent out of noise emissions *and* board space was very limited. I could see doing this with very small PCBs, where the via ring would take up an appreciable percentage of the board space. It should not have been much more expensive. In fact, as I recall, depending on the process, panel edges plate if you don't do something to prevent it! (The same electroless copper used to plate the inside of holes also plates the panel edge, I'd think, I don't remember actually seeing this; however, that edge is normally routed away when all the processing is done, leaving the unplated edges that we normally see. So to accomplish this relatively inexpensively, one would route the boards as one routes a breakaway board *before* going to the electroless copper; this would leave some unplated tabs but one might hide the unplated tabs behind mounting holes) Edge effect with regard to radiated noise is a controversial subject, but actually plating the board edge I have never before seen suggested. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 09:44 AM 11/9/01 -0700, Bob Fearon wrote: >Abdul-Rahman > Yes I have seen an inner plane layer come all the way out to an edge. > The design was supposed to be "better for RF", but made no difference > in board performance. The two outside layers were plated aound the edge > and shorted ( on purpose ) to the inner layer. This was a nightmare to > build and cost "extra". > The same performance was achieved by placing a row of vias 100 mils > from the edge on a "regular" board, at a much lower cost. This is not an example of what I asked for. Instead, this was a board deliberately fabricated without edge clearance. Yes, it was not a great idea from the start, as anyone who knows HF design would have anticipated, unless -- maybe -- one was trying to squeeze the last percent out of noise emissions *and* board space was very limited. I could see doing this with very small PCBs, where the via ring would take up an appreciable percentage of the board space. It should not have been much more expensive. In fact, as I recall, depending on the process, panel edges plate if you don't do something to prevent it! (The same electroless copper used to plate the inside of holes also plates the panel edge, I'd think, I don't remember actually seeing this; however, that edge is normally routed away when all the processing is done, leaving the unplated edges that we normally see. So to accomplish this relatively inexpensively, one would route the boards as one routes a breakaway board *before* going to the electroless copper; this would leave some unplated tabs but one might hide the unplated tabs behind mounting holes) Edge effect with regard to radiated noise is a controversial subject, but actually plating the board edge I have never before seen suggested. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Abdul-Rahman Yes I have seen an inner plane layer come all the way out to an edge. The design was supposed to be "better for RF", but made no difference in board performance. The two outside layers were plated aound the edge and shorted ( on purpose ) to the inner layer. This was a nightmare to build and cost "extra". The same performance was achieved by placing a row of vias 100 mils from the edge on a "regular" board, at a much lower cost. Bob Fearon Abd ul-Rahman Lomax wrote: > At 05:32 PM 11/8/01 -0500, Mike Reagan wrote: > > >you scare me man thinking that you are design aircraft components and dont > >know how to use the progam I think you better fligt test it > > Knowing how to use the program is a convenience, not a necessity. The > necessity is to know how to inspect the gerbers or films and the board itself. > > Let me put it this way. If I want reliability of a pcb, I will prefer it to > be designed by someone who knows electronics and reliability issues, but > who is a beginner with a piece of software he uses, than by one for whom > the reverse is true. > > (I don't think Mr. Robison is designing "aircraft components." Last we > spoke, he was designing equipment that might fly *on* a plane, but it does > not *fly* the plane. If one of his boards fails, if I am correct, it will > be a nuisance, not a disaster.) > > In my experience, boards for hi-rel usage (for me, it has been space > flight) are reviewed through several different stages, at least. While it > is obviously best and safest to get the board right in the first place > (after all, there is a statistical possibility that the later safeguards > could all fail), the knowledge that negative planes should not go to the > board edge is widespread. As I mentioned previously, most board houses, > perhaps all, will already create an edge clearance if you don't put one > there and you don't clearly specify that you *don't* want one. They have > been dealing with gerbers with no edge clearance for years, but they have > probably never encountered a request for planes to go to the edge. > > Has anyone reading this received fabricated boards with no inner plane > clearance? Was it from an established fabricator? (I'd be surprised if it > *never* happened, but I would also be surprised if it was at all common.) > > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
On 10:37 AM 9/11/2001 +, Stephen Casey said: > > Has anyone reading this received fabricated boards with no inner plane > > clearance? Was it from an established fabricator? (I'd be surprised if it > > *never* happened, but I would also be surprised if it was at all common.) > >Abd, > >Yes, I have received boards with no clearance. My mistake on my first Protel >job, but the board house didn't spot/query it. We stopped using them for >another reason, and the new fabricator is (so far) superb. In fact, I posted >a question to this list about board edge clearances a while back. I did add >the clearances to the job this time, but they queried and fixed another >issue that the first company would almost certainly have ignored. It would >be very nice if Protel could add some DRC features to trap this. > >Steve. I am giggling over this - not because it is a bad idea but more that Protel added a warning that there were entities on internal planes layers in lieu of full DRC for the planes. So now we get a warning that we have tracks on the internal planes and then along comes Steve and wants them to add a warning if we *don't* have tracks on the internal layers! Damed if we do, damed if we don't. Actually I think it would be a good idea - since we have poor plane DRC adding a warning that there does not appear to be a plane backoff would be a worthwhile addition. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
> Has anyone reading this received fabricated boards with no inner plane > clearance? Was it from an established fabricator? (I'd be surprised if it > *never* happened, but I would also be surprised if it was at all common.) Abd, Yes, I have received boards with no clearance. My mistake on my first Protel job, but the board house didn't spot/query it. We stopped using them for another reason, and the new fabricator is (so far) superb. In fact, I posted a question to this list about board edge clearances a while back. I did add the clearances to the job this time, but they queried and fixed another issue that the first company would almost certainly have ignored. It would be very nice if Protel could add some DRC features to trap this. Steve. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 07:59 PM 8/11/01 -0600, you wrote: >Someone please correct me if I am wrong, Consider yourself corrected :-) Ian Wilson >but I thought that the power plane >clearance rule in the manufacturing section also included clearance from the >keepout layer around the edge of the board. So far, I have never drawn any >copper on the internal planes to keep them away from the edge of the board, >and they have all turned out with clearance. This may be from the board >house changing this, but I figured I would have heard something. >Nick Cobb * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
i bet they pulled them back as SOP Dennis Saputelli Nicholas Cobb wrote: > > Someone please correct me if I am wrong, but I thought that the power plane > clearance rule in the manufacturing section also included clearance from the > keepout layer around the edge of the board. So far, I have never drawn any > copper on the internal planes to keep them away from the edge of the board, > and they have all turned out with clearance. This may be from the board > house changing this, but I figured I would have heard something. > Nick Cobb > - Original Message - > From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]> > To: "Protel EDA Forum" <[EMAIL PROTECTED]> > Sent: Thursday, November 08, 2001 7:34 PM > Subject: Re: [PEDA] keepoutlayer and planes ?? > > > At 06:02 PM 11/8/01 -0600, Jon Elson wrote: > > > What you need to do is place rectangular fills all around the edges > > >of the board to hold the power planes out of that area. This is what > I've > > >been doing for years. > > > > The practice of copying the outline track to the inner planes, as > described > > by others, and then blowing it out with a global edit to, say, 50 mils, is > > simpler and, with a complex outline, faster. > > > > Mr Elson made some good points about how to do gerber import. One note I > > would add is that Protel, if possible, flashes fills, it does not "fill" > > them, so when they are reimported, they become pads. Yes, pads. This > > introduces certain complications, trying to view solder mask imports. > > > > It's better, I suggest, to view gerbers in CAMtastic or another Gerber > > viewer. But it can be convenient to view them in Protel, and the ability > to > > import gerber is a real plus for many reasons. > > > > > > > > > > [EMAIL PROTECTED] > > Abdulrahman Lomax > > Easthampton, Massachusetts USA -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Someone please correct me if I am wrong, but I thought that the power plane clearance rule in the manufacturing section also included clearance from the keepout layer around the edge of the board. So far, I have never drawn any copper on the internal planes to keep them away from the edge of the board, and they have all turned out with clearance. This may be from the board house changing this, but I figured I would have heard something. Nick Cobb - Original Message - From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Thursday, November 08, 2001 7:34 PM Subject: Re: [PEDA] keepoutlayer and planes ?? > At 06:02 PM 11/8/01 -0600, Jon Elson wrote: > > What you need to do is place rectangular fills all around the edges > >of the board to hold the power planes out of that area. This is what I've > >been doing for years. > > The practice of copying the outline track to the inner planes, as described > by others, and then blowing it out with a global edit to, say, 50 mils, is > simpler and, with a complex outline, faster. > > Mr Elson made some good points about how to do gerber import. One note I > would add is that Protel, if possible, flashes fills, it does not "fill" > them, so when they are reimported, they become pads. Yes, pads. This > introduces certain complications, trying to view solder mask imports. > > It's better, I suggest, to view gerbers in CAMtastic or another Gerber > viewer. But it can be convenient to view them in Protel, and the ability to > import gerber is a real plus for many reasons. > > > > > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 06:02 PM 11/8/01 -0600, Jon Elson wrote: > What you need to do is place rectangular fills all around the edges >of the board to hold the power planes out of that area. This is what I've >been doing for years. The practice of copying the outline track to the inner planes, as described by others, and then blowing it out with a global edit to, say, 50 mils, is simpler and, with a complex outline, faster. Mr Elson made some good points about how to do gerber import. One note I would add is that Protel, if possible, flashes fills, it does not "fill" them, so when they are reimported, they become pads. Yes, pads. This introduces certain complications, trying to view solder mask imports. It's better, I suggest, to view gerbers in CAMtastic or another Gerber viewer. But it can be convenient to view them in Protel, and the ability to import gerber is a real plus for many reasons. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Just as a note, I have forgotten to "pull back" the planes on two different designs over the past five years. Both times, I received the boards "as drawn" with copper right up to the board edge. No flags were raised, and no questions were asked. This is from a large, high-quality fabrication house in the Midwestern US. They questioned other Gerber or design issues, but not the plane to board edge clearance. In their defense, on both occasions these were quick-turn orders (3 day). On the other hand, I have had other shops call to ask if they could increase the clearance from what I already had drawn. My point is that, yes, the majority of fabricators will question a design with no clearance. However, I would not go to the point of taking it completely for granted. Contact me off-line if you want the name of the board shop that let the two designs go through with no clearance. Since it was ultimately my own mistake and not theirs, I don't want to give the impression that I'm passing the blame. Mark Richards CAD Designer ON Semiconductor Phone: 602.244.7267 Fax: 602.244.6716 Pager: 866.208.9913 - Original Message - From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Thursday, November 08, 2001 4:26 PM Subject: Re: [PEDA] keepoutlayer and planes ?? > At 05:32 PM 11/8/01 -0500, Mike Reagan wrote: > > >you scare me man thinking that you are design aircraft components and dont > >know how to use the progam I think you better fligt test it > > Knowing how to use the program is a convenience, not a necessity. The > necessity is to know how to inspect the gerbers or films and the board itself. > > Let me put it this way. If I want reliability of a pcb, I will prefer it to > be designed by someone who knows electronics and reliability issues, but > who is a beginner with a piece of software he uses, than by one for whom > the reverse is true. > > (I don't think Mr. Robison is designing "aircraft components." Last we > spoke, he was designing equipment that might fly *on* a plane, but it does > not *fly* the plane. If one of his boards fails, if I am correct, it will > be a nuisance, not a disaster.) > > In my experience, boards for hi-rel usage (for me, it has been space > flight) are reviewed through several different stages, at least. While it > is obviously best and safest to get the board right in the first place > (after all, there is a statistical possibility that the later safeguards > could all fail), the knowledge that negative planes should not go to the > board edge is widespread. As I mentioned previously, most board houses, > perhaps all, will already create an edge clearance if you don't put one > there and you don't clearly specify that you *don't* want one. They have > been dealing with gerbers with no edge clearance for years, but they have > probably never encountered a request for planes to go to the edge. > > Has anyone reading this received fabricated boards with no inner plane > clearance? Was it from an established fabricator? (I'd be surprised if it > *never* happened, but I would also be surprised if it was at all common.) > > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Robison Michael R CNIN wrote: > hello, > > we're duplicating some legacy boards. in order to avoid flight testing i > hand-routed the traces to match the old artwork. i believe that i just > came close to making a SERIOUS mistake. i used the pcb wizard to > generate the board but then hand-editted the various notches in it. the > keepout was in the way and i was going to hand rout everything so i > deleted it. > > there is a power and ground plane on this board and there are machined > metal card guides that get mounted to the board. does this sound ugly? > i'm thinking (i know that's rare ;-) that by deleting the keepoutlayer i've > let the planes come right out to the edge of the board. is this correct? > if so, i've created a potential short between power and ground when the > card guides are attached to the board. I don't think the keepout prevents the internal power planes from existing under the keepout. (I think it will prevent an outer signal layer pour in that area.) What you need to do is place rectangular fills all around the edges of the board to hold the power planes out of that area. This is what I've been doing for years. > 2. after simply drawing the keepoutlayer back in, i am not seeing the > dark green power plane void outside the keepoutlayer. does this mean > that i still have the power plane running right to the board edge? Yes, I believe so. > > 3. without a keepoutlayer do the planes extend right to the board edge? > > 4. how do i recess the power and ground planes back in a few mils on > this board? See above. > 5. can i visibly see the planes recessed back from the card edge in protel > or do i need to generate gerbers and use camtastic to do that? Not really. You will see your fills, if you have them in ful mode, or just the outline of them if fills are in draft mode. My technique is this : 1. Generate Gerbers 2. Create "new" blank PCB 3. gang import (not exact term, but close) the gerbers onto this new PCB (do NOT make my mistake of importing getbers on TOP of existing PCB file!) 4. Shft/S to go to single layer mode 5. Now, you can go through the board, layer by layer with the + and - keys, and hit shift/S if you lose track of where you are spatially in the board. You can even use the report/measure function to measure pad sizes and clearances in the power or other inner layers to verify that your padstack settings are working right. Note that having the real PCB file open at the same time sets the gerber apertures so the gerber import works right. If you don't do this, the apertures may be set from the last board viewed, and a gerber import will make a picture that looks very wrong. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 02:00 PM 11/8/01 -0800, Dennis Saputelli wrote: >technically and to be pedantic you should say Place Line (not track) It is not merely pedantic. A very frequent question is "I'm trying to place a wide track (perhaps for the power plane clearance) and I can't place it on an inner plane and besides even though I set the width at 50 mils, it keeps coming out 10 mils. What gives?" Often it is a long-time Protel user, familiar with an earlier version, recently upgraded, who asks this. He is using the old command Place/Track (P-T) to place the line, not noticing that there is no more "Place Track" command. Instead there is Place/ interactive rouTing, same hotkeys, which follows width rules and which will only place track on copper layers, and Place Line, which has no such restrictions. It was, by the way, a kindness for Protel to keep P-T working for the most common line placement operation. I remember when Tango changed many of their hotkey assignments, ostensibly to make PCB match schematic, and it took me years to unlearn the old and learn the new. And the irony was that, in the end, PCB and Schematic still did not match, and so there was the additional problem that similar functions in PCB and Schematic had different sequences. One of the common PCB sequences, in particular, would send you into a fairly long and not interruptable routine if you hit it in Schematic. And then there was incompatibility between Schematic itself and the schematic library editor. I once brought this up with Jeannine, the Tango support manager, and she simply noted "the guy who did that is no longer with the company" [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 05:32 PM 11/8/01 -0500, Mike Reagan wrote: >you scare me man thinking that you are design aircraft components and dont >know how to use the progam I think you better fligt test it Knowing how to use the program is a convenience, not a necessity. The necessity is to know how to inspect the gerbers or films and the board itself. Let me put it this way. If I want reliability of a pcb, I will prefer it to be designed by someone who knows electronics and reliability issues, but who is a beginner with a piece of software he uses, than by one for whom the reverse is true. (I don't think Mr. Robison is designing "aircraft components." Last we spoke, he was designing equipment that might fly *on* a plane, but it does not *fly* the plane. If one of his boards fails, if I am correct, it will be a nuisance, not a disaster.) In my experience, boards for hi-rel usage (for me, it has been space flight) are reviewed through several different stages, at least. While it is obviously best and safest to get the board right in the first place (after all, there is a statistical possibility that the later safeguards could all fail), the knowledge that negative planes should not go to the board edge is widespread. As I mentioned previously, most board houses, perhaps all, will already create an edge clearance if you don't put one there and you don't clearly specify that you *don't* want one. They have been dealing with gerbers with no edge clearance for years, but they have probably never encountered a request for planes to go to the edge. Has anyone reading this received fabricated boards with no inner plane clearance? Was it from an established fabricator? (I'd be surprised if it *never* happened, but I would also be surprised if it was at all common.) [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
At 01:40 PM 11/8/01 -0800, Dwight wrote: >I didn't know about putting traces along the edges, but the board shop >called & asked if we'd like them to pull the planes back from the board >edges! So having a good board shop can pay off... I've understood that board shops know that you *never* want planes to go all the way to the edge, so if they see a board which could fab with exposed copper at the edge, they would pull it back sufficiently to guarantee that it was clear. If you design a setback into your board, they will use that unless they consider it insufficient to guarantee clearance. It is obviously good design practice to make the clearance explicit. Protel did not factor for this in designing the DRC. There is, actually, no defined board edge definition. There should be a layer hard-coded to board outline. This would allow an edge clearance design rule, and then primitives on the inner plane layers which did not bite into the plane beyond that clearance would not, properly, create the "primitives on inner plane" warning that we now get whenever we design an inner plane correctly [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
you scare me man thinking that you are design aircraft components and dont know how to use the progam I think you better fligt test it Mike Reagan EDSI - Original Message - From: Robison Michael R CNIN <[EMAIL PROTECTED]> To: 'Protel EDA Forum' <[EMAIL PROTECTED]> Sent: Thursday, November 08, 2001 5:18 PM Subject: Re: [PEDA] keepoutlayer and planes ?? > thanks to everyone that posted on this. i understand > now. it would have been inconceivably horrible if we > had built and sold off on defective boards. these parts > go in navy planes. and they could have very possibly > passed functional testing and then started failing left > and right once the planes started vibrating them around. > thank god i don't design suspension bridges. ;-) > > there's irony there, i guess... you spend so much time > sweating the details and then you let some big gaping > bug in the design slip right past you. > > thanks again, miker > > -Original Message- > From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] > Sent: Thursday, November 08, 2001 5:00 PM > To: Protel EDA Forum > Subject: Re: [PEDA] keepoutlayer and planes ?? > > > technically and to be pedantic you should say Place Line (not track) > Dennis Saputelli > > Ian Wilson wrote: > > > > On 03:29 PM 8/11/2001 -0500, Robison Michael R CNIN said: > > >hello, > > > > > >my questions: > > > > > >1. the dark green i'm seeing represents the "negative", or holes, in the > > >power plane, correct? > > > > Correct > > > > >2. after simply drawing the keepoutlayer back in, i am not seeing the > > >dark green power plane void outside the keepoutlayer. does this mean > > >that i still have the power plane running right to the board edge? > > > > Keepout does not affect planes. > > > > >3. without a keepoutlayer do the planes extend right to the board edge? > > > > With or without the keepout - Yes, planes extend to the edge. > > > > >4. how do i recess the power and ground planes back in a few mils on > > >this board? > > > > Use tracks on the plane layer. The simplest method is to use select all > > the board outline tracks and the use the Paste Special to paste onto the > > current layer, changing the layer to each of the plane layers and > > pasting. Then de-select all the tracks on the board outline layer, > leaving > > only the tracks on the plane layers selected, and then globally change the > > selected track widths to double your backoff - so a 50 mil track gives a > 25 > > mil backoff. You can go a bit higher but usually not necessary. > > > > >5. can i visibly see the planes recessed back from the card edge in > protel > > >or do i need to generate gerbers and use camtastic to do that? > > > > Yes see point 4) > > > > Ian Wilson > > -- > ___ > www.integratedcontrolsinc.comIntegrated Controls, Inc. >tel: 415-647-04802851 21st Street > fax: 415-647-3003San Francisco, CA 94110 > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
thanks to everyone that posted on this. i understand now. it would have been inconceivably horrible if we had built and sold off on defective boards. these parts go in navy planes. and they could have very possibly passed functional testing and then started failing left and right once the planes started vibrating them around. thank god i don't design suspension bridges. ;-) there's irony there, i guess... you spend so much time sweating the details and then you let some big gaping bug in the design slip right past you. thanks again, miker -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] Sent: Thursday, November 08, 2001 5:00 PM To: Protel EDA Forum Subject: Re: [PEDA] keepoutlayer and planes ?? technically and to be pedantic you should say Place Line (not track) Dennis Saputelli Ian Wilson wrote: > > On 03:29 PM 8/11/2001 -0500, Robison Michael R CNIN said: > >hello, > > > >my questions: > > > >1. the dark green i'm seeing represents the "negative", or holes, in the > >power plane, correct? > > Correct > > >2. after simply drawing the keepoutlayer back in, i am not seeing the > >dark green power plane void outside the keepoutlayer. does this mean > >that i still have the power plane running right to the board edge? > > Keepout does not affect planes. > > >3. without a keepoutlayer do the planes extend right to the board edge? > > With or without the keepout - Yes, planes extend to the edge. > > >4. how do i recess the power and ground planes back in a few mils on > >this board? > > Use tracks on the plane layer. The simplest method is to use select all > the board outline tracks and the use the Paste Special to paste onto the > current layer, changing the layer to each of the plane layers and > pasting. Then de-select all the tracks on the board outline layer, leaving > only the tracks on the plane layers selected, and then globally change the > selected track widths to double your backoff - so a 50 mil track gives a 25 > mil backoff. You can go a bit higher but usually not necessary. > > >5. can i visibly see the planes recessed back from the card edge in protel > >or do i need to generate gerbers and use camtastic to do that? > > Yes see point 4) > > Ian Wilson -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
technically and to be pedantic you should say Place Line (not track) Dennis Saputelli Ian Wilson wrote: > > On 03:29 PM 8/11/2001 -0500, Robison Michael R CNIN said: > >hello, > > > >my questions: > > > >1. the dark green i'm seeing represents the "negative", or holes, in the > >power plane, correct? > > Correct > > >2. after simply drawing the keepoutlayer back in, i am not seeing the > >dark green power plane void outside the keepoutlayer. does this mean > >that i still have the power plane running right to the board edge? > > Keepout does not affect planes. > > >3. without a keepoutlayer do the planes extend right to the board edge? > > With or without the keepout - Yes, planes extend to the edge. > > >4. how do i recess the power and ground planes back in a few mils on > >this board? > > Use tracks on the plane layer. The simplest method is to use select all > the board outline tracks and the use the Paste Special to paste onto the > current layer, changing the layer to each of the plane layers and > pasting. Then de-select all the tracks on the board outline layer, leaving > only the tracks on the plane layers selected, and then globally change the > selected track widths to double your backoff - so a 50 mil track gives a 25 > mil backoff. You can go a bit higher but usually not necessary. > > >5. can i visibly see the planes recessed back from the card edge in protel > >or do i need to generate gerbers and use camtastic to do that? > > Yes see point 4) > > Ian Wilson -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Even without the card guides, you could get a short from slivers of copper left when the boards are cut. I was lucky -- on my first board with planes, I didn't know about putting traces along the edges, but the board shop called & asked if we'd like them to pull the planes back from the board edges! So having a good board shop can pay off... > -Original Message- > From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]] > Sent: Thursday, November 08, 2001 12:30 PM > ... I've let the planes come right out to the edge of the board. > ... If so, i've created a potential short between power and > ground when the card guides are attached to the board. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
Robison Michael R CNIN wrote: > my questions: > > 1. the dark green i'm seeing represents the "negative", or holes, in the > power plane, correct? Yes > > 2. after simply drawing the keepoutlayer back in, i am not seeing the > dark green power plane void outside the keepoutlayer. does this mean > that i still have the power plane running right to the board edge? Yes - the power planes extend to the edge of the universe :-) The keepout boundary has no effect on them. > > 3. without a keepoutlayer do the planes extend right to the board edge? Far beyond it. > > 4. how do i recess the power and ground planes back in a few mils on > this board? Draw tracks on the plane layers, on or inside the board boundaries, to keep the copper of that plane away from the edges. > > 5. can i visibly see the planes recessed back from the card edge in protel > or do i need to generate gerbers and use camtastic to do that? If you put tracks around the edges you will see them in Protel. -- Peter Bennett TRIUMF 4004 Wesbrook Mall, Vancouver, BC, Canada GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
On 03:29 PM 8/11/2001 -0500, Robison Michael R CNIN said: >hello, > >my questions: > >1. the dark green i'm seeing represents the "negative", or holes, in the >power plane, correct? Correct >2. after simply drawing the keepoutlayer back in, i am not seeing the >dark green power plane void outside the keepoutlayer. does this mean >that i still have the power plane running right to the board edge? Keepout does not affect planes. >3. without a keepoutlayer do the planes extend right to the board edge? With or without the keepout - Yes, planes extend to the edge. >4. how do i recess the power and ground planes back in a few mils on >this board? Use tracks on the plane layer. The simplest method is to use select all the board outline tracks and the use the Paste Special to paste onto the current layer, changing the layer to each of the plane layers and pasting. Then de-select all the tracks on the board outline layer, leaving only the tracks on the plane layers selected, and then globally change the selected track widths to double your backoff - so a 50 mil track gives a 25 mil backoff. You can go a bit higher but usually not necessary. >5. can i visibly see the planes recessed back from the card edge in protel >or do i need to generate gerbers and use camtastic to do that? Yes see point 4) Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] keepoutlayer and planes ??
draw pimitives (lines) on the planes around the perimeter to exclude copper in those areas the keepout doesn't limit the plane copper you generally want more than a few mils back off from the boundary, we usually place a 50 mil line on the center of the outline on the plane layer we generally do not use the keepout for the outline, sometimes they coincide, sometimes you want the keepout a little smaller or just different to avoid redrawing all the plane primitives just copy them and paste on current layer (the other plane(s) the keepout generally, at least for us, has no significance to the board shop good luck Dennis Saputelli Robison Michael R CNIN wrote: > > hello, > > we're duplicating some legacy boards. in order to avoid flight testing i > hand-routed the traces to match the old artwork. i believe that i just > came close to making a SERIOUS mistake. i used the pcb wizard to > generate the board but then hand-editted the various notches in it. the > keepout was in the way and i was going to hand rout everything so i > deleted it. > > there is a power and ground plane on this board and there are machined > metal card guides that get mounted to the board. does this sound ugly? > i'm thinking (i know that's rare ;-) that by deleting the keepoutlayer i've > let the planes come right out to the edge of the board. is this correct? > if so, i've created a potential short between power and ground when the > card guides are attached to the board. > > i put the keepoutlayer back on there, but i'm nervous. when i add the > power plane to the viewable layers, the only place it is evident is around > the pads and vias, where a dark green edge appears to isolate them. > pads that are supposed to be tied to power have a broken circle out > away from them a bit. but the dark green vcc "void" hasn't appeared > outside my keepoutlayer. i get the feeling that putting the keepoutlayer > back in there has not cured my problem. > > my questions: > > 1. the dark green i'm seeing represents the "negative", or holes, in the > power plane, correct? > > 2. after simply drawing the keepoutlayer back in, i am not seeing the > dark green power plane void outside the keepoutlayer. does this mean > that i still have the power plane running right to the board edge? > > 3. without a keepoutlayer do the planes extend right to the board edge? > > 4. how do i recess the power and ground planes back in a few mils on > this board? > > 5. can i visibly see the planes recessed back from the card edge in protel > or do i need to generate gerbers and use camtastic to do that? > > thank you, miker -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
