[casper] sysgen GUI socket timeout

Hi CASPERites, In recent versions of Vivado on Ubuntu 18.04 (and probably some other versions) you might find you run into an error about the sysgen GUI timing out when opening a model. You might get the same error when trying to double-click Xilinx blocks in simulink, or maybe an error about recu

Re: [casper] RE: Matlab Toolbox Requirements

Just following up on this, because I just did something reckless and actually bought a MATLAB license. I can compile a simple design with some counters and yellow blocks with just MATLAB, Simulink, and Fixed Point Designer toolbox. This is the absolute minimum to get anything to work. (The UFix/Fi

Re: [casper] (Red Pitaya 125-14) RuntimeError: no programming informs yet. Odd?

Hi Lukas, I think while you might be able to compile vivado projects and make fpg files with the webpack license, I don't think you'll be able to compile anything from simulink, since I don't think the webpack license includes System Generator support. Cheers Jack On Thu, 13 Feb 2020 at 12:43, A

Re: [casper] RE: Matlab Toolbox Requirements

Follow up part 2: The PFB requires the DSP toolbox for functions like sinc / hamming / etc. This commit should get rid of this requirement -- https://github.com/casper-astro/mlib_devel/commit/22dc17baccba4aa1581fb0339056410f5a71a053 Cheers Jack On Wed, 12 Feb 2020 at 15:19, Jack Hickish wrote

Re: [casper] ROACH-2

Hi Jael, Welcome to casper! You're likely to have the best chance of success if you follow the prescribed software versions at https://casper-toolflow.readthedocs.io/en/latest/src/Installing-the-Toolflow.html (ISE 14.7, Simulink 2013b, the roach2 branch of the libraries at https://github.com/casp

[casper] COVID19: CASPER Workshop 2020

Hi CASPERites, As I'm sure you are all well-aware, the situation with the ongoing coronavirus pandemic is rapidly worsening. In the face of a mounting number of infections, the overwhelming advice from governmental and academic organizations is to avoid unnecessary travel. We don't yet know what

Re: [casper] HLS VIvado with the casper-toolflow

Hi Sebastian, What you're suggesting _should_ work, but I don't know of anyone that has actually tried. Before getting too deep, does your design compile without the HLS black box in simulink? Does your error come from system generator or from the backend vivado compile? If the latter, you can op

[casper] CASPER Workshop 2020 -- ***POSTPONED***

Hi all, I hope you are all keeping well in these difficult times. It will probably come as little surprise to you all that the Advisory Board and Organizing Committee of the upcoming 2020 workshop in Sardinia *have taken the decision to* *postpone this year's workshop*. Given the uncertainty abo

[casper] [Job Advert] FPGA design for radars

2020 at 22:02 Subject: Fwd: FPGA design for radars To: Jack Hickish Hi Jack, Here is a job posting from a colleague formerly at SRI who has founded a spin-off, if you wouldn’t mind forwarding. Thanks! Dave FPGA Engineerat LeoLabs (View all jobs) <https://www.leolabs.space/careers> Menlo

Re: [casper] casperfpga module error: no module named bitfield

Hi all It seems a bunch of people have made Py3 versions which, for very understandable reasons, mostly only work for the boards they have on hand to test. E.g., the ska-sa branch has only been tested (as far as I'm aware) with SKARAB, and when I used it wouldn't work out the box on SNAP. I've bee

Re: [casper] casperfpga module error: no module named bitfield

blem. But then it may > have worked. I forget. > > Regards, > James > > > On 2020/05/07 13:46, Jack Hickish wrote: > > Hi all > > It seems a bunch of people have made Py3 versions which, for very > understandable reasons, mostly only work for the boards they have on

Re: [casper] Red Pitaya access registers of snap blocks from PS

Hi Sean, Just to explicitly add to wes's advice - in addition to the telnet interface on localhost, you can "just" install full blown casperfpga to your red pitaya, and connect via localhost using the scripts you already have. Unless your performance requirements are such that python is out of the

Re: [casper] Red Pitaya access registers of snap blocks from PS

27;m > pretty comfortable writing C code to run on the red pitaya to manage the > registers, so that's the direction I've gone. > > Thanks! > Sean > > On Monday, June 1, 2020 at 3:59:13 AM UTC-6, Jack Hickish wrote: >> >> Hi Sean, >> >> Just to

Re: [casper] Issue programming SNAP Microblaze golden image

Hi Dan, What casperfpga version are you using,and what golden file are you trying to load / what mlib_devel are you building against if you're creating custom one? Cheers J On Sat, 6 Jun 2020, 1:09 am Danny Price, wrote: > Hi all, > > I am trying to set up a SNAP board for microblaze, followin

Re: [casper] Timing analysis

This is probably a good conversation to have amongst the developers. ISE used to not deliver bitstreams unless you set an environment flag. I'm not sure it wouldn't make sense for the current toolflow to do the same. Timing failure warnings _are_ printed to the MATLAB prompt, but not in as shouty

Re: EXTERNAL: Re: [casper] ZCU111 toolflow

Hi Lawrence, The YAML file is the easy bit -- i.e., if you want some functionality (eg, a 100GbE core) that the toolflow supports for the Ultrascale+, adding in the pins to the YAML file is just a case of looking up the board documentation and copying the right pin numbers over. For example, I sus

Re: [casper] references to recent cross-correlator technology developments

Hi Neil, In the O(100) input domain a few refs are: CHIME: https://arxiv.org/abs/1503.06202 https://ui.adsabs.harvard.edu/abs/2019PhDT40D/abstract LEDA: https://arxiv.org/abs/1411.3751 MWA: https://arxiv.org/pdf/1501.05992.pdf EPIC (direct imaging): https://arxiv.org/pdf/1904.11422.pdf

Re: [casper] Converting ADC output back to 8 bits

Hi Molly, On Mon, 10 Aug 2020, 3:31 am 'Molly Smith' via casper@lists.berkeley.edu, < casper@lists.berkeley.edu> wrote: > > Hello, > > I'm trying to get 8-bit real values from the katADC yellow block in > Simulink. I was wondering why the block outputs fixed 8.7 bit values > instead? I found the

Re: [casper] Compiling design

Hi Heystek, Somewhere in your design -- presumably outside the screenshot you just sent or inside one of your blocks -- you have a "Gateway In" block. This isn't allowed (when you compile the design, the toolflow doesn't know what to drive it with). If you find and delete this block, I think you'l

Re: [casper] references to recent cross-correlator technology developments

I'll join the group of people who aren't Danny responding to your message :) These days GPUs have much better non-floating point performance -- Nvidia's tensor cores will do INT8 / INT4 compute which are (I gather) good for machine learning. The Tesla T4 card specs specifically state low-precision

Re: [casper] references to recent cross-correlator technology developments

On Sun, 16 Aug 2020, 11:59 am Neil Salmon, wrote: > Hi Dan, > > > > I really appreciate the good points you make. > > > > Certainly, NLogN versus N^2 in processing power for the two approaches can > make a big difference. Some of the active (radar) security screening portal > systems currently us

Re: [casper] Installation of Matlab 2012B

Hi Heystek, Not sure what the linux flavour dependencies are, but this is quick and easy and works for (eg) making MATLAB 2016 work with Ubuntu 2018 -- https://blog.leiy.me/post/create-dummy-network-interfaces-on-linux Cheers Jack On Tue, 18 Aug 2020 at 12:00, James Smith wrote: > Hi Heystek,

Re: [casper] SNAP FPGA data endianness and networking

Hi Nitish, To try and answer your first question without adding confusion -- If you send a UFix64_0 value into the 10GbE block, you will need to interpret it on the other end via an appropriate 64-bit byte swap if your CPU is little-endian. If you send a 64-bit input into the 10GbE block where th

Re: [casper] SNAP FPGA data endianness and networking

: >> >>> Hi, >>> >>> Thanks a lot Jack. It makes sense. >>> And thank you very much for the note on the 2x32-bit pair. It is exactly >>> how our data is formatted. >>> Ok, we will go with an FPGA correction instead of a CPU byteswap. I am &g

Re: [casper] SNAP FPGA data endianness and networking

> sharing the design the latter part can be removed easily to re-compile for > the big-endian system. > > Many thanks. > Nitish > > > On Tue, Aug 18, 2020 at 10:13 PM David MacMahon > wrote: > >> Is it April already? :) :) :) >> >> On Aug 18, 2020, a

Re: [casper] PFB (taps): Effects on time resolution

Hi Colm, Just to add -- you might find this ipython notebook a useful place to start poking around if you want to do some software sims -- https://github.com/telegraphic/pfb_introduction/blob/master/pfb_introduction.ipynb On Fri, 28 Aug 2020 at 17:17, Ross Martin wrote: > Hi Colm, > > I realize

Re: [casper] Re: TDM data FIR LP filter

11 Sep 2020 at 13:13, mattana wrote: > Hi, > I'm Andrea Mattana and I have used for the Medicina Team a customized PFB > with few taps for the x64ADC designed by the "Oxford Team" (a different > repo not linked with the official one) many years ago. > Jack Hickish was a

Re: [casper] ROACH 2 10 GbE Troubleshooting

Hi Ben, Before getting too far into the power PC software side, some basic checks in firmware which are probably worth doing - - does EOF go high with (not after) the last valid sample? - can you (using a snapshot block) verify that what is happening in firmware with the vld / EOF signals matches

Re: [casper] ROACH 2 10 GbE Troubleshooting

now why this may be the case? > Ping definitely won't work without the tap interface. But if it doesn't even work with that, I'm not sure I have any suggestions. I generally never used the tap interface and just micromanaged the core configurations as you are now doing. Cheers

Re: [casper] ADCs in CASPER

Hi Gareth, On Mon, 26 Oct 2020 at 12:49, Gareth Callanan wrote: > Hi Casper Community > > Now that roach2 has been deprecated, I have been wondering where the > CASPER community is heading in terms of future ADC work. > > As far as I can tell there are three options available: > >1. SNAP boa

Re: [casper] ADCs in CASPER

Hi Glen, The CASPER tools support the Red Pitaya -- https://www.redpitaya.com/Catalog/p57/stemlab-125-10-starter-kit?cat=c99 -- which is ~200 EUR. Somewhat similar in price to the Pluto but admittedly without the RF front end. This support was added in the last couple of years by our South African

[casper] CASPER wiki / SSL obsolescence

Hi CASPERites, Somebody helpfully pointed out to me that the latest Firefox updates prevent access to the CASPER wiki because the https encryption scheme the server uses is ancient and deemed insecure. The casper wiki is currently being moved to a new system, which, amongst other improvements, wi

[casper] Red Pitaya Black Friday Sale

Just noticed -- Red Pitatya are having a sale... https://www.redpitaya.com/Catalog Cheers Jack -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to cas

[casper] SNAP 10G CPU Interface ("tapcp") corruption fix

Howdy all, HERA (and other users) were seeing flaky casperfpga transactions when doing SNAP board control over 10GbE. I'm not sure who else uses SNAPs this way, but after some playing around I believe the three most recent commits at https://github.com/realtimeradio/mlib_devel/tree/snap-debug (th

Re: Re: [casper] search demo model+ python script for QDR on ROACH2

The stock QDR link training ("calibration") code is at https://github.com/casper-astro/mlib_devel/tree/roach2/xps_sw_support/qdr/roach2 I'm not sure if that is the same or different from that which some of the other models use: e.g. https://github.com/sebajor/simulink_models/blob/a3928218930e9a51cc

Re: [casper] ROACH2 QDR testing address problem

I'm not sure how that particular script / firmware works, but in general, a single read/write action in the ROACH2 QDR transfers 144 bits. The granularity of the python read writes is 32-bits, so what actually happens is that a read from casperfpga grabs 144 bytes, carves it up into 4x36 bit words,

[casper] Re: How to check or modify the network setting on ROACH2 ?

Traffic from the ROACH doesn't go through the PowerPC, so my guess would be that it's unlikely anything is causing issues there. I'm not actually sure how you change PPC settings which aren't set via the "start_tap" command. For >8kB packets, you should check any options to increase the TX buffer o

Re: [casper] New setup installation problems (python setup.py egg_info" failed with error code 1)

Hi Kaj, What python version are you using? If that error is complaining that numpy is using f-string syntax then maybe it's a python<3.6 issue. Cheers Jack On Wed, 20 Jan 2021 at 15:45, Kaj Wiik wrote: > Hi! > > As per instructions, I installed an (ob

Re: [casper] New setup installation problems (python setup.py egg_info" failed with error code 1)

s :-): > - can a more recent Ubuntu version be used (with ZCU111)? > or > - should I try to install e.g. anaconda python, is the most recent > version of python3 compatible with Casper? > > Many thanks, > Kaj > > On 1/20/21 6:10 PM, Jack Hickish wrote: > > Hi Kaj,

Re: [casper] New setup installation problems (python setup.py egg_info" failed with error code 1)

t; Adam Isaacson > South African Radio Astronomy Observatory (SARAO) > Hardware Manager > Cell: (+27) 825639602 > Tel: (+27) 215067300 > email: aisaac...@ska.ac.za > > > > On Wed, Jan 20, 2021 at 6:49 PM Jack Hickish > wrote: > >> Hi Kaj, >> >> I t

Re: [casper] New setup installation problems (python setup.py egg_info" failed with error code 1)

he installation went fine using these > > workarounds. > > > > About ZCU111 Slack channel, I am very interested (and my colleague > > derek.mc...@utu.fi also), could you please send us an invitation? > > > > Many thanks for your kind help! > > > > Ka

Re: [casper] Ubuntu/MATLAB compatibility for ROACH2

Hi Matheus, I've never had a problem with Ubuntu 14 and MATLAB 2013b. In fact I sometimes do ROACH2 builds on Ubuntu 16.04 which is also fine. In general, almost all of my problems come from Xilinx, not MATLAB. However, you are absolutely right that MATLAB 2013b seems to only support Ubuntu 13.04

[casper] Fwd: Postdoctoral position on VLA commensal science

science To: , Nanograv , General CHIME discussion , < commun...@iaaseti.org>, Cc: Andrew Siemion , Namir Kassim < namir.kas...@nrl.navy.mil>, Tracy Clarke , Jack Hickish , Paul Demorest , Mark McKinnon , Allen Lewis , David DeBoer < ddeb...@berkeley.edu> Dear all, I&#x

Re: [casper] snap tutorial 3

Hi Guillermo, How many channels is that tutorial supposed to generate? It looks like the RAM is smaller than expected by the software. Is it possible that each even/odd RAM is supposed to be 512*4 (i.e., 512 words, each 32-bits wide) for 1024 channels total? Cheers Jack On Mon, 5 Apr 2021 at 22:

Re: [casper] snap tutorial 3

s of 64bits, > So I have to read 1024 * 8 = 8192 bits, from each register (even and odd). > > I compiled the project with those values and I got the same result as > before, (read ok with 128*4 bits, ,fpga.read('even',128*4,0) ) > > Cheers > > > > > > > &

Re: [casper] snap tutorial 3

alues is of 64bits, > >> So I have to read 1024 * 8 = 8192 bits, from each register (even and > odd). > >> > >> I compiled the project with those values and I got the same result as > >> before, (read ok with 128*4 bits, ,fpga.read('even',128*4,0) ) > &

Re: [casper] snap tutorial 3

tcpb3 log I got: > can't send spi message! (error -1) > > Cheers, > > > El mié, 7 abr 2021 a las 11:24, Jack Hickish () > escribió: > > > > > > > > On Wed, 7 Apr 2021, 2:57 pm Guillermo Gancio, > wrote: > >> > >> Hi, > >>

Re: [casper] snap tutorial 3

nspecting snapshots of ADC data. The whole thing requires quite a lot of register reads / writes / and the interface is pretty slow. The "no length specified" is probably fine -- sounds like if nothing else is specified, the default read is a single 4-byte register, which seems like rea

[casper] System Verilog

Hi CASPERites, Does anyone have any resources for learning System Verilog they've used and particularly like? Cheers Jack -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails fro

[casper] Fwd: GNU Radio conference

Howdy Casperites, See below, info about the upcoming GNU Radio conference. For those unfamiliar, GNU Radio is an open source software-defined radio project, and has a lot of crossover with CASPER's use cases and interests. As GPUs and CPUs get more powerful, there is an increasing amount of radio

[casper] Re: Cannot Join Casper List Server & Question about Error in Jasper Tutorial

Hi Kathryn, cc list Did emailing casper+subscr...@lists.berkeley.edu (as per https://casper.berkeley.edu/index.php/contact/) not work? In any case, I've added you manually, so you should be able to post directly to casper@lists.berkeley.edu from this JPL email address. Let me know if this doesn't

Re: [casper] System Verilog

Thanks, Dave, Bob, Brian. Great suggestions all round. Cheers Jack [Muses whether CASPERites should pool together for a training session...] On Fri, 25 Jun 2021 at 03:57, Hawkins, David W (US 334B) < david.w.hawk...@jpl.nasa.gov> wrote: > Sorry, I missed the rest of a comment: > > > > >> there

Re: [casper] SNAP error: no programming informs yet. Odd?

Hi Cynthia, Tristan, What model RPi are you using, and what type/length of ribbon cable is used to connect the Pi to the SNAP. Were both of these known-good hardware prior to installation in the case? Re. error recovery -- at the very least I would have thought restarting borphserver (probably `/e

Re: [casper] SNAP error: no programming informs yet. Odd?

the power > controllers on the SNAP board without a hard power cycle perhaps? > > > > Thanks, > > Tristan > > > > *From: *Tristan Ménard > *Sent: *July 22, 2021 11:24 AM > *To: *Jack Hickish ; casper > > *Subject: *RE: [casper] SNAP error: no programming

Re: [casper] SNAP Fusion power chip configuration (overtemperature shutdown)

Hi Eamon, That third file is, I think, some rogue configuration from testing which should never have been committed to that repository. I suspect the 80C threshold was set (by me!) based on a sample configuration file from the KC705 development board and/or based on the data sheet's 85C max tempe

Re: [casper] Error installing in python3 environment on SELinux7

I think your main issue is likely to be that the ROACH2 filesystem is so old the bundled version of tcpborphserver doesn't support the `upload_to_ram_and_program` infrastructure used by the latest casperfpga. Hopefully if this is the case updating your tcpborphserver (or the whole R2 filesystem) wi

Re: [casper] UFix/Fix data types and Fixed-Point Designer Toolbox

thing more complicated or whether you run into issues. Cheers Jack On Mon, 13 Sept 2021 at 12:55, Matheus Furlan Alpoin wrote: > Hi all, > > Recently, I came across an email by Jack Hickish on this list which > dated back to early 2020, on which he stated that the Fixed-Point > Des

[casper] HBM memory

Hi CASPERites, Hope everyone is keeping well. It looks like I'm imminently going to have to dip my toe (and then probably my entire self) in the world of HBM, in order to make some reasonably large data transposes / packet construction buffers. (For the interested, I'm using a VU37P AlphaData ADM

Re: [casper] HBM memory

; > Maybe we could work together on this? > > Kind regards, > > Adam > > > > On Mon, 04 Oct 2021, 8:59 PM Jack Hickish, wrote: > >> Hi CASPERites, >> >> Hope everyone is keeping well. >> >> It looks like I'm imminently going to have t

Re: [casper] Help to program BRAM blocks.

Hi Heystek, How big is the bram? Is it smaller than the length of `buf`? If so, I think that would give you the error you see. Relatedly, this code looks like it's going to write packed floats to the FPGA. Is this really what you want? (It might be, but most designs are set up for fixed point comp

Re: [casper] Synchronize a cluster of Red Pitayas using CASPER

Hi Stefan, Sounds fun! Depending what exactly you need to mess with you might need to dig around a bit, but as a starting point -- this is where the main RP infrastructure is instantiated: https://github.com/casper-astro/mlib_devel/blob/390b7c262f0f7418c45bfb98f5aa969a0a432564/jasper_library/yell

Re: [casper] Synchronize a cluster of Red Pitayas using CASPER

ter/FPGA_Hosts/RED_PITAYA/README.md >> >> >> >> These are definitely the main files you will need to change the MMCM >> parameters to produce a clock frequency of your choice and route out the >> synchronised clock. Good luck and feel free to use our slack group

[casper] Re: Help with packing data

Hi Heystek, All good here (in London), Thanks. Hope things are going ok with you too! I've taken this back on list for the benefit of others. Do you have: a) a snippet of some python code which you're using at the moment b) A Simulink snippet of the BRAM you're trying to write to, indicating how

[casper] Re: Help with packing data

e array: > > > The fourth snipped is where I write the packed data to the BRAM: > > > Snipped 5 is where I want to use the sine wave and cosine wave: > > > But to check that it is working, I have created the simple design in > snipped 6: > > > I have also attach

[casper] Fwd: Breakthrough Listen summer undergraduate research internships

Hi all, Please find below details of the upcoming Breakthrough Listen internship program, which would be a great opportunity for a CASPERite to get research experience at one of the project's many collaborating institutions. Happy holidays! Jack -- Forwarded message - From: Ste

[casper] AD9207 FMC board

Hi CASPER, On the off chance someone knows of one / has designed one for their own use; is anyone aware of an Analog Devices AD9207 FMC+ board? I'm interested in using such a board with this ZU11 platform -- https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/ . Relatedly

Re: [casper] AD9207 FMC board

27;s have > similar specs. Is it because this is lower cost that the RFSoCs? > > Regards, > > Ross > > > On Mon, Jan 10, 2022, 4:49 AM Jack Hickish wrote: > >> Hi CASPER, >> >> On the off chance someone knows of one / has designed one for their own >

Re: [casper] AD9207 FMC board

s are the best to do the design for the base board for you,they > offer that service. > > Regards, > Benjamin Hlophe > > On 10 Jan 2022, at 13:50, Jack Hickish wrote: > >  > Hi CASPER, > > On the off chance someone knows of one / has designed one for their own &

Re: [casper] ZCU111 board

On Tue, 11 Jan 2022 at 17:53, Giovanni Comoretto wrote: > Further steps. > I downloaded the repository (using ZIP, git-lfs fails on > top_adm_pcie_9h7.xpr.zip) at > https://github.com/casper-astro/mlib_devel/tree/m2019a > Hmmm. That's something I added to my repo, which possibly shouldn't have b

[casper] DSA2000 Lead Project Engineer/Manager Job Postings

Hi all, The Caltech-led DSA-2000 project -- 2000 dishes, 1.3GHz of bandwidth: that's a big machine! -- is looking for a project manager and engineer. Jobs adverts were recently posted on the AAS register. Please see below for details -- https://jobregister.aas.org/ad/07a3d54c https://jobregister.

Re: [casper] Inverting the Polyphase Filter Bank

On Fri, 4 Feb 2022 at 07:08, Morag Brown wrote: > Hey Nikhail, > > The FFT is a Hermitian function, which means that it has the property: > > [image: Screenshot from 2022-02-04 08-34-24.png] > > This principle is used in the real wideband FFT to compute 2 real FFTs > using one complex FFT core -

Re: [casper] Inverting the Polyphase Filter Bank

On Fri, 4 Feb 2022 at 10:41, Jack Hickish wrote: > > > On Fri, 4 Feb 2022 at 07:08, Morag Brown wrote: > >> Hey Nikhail, >> >> The FFT is a Hermitian function, which means that it has the property: >> >> [image: Screenshot from 2022-02-04 08-34-24.png

Re: [casper] Inverting the Polyphase Filter Bank

version is not possible > because the information in the Nyquist bin is thrown away? (I hope I am > wrong) > I am sorry to say that I don't think you are wrong. (Though maybe we are both wrong!) > > Cheers, > Nikhil > > On Fri, 4 Feb 2022 at 05:41, Jack Hickish wrote: > &

Re: [casper] Simulink window does not open when Matlab is started by startsg

Hi Kaj, Not sure whether it is at all relevant, but these days when faced with any sort of probably OS/sysgen/MATLAB version combination issues I start by installing the kde-full package. I'll also add that I'm running MATLAB 2019a / Vivado 2020.2 without issue on Ubuntu 18.04. Cheers Jack On S

Re: [casper] Simulink window does not open when Matlab is started by startsg

I think that's pretty much what mine looks like. :) On Sat, 12 Feb 2022 at 13:08, Kaj Wiik wrote: > Hi Jack, > > It indeed might be the fastest way to follow your setup. Screenshot of the > 'simulink' window I get is attached. > > Thanks, > Kaj >

[casper] Fwd: [rci] RCI software engineer hire

Hi Team Casper, Please see Gregg Hallinan's listing below for a DSA2000 software engineer, with a focus on various GPU-based DSP. Cheers Jack -- Forwarded message - From: Gregg Hallinan Date: Wed, 16 Feb 2022, 19:56 Subject: [rci] RCI software engineer hire To: Dear all, W

[casper] wideband real FFT with Xilinx Vector FFT

Hi All, As others have reported ( https://www.mail-archive.com/casper@lists.berkeley.edu/msg08238.html) the Xilinx SSR FFT is pretty good. However, I want to do two real transforms instead of one complex -- does anyone happen to have an unscrambler already made which I can steal? Otherwise I supp

Re: [casper] wideband real FFT with Xilinx Vector FFT

ed me off-list to ASTRONs complex->dual-real descrambler, which I think could probably be plugged straight into the Xilinx SSR FFT if necessary https://github.com/talonmyburgh/casper_dspdevel/blob/master/casper_wb_fft/fft_sepa_wide.vhd > Regards, > > Ross > > > > On Feb 23, 20

Re: [casper] wideband real FFT with Xilinx Vector FFT

can get code for, > I’d be happy to benchmark those also. These are the ones I could find. > This is super helpful, thanks! Cheers Jack > > Regards, > > Ross > > > On Feb 24, 2022, at 4:39 AM, Jack Hickish wrote: > > > > On Thu, 24 Feb 2022 at 05:05, 'Ross

Re: [casper] Trouble compiling diagram for Correlator in ROACH1

Hi Sebastián, Unfortunately, the issue is exactly as reported: The design is too big to fit on the device. In your case, you are running out of soft logic -- that is, you're running out of the FPGA's general purpose "SLICE" logic. It's possible your design just has too much going on, and you'll n

Re: [casper] ROACH2

Hi Wang, On Tue, 15 Mar 2022 at 12:21, 王钊 wrote: > Hello CASPER, > > How's it going? I am new to this, I am trying the tutorial of ROACH2.Now > I'm using Ubuntu16.04, Matlab2013b, ise14.7. > > I have two questions. > The first is I downloaded tutorial_devel at > https://github.com/casper-astro/t

Re: [casper] ROACH2

On my MATHWORKS account if I go to the downloads section I can "show more" on the left to find matlab version back to 2016, then "show all" to get versions back to pre-2006 [image: image.png] On Tue, 15 Mar 2022 at 14:08, 王钊 wrote: > Thank you so much, Jack. > > Jack, where did you download ma

Re: [casper] ROACH2

Oh, fun. Maybe it is because I have a license and you don't? Or something. If you have a local sysadmin in charge of your institutions software subscriptions probably they can help. On Tue, 15 Mar 2022 at 15:28, 王钊 wrote: > Thank you Jack！ > > This is what my MATLAB website shows, and I will

Re: [casper] Problems Encountered When Using MATLAB

On Thu, 17 Mar 2022 at 14:21, 王钊 wrote: > This is the first time I've seen this website! Me too! https://uk.mathworks.com/support/bugreports/968648 is a game changer! Thanks, authors! > I truly appreciate your timely help. > > Wang > 在2022年3月17日星期四 UTC+8 17:29:07 写道： > >> Hi, if it gets stuck

Re: [casper] IP hostname or address of FPGA board

Hi Wang, I think the default ROACH2 boot images all DHCP a dynamic address. I'm not sure if there is a fallback default. If you plug in a USB cable into the board while it boots you should be able to login over serial (device /dev/ttyUSB2, baudrate 115200; see https://casper.astro.berkeley.edu/wik

Re: [casper] viability of VCU128 eval board as production CASPER instrument

Hi Jonathan, On Mon, 9 May 2022 at 17:26, 'Jonathan Weintroub' via casper@lists.berkeley.edu wrote: > Hi CASPERites, > > At SAO we’ve been developing high performance instruments based on the > Xilinx VCU128 evaluation board > and the

Re: [casper] Some problems with ROACH2

Hi Wang, To transfer an fpg file to a ROACH2, you would usually use the standard linux utility scp. Unless you've installed VNC on your ROACH, you won't be able to connect to it that way. Most people communicate with ROACH2 boards using the casperfpga python package. If you install this you can c

Re: [casper] PAPER Correlator EQ Settings

Thanks Michael. I've updated the wiki link. On Fri, 24 Jun 2022 at 15:40, Michael D'Cruze < michael.dcr...@postgrad.manchester.ac.uk> wrote: > Hi Wang, > > The memos are on github now. See: > https://github.com/casper-astro/publications/blob/master/Memos/files/p011.quant.pdf > > BW > > >

[casper] CASPER 2022 workshop: Early registration ending soon

Hi All, Just a reminder that the early registration discount for the CASPER 2022 workshop only lasts till the end of June. Head over to https://sites.google.com/inaf.it/casper2022 for more info and to register now! Cheers Jack -- You received this message because you are subscribed to the Goog

Re: [casper] The link of " Setting Up BORPH on BEE2 " is invalid

HI Wang, That link works, you'll just have to click through to ignore the expired https certificate :-S Could someone at Berkeley generate a new certificate :) ? J On Thu, 30 Jun 2022 at 05:06, Wang wrote: > Hi CASPER， > > I want to see how we can set BORPH on ROACH. > > BORPH - Casper (berke

Re: [casper] Re: tcpborphserver violates katcp specification

On Tue, 19 Jul 2022, 19:01 Kiran Shila, wrote: > > ?wordread/?wordwrite was written with maximal human readability in > > mind. Somebody who has a misbehaving roach deployed somewhere can just > > telnet/netcat/socat/etc to port 7147 and issue a wordread > > to see if enough bits are toggling, or

Re: [casper] Converting Aurora IP core into yellow block

Hi Danny, This is probably a reasonable example. It actually does something similar, reading data from the VLA in their custom high-speed serial format. I just export the IP .xci file into mlib_devel and

[casper] Re: Hola Jack!

Hi Rolando, list, Googling the issue, I think you want this solution -- https://unix.stackexchange.com/questions/340844/how-to-enable-diffie-hellman-group1-sha1-key-exchange-on-debian-8-0 The issue is that the ROACH version of openSSH is old, and only seems to support deprecated key exchange metho

[casper] Re: Hola Jack!

the svn server on the old casper.berkeley.edu server was migrated to casper.astro.berkeley.edu? J > Regards > > Rolando > > El mié, 27 jul 2022 a las 6:02, Jack Hickish () > escribió: > >> Hi Rolando, list, >> >> Googling the issue, I think you want this solu

Re: [casper] Linkup is not displayed in Roach Tu2

Hi Kuma, I'd suggest using the most recent versions of that tutorial -- https://github.com/casper-astro/tutorials_devel/tree/master/roach2/tut_tge -- as Cedric says these use casperfpga. There's always a risk that your ROACH2 tcpborphserver might not be new enough to support this. A new version of

[casper] Polyphase synthesizer

Howdy all, Don't suppose anyone has FPGA code for a polyphase synthesizer knocking around? Cheers Jack -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email

Re: [casper] RFSOC onethundred GBE interface multicast mode

Hi, For sending multicast packets you shouldn't need to do anything special. Provided you set the destination IP to a multicast address, the core will recognize that the packet should have a multicast MAC and generate one from the IP. Receiving multicast packets is an entirely different story and

Re: [casper] Help with ROACH2 uboot issue

Hi Dale, That file looks like `/etc/exports` (see https://casper.astro.berkeley.edu/wiki/ROACH_NFS_guide#Installing_NFS) Cheers JAck On Tue, 23 Aug 2022 at 20:08, Gary, Dale E wrote: > Hi All, > > I upgraded my remote boot server to a new machine running ubuntu 20.04, > and although I tried to

Re: [casper] Help with ROACH2 uboot issue

No, I take that back. Having read Marc's message and then re-read yours, you should Ignore me :) On Tue, 23 Aug 2022 at 20:41, Jack Hickish wrote: > Hi Dale, > > That file looks like `/etc/exports` (see > https://casper.astro.berkeley.edu/wiki/ROACH_NFS_guide#Installing_NFS)

Re: [casper] Some questions about Shared_BRAM block

Hi Kuma, The two register options give you the ability to try to improve the timing performance of the RAM by adding extra internal register stages in its implementation. With neither of those options checked, the RAM has a latency of 1 (after presenting an address on the input, the value stored a

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