---
On 2011-01-18 16:49:14, Gabe Black wrote:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/419
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/419/
---
(Updated 2011-01-18 23:21:55.573947)
Review request for Default, Ali Saidi, Gabe
nathan binkert wrote:
If you add a function for it I'll use it. We should be careful, though,
since when nanoseconds (or microseconds or milliseconds) spill into seconds
might get a little tricky. Actually, right now nanoseconds, microseconds, and
milliseconds all change the same data,
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/428/
---
(Updated 2011-01-17 00:03:59.517382)
Review request for Default, Ali Saidi, Gabe
://reviews.m5sim.org/r/422/
---
(Updated 2011-01-12 09:12:18)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
O3: Enhance data address translation by supporting hardware
://reviews.m5sim.org/r/421/
---
(Updated 2011-01-12 09:11:45)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
O3: Fix itstate prediction and recovery.
Any change of control flow now
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/338/
---
(Updated 2011-01-12 09:06:31)
Review request for Default, Ali Saidi, Gabe Black
On 2011-01-17 00:58:49, Gabe Black wrote:
I still don't totally follow why this is necessary, although I believe it
probably is. One sticky problem you can run into with x86 (and probably
most ISAs) is if you enable interrupts and then immediately disable them
again, expecting
, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
x86: implements vtophys
Calls walker to look up virt. to phys. page mapping
Diffs
-
src/arch/x86/vtophys.cc 9f9e10967912
Diff: http://reviews.m5sim.org/r/385/diff
Testing
---
Thanks
/
---
(Updated 2011-01-12 09:06:31)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.
When this condition occurs
On 2011-01-17 00:28:39, Gabe Black wrote:
This change seems to have some dead functionality in it. The delay member
added to translations is never used, the delay() pure virtual function is
never used and not defined for any other ISAs (which I think will break
them all
I think the binaries are actually fine to distribute (I think they're
all GPL), it's actually the input sets which have restrictive licenses.
Gabe
On 01/17/11 20:55, Beckmann, Brad wrote:
Thanks Gabe.
I had completely forgotten about the fact we can freely distribute some of
those tests.
Right, the fault doesn't get ignored, but if the CPU handled it
directly without having to return it from initiateAcc, it should work
the same. What I was getting at in my review (assuming I actually wrote
down what I was thinking) is that we could make initiateAcc always
initiate a translation
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/428/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/425/
---
(Updated 2011-01-14 13:32:44)
Review request for Default, Ali Saidi, Gabe Black
changeset bd474b97535c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bd474b97535c
description:
SPARC: Adjust the call instruction so R15 doesn't get marked as a
source.
diffstat:
src/arch/sparc/isa/decoder.isa | 8 +++-
1 files changed, 3 insertions(+), 5
changeset 696063d6ed04 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=696063d6ed04
description:
SPARC: Update stats for the call r15 as source change.
diffstat:
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |
10 +-
/
---
(Updated 2011-01-13 19:43:31)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
time: improve time datastructure
Use posix clock functions (and librt) if it is available.
Inline a bunch of functions and implement more
changeset 7107a2f3e53a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7107a2f3e53a
description:
Style checker: Fix a couple bugs in style.py.
diffstat:
util/style.py | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diffs (21 lines):
diff -r c6bc8fe81e79
://reviews.m5sim.org/r/425/
---
(Updated 2011-01-13 19:43:31)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
time: improve time datastructure
Use posix clock functions
This looks like a stale build directory still. It's apparently obsolete
intermediate swig files that get mixed in when they shouldn't.
[SWIG] X86_SE/python/m5/internal/param_RubySystem.i - _wrap.cc, .py
scons: *** [build/ALPHA_FS/python/m5/internal/param_RubySystem_wrap.cc]
Error 1
scons:
Actually, I take that back. It looks like param_RubySystem.i isn't being
regenerated even though RubySystem.py was changed to not have a
RubyDebug parameter. I don't know why, but an obvious guess is
incomplete dependencies.
Gabe
Gabe Black wrote:
This looks like a stale build directory still
Flyspray would be good. We don't use it like we should, but it's
probably the most appropriate place. I'm not familiar with the
checkpoint tester. How does it work (link to the wiki would be fine),
and what were the differences?
Gabe
Beckmann, Brad wrote:
Hi All,
While using the
I initially thought this was your RubyDebug.hh change, Nate, but I don't
see RubyDebug in the repository anywhere now. In the past I've run into
problems where left over files make a build break until you wipe it out
and rebuild, specifically having to do with the python stuff. I suspect
if you
be good.
Thanks again.
- Ali
On January 10th, 2011, 4:21 p.m., Brad Beckmann wrote:
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt,
and Nathan Binkert.
By Brad Beckmann.
/Updated 2011-01-10 16:21:58/
Description
m5: added work completed monitoring support
We should be discussing this on m5-users, and it's probably better to
set those parameters on the scons command line than in the file with the
default settings. If you run scons --help, or scons --help
build/ALPHA_SE_MOESI_CMP_directory/m5.opt in this case, it will print
out what setting it's
WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include cassert
+#include iostream
+#include list
+
+#include base/refcnt.hh
+
+using namespace std;
+
+namespace {
+
+class TestRC;
+typedef listTestRC * LiveList
change or changes.
Gabe
Gabe Black wrote:
changeset b36af60dcb91 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b36af60dcb91
description:
RefCount: Add a unit test for reference counting pointers.
This test exercises each of the functions in the reference counting
changeset e49c7db3ac53 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e49c7db3ac53
description:
Curtick: Fix mysql.cc build needing curTick.
diffstat:
src/base/stats/mysql.cc | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diffs (11 lines):
diff -r
changeset c06505ff551e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c06505ff551e
description:
Root: Get rid of unnecessary includes in root.cc.
diffstat:
src/sim/root.cc | 6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diffs (16 lines):
diff -r
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/419/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
nathan binkert wrote:
diff -r e49c7db3ac53 -r c06505ff551e src/sim/root.cc
--- a/src/sim/root.cc Mon Jan 10 04:53:20 2011 -0800
+++ b/src/sim/root.cc Mon Jan 10 04:53:34 2011 -0800
@@ -29,12 +29,6 @@
* Steve Reinhardt
*/
-#include cstring
-#include fstream
-#include list
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/380/
---
(Updated 2011-01-10 10:48:23)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
mcpat: Adds
/
---
(Updated 2011-01-10 11:42:35)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
packet: function identifying whether data has been allocated
This function identifies whether static or dynamic data has been allocated and
is used
On 2011-01-10 13:54:18, Gabe Black wrote:
src/mem/packet.hh, line 775
http://reviews.m5sim.org/r/399/diff/3/?file=9462#file9462line775
You need spaces around |.
Brad Beckmann wrote:
I can add a space around |, but hat is inconsistent with the rest of the
file.
Ah, yeah, I
On 2011-01-07 04:45:16, Gabe Black wrote:
src/arch/x86/vtophys.cc, line 70
http://reviews.m5sim.org/r/385/diff/1/?file=9054#file9054line70
Having a temporary variable here seems unnecessary unless it's to
prevent having to wrap the next line. It's not a big deal, though.
Joel
On 2011-01-07 04:21:05, Gabe Black wrote:
I think there are two problems with this patch. First, if at all possible
we should avoid the code duplication we'd now have for the recvTiming
function. Second, while this probably does fix the legitimate problem of
deleting packets twice, I
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/417/
---
(Updated 2011-01-07 16:43:48)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
On 2011-01-07 05:51:30, Gabe Black wrote:
src/arch/x86/pagetable_walker.cc, line 77
http://reviews.m5sim.org/r/396/diff/1/?file=9103#file9103line77
These should use FastAlloc if at all possible since they're on a
critical path and the heap is slow.
Joel Hestness wrote
On 2011-01-07 05:51:30, Gabe Black wrote:
The code seems ok, but why do we need to have multiple outstanding page
walks in timing mode again?
Gabe Black wrote:
Actually, I wrote the above before I'd read it carefully. My question
still stands, but there are some areas that need
://reviews.m5sim.org/r/377/
---
(Updated 2011-01-06 15:51:09)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
x86: set IsCondControl flag for the appropriate microops
/
---
(Updated 2011-01-06 15:56:19)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
MessagePort: implemented virtual recvTiming avoiding double delete
Double packet delete problem is due to an interrupt device
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/383/
---
(Updated 2011-01-06 15:56:44)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
x86: page table walker functional support
src/arch/x86/pagetable_walker.hh: Added method to functionally walk page table
src/arch/x86/pagetable_walker.cc: Added method to functionally walk
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/386/
---
(Updated 2011-01-06 15:59:44)
Review request for Default, Ali Saidi, Gabe Black
Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
TimingSimpleCPU: split data sender state fix
In sendSplitData, keep a pointer to the senderState that may be updated after
the call to handle*Packet. This way, if the receiver updates the packet
senderState, it can
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/396/
---
(Updated 2011-01-06 16:12:34)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert
On 2011-01-07 05:51:30, Gabe Black wrote:
The code seems ok, but why do we need to have multiple outstanding page
walks in timing mode again?
Actually, I wrote the above before I'd read it carefully. My question still
stands, but there are some areas that need to be fixed up. Also, since
-01-06 16:12:56)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
dev: fixed bugs to extend interrupt capability beyond 15 cores
Diffs
-
src/arch/x86/interrupts.cc 9f9e10967912
src/dev/x86/i82094aa.hh
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/398/
---
(Updated 2011-01-06 16:13:29)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
m5
. To reply, visit:
http://reviews.m5sim.org/r/384/
---
(Updated 2011-01-06 15:57:01)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
IntDev: latency fix
Since the device
Oops, I mean to send this to m5-dev.
Gabe
Original Message
Subject:Re: Review Request: x86: set IsCondControl flag for the
appropriate microops
Date: Fri, 07 Jan 2011 12:04:38 -0800
From: Gabe Black gbl...@eecs.umich.edu
To: Brad Beckmann brad.beckm
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/384/
---
(Updated 2011-01-06 15:57:01)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
Hi. You should ask this on m5-users. Most or maybe all of the people on
this list are on that list as well, along with a lot of other people.
Gabe
zhanglunkai wrote:
Hi,
I am trying to build m5 with a non-root account and the operation system
is redhat 2.6.28.
The system does not have
:
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt,
and Nathan Binkert.
By Steve Reinhardt.
/Updated 2011-01-06 11:15:30/
Description
scons: show sources and targets when building.
I like the brevity of Ali's recent change, but the ambiguity of
sometimes showing the source
changeset c819526b7c2a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c819526b7c2a
description:
Params: Print the IP components in the right order.
diffstat:
src/base/inet.cc | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diffs (14 lines):
diff -r
changeset 3a790012d6ed in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3a790012d6ed
description:
RefCount: Fix reference counting pointer == and != with a T* on the
left.
These operators were expecting a const T instead of a const T*, and
were not
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/365/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/365/
---
(Updated 2011-01-03 12:56:11.143277)
Review request for Default, Ali Saidi, Gabe
.
Gabe
Steve Reinhardt wrote:
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/366/
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt,
and Nathan Binkert.
By Steve Reinhardt.
Description
scons: show sources and targets when
these newer versions? Just that they're
more verbose?
Steve
On Mon, Jan 3, 2011 at 3:45 PM, Gabe Black gbl...@eecs.umich.edu
mailto:gbl...@eecs.umich.edu wrote:
I like the original (Ali's version) better. When was it confusing?
Perhaps there's a particular action that would be better
Ali Saidi wrote:
On Jan 3, 2011, at 10:57 PM, Steve Reinhardt wrote:
With Nate's suggested change, for CXX lines we're really just tacking
on the ' - .o' at the end... the initial part of the line is
unchanged, and the number of extra chars per line is 6 or 7. If you
guys really insist,
I was looking through base/refcnt.hh the other day, and I noticed for
the == and != operators that take a regular pointer on the left side and
a reference counting pointer on the other, they use a const T instead
of a const T *. Is that a mistake? Also, I tried to compare a T * and a
reference
I didn't decipher the subtlety you're talking about, but I just wanted
to point out that we may be doing this manually moving forward, and it
would be best if it wasn't complicated, confusing, or overly subtle.
Gabe
nathan binkert wrote:
Wow, I forgot I had written that... it was only seven
No, I'm not disagreeing with you because I'm confused or belligerent.
I'm disagreeing with you because I think you're wrong, and I'm allowed
to do that. Sorting includes is not the issue here, the spacing is. The
hang up seems to be making life easier for the script, and while I
sympathize I am
nathan binkert wrote:
No, I'm not disagreeing with you because I'm confused or belligerent.
I'm disagreeing with you because I think you're wrong, and I'm allowed
to do that. Sorting includes is not the issue here, the spacing is. The
hang up seems to be making life easier for the script, and
to detect that only
whitespace changed and I really don't think it's worth it. We
discourage random whitespace changes, but this is a deliberate style
correction.
Nate
On Sat, Dec 25, 2010 at 11:16 PM, Gabe Black gbl...@eecs.umich.edu
mailto:gbl...@eecs.umich.edu wrote
On December 25th, 2010, 8:05 p.m., Nathan Binkert wrote:
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt,
and Nathan Binkert.
By Nathan Binkert.
/Updated 2010-12-25 20:05:55/
Description
util: python implementation of a routine that will sort includes
I didn't
I looked at that too, and while the grouping is mentioned and the order
seems to be implied (but not mentioned) the spacing doesn't seem to even
be implied. This change itself isn't a big deal, even though in a
perfect world it would be best to get rid of the whitespace only
changes. The thing
, Gabe Black gbl...@eecs.umich.edu
mailto:gbl...@eecs.umich.edu wrote:
I looked at that too, and while the grouping is mentioned and the
order
seems to be implied (but not mentioned) the spacing doesn't seem
to even
be implied. This change itself isn't a big deal, even though
Nathan Binkert wrote:
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/352/
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt,
and Nathan Binkert.
By Nathan Binkert.
/Updated 2010-12-21 08:36:19.936053/
Description (updated
/
---
(Updated 2010-12-21 08:36:19)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
trace: reimplement the DTRACE function so it doesn't use a vector
One question I have about this stuff is if I
/
---
(Updated 2010-12-21 08:25:49)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
python: cleanup python code so stuff doesn't automatically happen at startup
this allows things
I looked at dbllist.hh since I was thinking we could replace it with the
STL doubly linked list, but it looks like it's not being used. We can
probably get rid of it, I think.
Gabe
Ali Saidi wrote:
Everyone,
I think we really need some better documentation on the files is src/base.
They're
changeset 85e1847726e3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=85e1847726e3
description:
Params: Fix a broken error message in verifyIp.
diffstat:
src/python/m5/params.py | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (12 lines):
diff -r
without that cache added in, so I suspect the walker
is picking up stale data or something.
Gabe
Gabe Black wrote:
Of these, I think the walker cache sounds better for two reasons. First,
it avoids the L1 pollution Ali was talking about, and second, a new bus
would add mostly inert stuff
Or instead of pasting into it maybe importing it? The python path might
be fidgety to get right that way, though.
Gabe
Steve Reinhardt wrote:
Another thought... there's no reason to restrict an update script to
simple regex substitution. The checkpoint files are pretty easy
to thoroughly
.
Gabe
Gabe Black wrote:
Or instead of pasting into it maybe importing it? The python path might
be fidgety to get right that way, though.
Gabe
Steve Reinhardt wrote:
Another thought... there's no reason to restrict an update script to
simple regex substitution. The checkpoint files
)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
O3: Don't try to scoreboard misc registers.
Diffs
-
src/cpu/o3/rename_impl.hh 2b5fbdcbfb5d
Diff: http://reviews.m5sim.org/r/347/diff
Testing
/
---
(Updated 2010-12-06 16:14:46)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
O3: Keep around the last committed instruction and use for squashing.
Before this, 0 was used for the youngest sequence number
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/349/
---
(Updated 2010-12-06 16:15:03)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
O3
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/312/
---
(Updated 2010-12-09 01:57:37.367475)
Review request for Default.
Summary
---
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/350/
---
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
changeset 9bd6b37d0189 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9bd6b37d0189
description:
ARM: Get rid of some unused FP operands.
diffstat:
src/arch/arm/isa/operands.isa | 5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diffs (15 lines):
diff -r
changeset 998b217dcae7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=998b217dcae7
description:
ARM: Take advantage of new PCState syntax.
diffstat:
src/arch/arm/isa/insts/branch.isa | 55 ++
src/arch/arm/isa/insts/data.isa |9 +-
On 2010-12-08 23:56:50, Gabe Black wrote:
Malformed commit message again.
It would be nice not to lose the information in the commit message. Ideally
it would pop out if the fault was invoked in SE mode, but more trivially it
could be moved into a comment above the new version
On 2010-12-08 22:45:44, Gabe Black wrote:
src/arch/isa_parser.py, line 795
http://reviews.m5sim.org/r/339/diff/1/?file=5449#file5449line795
These values aren't passed directly to anything, they're exposed
through a header file and then imported into the ArmISA namespace
/
---
(Updated 2010-12-06 16:12:26)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
O3: Fixes the way prefetches are handled inside the iew unit. This patch
prevents the prefetch being added
changeset f455790bcd47 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f455790bcd47
description:
X86: Take advantage of new PCState syntax.
diffstat:
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 ++--
src/arch/x86/isa/microops/regop.isa | 13
changeset 9df469679ac7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9df469679ac7
description:
SPARC: Take advantage of new PCState syntax.
diffstat:
src/arch/sparc/isa/decoder.isa| 104 -
changeset 762276cd3cc7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=762276cd3cc7
description:
POWER: Take advantage of new PCState syntax.
diffstat:
src/arch/power/isa/decoder.isa| 36 +-
changeset 8ac74e34c6f4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8ac74e34c6f4
description:
MIPS: Take advantage of new PCState syntax.
diffstat:
src/arch/mips/isa/decoder.isa| 42 ---
src/arch/mips/isa/formats/branch.isa
changeset 8a7ba5a1b35d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8a7ba5a1b35d
description:
Alpha: Take advantage of new PCState syntax.
diffstat:
src/arch/alpha/isa/branch.isa | 19 +--
src/arch/alpha/isa/decoder.isa | 13 +
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/338/
---
(Updated 2010-12-06 16:10:48)
Review request for Default, Ali Saidi, Gabe
:17)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
ARM: Add support for moving predicated false dest operands from sources.
Diffs
-
src/arch/arm/isa/insts/misc.isa 2b5fbdcbfb5d
src/arch/isa_parser.py
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/341/
---
(Updated 2010-12-06 16:12:00)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan
for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
O3: Support timing translations for O3 CPU fetch.
Diffs
-
src/cpu/o3/fetch.hh 2b5fbdcbfb5d
src/cpu/o3/fetch_impl.hh 2b5fbdcbfb5d
Diff: http://reviews.m5sim.org/r/340/diff
/342/
---
(Updated 2010-12-06 16:12:26)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
O3: Fixes the way prefetches are handled inside the iew unit. This patch
:
http://reviews.m5sim.org/r/343/
---
(Updated 2010-12-06 16:12:44)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
---
Fix mispredicts from non control instructions. The squash
:
---
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/344/
---
(Updated 2010-12-06 16:12:58)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan
401 - 500 of 1750 matches
Mail list logo
