Re: [PEDA] Layer Stackup Info.
At 08:55 PM 7/9/01 -0400, Mike Reagan wrote: >I would like to correct you about the discount IPC offers. The coupon they >issue to the designers council members is not redeemable, you must be an IPC >member not a member of the designers council. They must have started this >policy this year because I redeemed my coupons in the past, but his year >they did not honor it when I purchased additional manuals. Have they >honored yours? I had to pay full price. From the Designer's Council web site: "Free Designers Council Membership! Did you know that when you join or renew your IPC Designers Council membership we give you a $50.00 coupon to be used towards attending a workshop or seminar or the purchase of IPC documents? This is like getting your IPC Designers Council membership for free! Also, up to three coupons can be saved up to use towards seminars or workshops. That's $150.00 off the price of a class! These are just some of the value added benefits that Designers Council members receive." The DC site implies that one may "Save money on design by using IPC design standards," listing this as a benefit of membership, but it is not explicit that one receives the same discount as IPC members on publications. However, on the page about the certification packages, there is a list of IPC publications for use in study for the exam, with "member" and "nonmember" prices. The non-member prices are the same as are advertised to the public. The member prices are half the nonmember prices. When I joined, I got the $50 coupon plus I paid the member prices. I was told that this was a benefit of membership. Perhaps only those specific publications are offered to DC members, which would be a tad misleading [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] How do I unlock component strings ?
On 10:28 AM 10/07/2001 +1000, Linden Doyle said: >OKgot it now! > >Saving as an ASCII (V2.8) file as per Ian's recommendation but couldn't find >the record that corresponded to the locked (or other) attributes. It works if you save as an ASCII V3 format (not V2.8 format) - then you will see all the records and the Locked=True for the text records that are designators (also have the Designator=True field). Then you should be able to find records something like (for designator "C14"): Record=Text|...|Locked=True|...|Text=C14|...|Designator=True All on the one line and with the '...' meaning other fields that I can't recall. I tried it - changing from Locked=False to True worked for me. The spread function is definitely one of those Protel functions that works well when you can work it well but can be a nightmare of confusion until you work out that you have to keep your Protel session and be careful in what happens to the magic handle in your manipulations. For complex manipulations I have cut and pasted data from the Protel SS into Excel, manipulated as required and then copy and pasted back into the same Protel SS session and the updated the PCB/Sch. (I love the spread export/import functionality.) I didn't think that the SS export included the locked state for the designator string - should have checked, glad Clive did. Glad you got it sorted. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
> > Mike, why not submit your article to a few designers for review before it > is finalized for publication? Many heads, almost always, think better than > one; you'd still be the organiser and writer! > > The best list for discussion of this topic is probably the Designer's > Council list Most Protel people are electronics engineers less involved > with formal specifications and more likely to do a Class A-documented > design. There are exceptions, of course. > Mr. Lomax, I currently am a member of the Chesapeake Designers Council and have spoken and at several meetings. I am also a member of the Washington Chapter SMTA. I make every effort to attend every meeting I can. I find the forum valuable. As for submitting a preliminary to anyone on this list, I would be glad to submit my article for critic and input. I have spent the past several months honing a set of 24 design notes that I feel are very important to the fabrication of boards. Don't laugh ...yes it took me several months because my primary duties are design and cough cough management. Anyone interested in helping me, please email me directly. I still need to contact Ronda Faries at PCD this week, but I am going on vacation in the next few days so you wont have me kick around anymore. ( BAD BRAD) I would like to correct you about the discount IPC offers. The coupon they issue to the designers council members is not redeemable, you must be an IPC member not a member of the designers council. They must have started this policy this year because I redeemed my coupons in the past, but his year they did not honor it when I purchased additional manuals. Have they honored yours? I had to pay full price. Mike Reagan [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] How do I unlock component strings ?
OKgot it now! Saving as an ASCII (V2.8) file as per Ian's recommendation but couldn't find the record that corresponded to the locked (or other) attributes. Exported to a spreadsheet, massaged the data and after a bit of trial and error re-importing got it all working again. Thanks Clive. Never having used the spreadsheet import/export before I found a couple of anomolies that needed to be overcome. 1. The SS server would not display a drag handle on selected cells, although this is not the case when BOM files are generated. Ended up using copy/paste to set the appropriate cells to TRUE 2. Before finding the UPDATE button in the SS server, I attempted to use the PCB_SS:Import process (assumed it was the opposite to PCB_SS:Export). It didn't work and seems to have no help file associated with it. Thanks again guys...learnt some new features of Protel again today :) This list and all its contributors are worth their weight in gold. LINDEN DOYLE Product Development Engineer Zener Electric Pty Ltd [EMAIL PROTECTED] Ph: +61 2 9795 3600 Fax: +61 2 9795 3611 -Original Message- From: Linden Doyle <[EMAIL PROTECTED]> To: Protel EDA Forum <[EMAIL PROTECTED]> Date: Tuesday, 10 July 2001 09:16 Subject: Re: [PEDA] How do I unlock component strings ? >Thanks guys, > >Your replies are much appreciated > >Unfortunately I've been side-tracked onto other issues at the moment. > >Geoff, I've tried your suggestions (they were fairly quick) but to no >avail. > >I have noticed that the new components that I have added are not >affected. > >I'll let you know how I get on as soon as I can. > > >Thanks again, > >LINDEN DOYLE >Product Development Engineer >Zener Electric Pty Ltd > >[EMAIL PROTECTED] >Ph: +61 2 9795 3600 >Fax: +61 2 9795 3611 > > > >-Original Message- >From: Dennis Saputelli <[EMAIL PROTECTED]> >To: Protel EDA Forum <[EMAIL PROTECTED]> >Date: Tuesday, 10 July 2001 03:17 >Subject: Re: [PEDA] How do I unlock component strings ? > > >>i think i remember running into this >>as i recall I had to go back to 2.8 to fix it up for re-import >> >>Dennis Saputelli >> >>Linden Doyle wrote: >>> >>> Greetings all, >>> >>> How do I unlock component strings ? >>> >>> I didn't even know they could be locked. >>> >>> I am editing a legacy design using 99SE+SP6 (somebody else started in >Autotrax, last edited in Protel98) >>> All mods have been completed and I'm now putting component >designators and comments in the positions that I want them. When selecting >each string to be moved Protel issues the warning: "Primitive is locked. >continue?" >>> Hitting "Yes" allows me to reposition the string. I have seen (and >used) locked components before but have never seen this type of thing when >manipulating component strings. This isn't the end of the world but it is >annoying when I need to move a lo >>t of strings. >>> >>> Has anyone seen this behaviour before? Or better still how to fix it? >Am I missing something blatantly obvious? (it is Monday after all...) >>> There is nothing in the string edit dialogue box that allows the >string to be locked or unlocked. The strings are behaving as though it is a >component primitive (ie: pad or track). I've never seen this behaviour in >all the designs I have done from s >>cratch or upgraded over the years. >>> >>> (I know about the existence of the string positioning functions but I >have some mechanical constraints that I want the text to avoid - easier done >manually) >>> >>> Any help appreciated... >>> >>> TIA >>> >>> LINDEN DOYLE >>> Product Development Engineer >>> Zener Electric Pty Ltd >>> >>> [EMAIL PROTECTED] >>> Ph: +61 2 9795 3600 >>> Fax: +61 2 9795 3611 >> >>-- >>__ _ >>www.integratedcontrolsinc.comIntegrated Controls, Inc. >> tel: 415-647-04802851 21st Street >> fax: 415-647-3003San Francisco, CA 94110 >> > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
First of all, none of what I have written was intended as a personal attack, you stupid idiots! ***JOKE!!!*** No one writing here is stupid, though sometimes some of us could use a little coffee. At 05:41 PM 7/9/01 -0400, Michael Reagan wrote: >Abdul and Brad, >If your design is critical to a particular thickness, then yes you must >specify it. no doubt, however if it aint, specify the min acceptable and >give your design house the latitude to build up. Brad's point, and mine, is that one may not think the thickness critical, but thickness *will* vary the high-speed performance of the board (and a few other things which are not so likely to cause trouble). If the board is all low frequency analog, no problem. But if the board has even one or two digital nets with fast transitions, thickness variations will cause differing amounts of ringing, crosstalk, and radiated noise. So a board that works from one vendor might not work with another. It would be a shame to discover that after one has tested a board with prototypes from one vendor and maybe a small production run, and then, for a large batch where the economics are forceful, has bought the boards elsewhere. *I have seen this happen.* Now, I have actually followed Mr. Reagan's described practice. The vast majority of my designs, over the years, have not specified many details of board fabrication but have instead relied upon the fabricator's standard production characteristics. So I have not followed the advice I am now giving. I should. >Funny we are all on this >subject, I plan to submit a paper to PCD magazine, about board specification >and fab notes later this month or early next month. Therefore it is a great time to review the subject and to consider new ideas. In another post, Mr. Reagan wrote: >to clarify IPC states" > Class C is a fully documented procurement package. Documentation is to the >extent that the information is self sufficient and be sent to multiple >vendors, with each producing the identical product. This documentation >package requires that all the full manufacturing allowances are disclosed >and documented. This is an IPC spec and a very important one. I write >specifications all the time, I did aprox 80 designs last year ranging in >various sizes and speeds to 2.7 Ghz. ( fast enough) Any specification >should be written with the minimum requirements without tying your vendors >hands. IPC 2221 4.2.1.2 notes that some laminate or prepreg characteristics *shall* not be included on the master drawing. I do not specify the thickness of the material, but of the finished product. How the fabricator gets there is his business; but if the board is a multilayer board, the finished internal dimensions are normally a critical attribute. Normally, I've seen layer distances specified as nominal value without stated tolerances, unless the board is controlled impedance, in which case impedance may be specified, with tolerance, rather than dielectric gap. Again, the fabricator can figure out how to get there. The advantage of specifying impedance is that it can be measured without slicing up the board. So, unless it is critical, fully specifying dielectric thickness can be omitted, but the nominal values should *not* be omitted, because it would then be possible for a fabricator to wildly vary the thickness, making it more likely that a significant change will take place in board performance. I don't have a copy of D-325, which is the PWB documentation standard, but I would read the certification guide's restatement of it on this point as requiring nominal dimensions on the master drawing for Class B documentation (5.1, p. 132). Class C documentation, essentially, is fully defined including tolerances, Class B is less formal. Class A is "usually used for internal use." What is the difference, by the way, between "usually used for internal use," "usually for internal use," or "normally for internal use," the latter two being good writing? But for the IPC publications, this is not bad, at least it is reasonably clear! Mike, why not submit your article to a few designers for review before it is finalized for publication? Many heads, almost always, think better than one; you'd still be the organiser and writer! The best list for discussion of this topic is probably the Designer's Council list Most Protel people are electronics engineers less involved with formal specifications and more likely to do a Class A-documented design. There are exceptions, of course. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Sea
Re: [PEDA] Layer Stackup Info.
Adb ul-Rahman, sometimes you make me laugh because your thoughts, although written differently, are identical to mine. You stumbled onto the same conclusion that I had, these charts do seem to be for finished laminate not prepreg. Then one must wonder about what was being checked for stackups if a main component was missing (prepreg)? Mark, do you have one of these stackups in electronic form? I would be interested in seeing what you fabricator does for this as compared to my contact with other fabricators. My take on the Drill column was that it was a general rating for drilling of the material. Better, 'blank' & worse. I believe that I have just found a glaring technical error in the charts for FR4 and High Tg FR4. Notice how there are absolutely no differences in the Dk across the two sets of materials? My experience tells me that this is impossible, different Tg = different resin, different resin = different Dk, I have never seen the same Dk spec from any manufacturer across their regular or high Tg rated materials, there is always a variance. Seems somebody at IPC might have taken a shortcut instead of actually researching their materials. See even the IPC knows that nobody is actually supposed to read all their material. 8^> Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: Monday, July 09, 2001 3:45 PM > To: Protel EDA Forum > Subject: Re: [PEDA] Layer Stackup Info. > > > At 09:21 AM 7/9/01 -0700, Brad Velander wrote: > >Mark, > > I read your comments and went to my IPC-. I am > no IPC expert by > >any stretch but aren't the tables you specify (4-2 ... 4-6) > only for copper > >clad laminates, where are the prepregs? > > However, if you read the specification several times, you > might notice that > 4.3.6 explains that the tables "provide information on the > properties of > finished bare laminates for different prepreg constructions. > To establish > final laminate thickness with copper, add 35 um for each oz. > of copper on > the laminate." > > > By the way, looking into this made me realize that the tables cover > laminate, not prepreg. There are other specs for prepreg, > IPC-L-109 and > IPC-4101. Full employment for IPC staff! > > What DRILL means in this chart I find obscure. > > > [EMAIL PROTECTED] > Abdulrahman Lomax > P.O. Box 690 > El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] How do I unlock component strings ?
Thanks guys, Your replies are much appreciated Unfortunately I've been side-tracked onto other issues at the moment. Geoff, I've tried your suggestions (they were fairly quick) but to no avail. I have noticed that the new components that I have added are not affected. I'll let you know how I get on as soon as I can. Thanks again, LINDEN DOYLE Product Development Engineer Zener Electric Pty Ltd [EMAIL PROTECTED] Ph: +61 2 9795 3600 Fax: +61 2 9795 3611 -Original Message- From: Dennis Saputelli <[EMAIL PROTECTED]> To: Protel EDA Forum <[EMAIL PROTECTED]> Date: Tuesday, 10 July 2001 03:17 Subject: Re: [PEDA] How do I unlock component strings ? >i think i remember running into this >as i recall I had to go back to 2.8 to fix it up for re-import > >Dennis Saputelli > >Linden Doyle wrote: >> >> Greetings all, >> >> How do I unlock component strings ? >> >> I didn't even know they could be locked. >> >> I am editing a legacy design using 99SE+SP6 (somebody else started in Autotrax, last edited in Protel98) >> All mods have been completed and I'm now putting component designators and comments in the positions that I want them. When selecting each string to be moved Protel issues the warning: "Primitive is locked. continue?" >> Hitting "Yes" allows me to reposition the string. I have seen (and used) locked components before but have never seen this type of thing when manipulating component strings. This isn't the end of the world but it is annoying when I need to move a lo >t of strings. >> >> Has anyone seen this behaviour before? Or better still how to fix it? Am I missing something blatantly obvious? (it is Monday after all...) >> There is nothing in the string edit dialogue box that allows the string to be locked or unlocked. The strings are behaving as though it is a component primitive (ie: pad or track). I've never seen this behaviour in all the designs I have done from s >cratch or upgraded over the years. >> >> (I know about the existence of the string positioning functions but I have some mechanical constraints that I want the text to avoid - easier done manually) >> >> Any help appreciated... >> >> TIA >> >> LINDEN DOYLE >> Product Development Engineer >> Zener Electric Pty Ltd >> >> [EMAIL PROTECTED] >> Ph: +61 2 9795 3600 >> Fax: +61 2 9795 3611 > >-- >___ >www.integratedcontrolsinc.comIntegrated Controls, Inc. > tel: 415-647-04802851 21st Street > fax: 415-647-3003San Francisco, CA 94110 > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
At 09:21 AM 7/9/01 -0700, Brad Velander wrote: >Mark, > I read your comments and went to my IPC-. I am no IPC expert by >any stretch but aren't the tables you specify (4-2 ... 4-6) only for copper >clad laminates, where are the prepregs? Or is this a typical IPC f***up and >they have mislabeled their tables to imply something which was not intended, >I hate their documents because of these types of incongruities. > Can anybody answer these questions in regards to these tables? > >What is DS? >Where is the X & Y CTEs? Why are they not included? >What exactly is CHEM? >What do the +, - and blanks mean in the last three columns? > >Damn the IPC is so stupid when it comes to their documents, you need a guide >to their guides because they don't adequately support their information. I'm not convinced that the IPC specifications were put together by the best and brightest in our field, but let's assume that it was. Unfortunately, being the best and brightest designer or engineer does not make one the best and brightest technical writer. As to a guide to the guides, they will also sell you that. (The IPC PWB Designer Certification Study Guide). Unfortunately -- I've been using that word a lot today, haven't I? -- it does not cover the questions Mr. Velander asked. However, if you read the specification several times, you might notice that 4.3.6 explains that the tables "provide information on the properties of finished bare laminates for different prepreg constructions. To establish final laminate thickness with copper, add 35 um for each oz. of copper on the laminate." I could guess at what some of the abbreviations mean, but it would be just that: a guess. Here are my guesses: DS: Dielectric Strength (this would be measured in volts/mm, for example) Or it might mean Dimensional Stability. Z CTE: Coefficient of Thermal Expansion in the Z axis (i.e., thickness). I don't know why the X and Y CTEs are not given. By the way, looking into this made me realize that the tables cover laminate, not prepreg. There are other specs for prepreg, IPC-L-109 and IPC-4101. Full employment for IPC staff! + means "better," and - means "worse," and a blank is in between. It's an intelligence test. As a consolation, it took me about an hour to figure this out. There is a little + after the Better label on the symbol chart. What DRILL means in this chart I find obscure. I've managed to avoid, in my career, highly-specified boards for military or other use; other boards have simply referred to the specification, and the engineer did not understand the specification any more than anyone else. I think the idea is that if the board turns out to have a problem, and you just made 10,000 of them, you could do the research to find out what the spec means and thus if the fabricator violated it. But if one has specified the prepreg material, that won't work, since the fabricator will have followed specific instructions, and the chart was merely a design guide, not a specification, per se. In other words, the IPC has mixed a design guide with a specification. They are different animals and should not be combined. They have done this all over the place. It makes the documents hard to read as design guides and even harder to read as specifications. Sorry, mention the IPC and I tend to get a little steamed. They are living in a world about twenty years old, before the internet. I asked them why the CD version of the design certification kit was more expensive than the printed version. I was told that it was because they had a warehouse full of the printed versions and they needed to get rid of them. Way to go! Not only does this mean that they made a serious error in their print run, but they also apparently never heard of print-on-demand, which for specifications is most appropriate. Otherwise you end up delaying the next rev until that warehouse starts to look empty. g I was a member of the Designer's Council, it recently lapsed and I haven't renewed yet. The Designer's Council is not responsible to the members, it is a top-down organization. You can find the list of the Board of Directors on http://www.ipc.org/html/designeb.htm The site is not specific about this, but from that fact that I never heard of anything like elections, as a member-at-large, I would assume that it is a typical non-profit with a self-electing board; that is, the board elects its successor members. They might pay attention to local council recommendations, they might not. Such organizations tend to become turgid bureaucracies in spite of the best intentions. It can be just as bad when the members can vote, if the organizations are very large and the members not highly motivated to vote, and proxy voting is allowed, and the board has privileged access to the members for the issuance of proxies. An example is the California State Automobile Association, which is largely a device fo
Re: [PEDA] Layer Stackup Info.
Mike, re-reading your original post a couple of times, and this new message, I am still a little confused about not what you are spec'ing but the possible variations one could see in circuit performance. I am pretty sure I now understand exactly what you are spec'ing and 'your' reasons for doing such. Then my thoughts immediately flash to the possible variation in your build-up and the possible electrical ramifications of that methodology. I may be wrong because of the sensitivity of our company's circuits but I would think that somewhere your method could be a disaster for the unwary. And on that note, it is my belief that most design shops do not do 'any' signal integrity simulation, especially across such a possible wide variation of build up profiles. Well I look forward to your article in PCD. I am betting it will probably be a useful article, rather then the usual articles telling us everything that we already knew or didn't know, in general terms and not really supplying any useful knowledge or techniques. Mike, do you know it will be published, or is this a hopeful submission? Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: Michael Reagan [mailto:[EMAIL PROTECTED]] > Sent: Monday, July 09, 2001 2:41 PM > To: Protel EDA Forum > Subject: Re: [PEDA] Layer Stackup Info. > > > Abdul and Brad, > If your design is critical to a particular thickness, then > yes you must > specify it. no doubt, however if it aint, specify the min > acceptable and > give your design house the latitude to build up. Funny we > are all on this > subject, I plan to submit a paper to PCD magazine, about > board specification > and fab notes later this month or early next month. > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Abdul and Brad, If your design is critical to a particular thickness, then yes you must specify it. no doubt, however if it aint, specify the min acceptable and give your design house the latitude to build up. Funny we are all on this subject, I plan to submit a paper to PCD magazine, about board specification and fab notes later this month or early next month. > -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: Monday, July 09, 2001 5:15 PM > To: Protel EDA Forum > Subject: Re: [PEDA] Layer Stackup Info. > > > At 08:41 AM 7/9/01 -0700, Brad Velander wrote: > >Michael, > > while I can generally agree with your advice you leave > one aspect > >wide open. If you do not specify your layer thickness, you could > get a board > >that works fine from manufacturer A, switch to manufacturer B and have a > >board that doesn't work fine. > > > I want to underscore this. > > If one is comfortable with a particular fabricator, there is no > harm asking > that fabricator what thicknesses they would recommend based on what is > easily available, and then writing that into the board stackup > specification. Work with the fabricator. > > The down side of this would be that a less than scrupulous > fabricator might > suggest a thickness that they happen to have a lot of and need to > dump. But > that is not very likely. > > IPC- does have a table of laminates. > > If you join the IPC Designer's Council, $50, you get -- last time > I looked > -- a $50 credit toward publications, *and* you get the > publications at the > member prices. > > The sizes of FR-4 material marked in the chart as low cost are, in mm.: > > 0.07 > 0.11 > 0.13 > 0.18 > 0.26 > 0.32 > 0.37 > 0.43 > 0.53 > 0.61 > 0.64 > 0.74 > 1.52 is not given the lowest cost value, but it is very available. > > > Abd ul-Rahman Lomax > LOMAX DESIGN ASSOCIATES > PCB design, consulting, and training > Protel EDA license resales > Sonoma, California, USA > (707) 939-7021, efax (419) 730-4777 > [EMAIL PROTECTED] > [EMAIL PROTECTED] > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
At 08:41 AM 7/9/01 -0700, Brad Velander wrote: >Michael, > while I can generally agree with your advice you leave one aspect >wide open. If you do not specify your layer thickness, you could get a board >that works fine from manufacturer A, switch to manufacturer B and have a >board that doesn't work fine. I want to underscore this. If one is comfortable with a particular fabricator, there is no harm asking that fabricator what thicknesses they would recommend based on what is easily available, and then writing that into the board stackup specification. Work with the fabricator. The down side of this would be that a less than scrupulous fabricator might suggest a thickness that they happen to have a lot of and need to dump. But that is not very likely. IPC- does have a table of laminates. If you join the IPC Designer's Council, $50, you get -- last time I looked -- a $50 credit toward publications, *and* you get the publications at the member prices. The sizes of FR-4 material marked in the chart as low cost are, in mm.: 0.07 0.11 0.13 0.18 0.26 0.32 0.37 0.43 0.53 0.61 0.64 0.74 1.52 is not given the lowest cost value, but it is very available. Abd ul-Rahman Lomax LOMAX DESIGN ASSOCIATES PCB design, consulting, and training Protel EDA license resales Sonoma, California, USA (707) 939-7021, efax (419) 730-4777 [EMAIL PROTECTED] [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Library problem
At 10:19 AM 7/9/01 -0400, you wrote: > I wonder if it's possible after creating a lot of duplicates, you > could export all the copied parts fields into a spread sheet, in the > spread sheet, import & past over the fields from you supply data base > directly into Protel's spread sheet and make a whole bunch of components > at once. Unfortunately, I see no spreadsheet export from the Schematic Library editor. I'd expect there to be another relatively easy way, but it is blocked. The ASCII database form of the schematic libraries does not include the necessary fields. Protel's Group facility follows the OrCAD path. In fact, the ASCII library is either compatible with older OrCAD schematic libraries, or it is close; it may depend on OrCAD version. The OrCAD groups -- and thus the Protel groups -- are really just aliases, nothing more. The parts, in the library, are identical except for their names; if one edits one of them, including the text fields, one is editing all of them simultaneously. Another path, through the schematic editor and the MakeProjectLibrary command, is blocked because it ignores the data which one might want to take back into the Schematic Library editor. I also verified that certain key fields cannot be modified in the spreadsheet editor and taken back into the schematic. In particular, the Type field (Part Field 1) is like this, but also the Symbol name. Basically, the only way I can see to modify library symbol data is to manually edit it for each part. This is not satisfactory. Perhaps I have overlooked something. So the only way I would know to get at the library data so that one could import data from another source would be through a server for that purpose -- a library/database server --, or, what would be less convenient, an offline utility that translated symbol data into a tab-delimited database, from whence it could easily be taken into Excel, and then the modified data could be written back as tab-delimited and then rewritten as a library (or merged with an existing library file to replace fields). It is irritating to not know what is coming in SP7 and Protel 2001 or whatever they are going to call it. If we knew that Protel was not going to provide a data path into the libraries we might do this. As I recall, someone has written a program which will do what is needed at the schematic level. This, however, is not library-based control, which would be much superior. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
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Re: [PEDA] Layer Stackup Info.
Re: [PEDA] Layer Stackup Info.
At 12:04 PM 7/9/2001 -0700, you wrote: >Frank, > I am quite sure that both Mark and I both understood that. I (we?) >were wondering why they were not included in the IPC tables as a significant >piece of information when the materials quoted have such varying weaves and >resin contents. If significantly mismatched X/Y CTEs were mixed in a >stackup, it would contribute negatively to the board bow and twist. Yes it would. Sorry, I should have known you guys knew what that meant :) Misunderstandings all round today, I guess. Frank Frank Gilley Dell-Star Technologies (918) 838-1973 Phone (918) 838-8814 Fax [EMAIL PROTECTED] http://www.dellstar.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Legend
Mr.Lomax, It does in fact come with SP6. There is no NDA in force. Check it out first. At 11:20 AM 7/9/2001 -0700, Abd ul-Rahman Lomax wrote: >At 10:24 AM 7/9/01 +1000, Geoff Harland wrote: >>The documentation for this process leaves something to be desired. No >>LayerStackupAnalyzer.hlp file was provided with the prerelease version, and >>nor was such a file provided with SP6. However, given that SP6 has now been >>released on a public basis, it is now permissible for users such as myself >>to provide assistance on this server. > >The Layer Stackup Legend tool is currently available for download from >Protel as Pre-release. There is nothing to indicate that it is associated >with SP6. I don't think there is any harm in mentioning the function of >TAB in the use of this tool, but, technically, Protel has not released us >from the NDA obligations. They could remedy that easily. > >I had occasion to uninstall and reinstall 99SE and SP6, and that is why, >even though I had previously downloaded -- and probably installed -- the >tool, it was not on my Tools menu. It may very well be that the process is >made available in SP6, but it was not placed in the default menus; that >would explain what has been revealed here. > >[EMAIL PROTECTED] >Abdulrahman Lomax >P.O. Box 690 >El Verano, CA 95433 Also there was this: >At 11:26 AM 7/9/2001 -0700, Abd ul-Rahman Lomax wrote: >Protel is well-known for giving us more than it tells us it has given us > >Here is what one is "supposed to just know": > >When an object is floating on the cursor, hitting TAB will generally open >an edit menu for that object. Thus the tool designer used a Protel >standard procedure. However, since the object is complex, it is also easy >to understand why many users overlooked this. We just didn't expect it. > >One more Protel procedure: while in various screens and menus, try using >rt.click. It will often bring up a menu with available commands. Sometimes >these commands are not available any other way (in the default menus). Of >late, Protel has been filling out the default menus, so this is becoming >less true. I am very well versed on how to use Protel. I know you mean well, Abd ul-Rahman, but you often leave the impression of condescension in your posts. This has raised my Ire on numerous occasions, but I've bit my tongue until now. You reply to almost everything posted here, whether it needs replied to or not. This is a mixed blessing. However, there certainly is no reason to talk down to literally all of us, all the time. This point has been raised before in a very diplomatic manner by a certain individual we all know well here- I think this individuals' concern was what happens to the flow of ideas when one poster asserts dominance in a user group. My point was that unlike all the OTHER functions, TAB isn't accessible until you define the first point. This is in NOTABLE contrast to other functions. -Frank Frank Gilley Dell-Star Technologies (918) 838-1973 Phone (918) 838-8814 Fax [EMAIL PROTECTED] http://www.dellstar.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Frank, I am quite sure that both Mark and I both understood that. I (we?) were wondering why they were not included in the IPC tables as a significant piece of information when the materials quoted have such varying weaves and resin contents. If significantly mismatched X/Y CTEs were mixed in a stackup, it would contribute negatively to the board bow and twist. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: Frank Gilley [mailto:[EMAIL PROTECTED]] > Sent: Monday, July 09, 2001 11:35 AM > To: Protel EDA Forum > Subject: Re: [PEDA] Layer Stackup Info. > > > Brad & Mark > > X&Y CTE are Coefficient of Thermal Expansion, X and Y directions. > > -Frank > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Select & Copy Bug?
At 03:33 PM 7/9/01 +0200, Joop Reekers wrote: >Yes, this way they are properly copied and pasted. >I only need the resulting tracks of the polygons to build a simple cluster. >Thanks for the tip (or workaround)! If you only need the resulting tracks, you could also explode the polygon, which reduces it to individual independent tracks. Tools/Convert/ExplodePolygonToFreePrimitives. The tracks would then select and move like any other primitive. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Matched Net Length Rule
At 02:19 PM 7/9/01 +0200, [EMAIL PROTECTED] wrote: >Hi all, > >in the definition of the rule for "Matched Net Length" there is an item >called gap. Does anyone know what this is supposed to be and how to alter >it? In the respective properties window there is no such item. Design/Rules/HighSpeed/MatchedNetLengths/Add, you should see a drawing that explains the terms. Protel will add wiggles to tracks to attempt to equalize lengths, using the specified parameters, when you execute Tools/EqualizeNetLengths. If the wiggle were a waveform, amplitude would be its -- amplitude, and gap would be the frequency. Three styles are given; the rounded style, because it uses circular arcs, has no gap parameter. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Brad & Mark X&Y CTE are Coefficient of Thermal Expansion, X and Y directions. -Frank At 02:03 PM 7/9/2001 -0500, you wrote: >Hi Brad, > Your right about the tables they are mislabeled. They were > correct in the 9-26-99 document put out by The Copper Connection Inc. > >DS= dimensional Stability >CHEM= Chemical resistance >+ = better >- = worse >%RC = % of resin content >as for X&Y CTE you got me >Cheers >Mark >At 09:21 AM 7/9/01 -0700, you wrote: >>Mark, >> I read your comments and went to my IPC-. I am no IPC expert by >>any stretch but aren't the tables you specify (4-2 ... 4-6) only for copper >>clad laminates, where are the prepregs? Or is this a typical IPC f***up and >>they have mislabeled their tables to imply something which was not intended, >>I hate their documents because of these types of incongruities. >> Can anybody answer these questions in regards to these tables? >> >>What is DS? >>Where is the X & Y CTEs? Why are they not included? >>What exactly is CHEM? >>What do the +, - and blanks mean in the last three columns? >> >>Damn the IPC is so stupid when it comes to their documents, you need a guide >>to their guides because they don't adequately support their information. >> >> Oh, spotted one for Mike Reagan, see IPC- section 4.3.2. There >>is your requirement for specifying individual dielectric thickness within >>the stack up or else the manufacturer can do anything down to 0.09mm >>(3.5mil) minimal thickness. Note that in all legal documents the word >>"Shall" is synonymous with "must", it is a requirement for the standard. >> >>Brad Velander, >>Lead PCB Designer, >>Norsat International Inc., >>#300 - 4401 Still Creek Dr., >>Burnaby, B.C., V5C 6G9. >>Tel. (604) 292-9089 direct >>Fax (604) 292-9010 >>website www.norsat.com >> >> >> > -Original Message- >> > From: Mark E Witherite [mailto:[EMAIL PROTECTED]] >> > Sent: Monday, July 09, 2001 9:35 AM >> > To: Protel EDA Forum >> > Subject: Re: [PEDA] Layer Stackup Info. >> > >> > >> > Hi Jeff, >> > The IPC- is the one that has the prepreg and >> > core info you >> > want. I have always let the board house decided how they are >> > going to meet >> > my specks of board thickness and layer separation. Then have >> > them send me >> > the stack up configuration that they propose to use. I then >> > check their >> > stack up with the tables (4.2 to 4.6) just to insure a good stack up. >> > Cheers >> > Mark >> > > >Mark Witherite >Assistant Research Engineer >Astronomy & Astrophysics >Penn State University >2565 Park Center Blvd >Suite 200 >State College, PA. 16801 >email [EMAIL PROTECTED] >telephone 814 865 9839 >fax 814 865 9100 >IPC PWB Certified > Frank Gilley Dell-Star Technologies (918) 838-1973 Phone (918) 838-8814 Fax [EMAIL PROTECTED] http://www.dellstar.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Thanks Mark, the only one that I couldn't make a 'reasonable' guess at was the DS (dimensional stability hadn't occurred to me), but then I would argue this is a spec and one shouldn't have to guess. DS doesn't make much sense to me when they talk of tolerance and CTE separately or by other titles (not necessarily within the tables). The missing X/Y stabilities mystifies me because I am sure that these various materials, weaves and resin contents will vary significantly on X/Y stabilities and if those X/Y stabilities are too mismatched in a stack up, watch out for your bow and twist spec. I stopped trying to learn or use the IPC specs for materials a long time ago because it just confused too many fabricators. I now just work closely with them to determine which manufacturers materials meet our requirements from their standard selection using standard required performance details specific to our designs. I don't really care about the weave or %RC but do care about the x/y/z stabilities, DK, thickness and loss tangent. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: Mark E Witherite [mailto:[EMAIL PROTECTED]] > Sent: Monday, July 09, 2001 12:04 PM > To: Protel EDA Forum > Subject: Re: [PEDA] Layer Stackup Info. > > > Hi Brad, > Your right about the tables they are mislabeled. > They were correct > in the 9-26-99 document put out by The Copper Connection Inc. > > DS= dimensional Stability > CHEM= Chemical resistance > + = better > - = worse > %RC = % of resin content > as for X&Y CTE you got me > Cheers > Mark * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
ok I forgive you, Brad, I love you, man > -Original Message- > From: Brad Velander [mailto:[EMAIL PROTECTED]] > Sent: Monday, July 09, 2001 1:23 PM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Layer Stackup Info. > > > Mike, > please settle down. I am sorry that you felt I was attacking you > personally. I did not attack you or your comments, challenge you or your > experience, I only responded to your statement quoted below. > > "The only conditions in which we specify a thickness and we only > spec it for these layers, are controlled impedance, and where the min > dielectric breakdown voltage is required for Bell-Core, FCC, and space > applications." > > Now does that not sound like the situation I was describing, it > sounds as though you were saying that you do not specify the dielectric > (laminate) thickness except in the specified conditions mentioned. > > I cannot remember everyone's experience or abilities to best judge > when a statement may have been written poorly or conveyed the > wrong idea. My > comment was to point out the possible danger (even in non-specific > performance requirements, i.e. basic digital circuits) of not > specifying the > dielectric thickness in all cases. I hope that you can now see the issue > which I responded to, it was not a personal attack nor was it questioning > your abilities and I am sorry that you mistook it as such. > > Brad Velander, > Lead PCB Designer, > Norsat International Inc., > #300 - 4401 Still Creek Dr., > Burnaby, B.C., V5C 6G9. > Tel. (604) 292-9089 direct > Fax (604) 292-9010 > website www.norsat.com > > > > -Original Message- > > From: Michael Reagan [mailto:[EMAIL PROTECTED]] > > Sent: Monday, July 09, 2001 9:44 AM > > To: Protel EDA Forum > > Subject: Re: [PEDA] Layer Stackup Info. > > > > > > > > Brad, > > You failed to either comprehend what I wrote or I failed to > > communicate > > what I wrote. > > > > > Mike Reagan > > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Legend
At 11:51 AM 7/9/01 -0500, Frank Gilley wrote: >Wow, I never knew that "hidden" Tab box was in the layer stackup >legend. That feature has suddenly become useful ! >Who would have guessed that it was only available after selecting the >first corner? How is it that we are supposed to just know about these >sorts of things? Protel is well-known for giving us more than it tells us it has given us Here is what one is "supposed to just know": When an object is floating on the cursor, hitting TAB will generally open an edit menu for that object. Thus the tool designer used a Protel standard procedure. However, since the object is complex, it is also easy to understand why many users overlooked this. We just didn't expect it. One more Protel procedure: while in various screens and menus, try using rt.click. It will often bring up a menu with available commands. Sometimes these commands are not available any other way (in the default menus). Of late, Protel has been filling out the default menus, so this is becoming less true. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Legend
The layer stackup legend was included with the service pack because it is installed on my machine and I never downloaded the standalone. Nick Cobb -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Monday, July 09, 2001 1:21 PM To: Protel EDA Forum Subject: Re: [PEDA] Layer Stackup Legend At 10:24 AM 7/9/01 +1000, Geoff Harland wrote: >The documentation for this process leaves something to be desired. No >LayerStackupAnalyzer.hlp file was provided with the prerelease version, and >nor was such a file provided with SP6. However, given that SP6 has now been >released on a public basis, it is now permissible for users such as myself >to provide assistance on this server. The Layer Stackup Legend tool is currently available for download from Protel as Pre-release. There is nothing to indicate that it is associated with SP6. I don't think there is any harm in mentioning the function of TAB in the use of this tool, but, technically, Protel has not released us from the NDA obligations. They could remedy that easily. I had occasion to uninstall and reinstall 99SE and SP6, and that is why, even though I had previously downloaded -- and probably installed -- the tool, it was not on my Tools menu. It may very well be that the process is made available in SP6, but it was not placed in the default menus; that would explain what has been revealed here. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Legend
At 10:24 AM 7/9/01 +1000, Geoff Harland wrote: >The documentation for this process leaves something to be desired. No >LayerStackupAnalyzer.hlp file was provided with the prerelease version, and >nor was such a file provided with SP6. However, given that SP6 has now been >released on a public basis, it is now permissible for users such as myself >to provide assistance on this server. The Layer Stackup Legend tool is currently available for download from Protel as Pre-release. There is nothing to indicate that it is associated with SP6. I don't think there is any harm in mentioning the function of TAB in the use of this tool, but, technically, Protel has not released us from the NDA obligations. They could remedy that easily. I had occasion to uninstall and reinstall 99SE and SP6, and that is why, even though I had previously downloaded -- and probably installed -- the tool, it was not on my Tools menu. It may very well be that the process is made available in SP6, but it was not placed in the default menus; that would explain what has been revealed here. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Re: [PEDA] Layer Stackup Info.
this is why business guys still fly all over to meet face to face, it's easier and better Dennis Saputelli -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Mike, please settle down. I am sorry that you felt I was attacking you personally. I did not attack you or your comments, challenge you or your experience, I only responded to your statement quoted below. "The only conditions in which we specify a thickness and we only spec it for these layers, are controlled impedance, and where the min dielectric breakdown voltage is required for Bell-Core, FCC, and space applications." Now does that not sound like the situation I was describing, it sounds as though you were saying that you do not specify the dielectric (laminate) thickness except in the specified conditions mentioned. I cannot remember everyone's experience or abilities to best judge when a statement may have been written poorly or conveyed the wrong idea. My comment was to point out the possible danger (even in non-specific performance requirements, i.e. basic digital circuits) of not specifying the dielectric thickness in all cases. I hope that you can now see the issue which I responded to, it was not a personal attack nor was it questioning your abilities and I am sorry that you mistook it as such. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: Michael Reagan [mailto:[EMAIL PROTECTED]] > Sent: Monday, July 09, 2001 9:44 AM > To: Protel EDA Forum > Subject: Re: [PEDA] Layer Stackup Info. > > > > Brad, > You failed to either comprehend what I wrote or I failed to > communicate > what I wrote. > > Mike Reagan > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] How do I unlock component strings ?
i think i remember running into this as i recall I had to go back to 2.8 to fix it up for re-import Dennis Saputelli Linden Doyle wrote: > > Greetings all, > > How do I unlock component strings ? > > I didn't even know they could be locked. > > I am editing a legacy design using 99SE+SP6 (somebody else started in Autotrax, >last edited in Protel98) > All mods have been completed and I'm now putting component designators and >comments in the positions that I want them. When selecting each string to be moved >Protel issues the warning: "Primitive is locked. continue?" > Hitting "Yes" allows me to reposition the string. I have seen (and used) locked >components before but have never seen this type of thing when manipulating component >strings. This isn't the end of the world but it is annoying when I need to move a lot >of strings. > > Has anyone seen this behaviour before? Or better still how to fix it? Am I >missing something blatantly obvious? (it is Monday after all...) > There is nothing in the string edit dialogue box that allows the string to be >locked or unlocked. The strings are behaving as though it is a component primitive >(ie: pad or track). I've never seen this behaviour in all the designs I have done >from scratch or upgraded over the years. > > (I know about the existence of the string positioning functions but I have some >mechanical constraints that I want the text to avoid - easier done manually) > > Any help appreciated... > > TIA > > LINDEN DOYLE > Product Development Engineer > Zener Electric Pty Ltd > > [EMAIL PROTECTED] > Ph: +61 2 9795 3600 > Fax: +61 2 9795 3611 -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Legend
Wow, I never knew that "hidden" Tab box was in the layer stackup legend. That feature has suddenly become useful ! Who would have guessed that it was only available after selecting the first corner? How is it that we are supposed to just know about these sorts of things? Thanks for the info, guys Frank At 10:24 AM 7/9/2001 +1000, Geoff Harland wrote: >When using this process, you should previously switch to the layer (i.e. >make that layer the current/active layer) you want the layer legend to be >added to. When prompted, select the first corner, *then* press the Tab key >to invoke the "Layer Stackup Analyzer Setup" dialog box. That dialog box >contains checkboxes which permits you to select which details of the layer >stackup will be subsequently reported. (I regard it as confusing that this >dialog box is not invoked if the Tab key is pressed prior to selecting the >first corner.) After selecting the required items and closing the dialog >box, you will be prompted for the second corner, and the location of this >will determine how much area is occupied by the resulting text (and how high >the associated text strings consequently are). > >The documentation for this process leaves something to be desired. No >LayerStackupAnalyzer.hlp file was provided with the prerelease version, and >nor was such a file provided with SP6. However, given that SP6 has now been >released on a public basis, it is now permissible for users such as myself >to provide assistance on this server. > >Regards, >Geoff Harland. >- Frank Gilley Dell-Star Technologies (918) 838-1973 Phone (918) 838-8814 Fax [EMAIL PROTECTED] http://www.dellstar.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Brad, You failed to either comprehend what I wrote or I failed to communicate what I wrote. to clarify IPC states" Class C is a fully documented procurement package. Documentation is to the extent that the information is self sufficient and be sent to multiple vendors, with each producing the identical product. This documentation package requires that all the full manufacturing allowances are disclosed and documented. This is an IPC spec and a very important one. I write specifications all the time, I did aprox 80 designs last year ranging in various sizes and speeds to 2.7 Ghz. ( fast enough) Any specification should be written with the minimum requirements without tying your vendors hands. I am disappointed with you, that you would attack my credibility for design. My reputation stands fairly solid and I am proud and confident and outright cocky about my ability to understand high speed design issues, impedance, propagation, wavelength, and any other topic you wish to take offline. I have never blasted anyone on this list, but I take issue with your comments below Mike Reagan > > Michael, > while I can generally agree with your advice you leave one aspect > wide open. If you do not specify your layer thickness, you could > get a board > that works fine from manufacturer A, switch to manufacturer B and have a > board that doesn't work fine. The problem, one manufacturer used > a stack up > with inter-layer thickness X, manufacturer B used inter-layer thickness Y > and the board now has different impedance, inductance > characteristics. In a > lot of designs this would not cause a problem but then there could be that > one slightly longer clock trace or other timing or very level transition > sensitive signal which may not meet specs and cause a board > failure. You ran > thousands of boards from one manufacturer and they worked fine, purchasing > changed manufacturers, ordered 10,000 and now none of them work > reliably. Or > the techs nightmare, 50% of them fail but very unreliably. > Specifying just the minimum prepreg thickness does not give you any > control over the repeatability of that design and therefore does not meet > the IPC condition that any manufacturer should be able to build a > "working" > version of your PCB. If you do not specify your total laminated prepreg > thickness, you are rolling the dice. I know of some manufacturers who will > by default use a 30 - 40 mil core, others will use a 20 mil core, > if you do > not think this is significant to your design, that 'may' just be > because you > don't know your design well enough. It is not always a matter of > specifying > only for controlled impedances, it is a matter of specifying such that you > can get a reliable 'known' product from multiple manufacturers as the IPC > spec suggests. > > Brad Velander, > Lead PCB Designer, > Norsat International Inc., > #300 - 4401 Still Creek Dr., > Burnaby, B.C., V5C 6G9. > Tel. (604) 292-9089 direct > Fax (604) 292-9010 > website www.norsat.com > > > > -Original Message- > > From: Michael Reagan [mailto:[EMAIL PROTECTED]] > > Sent: Monday, July 09, 2001 8:28 AM > > To: Protel EDA Forum > > Subject: Re: [PEDA] Layer Stackup Info. > > > > > > Jeff, > > > > Word of advice...and this is a rule and a fab note we use for > > all designs. > > We specify a MIN core and prepreg thickness for all > > layers, in one fab > > note. We spec .0035 inch min. This gives your fabricator > > the latitude to > > adjust for copper distribution, laminates he has in stock, epoxies, > > pressing, over all thickness variations, etc. The only > > conditions in which > > we specify a thickness and we only spec it for these layers, > > are controlled > > impedance, and where the min dielectric breakdown voltage is > > required for > > Bell-Core, FCC, and space applications. My advice is to > > leave the majority > > of your stack up determined by your board house, unless you > > have specific > > reason to do otherwise. > > The IPC spec in 6012 for level 3 is to specify a design so > > that any board > > house can build your design with the same result. Remember you are > > designing/ writing a specification, give the fabricator > > some latitude > > > > > > Mike Reagan > > EDSI > > Frederick MD > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Michael, while I can generally agree with your advice you leave one aspect wide open. If you do not specify your layer thickness, you could get a board that works fine from manufacturer A, switch to manufacturer B and have a board that doesn't work fine. The problem, one manufacturer used a stack up with inter-layer thickness X, manufacturer B used inter-layer thickness Y and the board now has different impedance, inductance characteristics. In a lot of designs this would not cause a problem but then there could be that one slightly longer clock trace or other timing or very level transition sensitive signal which may not meet specs and cause a board failure. You ran thousands of boards from one manufacturer and they worked fine, purchasing changed manufacturers, ordered 10,000 and now none of them work reliably. Or the techs nightmare, 50% of them fail but very unreliably. Specifying just the minimum prepreg thickness does not give you any control over the repeatability of that design and therefore does not meet the IPC condition that any manufacturer should be able to build a "working" version of your PCB. If you do not specify your total laminated prepreg thickness, you are rolling the dice. I know of some manufacturers who will by default use a 30 - 40 mil core, others will use a 20 mil core, if you do not think this is significant to your design, that 'may' just be because you don't know your design well enough. It is not always a matter of specifying only for controlled impedances, it is a matter of specifying such that you can get a reliable 'known' product from multiple manufacturers as the IPC spec suggests. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: Michael Reagan [mailto:[EMAIL PROTECTED]] > Sent: Monday, July 09, 2001 8:28 AM > To: Protel EDA Forum > Subject: Re: [PEDA] Layer Stackup Info. > > > Jeff, > > Word of advice...and this is a rule and a fab note we use for > all designs. > We specify a MIN core and prepreg thickness for all > layers, in one fab > note. We spec .0035 inch min. This gives your fabricator > the latitude to > adjust for copper distribution, laminates he has in stock, epoxies, > pressing, over all thickness variations, etc. The only > conditions in which > we specify a thickness and we only spec it for these layers, > are controlled > impedance, and where the min dielectric breakdown voltage is > required for > Bell-Core, FCC, and space applications. My advice is to > leave the majority > of your stack up determined by your board house, unless you > have specific > reason to do otherwise. > The IPC spec in 6012 for level 3 is to specify a design so > that any board > house can build your design with the same result. Remember you are > designing/ writing a specification, give the fabricator > some latitude > > > Mike Reagan > EDSI > Frederick MD * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Re: [PEDA] Layer Stackup Info.
Jeff, Word of advice...and this is a rule and a fab note we use for all designs. We specify a MIN core and prepreg thickness for all layers, in one fab note. We spec .0035 inch min. This gives your fabricator the latitude to adjust for copper distribution, laminates he has in stock, epoxies, pressing, over all thickness variations, etc. The only conditions in which we specify a thickness and we only spec it for these layers, are controlled impedance, and where the min dielectric breakdown voltage is required for Bell-Core, FCC, and space applications. My advice is to leave the majority of your stack up determined by your board house, unless you have specific reason to do otherwise. The IPC spec in 6012 for level 3 is to specify a design so that any board house can build your design with the same result. Remember you are designing/ writing a specification, give the fabricator some latitude Mike Reagan EDSI Frederick MD > -Original Message- > From: Jeff Adolphs [mailto:[EMAIL PROTECTED]] > Sent: Monday, July 09, 2001 9:22 AM > To: Protel EDA Forum (E-mail) > Subject: [PEDA] Layer Stackup Info. > > > Hello, > > What IPC Standard shows core and prepreg sizes? I have IPC-6011, > IPC-6012A, > and IPC-2221 which do not have this information. > ( at a IPC workshop I was shown some slash sheet that had the > sizes and told > it was in IPC-6011 but I don't see it there, I also got the > impression I was > an idiot for not having all the IPC standards --I don't work for a large > company that buys everything and my company won't buy me $400 design > guides!! It wasn't easy to get the standards I have and frustrating when I > buy the wrong ones.) > > I have been told I should be telling on the Fab Layer the Layer Stackup > Info. I have only been specifying two thicknesses 0.080 +/- > 0.006" or 0.062 > +/- 0.006". The problem is I don't know the core and prepreg sizes. The > second problem is I don't know the PCB manufacturers stocked core and > prepreg sizes. > > Finding out what cores and prepreg sizes are stocked at the PCB > manufacturers will be time consuming and a pain in the $#&. I have had > trouble with 0.080 +/- 0.006 PCBs coming in as 0.062 or 0.092 which is out > of my specification. > > Sincerely, > > Jeff Adolphs > Lake Shore Cryotronics, Inc. > Westerville, Ohio, USA > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Jeff, I think you are referring to IPC- Sectional Design Standard for Rigid Organic Printed Boards. I do not have the standard in front of me, but I believe the tables you are looking for are in there. For a hard copy it is $15 member price and $30 for a non-member price. If you join the designers council you can buy the standards for PWB design at member prices. Regards, Ted -Original Message- From: Jeff Adolphs [mailto:[EMAIL PROTECTED]] Sent: Monday, July 09, 2001 8:22 AM To: Protel EDA Forum (E-mail) Subject: [PEDA] Layer Stackup Info. Hello, What IPC Standard shows core and prepreg sizes? I have IPC-6011, IPC-6012A, and IPC-2221 which do not have this information. ( at a IPC workshop I was shown some slash sheet that had the sizes and told it was in IPC-6011 but I don't see it there, I also got the impression I was an idiot for not having all the IPC standards --I don't work for a large company that buys everything and my company won't buy me $400 design guides!! It wasn't easy to get the standards I have and frustrating when I buy the wrong ones.) I have been told I should be telling on the Fab Layer the Layer Stackup Info. I have only been specifying two thicknesses 0.080 +/- 0.006" or 0.062 +/- 0.006". The problem is I don't know the core and prepreg sizes. The second problem is I don't know the PCB manufacturers stocked core and prepreg sizes. Finding out what cores and prepreg sizes are stocked at the PCB manufacturers will be time consuming and a pain in the $#&. I have had trouble with 0.080 +/- 0.006 PCBs coming in as 0.062 or 0.092 which is out of my specification. Sincerely, Jeff Adolphs Lake Shore Cryotronics, Inc. Westerville, Ohio, USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Library problem
Hi Rich, I've had problems with the group in the past too. You basically want your library to contain only what is exactly available in your stock. So for example, having a single 0603 cap # xxxXXX-X is, and placing a value after inserting is unacceptable. The only thing I can recommend would be to generate the first generic 0603 cap, setting the footprint & general description. Copy components & change each ones name # part value & number. I wonder if it's possible after creating a lot of duplicates, you could export all the copied parts fields into a spread sheet, in the spread sheet, import & past over the fields from you supply data base directly into Protel's spread sheet and make a whole bunch of components at once. Anyways, if you want basically all the discrete symbols pre-done for Protel's schematic capture, they are available off of my public access FTP site. Just copy this link to your Internet explorer address bar & download the files that you want. ftp://ftp.point-lab.com/quartus/Public/ProtelUsers/ Supercompact.zip - 3.1kb -> Super compact schematic symbols for almost all discrete components. _ Brian Guralnick - Original Message - From: "Richard Thompson" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Monday, July 09, 2001 9:14 AM Subject: [PEDA] Library problem | Hi, | | I am just creating a set of schematic libraries for all of our companies | components (each component is assigned its own stock number and must be | approved) the library contains only approved parts which we stock. we only | use stocked items. | i assumed that i would only have to draw one symbol for each component group | eg. one non-electrolytic capacitor, one non-electrolytic capacitor, one | diode etc with the (T)ools, New (C)omponent. which could then be assigned a | value (say 100n) then just keep adding to the group with the same symbol | with the Add to group button.(above update schematics in library editor) | however this doesnt work as it copies the description and footprint fields | across too!! how do i solve this problem? | | the only way i can see, is if i draw a schematic symbol for each component | but if i need to change it for any reason, what a pain! | | i need one symbol for each group, with its own value(description, linked to | the library fields which we need) and then the part fields linked to an | external database with our own info in them (stock number etc) | | Rich | | Richard Thompson | BLT Industries | Laney Amplification | HH Audio | | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Matched Net Length Rule
Hi all, in the definition of the rule for "Matched Net Length" there is an item called gap. Does anyone know what this is supposed to be and how to alter it? In the respective properties window there is no such item. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Select & Copy Bug?
Ian Wilson wrote: > Joop, > > Instead of using Select-Connected Copper, can you try Shift-Click on the > polygons and seeing if they copy then. I suspect that you need to select > the polygon *not* just the tracks of the polygon. There is a > difference. Using select selected copper you are only selecting > the tracks > (I suspect) and not the polygon. Yes, this way they are properly copied and pasted. I only need the resulting tracks of the polygons to build a simple cluster. Thanks for the tip (or workaround)! > Maybe there > should be a new select command Select-Polygons, possibly there would be > some use for a Expand Selection server that could expand any partially > selected copper connections and polygons which have one or more selected > tracks. Maybe this server could have an option box to control what > entities are included in the expanded selection. Maybe maybe maybe...but > not by me at this time (anyway), anyone else want a go? Yes, I agree, maybe next Service Pack (if any)? Have a nice day! Joop Reekers Semecs bv, Almelo NL. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Layer Stackup Info.
Hello, What IPC Standard shows core and prepreg sizes? I have IPC-6011, IPC-6012A, and IPC-2221 which do not have this information. ( at a IPC workshop I was shown some slash sheet that had the sizes and told it was in IPC-6011 but I don't see it there, I also got the impression I was an idiot for not having all the IPC standards --I don't work for a large company that buys everything and my company won't buy me $400 design guides!! It wasn't easy to get the standards I have and frustrating when I buy the wrong ones.) I have been told I should be telling on the Fab Layer the Layer Stackup Info. I have only been specifying two thicknesses 0.080 +/- 0.006" or 0.062 +/- 0.006". The problem is I don't know the core and prepreg sizes. The second problem is I don't know the PCB manufacturers stocked core and prepreg sizes. Finding out what cores and prepreg sizes are stocked at the PCB manufacturers will be time consuming and a pain in the $#&. I have had trouble with 0.080 +/- 0.006 PCBs coming in as 0.062 or 0.092 which is out of my specification. Sincerely, Jeff Adolphs Lake Shore Cryotronics, Inc. Westerville, Ohio, USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Select & Copy Bug?
Joop, Instead of using Select-Connected Copper, can you try Shift-Click on the polygons and seeing if they copy then. I suspect that you need to select the polygon *not* just the tracks of the polygon. There is a difference. Using select selected copper you are only selecting the tracks (I suspect) and not the polygon. I think there may be a bug of omission - in that they polygon is apparently selected (tracks highlighted) but really it is not. I seem to remember some problems with shift-click selection of polygons but thought this may have been fixed in a service pack. I am working from memory here. Maybe there should be a new select command Select-Polygons, possibly there would be some use for a Expand Selection server that could expand any partially selected copper connections and polygons which have one or more selected tracks. Maybe this server could have an option box to control what entities are included in the expanded selection. Maybe maybe maybe...but not by me at this time (anyway), anyone else want a go? Ian Wilson On 02:37 PM 9/07/2001 +0200, Joop Reekers said: >Hi All, > >I stumbled on a problem, trying to copy a part of a PCB design. >This is what happened: >First try: >Select Inside Area, to select a major part of a PCB, including 2 complete >polygons. >The polygons were not selected, I can understand that, because the >originally "polygoned" area was larger than the selected area. Outer parts >of the polygons were removed as dead copper. >Then I selected the polygons by Select Connected Copper, indeed, they were >selected. >Now, copying and pasting the selection, the polygons are NOT pasted. >Another try: >I unlocked the primitives of the polygons. >Select Inside Area: the polygon tracks are now selected. >However, copying and pasting the selection, again the polygon tracks are NOT >pasted! > >The only way to copy these polygons seems to be, to Select All, then >deselect everything I do not want to copy. Then the polygons or polygon >tracks are pasted. >A (minor?) bug or am I overlooking something? > >Have a nice day! > >Joop Reekers >Semecs bv, Almelo NL. > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Select & Copy Bug?
Hi All, I stumbled on a problem, trying to copy a part of a PCB design. This is what happened: First try: Select Inside Area, to select a major part of a PCB, including 2 complete polygons. The polygons were not selected, I can understand that, because the originally "polygoned" area was larger than the selected area. Outer parts of the polygons were removed as dead copper. Then I selected the polygons by Select Connected Copper, indeed, they were selected. Now, copying and pasting the selection, the polygons are NOT pasted. Another try: I unlocked the primitives of the polygons. Select Inside Area: the polygon tracks are now selected. However, copying and pasting the selection, again the polygon tracks are NOT pasted! The only way to copy these polygons seems to be, to Select All, then deselect everything I do not want to copy. Then the polygons or polygon tracks are pasted. A (minor?) bug or am I overlooking something? Have a nice day! Joop Reekers Semecs bv, Almelo NL. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
