On 01:26 PM 12/04/2002 -0400, [EMAIL PROTECTED] said:
><..snip..>
>If you ask Ian Wilson he has a Consolidated Partlist Server which I
>commissioned last year, that works incredibly well I might add.
>This server is configurable and may well serve your purpose.
>Regards,
http://www.considered.com
Ok, I'm starting to get the feel of it. Wish I could find a working example
though, where the subckt is used as a component in a schematic. Filling out
the fields correctly is the main confusion. Is there a schematic included
in the examples that uses one of the .ckt files from Simulation Model
Subject: Re: [PEDA] dashed box around designator
> its possible that maybe i need to close protel and reopen
> it. i tend to leave it open for days at a time, and some-
> times i notice it starts acting strange and restarting it
> often fixes the problem.
>
WOW!! You are a VERY brave fellow.
You need to have entries in your schematic symbols Library fields (enter in
Schematic Library editor). These fields designate type of model or
subcircuit, location and name of model or subcircuit, and pin assignments of
your symbol to the models internal pinout.
see Library Fields and Part Field
At 05:08 PM 4/12/2002 -0400, Watnoski, Michael wrote:
> As long as they are a unique size, they can all be changed
>afterwards with a global selection.
I don't know, offhand, the answer to the original question, but I'd think
this answer would be less than fully satisfactory, because it
I have the netlist for the guts of an OPA548 and have created a schematic
symbol to represent it and placed it in a test circuit with the schematic
editor. I want to simulate this circuit using the netlist of the OPA548 as
the subckt representation to be used in the simulation, without any speci
At 02:06 PM 4/12/2002 -0700, Embedded Matt wrote:
>Thanks to a tip from the FAQ for this mailing list, I
>got a copy of the BMP2PCB that I want to use to add my
>company logo to a PCB.
>
>I noticed that the tracks generated are 1 mil. Do
>board houses typically complain about these 1 mil
>tracks
At 11:53 AM 4/12/2002 -0700, JaMi Smith wrote:
>Interesting way of ascribing Intelligent Design to Sheer Oversight ...
No, it was merely a theory, as I wrote later, unverified. And indeed I
could not verify it, but perhaps only because I could not duplicate the
stray designator problem, even th
got it!
- Original Message -
From: "Abd ulRahman Lomax" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Friday, April 12, 2002 1:30 PM
Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic)
> I've been having ISP problems. Verizon. Need I say more? Anyway, I think
> they
Thanks to a tip from the FAQ for this mailing list, I
got a copy of the BMP2PCB that I want to use to add my
company logo to a PCB.
I noticed that the tracks generated are 1 mil. Do
board houses typically complain about these 1 mil
tracks or do they, seeing the are just a logo, let
them slide un
I've been having ISP problems. Verizon. Need I say more? Anyway, I think
they are fixed, courtesy of addr.com.
At 05:52 PM 4/11/2002 +0100, Jason Morgan wrote:
>As for the latest on the actual problem - board warping to well within IPC
>recomendations but outside of what we'd like, it seems that
Interesting way of ascribing Intelligent Design to Sheer Oversight ...
...
Actully, a feature. Here is why this happens, I think:
Protel assumes, when you are placing parts, that you will want the
relative
locations of reference designators etc. to be as you used for the last
part
placed. So
I am setting up a new design that is going to require me to use test
points on the board. I would like to use .9mm (.035") for the test point
size. I am trying to find a way to set up the design rules to automatically
place a square test pad instead. I am running 99SE SPK6, I looked in the
Speaking just to the second part of your question as applied to item 2),
i.e. the "legality".
Whether it is "legal" or not, being as charitable and kind as possible,
it is simply a very bad idea.
JaMi Smith
* * *
-Original Message-
From: Matthew Leigh [mailto:[EMAIL PROTECTED]]
Sent:
I haven't received that issue yet. But now I'm looking forward to it. I
wonder what this months center-fold will be... :)
Tim
-Original Message-
From: Samuel Cox "Sam" [mailto:[EMAIL PROTECTED]]
Sent: Friday, April 12, 2002 2:01 PM
To: Protel EDA Forum
Subject: Re: [PEDA] PCB Panelizatio
Tim and Brad,
The BOM generator in Protel only considers two fields when sorting, the Part
Type and the footprint. This has been a source of pain for me in the past,
as unless you indicate on the schematic in the part type there is a
difference (ie. 10K 1% vs 10K 5%) these parts will be grouped to
FYI,
Take a look at the April 2002 issue of Printed Circuit Design Magazine
It's focus this month is on
Panelization as a means to High-Volume Manufacturing...
Sam Cox.
At 01:36 PM 4/12/2002 -0300, you wrote:
>Thanks to all who helped with this thread. I'm reviewing them and haven't
I actually like to go with option three, which is, find out what the
Atmel / AVR / PIC / Embedded Processor / etc. is actually doing, that is
how it is actually being used in the circuit, with inputs drawn as
inputs, outputs drawn as outputs, busses drawn as busses, control lines
drawn as control
Tim,
the first source by which schematic symbols are consolidated is the
PartType field. I couldn't find any Protel documentation which defines the
criteria for consolidation in a BOM but I know it starts with the PartType
field. Don't you think that Protel could give the schematic BOM gen
Thanks to all who helped with this thread. I'm reviewing them and haven't
made a decision yet...
Tim Fifield
-Original Message-
From: Mike Reagan [mailto:[EMAIL PROTECTED]]
Sent: Friday, April 12, 2002 9:49 AM
To: Protel EDA Forum
Subject: Re: [PEDA] PCB Panelization
Thank you Dennis S
When we generate a BOM in Protel format in P99SE SP6 some parts get
consolidated even though their libref and several attributes are different.
Does anybody know why this might be happening?
Tim Fifield
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* To post a message: mailto:[EMAI
Mike,
your comments sound like a good start. As Terry had suggested,
normally a click elsewhere turns off the focus on that designator or
partfield.
Sincerely,
Brad Velander.
Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel (604) 292-9089 (direct line)
Fax (604) 292-
Waldemar,
the bugs that I have seen are invariably the ones where it causes
your system to apparently go to sleep while performing certain functions
like prints, Cam generation, etc.. The system takes forever to complete
those tasks, possibly 20 - 30 minutes for a print of your panel or
ge
Anthony,
your problem sounds like a Protel preferences or configuration
option problem. Protel stores key configuration details on particular
systems and not with a DDB, this includes items such as layer or object
colors.
The setting which I believe is effecting you is in Tools "T"
> If it is a feature, HOW DO I TURN IT OFF?
Disable 'OrCAD (TM) Ports' in 'Tools' > 'Preferences' (Schematic tab). That
should fix it.
Steve.
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* To post a message: mailto:[EMAIL PROTECTED]
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I got it. In searching my [PEDA] archive I found the ORCAD PORTS issue.
Problem fixed.
Anthony Whitesell
Sunrise Labs
mailto:[EMAIL PROTECTED]
-Original Message-
From: Anthony Whitesell [mailto:[EMAIL PROTECTED]]
Sent: Friday, April 12, 2002 11:17 AM
To: Protel EDA Forum
Subject: [PED
I have a ddb with ports on each of 4 pages of the schematic. On the first
machine, the length can be changed and is set so the schematic looks good.
When I open the schematic on a second machine, the lengths of the ports gets
changed and is fixed. I cannot change the port lengths in this ddb on
thanks for responding terry. for the life of me, i can't
get the "focus" off this one designator. i've slow clicked
and fast clicked a billion times elsewhere. i'm wiring it
now and the thing is still selected. i had the same thing
happen on earlier pages of the schematic and i finally got
tir
On Fri, 12 Apr 2002 07:45:34 -0500, miker wrote:
>what is this dashed box, why am i getting it sometimes when
>i click a designator and not others, and how do i get rid
>of it?
It indicates the designator has 'focus'.
Just left click on a blank area of the schematic to 'focus' nothing.
If y
On Fri, 12 Apr 2002 10:58:40 +0800, Matthew Leigh wrote:
>I'm drawing up a library component for an Atmel microcontroller, which has
>a large number of multi-function pins (for instance, pins 32-39 are either
>an 8-bit I/O port or half of the memory bus). I can see two ways of
>representing th
Thank you Dennis S for the pitch
- Original Message -
From: Dennis Saputelli <[EMAIL PROTECTED]>
To: Protel EDA Forum <[EMAIL PROTECTED]>
Sent: Thursday, April 11, 2002 9:05 PM
Subject: Re: [PEDA] PCB Panelization
>
> this has been kicked around a lot and i do not at all dispute what
hello,
i'm doing a schematic in protel and when i cruise around
and click to change the font on the component designators,
every so often one of them gets a dashed square around it
with a dashed line leading off to some point. once i get
the darned dashed box around the designator, i can't get
Hi,
use one pin and name it like you suggested. Even though double pin numbers
would probably work, it makes the schematic less readable in my view. For
example, I have been doing some designs with Motorola MPC8260 lately, which
has some 120+ port pins with up to 4 different programmable functio
> From: Ian Wilson [mailto:[EMAIL PROTECTED]]
> There is a KB item (2403) on the Protel KB about this. (I just searched
> for "member not found"). The item includes a fix.
>
> Ian Wilson
Ian,
That has sorted out the problem. Thank you very much indeed, and apologies
for not checking the KB fir
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