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ddress is within a range of a memory that
@@ -593,10 +586,6 @@
public:
-/// Allocate npages contiguous unused physical pages
-/// @return Starting address of first page
-Addr allocPhysPages(int npages, int poolID = 0);
-
void registerThreadContext(
ThreadCon
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}
void
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
eSize", &RangeSize);
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{ return physmem; }
/** Amount of physical memory that is still free */
Addr freeMemSize(int poolID = 0) const;
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or now, assume the only type of events are system calls.
void event(ThreadContext *tc) override { syscall(tc); }
+
+Addr allocPhysPages(int npages, int pool_id=0);
+Addr memSize(int pool_id=0) const;
+Addr freeMemSize(int pool_id=0) const;
};
} // namespace gem5
--
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memPools.push_back(pool);
+}
// also unserialize the memories in the system
physmem.unserializeSection(cp, "physmem");
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izeSection(cp, "physmem");
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Source('a9scu.cc')
-Source('amba_device.cc')
-Source('amba_fake.cc')
-Source('base_gic.cc')
-Source('display.cc')
- Source('flash_device.cc')
-Source('generic_timer.cc')
-Source('gic_v2.cc'
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hange-Id: I0aca1ef830bcc7beaee80c54d58ba8a188968491
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public/gem5
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pace gem5
#endif // __DEV_ARM_VIO_MMIO_HH__
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ions/traps")
DebugFlag('LocalApic', "Local APIC debugging")
-DebugFlag('Decoder', "Decoder debug output")
DebugFlag('X86', "Generic X86 ISA debugging")
DebugFlag('ACPI', "ACPI debug
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
if not isinstance(tags, set):
-tags = set(tags)
- self.tags = tags
-
-if add_tags:
- if isinstance(add_tags, str):
-add_tags = { add_tags }
-if not isinstance(add_tags, set):
-add_tags = set(add_tags)
-self
get(name, None)
if not func:
raise AttributeError
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27;)
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ansform("TRACING", 0)))
Source('debug/flags.cc', add_tags='gem5 trace')
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%(we
# First make a library of everything but main() so other programs can
-# link against m5.
-static_lib = env.StaticLibrary(libname, static_objs)
-shared_lib = env.SharedLibrary(libname, shared_objs)
-
-# Keep track of the object files generated so far so Executables can
-# inclu
ol', 'ToValue', 'FromValue']
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
h
index 0cf1b3b..7b98e4d 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -41,7 +41,6 @@
#ifndef __INSTRECORD_HH__
#define __INSTRECORD_HH__
-#include "arch/vecregs.hh"
#include "base/types.hh"
#include "cpu/inst_res.hh"
#include "cpu/inst_seq.hh"
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flags; }
bool getMemValid() const { return mem_valid; }
-uint64_t getIntData() const { return data.as_int; }
-double getFloatData() const { return data.as_double; }
-int getDataStatus() const { return data_status; }
+uint64_t getIntData() const { return data.asInt; }
+double get
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al);
}
void
setRegOperand(const StaticInst *si, int idx, const void *val) override
{
-cpu->setReg(regs.renamedDestIdx(idx), val);
-//TODO setResult
+const PhysRegIdPtr reg = regs.renamedDestIdx(idx);
+
ected:
-static const char* regClassStrings[];
const RegClass *_regClass = nullptr;
RegIndex regIdx;
int numPinnedWrites;
@@ -223,7 +224,7 @@
constexpr const char*
className() const
{
- return regClassStrings[classVa
te pcState;
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for source in PySource.all:
-marshal_env.Command(source.cpp, [ py_marshal, source.tnode ],
-MakeAction(embedPyFile, Transform("EMBED PY")))
Source(source.cpp, tags=source.tags, add_tags='python')
#
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er
-asPred() const
-{
-panic_if(!isPred(), "Converting scalar (or invalid) to
predicate!!");
-return std::any_cast(result);
+if (!is())
+return T{};
+return as();
}
/** @} */
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
ion; })
+.def("getAllFlagsVersion",
+ []() { return debug::AllFlagsFlag::version(); })
.def("allFlags", &debug::allFlags,
py::return_value_policy::reference)
.def("schedBreak", &schedBreak)
--
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secondary_type = RubyRequestType_ST;
} else {
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'm5.objects.'):
exec("from %s import *" % module)
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(result);
}
/** @} */
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+{
using namespace X86ISA;
+} // namespace gem5::X86ISAInst
}};
-
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cpu.threads[0]->getIsaPtr()->regClasses());
+dyn_inst->staticInst->isMacroop()) {
+dyn_inst->minorTraceInst(*this);
}
}
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%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
O3', 'IsInteger', 13),
-'O4': IntReg('udw', 'INTREG_O4', 'IsInteger', 14),
-'O5': IntReg('udw', 'INTREG_O5', 'IsInteger', 15),
# Control registers
'Y'
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: I4869eeeb4aef5884ad52025b52c9616e0541f3e6
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Id(type(), idx);
+ return RegId(*this, idx);
}
template
@@ -331,14 +336,14 @@
bool pinned;
public:
-explicit PhysRegId() : RegId(InvalidRegClass, -1), flatIdx(-1),
+explicit PhysRegId() : RegId(invalidRegClass, -1), flatIdx(-1),
numPinnedWritesToComplete(0)
{}
/** Scalar PhysRegId constructor. */
-explicit PhysRegId(RegClassType _regClass, RegIndex _regIdx,
+explicit PhysRegId(const RegClass ®_class, RegIndex _regIdx,
RegIndex _flatIdx)
-: RegId(_regClass, _regIdx), flatIdx(_flatIdx),
+: RegId(reg_class, _regIdx), flatIdx(_flatIdx),
numPinnedWritesToComplete(0), pinned(false)
{}
@@ -432,7 +437,7 @@
{
// Extract unique integral values for the effective fields of a
RegId.
const size_t index = static_cast(reg_id.index());
-const size_t class_num = static_cast(reg_id.regClass);
+const size_t class_num = static_cast(reg_id.classValue());
const size_t shifted_class_num =
class_num << (sizeof(gem5::RegIndex) << 3);
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ses();
-const size_t numFloats = regClasses.at(FloatRegClass).size();
+const size_t numFloats = regClasses.at(FloatRegClass)->size();
RegVal floatRegs[numFloats];
// This is a bit ugly, but needed to maintain backwards
// compatibility.
arrayParamIn(cp, "floatRegs.i", flo
(makeDebugFlagHH, Transform("TRACING", 0)))
-env.Command('debug/flags.cc', Value(debug_flags),
-MakeAction(makeDebugFlagCC, Transform("TRACING", 0)))
-Source('debug/flags.cc', add_tags='gem5 trace')
-
# version tags
tags = \
env.Command('sim/tags.cc', None,
--
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id, ccRegs[id.index()]);
}
TheISA::PCState pcState;
--
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G
f.hh"
#include "params/TimingExprSrcReg.hh"
#include "params/TimingExprUn.hh"
@@ -124,19 +123,6 @@
uint64_t eval(TimingExprEvalContext &context);
};
-class TimingExprReadIntReg : public TimingExpr
-{
- public:
-TimingExpr *reg;
-
-TimingExprReadIntReg(const Ti
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anch, and if that instruction's
@@ -120,7 +120,7 @@
str << "?? (x" << reg.index() << ')';
return str.str();
}
-return IntRegNames[reg.index()];
+return int_reg::RegNames[reg.index()];
} else {
i
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reg::NumArchRegs];
uint64_t fpr[NumFloatArchRegs];
uint32_t pc;
uint32_t msr;
@@ -85,7 +85,7 @@
private:
struct GEM5_PACKED
{
-uint64_t gpr[NumIntArchRegs];
+uint64_t gpr[int_reg::NumArchRegs];
uin
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ISCREG_CWP, CWP);
// Do the stores
-RegVal sp = tc->readIntReg(StackPointerReg);
+RegVal sp = tc->getReg(StackPointerReg);
Addr addr = is_64 ? sp + 2047 : sp;
for (int index = 16; index < 32; index++) {
+ RegId reg(IntRegClass, index);
0 @@
// the CC flags on top of the value
if (regRelIdx == MISCREG_CPSR) {
CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
-cpsr.nz = thread->readCCReg(CCREG_NZ);
-cpsr.c = thread->readCCReg(CCREG_C);
-cpsr.v = thread->readCCReg(CCREG_V)
umVecElemPerVecReg; j++, ei++) {
RegId elem_id(VecElemClass, ei);
-reg.as()[j] = tc->readVecElem(elem_id);
+reg.as()[j] = tc->getReg(elem_id);
}
RegId reg_id(VecRegClass, ri);
- tc->setVecReg(reg_id, reg);
+
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@
const double value(X86ISA::loadFloat80(fpu.fpr[i]));
DPRINTF(KvmContext, "Setting gem5 FP reg %i (st[%i]) := %f\n",
reg_idx, i, value);
-tc->setFloatReg(FLOATREG_FPR(reg_idx), floatToBits64(value));
5Reg.mode != LongMode) {
DPRINTF(TLB, "Not in long mode. Checking segment
protection.\n");
// Check for a NULL segment selector.
-if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
-
mreg)
FOREACH_IREG();
#undef APPLY_IREG
@@ -979,7 +979,7 @@
X86KvmCPU::updateThreadContextRegs(const struct kvm_regs ®s,
const struct kvm_sregs &sregs)
{
-#define APPLY_IREG(kreg, mreg) tc->setIntReg(mreg, regs.kreg)
+#define APPLY_IREG(kreg, mreg) tc->setReg(mreg, regs.kreg)
FOREACH_IREG();
--
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gMask);
+tc->setReg(X86ISA::cc_reg::Cfof, val & CfofMask);
+tc->setReg(X86ISA::cc_reg::Df, val & DFBit);
// Internal microcode registers (ECF & EZF)
-tc->setCCReg(X86ISA::CCREG_ECF, 0);
-tc->setCCReg(X86ISA::CCREG_EZF, 0);
+tc->setReg(X86ISA::cc_reg::Ecf, (RegVal)0);
+tc
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p, r.esp);
+context->setIntReg(int_reg::Rbp, r.ebp);
+context->setIntReg(int_reg::Rsi, r.esi);
+context->setIntReg(int_reg::Rdi, r.edi);
context->pcState(r.eip);
context->setMiscReg(MISCREG_RFLAGS, r.eflags);
if (r.cs != context->readMiscRegNoEffec
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PC state itself.
-return '%s = xc->pcState();\n' % self.base_name
+return f'{self.base_name} = xc->pcState();\n'
-def makeWrite(self, op_idx):
+def makeWrite(self):
if self.reg_spec:
# A component of the PC state.
return '__parserAutoPCState.%s(%s);\n' % \
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 4e61011..677396d 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -66,9 +66,9 @@
class PickedReg(IntReg):
@overrideInOperand
-def makeRead(self, op_idx):
+def makeRead(self):
return f'{self.base_name} = pick(xc->getRegOperand(' \
-f'this, {op_idx}), {self.reg_spec}, ' \
+f'this, {self.src_reg_idx}), {self.reg_spec}, ' \
f'{self.data_size});\n'
def __init__(self, idx, id, data_size='dataSize'):
@@ -76,9 +76,9 @@
class SignedPickedReg(IntReg):
@overrideInOperand
-def makeRead(self, op_idx):
+def makeRead(self):
return f'{self.base_name} = signedPick(xc->getRegOperand(' \
-f'this, {op_idx}), {self.reg_spec}, ' \
+f'this, {self.src_reg_idx}), {self.reg_spec}, ' \
f'{self.data_size});\n'
def __init__(self, idx, id, data_size='dataSize'):
--
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INTFV(reg_class.debug(), "Setting %s register %s (%d)
to %#x.\n",
@@ -488,7 +488,7 @@
auto ®_file = regFiles[reg.classValue()];
const auto ®_class = reg_file.regClass;
-if (reg.index() == reg_class.zeroReg() || reg.is(InvalidRegClass))
+if (reg.is(In
011 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -66,7 +66,7 @@
class PickedReg(IntReg):
@overrideInOperand
-def makeRead(self, predRead, op_idx):
+def makeRead(self, op_idx):
return f'{self.base_name} = pick(xc->getRegOperand(' \
f'this, {op_idx}), {self.reg_spec}, ' \
f'{self.data_size});\n'
@@ -76,7 +76,7 @@
class SignedPickedReg(IntReg):
@overrideInOperand
-def makeRead(self, predRead, op_idx):
+def makeRead(self, op_idx):
return f'{self.base_name} = signedPick(xc->getRegOperand(' \
f'this, {op_idx}), {self.reg_spec}, ' \
f'{self.data_size});\n'
--
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return;
DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
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