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• • Re: [OpenRISC] adv_jtag_bridge Franck JULLIEN
• Re: [OpenRISC] [Openrisc] [Legal] A question or two about FPGAs, license boundaries Eric Anderson
• [OpenRISC] (no subject) Franck JULLIEN
  • Re: [OpenRISC] (no subject) Ouabache Designworks
  • Re: [OpenRISC] (no subject) Stefan Kristiansson
  • Re: [OpenRISC] (no subject) Franck JULLIEN
  • [OpenRISC] (no subject) Jose Teixeira de Sousa
• [OpenRISC] Simulation log Franck JULLIEN
  • Re: [OpenRISC] Simulation log Julius Baxter
  • Re: [OpenRISC] Simulation log Franck JULLIEN
  • Re: [OpenRISC] Simulation log Franck JULLIEN
• [OpenRISC] Barebox port Franck JULLIEN
  • Re: [OpenRISC] Barebox port Stefan Kristiansson
  • Re: [OpenRISC] Barebox port Franck JULLIEN
• [OpenRISC] Encoding of jump/branch immediates by assembler Julius Baxter
• [OpenRISC] CGEN and binutils Julius Baxter
  • Re: [OpenRISC] [Openrisc] CGEN and binutils Richard Herveille
  • Re: [OpenRISC] [Openrisc] CGEN and binutils Julius Baxter
  • Re: [OpenRISC] [Openrisc] CGEN and binutils Richard Herveille
• [OpenRISC] Enabling SDHC on the new ordb2a-ep4ce22 board James Bartlett
  • Re: [OpenRISC] Enabling SDHC on the new ordb2a-ep4ce22 board Yann Vernier
• [OpenRISC] Geting started with the ordb2a-ep4ce22 board, Ubuntu image Iztok Jeras
• [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Matthew Hicks
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Julius Baxter
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Matthew Hicks
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Stefan Kristiansson
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Julius Baxter
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Matthew Hicks
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Julius Baxter
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Stefan Kristiansson
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Julius Baxter
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Stefan Kristiansson
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Matthew Hicks
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Julius Baxter
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Stefan Kristiansson
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Jonas Bonn
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers R. Diez
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Jonas Bonn
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Julius Baxter
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Ouabache Designworks
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Julius Baxter
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Jonas Bonn
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Stefan Kristiansson
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Jonas Bonn
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Pekon Gupta
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Julius Baxter
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Pekon Gupta
  • Re: [OpenRISC] Arch. manual discrepancy w.r.t. cache registers Julius Baxter
  • [OpenRISC] Bug in OpenOCD? Steve Battazzo
  • Re: [OpenRISC] Bug in OpenOCD? Julius Baxter
  • Re: [OpenRISC] Bug in OpenOCD? Jeremy Bennett
  • Re: [OpenRISC] Bug in OpenOCD? Steve Battazzo
• [OpenRISC] [Linux][PATCH] Clear register macro and clear r0 in _start Matthew Hicks
  • Re: [OpenRISC] [Linux][PATCH] Clear register macro and clear r0 in _start Julius Baxter
  • Re: [OpenRISC] [Linux][PATCH] Clear register macro and clear r0 in _start Matthew Hicks
• [OpenRISC] or1ktrace library linking questions Julius Baxter
  • Re: [OpenRISC] [Openrisc] or1ktrace library linking questions Jeremy Bennett
  • Re: [OpenRISC] [Openrisc] or1ktrace library linking questions Julius Baxter
  • Re: [OpenRISC] [Openrisc] or1ktrace library linking questions Joern Rennecke
• Re: [OpenRISC] [Bug 1] [confirmed] [patch] Yann Vernier
  • Re: [OpenRISC] [Bug 1] [confirmed] [patch] Olof Kindgren
  • Re: [OpenRISC] [Bug 1] [confirmed] [patch] Yann Vernier
• [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 Matthew Hicks
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 Stefan Kristiansson
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 Matthew Hicks
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 Olof Kindgren
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 Jonas Bonn
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 Jonas Bonn
  • Re: [OpenRISC] [Openrisc] [OR1200][PATCH] Ignore writes to register 0 Richard Herveille
  • Re: [OpenRISC] [Openrisc] [OR1200][PATCH] Ignore writes to register 0 Jeremy Bennett
  • Re: [OpenRISC] [Openrisc] [OR1200][PATCH] Ignore writes to register 0 Richard Herveille
  • Re: [OpenRISC] [Openrisc] [OR1200][PATCH] Ignore writes to register 0 Jeremy Bennett
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 lobachevsky
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 lobachevsky
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 lobachevsky
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 Yann Vernier
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 Matthew Hicks
  • Re: [OpenRISC] [Openrisc] [OR1200][PATCH] Ignore writes to register 0 Richard Herveille
  • Re: [OpenRISC] [Openrisc] [OR1200][PATCH] Ignore writes to register 0 Olof Kindgren
  • Re: [OpenRISC] [OR1200][PATCH] Ignore writes to register 0 Yann Vernier
• Re: [OpenRISC] Memory Init that allows Linux simulation Matthew Hicks
  • Re: [OpenRISC] Memory Init that allows Linux simulation Julius Baxter
  • Re: [OpenRISC] Memory Init that allows Linux simulation Matthew Hicks
  • Re: [OpenRISC] Memory Init that allows Linux simulation Julius Baxter
  • Re: [OpenRISC] Memory Init that allows Linux simulation Olof Kindgren
  • Re: [OpenRISC] [ORLinux] Memory Init that allows Linux simulation Jonas Bonn
  • Re: [OpenRISC] [ORLinux] Memory Init that allows Linux simulation Olof Kindgren
  • Re: [OpenRISC] [Openrisc] [ORLinux] Memory Init that allows Linux simulation Jeremy Bennett
  • Re: [OpenRISC] [ORLinux] Memory Init that allows Linux simulation Matthew Hicks
  • Re: [OpenRISC] [Openrisc] [ORLinux] Memory Init that allows Linux simulation Richard Herveille
  • Re: [OpenRISC] [Openrisc] [ORLinux] Memory Init that allows Linux simulation Stefan Kristiansson
  • Re: [OpenRISC] [Openrisc] [ORLinux] Memory Init that allows Linux simulation Matthew Hicks
  • Re: [OpenRISC] [Openrisc] [ORLinux] Memory Init that allows Linux simulation Julius Baxter
  • Re: [OpenRISC] [Openrisc] [ORLinux] Memory Init that allows Linux simulation Julius Baxter
• Re: [OpenRISC] Programming OpenRISC board fails Yann Vernier
• Re: [OpenRISC] link libgcc Jeremy Bennett
  • Re: [OpenRISC] link libgcc Jonas Bonn

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