This problem is likely either that prefetches don't mark themselves as
such, or that they do and it gets lost somewhere. I'll look at this
tonight. Could you throw together a simple program that demonstrates the
problem quickly?
Gabe
Vince Weaver wrote:
> Hello
>
> I tried tracking this problem d
g happened, complicating logic
downstream? Do they return a fault that gets squelched if the access was
a prefetch? I think the later has a better chance of avoiding subtle issues.
Gabe
Vince Weaver wrote:
> On Fri, 16 Oct 2009, Gabe Black wrote:
>
>
>> This problem is likely ei
changeset 34191eea18c1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=34191eea18c1
description:
ISA: Fix compilation.
diffstat:
5 files changed, 15 insertions(+), 10 deletions(-)
src/arch/alpha/isa.cc|4 ++--
src/arch/alpha/isa.hh|5 +++--
src/arch/arm/is
Ali Saidi wrote:
> I'm just scratching my head on this one. It seems like since July
> checkpointing was broken since we weren't properly serializing the miscReg
> stuff (now ISA)?
>
> EventManager is a proxy to let objects call schedule(event, when) without
> having to know anything about the eve
etch. This is how software prefetch instructions work on Alpha
> (or at least worked at some point in the past). If something in a CPU
> model is not handling NO_FAULT properly, then I'd say that's your bug.
>
> Steve
>
> On Fri, Oct 16, 2009 at 11:47 PM, Gabe Black <mailt
tentially
block execution, and the other you wouldn't. So my question to the
memory guys is, do we care? Which flags do we actually want? How should
they work within the CPU as far as how far faults get, etc?
Gabe
Gabe Black wrote:
> It seems like we have three flags that all look like the
In the simple CPU, the requests are all translated before any are sent,
so you can't have something half in the memory system and then take a
fault on it. I don't know exactly how that would map to O3. I believe
it's fine to do 3 bytes and 1 byte as two requests since they only have
to avoid block
Sorry I didn't respond yesterday. I was sick and went right to bed after
work. This is probably ok, although I haven't looked at it in great
depth. If you boot the x86 disk image all the way to the login prompt,
one of the startup scripts will fail. If it fails and prints an error
message once, the
Timothy M Jones wrote:
> On Wed, 21 Oct 2009 18:12:59 +0100, Gabe Black
> wrote:
>
>
>> In the simple CPU, the requests are all translated before any are sent,
>> so you can't have something half in the memory system and then take a
>> fault on it. I don&#
Vince Weaver wrote:
>> +// I'm not sure why, but the length argument is in arg reg 3
>> +loff_t length = process->getSyscallArg(tc, 3);
>>
>
> The reason for this is that on various architectures, if you are passing a
> 64-bit value on a 32-bit architecture, the 64-bit value has to be
Vince Weaver wrote:
> On Sat, 24 Oct 2009, Gabe Black wrote:
>
>> The getSyscallArg function can be defined differently for different
>> types of processes, typically 32 bit vs. 64 bit. Defining those
>> differently might do it. It could be more complicated than that
Vince Weaver wrote:
> On Sat, 24 Oct 2009, nathan binkert wrote:
>
>> I don't know the code super well, but I'd think it possible to process
>> arguments in order without too much trouble. Given the C calling
>> convention, it would be extraordinarily odd to have a later argument
>> define the
# HG changeset patch
# User Gabe Black
# Date 1256506479 25200
# Node ID c10c055aac81c3c80db173edec40069416aee4e4
# Parent 67d980fcbc7a4957bcfb42fe5b89db5e62d79d60
Syscalls: Make system calls access arguments like a stack, not an array.
When accessing arguments for a syscall, the position of an
used by any ISA so I can't really
test it explicitly. Also, I only put in special rules for 32 bit x86. It
sounds like other ISAs have other rules which I'm not necessarily
familiar with. It should be easy to fix them up using I386LinuxProcess
as an example.
Gabe
G
Ali Saidi wrote:
> I believe that the rules are as follows (from some google searches,
> but I couldn't find a definitive list):
> 64 bit arch/app -- Do nothing special
> 32 bit arch/app -- 64 bit values are aligned evenly with the exception
> of x86 and ARM OABI (which we don't support and don
Once the argument fix makes it into the tree, please send this out again
taking advantage of the new system. It looks fine otherwise. Also, if
you wouldn't mind, could you please try out my patch and make sure it
actually works correctly for you? I'd hate to change everything around
and not actuall
Timothy M Jones wrote:
> On Thu, 22 Oct 2009 09:36:49 +0100, Gabe Black
> wrote:
>
>> If you'd be willing,
>> making it into a timing translation while you're allowing split accesses
>> would be helpful for x86 in the future.
>
> I've made a
Vince Weaver wrote:
> Hello
>
> was doing some more work trying to get spec2k running on x86_64.
>
> Below is a patch where I implemented movdqu/movdqa. This is enough (in
> conjunction with some other syscall patches) to get many of the benchmarks
> working.
>
> I'm not sure if doing the 16-byt
Vince Weaver wrote:
> Hello
>
> I've tested this patch. It is broken on 32-bit x86 unless the below patch
> is applied. With that applied, it seems to work fine on the various test
> cases I have, including truncate64 and ftruncate64.
>
> Vince
>
> diff -r 62800dbea5a8 src/arch/x86/process.cc
>
changeset 21047815f78e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=21047815f78e
description:
X86: Replace "DISPLACEMENT" with disp in movhpd.
diffstat:
1 file changed, 4 insertions(+), 4 deletions(-)
src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.p
I was going to push the arguments-as-a-stack patch with Vince's
fixes, but I couldn't build power because there were no default scons
options. Is there something I'm missing, or was a file left out?
Gabe
___
m5-dev mailing list
m5-dev@m5sim.org
http:
There's a subtle bug in this implementation that crops up when the
operations are split in half like they are. In HADDPD_XMM_XMM, if xmml
and xmmlm refer to the same register, you'll overwrite the value you're
supposed to use in the second uop. You'll want to use maybe ufp1 in the
first uop and a m
> // repne (0xF2)
> diff -r a3c85a29b838
> src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py
> --- a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.pyTue Oct
> 27 09:24:40 2009 -0700
> +++ b/src/arch/x86/isa/insts/simd128/integer/data_t
nathan binkert wrote:
> Sorry for the duplicate e-mail. Anyway, I got a new machine that I
> just set up yesterday with ubuntu 9.10 and I fixed the new problems.
> Can people please look this over? Mostly what happened:
>
> 1) cstdio was not implicitly included by some other headers, so we
> need
changeset 4842482e1bd1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4842482e1bd1
description:
Syscalls: Make system calls access arguments like a stack, not an array.
When accessing arguments for a syscall, the position of an argument
depends on
the p
These sorts of questions should go to m5sim-users. Please resend your
question there.
Gabe
Mark Desuja wrote:
> Hi,
>I'm a new user of M5./ /I would like to integrate dramsim1.0/2.0
> with M5. Could you please send me the patch.
>
> thanks,
> -mark
>
> --
changeset 21f032e2ee9b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=21f032e2ee9b
description:
Syscalls: Fix a warning turned error about an unused variable in
m5.fast.
diffstat:
1 file changed, 2 insertions(+)
src/sim/syscall_emul.cc |2 ++
diffs (13 lines):
di
I'm currently waiting for memtest-ruby to finish running, and looking at
the stats that's going to take about 55 minutes all together. That
doesn't qualify as quick to me, so maybe it shouldn't be in the quick
regressions?
Gabe
___
m5-dev mailing list
m5
If you set destSize=8 I think that'll solve the first problem. The
source register is put into a uint64_t, and then that's put into a
destSize sized chunk of the destination register. If you set that to be
8, the uint64_t will take up the whole xmml, and the uint64_t is zero
extended. The second bu
This looks fine and I'll commit it. One thing that would be nice,
though, is if you put a short tag at the beginning of the first line of
your patch. This way, if someone is looking through changesets, they can
easily see what affected what. For this patch, I'd use X86, for some of
your others mayb
The change itself seems to be correct, but I'm not sure why it's
necessary. Basically, what's going on with the code you're changing is
that the instruction has a one byte immediate encoded as part of the
instruction. The predecoder collects that one byte, and then sign
extends it to 64 bits an
r 0e5037cecaf7 -r aef69bb302b5
> src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py
> ---
> a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py
> Fri Oct 30 12:49:37 2009 -0400
> +++
> b/src/arch/x86/isa/insts/simd128/float
You seem to be missing the majority of the PC relative version... Would
you like to fix that up, or should I?
Gabe
Gabe Black wrote:
> I debated adding an hadd microop or adding a flag that changed the
> behavior of maddf, but in the end I didn't do either since I didn't have
Vince Weaver wrote:
> On Fri, 6 Nov 2009, Gabe Black wrote:
>
>
>> You seem to be missing the majority of the PC relative version... Would
>> you like to fix that up, or should I?
>>
>
> I'll fix it, I can't believe I missed that. I need
Nathan Binkert wrote:
> # HG changeset patch
> # User Nathan Binkert
> # Date 1257554904 28800
> # Node ID 4295150ba57fcd97ec518ec085fb62ffc89783be
> # Parent fb4a3a61bc745c49975c552927ae9a35405f02dd
> compile: wrap 64bit numbers with ULL() so 32bit compiles work
> In the isa_parser, we need to c
Vince Weaver wrote:
> Hello
>
> The attached patch implements the x87 fsincos and fnstsw instructios on
> x86.
>
> These are actually the only unimplemented x86 instructions used by -msse3
> compiled benchmarks.
>
> Because of that, I created this hackish patch, which lets the benchmarks
> run.
changeset 0ad05775b549 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0ad05775b549
description:
ARM: Get rid of some unneeded register indexes.
diffstat:
1 file changed, 30 deletions(-)
src/arch/arm/registers.hh | 30 --
diffs (47 lines):
S SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include
+
+#ifndef __ARCH_ARM_INTREGS_HH__
+#define __ARCH_ARM_INTREGS_HH__
+
+namespace ArmISA
+{
+
+enum IntRegIndex
+{
+/* All the unique register indices. */
+INTREG_R0,
+INTREG_R1,
+
changeset 2a131d15ec34 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2a131d15ec34
description:
ARM: Implement the shadow registers using register flattening.
diffstat:
1 file changed, 41 insertions(+), 2 deletions(-)
src/arch/arm/isa.hh | 43
changeset 260676453f66 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=260676453f66
description:
ARM: Initialize processes in user mode.
I accidentally left in a change to test using int registers in system
mode.
This change reverts that.
diffstat:
1 f
changeset 36aa46630e62 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=36aa46630e62
description:
ARM: Get rid of the Raddr operand.
diffstat:
1 file changed, 1 deletion(-)
src/arch/arm/isa/operands.isa |1 -
diffs (11 lines):
diff -r 260676453f66 -r 36aa46630e62 sr
changeset 77318ac91316 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=77318ac91316
description:
ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.
diffstat:
2 files changed, 5 insertions(+), 3 deletions(-)
src/arch/arm/intregs.hh |2 ++
s
changeset 93f1e520447d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=93f1e520447d
description:
ARM: Get rid of NumInternalProcRegs.
That constant is a carry over from Alpha and doesn't do anything in ARM.
diffstat:
1 file changed, 1 deletion(-)
src/arch/arm/r
changeset ea7c71a3433a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ea7c71a3433a
description:
ARM: Add in more bits for the mon mode.
diffstat:
3 files changed, 5 insertions(+)
src/arch/arm/isa.hh |3 +++
src/arch/arm/miscregs.hh |1 +
src/arch/arm/types.h
changeset 70129fdded75 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=70129fdded75
description:
ARM: Split the condition codes out of the CPSR.
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
I'm looking at it. I think there were three x86 changes since these last
passed, "X86: Hook up time syscall on X86", "X86: Enable x86_64 vsyscall
support", and "X86: Fix problem with movhps instruction". I figure out
which one, and look at the stats changes.
Gabe
nathan binkert wrote:
>> * bu
It was the change to add the vsyscall page. atomic didn't change, and I
think timing changed just because the layout of memory changed a little.
It should be fine to update the stats.
Gabe
Gabe Black wrote:
> I'm looking at it. I think there were three x86 changes since these last
&
changeset c469a9365a4a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c469a9365a4a
description:
ARM: Simplify the load/store multiple generation code.
Specifically, get rid of the big switch statement so more cases can be
handled. Enumerating all the pos
changeset a5322e816a2a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a5322e816a2a
description:
ARM: Support forcing load/store multiple to use user registers.
diffstat:
4 files changed, 32 insertions(+), 26 deletions(-)
src/arch/arm/insts/macromem.hh| 25 +++
These patches fix up x86 and the simple CPUs to handle prefetches correctly.
I've run the quick regressions for everything, SE and FS, and ran a good ways
into X86_FS manually. I haven't run any of the long regressions, and I haven't
done anything with any of the other CPU models. With this change,
# HG changeset patch
# User Gabe Black
# Date 1257749397 28800
# Node ID 530e457c88c7850e84c8df2cb478d566094ad39e
# Parent eea52bdaf4acce7788ceea2406dc33a24bdda0b2
X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops
# HG changeset patch
# User Gabe Black
# Date 1257749397 28800
# Node ID b3ab661715ac41e528c48843ebfe5885aa33b7a7
# Parent 530e457c88c7850e84c8df2cb478d566094ad39e
X86: Explain what really didn't work with unmapped addresses in SE mode.
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/t
# HG changeset patch
# User Gabe Black
# Date 1257749398 28800
# Node ID 44010fc924d4778fb0900ff59704673767c76708
# Parent b3ab661715ac41e528c48843ebfe5885aa33b7a7
X86: Don't panic on faults on prefetches in SE mode.
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
--- a/src/arc
# HG changeset patch
# User Gabe Black
# Date 1257749399 28800
# Node ID 6824ff4b01847b1b35095e1cad5c57b1c5c481b6
# Parent 44010fc924d4778fb0900ff59704673767c76708
Mem: Eliminate the NO_FAULT request flag.
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
--- a/src/arch/alpha
Gabe Black wrote:
> ___
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
Whoops. It looks like I forgot to start a new patch here. This
eliminates NO_FAULT and also makes the simple CPU handle faultin
nathan binkert wrote:
> Gabe, can you send out your patches inline, not as attachments? Did
> you switch intentionally? It makes it harder to comment on your
> changes.
>
> Nate
> ___
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman
changeset 4ac7bc30c482 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4ac7bc30c482
description:
ARM: Fix the integer register indexes.
The PC indexes in the various register sets was defined in the section
for
unaliased registers which was throwing off
@@ -26,488 +26,114 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Gabe Black
- * Stephen Hines
+ * Authors: Ali Saidi
+ * Gabe Black
*/
#include "arch/arm
changeset 530e457c88c7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=530e457c88c7
description:
X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/arch/x86/isa/microops/ldstop.isa |4 ++--
diffs (21 lin
changeset b3ab661715ac in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b3ab661715ac
description:
X86: Explain what really didn't work with unmapped addresses in SE mode.
diffstat:
1 file changed, 13 insertions(+), 3 deletions(-)
src/arch/x86/tlb.cc | 16 +-
changeset 44010fc924d4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=44010fc924d4
description:
X86: Don't panic on faults on prefetches in SE mode.
diffstat:
1 file changed, 15 insertions(+), 11 deletions(-)
src/arch/x86/tlb.cc | 26 +++---
diffs
changeset 48d10ba361c9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=48d10ba361c9
description:
Mem: Eliminate the NO_FAULT request flag.
diffstat:
8 files changed, 26 insertions(+), 10 deletions(-)
src/arch/alpha/faults.cc |2 +-
src/arch/alpha/isa/decoder
Tue Nov 10 21:12:53 2009 -0800
@@ -26,488 +26,114 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Gabe Black
- * Stephen Hines
+ * Authors: Ali Saidi
+ * Gabe Black
changeset 73d89772f409 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=73d89772f409
description:
ARM: Fix some bugs in the ISA desc and fill out some instructions.
diffstat:
5 files changed, 98 insertions(+), 41 deletions(-)
src/arch/arm/isa/bitfields.isa|1
src
Would you be able to use srcSizeBits instead of srcSignIndex? This is
defined as the number of bits in a source operand, so you might need to
subtract one to get the right index. If you substitute and simplify your
expression for srcSignIndex (which the compiler is hopefully doing
already), I think
changeset cdc62b81747e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cdc62b81747e
description:
ARM: Hook up the moded versions of the SPSR.
These registers can be accessed directly, or through MISCREG_SPSR which
will
act as whichever SPSR is appropriat
changeset 7d2767d7896f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7d2767d7896f
description:
ARM: More accurately describe the effects of using the control operands.
diffstat:
1 file changed, 6 insertions(+), 6 deletions(-)
src/arch/arm/isa/operands.isa | 12 +
changeset dc2adb75 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=dc2adb75
description:
ARM: Write some functions to write to the CPSR and SPSR for
instructions.
diffstat:
1 file changed, 50 insertions(+)
src/arch/arm/insts/static_inst.hh | 50 ++
changeset ad8698d92176 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ad8698d92176
description:
ARM: Fix up the implmentation of the mrs instruction.
diffstat:
1 file changed, 4 insertions(+), 2 deletions(-)
src/arch/arm/isa/decoder.isa |6 --
diffs (23 lines):
changeset ac658ad78659 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ac658ad78659
description:
ARM: Add a bitfield to indicate if an immediate should be used.
diffstat:
2 files changed, 2 insertions(+)
src/arch/arm/isa/bitfields.isa |1 +
src/arch/arm/types.hh
changeset 33ac9df63f3e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=33ac9df63f3e
description:
ARM: Define a mask to differentiate purely CPSR bits from CondCodes
bits.
diffstat:
1 file changed, 4 insertions(+)
src/arch/arm/miscregs.hh |4
diffs (14 lines):
changeset 065d296b929b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=065d296b929b
description:
ARM: Fix up the implmentation of the msr instruction.
diffstat:
1 file changed, 27 insertions(+), 10 deletions(-)
src/arch/arm/isa/decoder.isa | 37 +++
changeset 097d0a64650f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=097d0a64650f
description:
ARM: Switch the immediate and register versions of msr.
These were accidently transposed. This change straightens them out.
diffstat:
0 files changed
__
changeset c2b6531c305c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c2b6531c305c
description:
ARM: Check in the actual change from the last commit.
The last commit was somehow empty. This was what was supposed to go in
it.
diffstat:
1 file changed, 12 inser
changeset 72836109775f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=72836109775f
description:
ARM: Create a new type of load uop that restores spsr into cpsr.
diffstat:
1 file changed, 17 insertions(+)
src/arch/arm/isa/formats/macromem.isa | 17 +
d
changeset e9970c1bccdd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e9970c1bccdd
description:
ARM: Make the exception return form of ldm restore CPSR.
diffstat:
1 file changed, 10 insertions(+), 3 deletions(-)
src/arch/arm/isa/formats/macromem.isa | 13 ++--
This sort of question should be on the m5sim-users mailing list. Please
move it there.
Gabe
Sujay Phadke wrote:
> Hello,
> I am trying to use M5-dev (latest) in SE mode with multiple cpu's
> (n=4) switching from atomic->timing->detailed. However, the assertion
> in src/cpu/o3/thread_context_
if (interrupts[IT_DEV_MONDO]) {
> - return new DevMondo;
> -}
> -if (interrupts[IT_SOFT_INT]) {
> -int level = InterruptLevel(interrupts[IT_SOFT_INT]);
> -return new Inter
Why did you change the namespaces from ArmISA to ArmISAInst? ArmISAInst
is supposed to be a private namespace for the isa_parser to dump into.
It avoids mixing generated and handcoded namespaces and all the problems
that can cause. Also, while I don't disagree with your indentation
changes, cou
I've been meaning to, but I wanted to wait until I got back from
vacation. I'll try to look at it this evening. I'd feel best if Steve
looked at it too.
Gabe
nathan binkert wrote:
> Gabe is really the one that should review these. (Or perhaps steve.)
> Can one of you take a quick look?
>
> Tha
Generally this looks like a fairly straightforward port replacement of
the original code with something essentially equivalent which is fine.
One issue is the new virtual finishTranslation function. Since
translation will happen very frequently (at least once a fetch), it's
best to avoid a virt
Timothy M Jones wrote:
On Wed, 02 Dec 2009 01:31:03 -, Gabriel Michael Black
wrote:
Quoting Timothy M Jones :
Thanks Gabe.
I've run all regressions and there are some that fail. I've checked the
differences and it's mainly changes in the number of DTB accesses (as
expected).
Hi everybody. I've been doing a bunch of work on our ARM support,
and I've run into a few issues unique (or at least especially present)
to that ISA. I have solutions that I've partially implemented, but I
wanted to talk about them here so everyone will have a chance to comment.
1. Many (most?
Does anybody have any comments? I'd like to address any issues sooner
rather than later.
Gabe
Gabe Black wrote:
> Hi everybody. I've been doing a bunch of work on our ARM support,
> and I've run into a few issues unique (or at least especially present)
> to that IS
Gabriel Michael Black wrote:
> Quoting Korey Sewell :
>
>
>>> I haven't checked too carefully, but this same problem may be
>>> affecting ARM as well (since I think it uses the same paired
>>> floating-point register scheme). Also, other double-precision things
>>> like checking for NaNs may be
Gabe Black wrote:
> Gabriel Michael Black wrote:
>
>> Quoting Korey Sewell :
>>
>>
>>
>>>> I haven't checked too carefully, but this same problem may be
>>>> affecting ARM as well (since I think it uses the same paired
>>
Matt wrote:
> I'm having problems getting double-precision floating-point to work in
> m5 for the MIPS isa.
>
> The 32-bit MIPS isa has 32 32-bit floating-point registers.
> Double-precision floating-point numbers are stored in pairs of
> floating-point registers. At least that's how I understand
Hi everybody. Rather than blowing out your inboxes with 90 patches,
please pull my patch queue from ssh://h...@m5sim.org/arm-patches.
Everything is included except the obviously labeled final patch. As far
as I know I haven't broken anything, but since we've only got one fairly
easy regress
to get it to handle some of the more recent changes to the Linux
> MIPS syscall interface. So hopefully, since this is a pretty simple
> little program, it won't do anything your version of M5 doesn't yet
> support.
>
> On Sat, Dec 12, 2009 at 4:54 PM, Gabe Black wrote:
>
There are a few minor things I notice. First, you should have spaces
around your operators, ie. "a Hi Soumyaroop,
>
> Thanks for the patches. They look good to me, if no one else has any
> comments I'll commit them. Is Soumyaroop Roy ok for
> the commit log?
>
> Thanks,
> Ali
>
> On Dec 10, 20
change is relatively minor, so you can go ahead and commit this and
I'll fix it up in my change, or you can wait and I can describe what
you'd need to do.
Gabe
Vince Weaver wrote:
> On Fri, 6 Nov 2009, Gabe Black wrote:
>
>
>> You seem to be missing the majority of the P
Vince Weaver wrote:
> On Sun, 13 Dec 2009, Gabe Black wrote:
>
>
>> Looking through my email, I found this patch which I don't think ever
>> got committed. Do you know of any others like this, Vince? I found this
>> one specifically because I'm getting read
In the mean time, is there any way to get a binary that will work right
now so I can fix the floating point problem?
Gabe
Korey Sewell wrote:
>
> I think the unsupported instruction is the rdhwr instruction.
>
> Aaah, i see more than likely that instructions is impl. specific
> so GDB m
That could be but it wasn't the intention. Did you try cloning them over
http?
Gabe
soumyaroop roy wrote:
> Hey Gabe, do only certain people have access to the arm patches?
>
> -S
>
> On Sun, Dec 13, 2009 at 3:01 AM, Gabe Black wrote:
>
>>Hi everybody.
of integer register Ra already
>>> takes care of that. I verified that the generated decoder.cc.
>>> c. removed 'temp' variable from 'ctpop'
>>>
>>> Also verified that the changes did not break anything!
>>>
>>> I am happy
t;
>> Quoting soumyaroop roy :
>>
>>
>>> I tried pulling them using 'hg pull ssh://h...@m5sim.org/arm-patches'.
>>> Where should I clone them from?
>>>
>>> -Soumyaroop
>>>
>>> On Tue, Dec 15, 2009 at 2:
changeset 335f8b406bb9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=335f8b406bb9
description:
X86: Create a common flag with a name to indicate high multiplies.
diffstat:
5 files changed, 30 insertions(+), 23 deletions(-)
src/arch/x86/insts/micromediaop.hh
changeset 353726c415f4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=353726c415f4
description:
X86: Add a common named flag for signed media operations.
diffstat:
15 files changed, 158 insertions(+), 147 deletions(-)
src/arch/x86/insts/micromediaop.hh
changeset e649cb8af113 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e649cb8af113
description:
X86: Record the memory mode when building an X86 system.
diffstat:
1 file changed, 2 insertions(+)
configs/common/FSConfig.py |2 ++
diffs (12 lines):
diff -r 353726c41
changeset c647872c6590 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c647872c6590
description:
X86: Add a latency that describes how long an interrupt takes to
propagate through the IO APIC.
diffstat:
2 files changed, 4 insertions(+), 1 deletion(-)
src/dev/x86/I82094
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