Re: [PEDA] Project woes
Dwight Harm wrote: > I'd tend to agree with Ian. Me too! But what comes to my mind is an alternative method (though I actually never did it myself): What's about a mixed rigid/flex PCB? That could keep the single project while offering a "dual slot" mounting. Don't know if the costs for rigid/flex increase over the additional connector/cable/test/assembly costs in your project. Regards, Emanuel -- MPL AG www.mpl.ch Emanuel Zimmermann [EMAIL PROTECTED] Manager R&D Phone: +41 (0)56 483 34 34 Taefernstrasse 20 Fax: +41 (0)56 493 30 20 CH-5405 Daettwil * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Project woes
I'd tend to agree with Ian. If it's a one-shot thing maybe not ... but if it's going to stay around, maintenance will be a lot more understandable if it's split. Sometimes an easy way to split something like this is to copy the whole project, then delete the unneeded parts from each copy to get the two "halves". -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: Thursday, December 20, 2001 8:41 PM At 02:36 PM 21/12/01 +1100, you wrote: >I have a 5 sheet project that I was planning to put on one PCB. > >What I was planning to do was draw the two pcbs in one file connected >together and have a perforation or groove for splitting the two pcbs. > I am firmly in the "one sch <=> one PCB" camp myself. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Project woes
At 02:36 PM 21/12/01 +1100, you wrote: >I have a 5 sheet project that I was planning to put on one PCB. >However It has become clear that there is no way all the parts are going to >fit in the space available. > >To solve this I will have to stack 2 PCBs (there are mounting slots provided >for two PCBs in the enclosure). > >The problem is that the most efficient way to do this requires all the >display parts on one PCB - the rest on the other. Unfortunately this is not >the way the schematic sheets are arranged. So it will be impossible to get a >netlist for individual PCBs. > >What I was planning to do was draw the two pcbs in one file connected >together and have a perforation or groove for splitting the two pcbs. > >Placing correctly sized vias on a 2.54mm pitch for PCB interconnections on >both PCBs should allow me to use a ribbon cable from another one of our >standard products. > >I plan to annotate the schematics showing which parts are on the second PCB. > >All this should still be quicker than redrawing the project. > >Any one see any problems with this idea? Or a better way of proceeding? > >Thanks, > >Tom. I am firmly in the "one sch <=> one PCB" camp myself. So if it was me I would copy and paste the schematics until I had the division correct, then I would have to manage two sets of manufacturing docs and test docs etc etc but I would still do it. The additional overhead over what the combined assy would have taken is not great - there is the same number of components (or close to it) and the overall complexity is not much greater. But that is just the way I would do it - maybe a smart panelization and clever layout will work for you. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
At 06:26 PM 20/12/01 -0800, you wrote: >but is it true that to use the synchronizer the schematics have to have >all the right footprints plugged into the sch symbol? > >Dennis Saputelli No more so than with the netlist. If you run the Synch without all the sch symbols having footprints you will get a Warning tab on the Synch dialog stating the number of compoents without footprints and a button allowing you to generate a report showing those components missing footprints - very useful feature #1. Then Previewing the macros (rather than executing them) will allow you to see which macros have errors - very useful feature #2. Again, you can generate a report - VUF #3. You can check check box to only show/report errors - VUF#4. Even if you have errors, executing the macros will run as many as it can - VUF#5. What you will not end up with, though, is nodes (read pins) loaded into the PCB internal netlist that do not exist on the PCB when the Synch was done. But you can make your changes, and fix the libraries or manually add the components as you wish and then re-run the Sych at any time. What I love most is the fact that matching is not done by designator allowing manual or automatic re-annotation to your hearts content. Once Synch'ed you can then update the Sch with changes made in the PCB - such as flipping a component onto the bottom layer and changing the footprint to the wave version. Such footprint changes can then be reflected back up to the Sch through the synchronizer. VUF #6. And there is more - a few small gotchas the main one being not to not mix netlist imports with the synchronizer - recipe for disaster - but even this is recoverable. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Project woes
I have a 5 sheet project that I was planning to put on one PCB. However It has become clear that there is no way all the parts are going to fit in the space available. To solve this I will have to stack 2 PCBs (there are mounting slots provided for two PCBs in the enclosure). The problem is that the most efficient way to do this requires all the display parts on one PCB - the rest on the other. Unfortunately this is not the way the schematic sheets are arranged. So it will be impossible to get a netlist for individual PCBs. What I was planning to do was draw the two pcbs in one file connected together and have a perforation or groove for splitting the two pcbs. Placing correctly sized vias on a 2.54mm pitch for PCB interconnections on both PCBs should allow me to use a ribbon cable from another one of our standard products. I plan to annotate the schematics showing which parts are on the second PCB. All this should still be quicker than redrawing the project. Any one see any problems with this idea? Or a better way of proceeding? Thanks, Tom. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
Yes, and to me this seems like good design practice. It's not that hard either, protel allows you to associate up to 4 footprints with each schematic symbol when you create it, if you need more than that there are easy ways around it. For example I have a heap of 20mm disc MOVs (metal oxide varistors) all with different footprint widths related to different working voltages, but only one MOV schematic symbol. The default footprint is something like 20MOV___ where the ___ has to be filled in by me with values like 275 or 680 (for 275V/680V working voltage MOVS). Morphing components (using the [Insert] key) means that I (usually) only have to do this a couple of times. The other three footprints associated with this schematic symbol are TAG__ 14MOV___ and 07MOV___ for different MOV diameters and, TAG is for a square version. So one schematic symbol can be quite easily linked to a large number of footprints. -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] Sent: Friday, 21 December 2001 1:27 PM To: Protel EDA Forum Subject: Re: [PEDA] multi sheet problems but is it true that to use the synchronizer the schematics have to have all the right footprints plugged into the sch symbol? Dennis Saputelli Abd ul-Rahman Lomax wrote: > > At 04:26 PM 12/20/01 -0800, Dennis Saputelli wrote: > >i'll probably take flak for this but i don't use the synchronizer, > >fearing that it would make more work > >we just use the good old netlist load, myabe i don't know what i'm > >missing > > You don't know what you are missing, Dennis. > > The Synchronizer is faster to use, you can make it almost one-button if you > like (but there are still some dialogs). It uses the same macro creation > process, apparently, as does the Netlist Load process. In addition, it > correctly handles multiple pads with the same name in the same footprint. I > only generate a net list when I need to visually inspect it because of some > problem or other, which is rare. > > And I am an old-time net lister. Dennis might remember some jobs I did for > him and one which he did for me, something like fifteen years ago, complex > multilayer boards done with tape and mylar. I used to create a net list > from each of the layers (numbering the vias) and pull all the layer lists > together with a Commodore computer. Another list was made from the > schematic and the lists were compared. Errors did not survive that process. > Sometimes on the cheap I would just mark off the net list against the > schematic, which was almost as good. > > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA > -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel to Orcad DSN ?
here i go again (desperate) anyone know of a third party translator for Protel Schem to Orcad Capture DSN files? Protel suggested rsi-inc rsi-inc said they don't do schematics, they gave a few links which i have checked out below in short nobody in the business seems to do anything with protel schematic SEARCH RESULTS, see comments below links http://www.edaexchange.com/ocad-sch.htm notice there is nothing for protel schematic http://www.e-tools.com search for protel was null * they have EDIF stuff, will this actually work? *** http://www.dataxpress.com/prods_svs.html many schem to/from translators! no protel anything http://www.intercept.com/ several orcad translators no reference to protel anything Protel took the position that importing is always the other guys' problem They read DSN, so Orcad should read Protel sch Dennis Saputelli -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
To all, I will second that rule to do the preview. I was in a situation where IF had I done it I would have realized what it did to me before I just went on fat dump an happy making changes to an existing design. The 99SE synchronizer works very well. I have completed many designs now (being a newcommer) with no problems other than like above self induced. I do however agree with the person talking about how Protel updates board and schematic from library, it is a little less than I had hoped for in my setup. I really wish the footprints would REALLY update all symbols from the library. It does but it will not use those new footprints on a board you need to go into th eschematic for each unique part and force it to that new footprint. ie if you get properties of the symbol you see a pulldowm menu for footprint which now does contain the new part too BUT until you select the new footprint you will still see the old footprint on the board. Bob Robert M. Wolfe, C.I.D. [EMAIL PROTECTED] - Original Message - From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Thursday, December 20, 2001 9:03 PM Subject: Re: [PEDA] multi sheet problems > At 08:09 PM 12/20/01 -0500, Brian Guralnick wrote: > >It may look > >potentially bug prone, but I've learned to always do a "Preview Changes", > >then "Apply > >changes" instead of just "Execute" to help with the feeling that > >everything will get > >messed up. After 2 to 3 times with a simple PCB, you will never want to > >go back to > >the old ways. > > Mr. Guralnick's process is recommended, particularly when only a few > changes are being made. It only takes a moment to look over a few macros > and confirm that everything looks okay. > > >However, I have learned not to use the update with old PCB98 documents > >unless I have > >completely made sure that all of the old libs conform within my latest P99 > >setup. > > As far as I know, there is no problem with older designs if you don't allow > footprint updates. You might consider running update once without allowing > footprint changes, then run it again allowing it and see if any macros are > created > > Again, as far as I have seen, no changes are made unless a macro is created > and accepted. Another reason to get in the habit of previewing changes. > It's too easy to change a footprint and not notice it until a few hours > later when all the backups have been overwritten. > > > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
but is it true that to use the synchronizer the schematics have to have all the right footprints plugged into the sch symbol? Dennis Saputelli Abd ul-Rahman Lomax wrote: > > At 04:26 PM 12/20/01 -0800, Dennis Saputelli wrote: > >i'll probably take flak for this but i don't use the synchronizer, > >fearing that it would make more work > >we just use the good old netlist load, myabe i don't know what i'm > >missing > > You don't know what you are missing, Dennis. > > The Synchronizer is faster to use, you can make it almost one-button if you > like (but there are still some dialogs). It uses the same macro creation > process, apparently, as does the Netlist Load process. In addition, it > correctly handles multiple pads with the same name in the same footprint. I > only generate a net list when I need to visually inspect it because of some > problem or other, which is rare. > > And I am an old-time net lister. Dennis might remember some jobs I did for > him and one which he did for me, something like fifteen years ago, complex > multilayer boards done with tape and mylar. I used to create a net list > from each of the layers (numbering the vias) and pull all the layer lists > together with a Commodore computer. Another list was made from the > schematic and the lists were compared. Errors did not survive that process. > Sometimes on the cheap I would just mark off the net list against the > schematic, which was almost as good. > > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA > -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] bug plotting rotated fill
At 11:24 AM 12/18/01 -0800, Brad Velander wrote: >Abd ul-Rahman, > have you noticed any of the rotated fills where the drawn gerber >generation leaves gaps in your otherwise solid fill? Like a database that I >am looking at right now which has approx. 0.5 mil gaps in the gerber draws >of a Protel fill. Not pretty! Drawing rotated fills was basically a mistake. Further, it is not easy. Protel draws tight fills, i.e., the draws exactly abut their neighbors. When you rotate a fill, however, the line endpoints typically become irrational numbers, so there is going to be roundoff error, plus there is the photoplot rounding. To compensate for this, it would be necessary to plot oversize by the appropriate amount, and to correct the fill outline accordingly. *Much* easer to define the macro and specify the rotation, clean and simple. At least I think it is, I haven't tried it. I will. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
At 08:09 PM 12/20/01 -0500, Brian Guralnick wrote: >It may look >potentially bug prone, but I've learned to always do a "Preview Changes", >then "Apply >changes" instead of just "Execute" to help with the feeling that >everything will get >messed up. After 2 to 3 times with a simple PCB, you will never want to >go back to >the old ways. Mr. Guralnick's process is recommended, particularly when only a few changes are being made. It only takes a moment to look over a few macros and confirm that everything looks okay. >However, I have learned not to use the update with old PCB98 documents >unless I have >completely made sure that all of the old libs conform within my latest P99 >setup. As far as I know, there is no problem with older designs if you don't allow footprint updates. You might consider running update once without allowing footprint changes, then run it again allowing it and see if any macros are created Again, as far as I have seen, no changes are made unless a macro is created and accepted. Another reason to get in the habit of previewing changes. It's too easy to change a footprint and not notice it until a few hours later when all the backups have been overwritten. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
At 04:26 PM 12/20/01 -0800, Dennis Saputelli wrote: >i'll probably take flak for this but i don't use the synchronizer, >fearing that it would make more work >we just use the good old netlist load, myabe i don't know what i'm >missing You don't know what you are missing, Dennis. The Synchronizer is faster to use, you can make it almost one-button if you like (but there are still some dialogs). It uses the same macro creation process, apparently, as does the Netlist Load process. In addition, it correctly handles multiple pads with the same name in the same footprint. I only generate a net list when I need to visually inspect it because of some problem or other, which is rare. And I am an old-time net lister. Dennis might remember some jobs I did for him and one which he did for me, something like fifteen years ago, complex multilayer boards done with tape and mylar. I used to create a net list from each of the layers (numbering the vias) and pull all the layer lists together with a Commodore computer. Another list was made from the schematic and the lists were compared. Errors did not survive that process. Sometimes on the cheap I would just mark off the net list against the schematic, which was almost as good. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Dual Footprints
At 05:24 PM 12/20/01 -0500, Abd ul-Rahman Lomax wrote: >Last time I looked, Protel does not generate a DRC error for pads where >the pads have the same name. If one of the pads has no name, it will >create a DRC error. This was a bit garbled. If two pads have the same net assignment, they will not generate a DRC error no matter what they are named. My point was that the synchronizer (the Schematic Update PCB command) will properly assign pads belonging to the same footprint the same net if they have the same name. If the names are different, they will not be assigned the same net unless both pads occur in the net list and are in the same net. You can, of course, manually change net assignments. This is not recommended except in emergencies. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
I went through that particular stage about a year and a half ago. It may look potentially bug prone, but I've learned to always do a "Preview Changes", then "Apply changes" instead of just "Execute" to help with the feeling that everything will get messed up. After 2 to 3 times with a simple PCB, you will never want to go back to the old ways. However, I have learned not to use the update with old PCB98 documents unless I have completely made sure that all of the old libs conform within my latest P99 setup. Brian Guralnick - Original Message - From: "Dennis Saputelli" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Thursday, December 20, 2001 7:26 PM Subject: Re: [PEDA] multi sheet problems | i'll probably take flak for this but i don't use the synchronizer, | fearing that it would make more work | we just use the good old netlist load, myabe i don't know what i'm | missing | | Dennis Saputelli | | | Steve Pfeifenroth wrote: | > | > Yeah I do the same thing. I have troubles getting lib devices to "update" | > the schematics or pcb after editing. | > | > Steve | > | > -Original Message- | > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]On | > Behalf Of Jon Elson | > Sent: Thursday, December 20, 2001 3:45 PM | > To: Protel EDA Forum | > Subject: Re: [PEDA] multi sheet problems | > | > Steve Pfeifenroth wrote: | > | > > I don't know what happened. I am chalking it up as a software glich. I | > > started a new project and imported my two schematics and it works fine. | > | > Yes, I have a 3-sheet project I'm doing right now. Every once in a while, | > like once a day, the schematic and the PCB get wildly out of sync, and | > the resynchronize reports all sorts of things it can't match. I close all | > files and restart Protel, and then the netlist and all synchronize functions | > work fine. | > | | -- | ___ | www.integratedcontrolsinc.comIntegrated Controls, Inc. |tel: 415-647-04802851 21st Street | fax: 415-647-3003San Francisco, CA 94110 | | * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
i'll probably take flak for this but i don't use the synchronizer, fearing that it would make more work we just use the good old netlist load, myabe i don't know what i'm missing Dennis Saputelli Steve Pfeifenroth wrote: > > Yeah I do the same thing. I have troubles getting lib devices to "update" > the schematics or pcb after editing. > > Steve > > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]On > Behalf Of Jon Elson > Sent: Thursday, December 20, 2001 3:45 PM > To: Protel EDA Forum > Subject: Re: [PEDA] multi sheet problems > > Steve Pfeifenroth wrote: > > > I don't know what happened. I am chalking it up as a software glich. I > > started a new project and imported my two schematics and it works fine. > > Yes, I have a 3-sheet project I'm doing right now. Every once in a while, > like once a day, the schematic and the PCB get wildly out of sync, and > the resynchronize reports all sorts of things it can't match. I close all > files and restart Protel, and then the netlist and all synchronize functions > work fine. > -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
>like once a day, the schematic and the PCB get wildly out of sync, and >the resynchronize reports all sorts of things it can't match. >I close all files and restart Protel, and then the netlist and all >synchronize functions work fine. Yeah I know what you mean. I'm cruising down the road at 60mph in my new MS Turbo 1.2G. I paid a lot for it but it's a real beauty. However, every 20-50 miles (varies) the motor just quits running. I have to pull off the road, turn off the ignition, wait 45 seconds, then it fires right up and I'm on my way again. The dealer says this is perfectly normal and I should be happy like everyone else and stop complaining. He did say I could trade up to the new XP model (for only 1.5x what I paid for this one), but he couldn't guarantee that it wouldn't do the same thing. I guess I'll keep driving it regardless, since it beats walking to work every day. When it's time to buy a new car I'll probably just go out and get another MS since that's what everybody else drives, plus I doubt if I could learn to drive anything else--all the controls are in different places! >-Original Message- >From: Jon Elson [mailto:[EMAIL PROTECTED]] >Sent: Thursday, December 20, 2001 18:45 >To: Protel EDA Forum >Subject: Re: [PEDA] multi sheet problems > > >Steve Pfeifenroth wrote: > >> I don't know what happened. I am chalking it up as a >software glich. I >> started a new project and imported my two schematics and it >works fine. > >Yes, I have a 3-sheet project I'm doing right now. Every once >in a while, >like once a day, the schematic and the PCB get wildly out of sync, and >the resynchronize reports all sorts of things it can't match. >I close all >files and restart Protel, and then the netlist and all >synchronize functions >work fine. > >Jon > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
Yeah I do the same thing. I have troubles getting lib devices to "update" the schematics or pcb after editing. Steve -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]On Behalf Of Jon Elson Sent: Thursday, December 20, 2001 3:45 PM To: Protel EDA Forum Subject: Re: [PEDA] multi sheet problems Steve Pfeifenroth wrote: > I don't know what happened. I am chalking it up as a software glich. I > started a new project and imported my two schematics and it works fine. Yes, I have a 3-sheet project I'm doing right now. Every once in a while, like once a day, the schematic and the PCB get wildly out of sync, and the resynchronize reports all sorts of things it can't match. I close all files and restart Protel, and then the netlist and all synchronize functions work fine. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
Steve Pfeifenroth wrote: > I don't know what happened. I am chalking it up as a software glich. I > started a new project and imported my two schematics and it works fine. Yes, I have a 3-sheet project I'm doing right now. Every once in a while, like once a day, the schematic and the PCB get wildly out of sync, and the resynchronize reports all sorts of things it can't match. I close all files and restart Protel, and then the netlist and all synchronize functions work fine. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] special board requirements ??
At 09:03 AM 12/20/01 -0500, Robison Michael R CNIN wrote: >i need a 330mil thick board with 70mil taken off of mirrored sections on >both sides. i'm thinking a 100mil radius tolerance on the inside of the >milled corners, and probably +/- 5 or 10 mil on the milled edges. the >size of the board is 12"x7". That's not a printed circuit board, that is a brick. Because you are far outside standard board production, it may be much more cost-effective to make two boards and sandwich them around some board or other material in the middle. Vias can be skewers (I've seen this done for space-flight boards). If you really want to plate holes through 330 mil of board thickness, know that the rule of thumb is that hole plating starts to get dicey at about one-third the board thickness. i.e., over 100 mils in your case, though the rule of thumb might not apply with such large holes. The sandwich approach, if the outer boards are standard 062 material, will give you close to the 70 mil section removal. This, too, should save on processing. To do the whole thing in PCB material, the inner boards could be, say .125 board material or other standard size or sizes to make up what you need; to save money, I'd have the inner boards have no copper at all, they would just be routed board blanks, drilled where necessary for skewers, and I would glue the stack together. If the inner boards have copper pads, however, skewer wires, when soldered, could hold the stack together. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Dual Footprints
Thanks for the tips. My SO14-SO16W has short track segments between the equivalent pads -- maybe this causes the DRC problems. I was unaware of the function of Design/Netlist Manager/Menu/Update Free Primitives, so I'll look into it. Damon Kelly R&D Engineer Blastronics Systems and Services Infratech Systems & Services ...business units of: Texcel Pty Ltd PO Box 3699 South Brisbane, QLD 4101 AUSTRALIA 24 Bank St West End, QLD 4101 AUSTRALIA Ph +61 7 3237 8109 Fax +61 7 3237 8188 > -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: Friday, 21 December 2001 08:25 > To: Protel EDA Forum > Subject: Re: [PEDA] Dual Footprints > > > At 08:48 AM 12/20/01 +1000, Damon Kelly wrote: > > > If you want one footprint that can except two different > > > devices you can > > > do that with a special footprint (named ssop14-ssop16??). > > > >This option causes DRC errors - or at least it does in my > implementation. I > >sometimes require an SO-14/SO-16W footprint, to allow > alternative op-amps, > >and I always seem to get DRC errors of the type "extra pads > on net" etc...I > >can live with them, but it's irritating. > >Is there anyway to prevent the DRC from tripping over the extra pads? > > Last time I looked, Protel does not generate a DRC error for > pads where the > pads have the same name. If one of the pads has no name, it > will create a > DRC error. However, in either case, track connecting the > pads, if it is > part of the footprint, will create short errors until the > track is assigned > the appropriate net, either as part of the synchronization > process or using > Design/Netlist Manager/Menu/Update Free Primitives -- which also > updates component non-pad primitives. Technically, this is a > minor bug, but > we use it. > > To summarize, there are three ways to handle double-padding: > > (1) Place two symbols on the schematic with a note that only > one of them is > to be inserted. If the two symbols are placed on top of each > other, the > note may not be necessary. Name one of them, for example, > U14A, the other > U14B. Each one of these may then have its own footprint. > There will be two > separate components on the PCB, they can be placed in any > arrangement that > works. > > When one symbol is placed atop another, one may wish to hide > some of the > various text displays > > (2) Use a single symbol on the schematic but place a > double-pad pattern on > the PCB. This footprint has two pads for each original > schematic pin. Each > of these pads will have the same name. If the Synchronizer is used to > transfer net information, the pads will be properly assigned > nets; if track > or other primitives are added, Update will be required. If > Load Netlist is > used, there is still a bug which can cause assignment oscillation. > > (3) Create a schematic symbol with double pins. I won't go > into detail on this. > > Protel does not support multiple components with the same reference > designator. It will cheerfully allow you to create them, but > it does not > properly handle net assignments. I can see arguments for > leaving it this > way, but it could also be argued that allowing multiple > components with the > same refdes (and which would be assigned identical nets) > would be useful > for double-padding. On the other hand, a single footprint for > double-padding is schematic-controlled and thus will survive > synchronization with unused component removal, etc., and I think it's > better to leave it as-is. > > Protel does not seem to support free primitives in Unions. If > it did, this > would provide another solution to this problem (though Update > would still > be required); one could simply add pads and create a union with the > original footprint. Free primitives in Unions would be useful > for other > reasons. My guess is that they did not do it because it would > have added > another field to all the primitives, whereas component Unions > only involved > the component primitive, not all its parts. Maybe next release. > > > > > [EMAIL PROTECTED] > Abdulrahman Lomax > Easthampton, Massachusetts USA > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Altium preps topological autorouter
On 01:51 PM 20/12/2001 -0500, Bagotronix Tech Support said: >Oh, well. Bad ideas never die. They just get recycled :-(Or reborn. >Hey, maybe that's why they call it "Phoenix"! > >IMO, most all-in-one files suck. Does the Windows registry come to mind? I agree with this statement, mostly. >Corruption of a single file can ruin the whole system and it's applications. >The all-in-one file concept has been refuted long ago. Look at the >Unix/Linux system: lots of little configuration files. It's hard to >remember where they are, but at least you don't have to search through >unrelated stuff inside the file, and corruption of that one file won't ruin >the entire system. I disagree with this one - the Unix/Linux arrangement of many interacting config files in multiple places is not an example I would like to see propagated - think why *nix is only used by computer geeks. Not a model that can claim wide success. It will take a radical improvement in installing and maintaining the OS, and managing and installing applications before *nix enjoys wide success with the wider non-geek public. I will happily follw this part of this thread onto the OT list for ongoing (reasoned) discussion - and my re-education :-) I much prefer the INI file concept - but not stored in the Windows directory. It has always been pleasing to me that Protel largely eschewed the registry in favour of its various INI/RCS files. Now we just need them to allow us to control where the config files reside. This is where the registry may have some use. A central data store of pointers to the locations of program's config file locations. (In the registry's favour - it is much faster than ini file access, but it is good to know that many companies (including MS) are moving away from indiscriminate use of the Registry as the be-all-and-end-all.) I do accept that the *nix style config files can be smarter the simple INI files and there are sometimes advantages to this. I just hate the scatter gun approach to configuration that has developed and seems not to have been questioned during *nix's growth. >However, I do like Protel's DDB file, for the most part. The only thing I >can't stand about it is that if you merely open it to look at what's inside, >it updates the file date and time. Ridiculous! One assumes that with the "Support for full version control with interfaces to popular third-party version control tools such as Visual Source Safe" there is some method of storing files that does not twiddle the dates on view-only. There is a press release on the Protel WWW site as well as the EE Times article, the press release gives some different emphasis. On integrated libraries - I have no problem with the concept of integrated libraries - it really comes down to implementation, and whether it will *force* a pattern of use rather than allow a new pattern. One assumes it will be able to support old designs, so maybe there is a method of using separate libraries much as we do now. Better library management and traceability has been something that many of us have been screaming for for a long time. The current system does not lend itself to any sort of reliable configuration control. Can you say for sure which library a symbol/footprint came from? I, for one, am not fussed by the integrated libraries per se but, as usual, the devil is no doubt in the detail. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
At 01:40 AM 12/20/01 -0800, Steve Pfeifenroth wrote: >I have created a project file with two sheet symbols on it referencing two >.sch files (both are open and active). I am using simple "flat design" for >linking two .sch together sharing only net labels and power ports. I get conflicting information from this. Either net labels are shared or they are not. Power ports are always shared (global). One cannot share "only" net labels and power ports. If net labels are shared, so will be ports (which means regular ports. Forget the term "power ports," it is misleading. Think of them as global power objects.) It seems that you want "net labels and ports global." > When I >select the .prj file and try an ERC there are no warnings. Which is almost meaningless if no connectivity is being established, assuming that the .prj file has no wiring on it. > When I select the >.prj and try to create a Netlist the net list file is completely empty. I am >selecting the scope of the net identifiers to "global nets/ports". What am I >doing wrong. I have no problem doing it on each individual file. How do I >link all the files so that I create 1 netlist and 1 ERC? The files display >correctly in the file viewer so I know at least Protel understands my setup >it just isn't producing any output. Well, I wouldn't assume that it "understands" beans. If you use the descend hierarchy tool, does it properly send you to the subsheet? Here is how it should work: If you have a project sheet which correctly references subsheets -- in P99SE I assume that they are in the same .ddb and for simplicity they are in the same folder -- and net scope is set to Net Labels and Ports Global, any net label on the project sheet or any subsheet should be netlisted as such. Do not "Descend into Sheet Parts" unless you know what you are doing. Likewise, unless you are a certified Protel Guru, the Sheet Path field should be empty for all components. Sheet Path is a device for representing a subassembly as if it were an ordinary component. Let us not go there today. If ERC were detecting the subsheets and it were not detecting the net connections, it would almost certainly create a pile of ERC Warnings at the least, assuming that the error matrix has not been poked in the eye. In fact, you should add more warnings; I generate a warning for any unconnected pin regardless of type and then suppress the warnings that are safe to ignore with No-ERC Directives. So I can assume, for starters, that ERC is not detecting your subsheets, and if ERC is not detecting them, neither will the netlister. By the way, the synchronizer is a step up from the Netlist process. But first things first. Naturally, this happens when you have to get the job out the door in fifteen minutes. I would take one of the sample hierarchical schematics supplied with Protel and see if it works. If it doesn't, you may have a garbaged installation and reinstallation would be in order. ERC will detect duplicate page numbers. Schematic page numbers are under Documentation Options. If two of your sheets are given the same number and ERC does not pick them up, definitely the sheets are not being detected. Try the Tools/Up-Down Hierarchy command from your .prj sheet and see if you can pop to a subsheet using it. If not, check the sheet symbol parameters. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Dual Footprints
At 08:48 AM 12/20/01 +1000, Damon Kelly wrote: > > If you want one footprint that can except two different > > devices you can > > do that with a special footprint (named ssop14-ssop16??). > >This option causes DRC errors - or at least it does in my implementation. I >sometimes require an SO-14/SO-16W footprint, to allow alternative op-amps, >and I always seem to get DRC errors of the type "extra pads on net" etc...I >can live with them, but it's irritating. >Is there anyway to prevent the DRC from tripping over the extra pads? Last time I looked, Protel does not generate a DRC error for pads where the pads have the same name. If one of the pads has no name, it will create a DRC error. However, in either case, track connecting the pads, if it is part of the footprint, will create short errors until the track is assigned the appropriate net, either as part of the synchronization process or using Design/Netlist Manager/Menu/Update Free Primitives -- which also updates component non-pad primitives. Technically, this is a minor bug, but we use it. To summarize, there are three ways to handle double-padding: (1) Place two symbols on the schematic with a note that only one of them is to be inserted. If the two symbols are placed on top of each other, the note may not be necessary. Name one of them, for example, U14A, the other U14B. Each one of these may then have its own footprint. There will be two separate components on the PCB, they can be placed in any arrangement that works. When one symbol is placed atop another, one may wish to hide some of the various text displays (2) Use a single symbol on the schematic but place a double-pad pattern on the PCB. This footprint has two pads for each original schematic pin. Each of these pads will have the same name. If the Synchronizer is used to transfer net information, the pads will be properly assigned nets; if track or other primitives are added, Update will be required. If Load Netlist is used, there is still a bug which can cause assignment oscillation. (3) Create a schematic symbol with double pins. I won't go into detail on this. Protel does not support multiple components with the same reference designator. It will cheerfully allow you to create them, but it does not properly handle net assignments. I can see arguments for leaving it this way, but it could also be argued that allowing multiple components with the same refdes (and which would be assigned identical nets) would be useful for double-padding. On the other hand, a single footprint for double-padding is schematic-controlled and thus will survive synchronization with unused component removal, etc., and I think it's better to leave it as-is. Protel does not seem to support free primitives in Unions. If it did, this would provide another solution to this problem (though Update would still be required); one could simply add pads and create a union with the original footprint. Free primitives in Unions would be useful for other reasons. My guess is that they did not do it because it would have added another field to all the primitives, whereas component Unions only involved the component primitive, not all its parts. Maybe next release. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Importing Tango V2.xx Files
Protel used to provide v. 2.8 PCB to users who requested it, so that they could import Tango. I don't know if they still do this, but plenty of us have 2.8 and could help users who need assistance with this. (I jumped into the Protel pond with P98 but since I was a heavy Tango user I asked for and was given 2.8.) [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Altium preps topological autorouter
Sean, I hope you charge this guy by the hour!! -Original Message- From: Sean James [mailto:[EMAIL PROTECTED]] Sent: Thursday, December 20, 2001 1:27 PM To: Protel EDA Forum Subject: Re: [PEDA] Altium preps topological autorouter To quote Mike Reagan - "What could be simpler and faster than create a part, import a netlist that associates the part, the netlist assigns the Ref designator? I don't get it. I'm just a simpleton." I cna't convince a engineer to do his boards & schematics this way, so it takes forever to create/clean up his schematics, etc. It's a waste of time 7 money not to use the software properly. Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
Steve Pfeifenroth wrote: > I bypassed the web site posting because it just hangs on me (Never goes > through). Hope this is ok and I am not getting into trouble. I just have an > urgent question because my boards need to be at the board house tomorrow > otherwise I won't get them until Jan 3. > > [EMAIL PROTECTED] > > I have created a project file with two sheet symbols on it referencing two > .sch files (both are open and active). I am using simple "flat design" for > linking two .sch together sharing only net labels and power ports. When I > select the .prj file and try an ERC there are no warnings. When I select the > .prj and try to create a Netlist the net list file is completely empty. I am > selecting the scope of the net identifiers to "global nets/ports". What am I > doing wrong. I have no problem doing it on each individual file. How do I > link all the files so that I create 1 netlist and 1 ERC? The files display > correctly in the file viewer so I know at least Protel understands my setup > it just isn't producing any output. There are two ways to do this. One is to 'import' all the sheets so they are part of the whole. I'm getting vague on how to do this in 99SE. What I do, even for a flat schematic, is to have a master sheet. With that in 'focus', click on design, create symbol from sheet, and specify the name of each sheet. When you are done, in the explorer part of the screen, you should see all the sub sheets should appear as "sub" to the master sheet, and you'll have a bunch of green blocks on your master sheet, which link to the sub-sheets. When you do an ERC or netlist, select descend into sheet parts, and you should get one error check or netlist that includes all the subsheets. You can still have nets global with this. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] multi sheet problems
I don't know what happened. I am chalking it up as a software glich. I started a new project and imported my two schematics and it works fine. Thanks Steve -Original Message- From: Cliff Gerhard [mailto:[EMAIL PROTECTED]] Sent: Thursday, December 20, 2001 11:12 AM To: Protel EDA Forum Subject: Re: [PEDA] multi sheet problems The setup you described sounds ok. Sorry if these suggestions seem obvious, but I do not know your level of experience with Protel. Do you have the "Sheets to Netlist" scope set to "Active Project" (not Active Sheet or Active Sheets and Subsheets)? Do the sheets show up underneath the Project file in the Explorer Window? If not, Protel has not associated the SCH files to the PRJ file. That's about all can think of. Hope it was of some help. Cliff ~~ Cliff Gerhard, P.E. Director - EE Group E-M Designs, Inc. 32122 Camino Capistrano Suite 200 San Juan Capistrano, CA 92675 PH 949.661.3016 x 501 FX 949.661.3017 www.GerhardEng.com www.emdesigns.com www.emmanufacturing.com -Original Message- From: Steve Pfeifenroth [mailto:[EMAIL PROTECTED]] Sent: Thursday, December 20, 2001 1:41 AM To: Protel EDA Forum Subject: [PEDA] multi sheet problems I bypassed the web site posting because it just hangs on me (Never goes through). Hope this is ok and I am not getting into trouble. I just have an urgent question because my boards need to be at the board house tomorrow otherwise I won't get them until Jan 3. [EMAIL PROTECTED] I have created a project file with two sheet symbols on it referencing two .sch files (both are open and active). I am using simple "flat design" for linking two .sch together sharing only net labels and power ports. When I select the .prj file and try an ERC there are no warnings. When I select the .prj and try to create a Netlist the net list file is completely empty. I am selecting the scope of the net identifiers to "global nets/ports". What am I doing wrong. I have no problem doing it on each individual file. How do I link all the files so that I create 1 netlist and 1 ERC? The files display correctly in the file viewer so I know at least Protel understands my setup it just isn't producing any output. Thank you Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Altium preps topological autorouter
To quote Mike Reagan - "What could be simpler and faster than create a part, import a netlist that associates the part, the netlist assigns the Ref designator? I don't get it. I'm just a simpleton." I cna't convince a engineer to do his boards & schematics this way, so it takes forever to create/clean up his schematics, etc. It's a waste of time 7 money not to use the software properly. Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Laptop recommendations anyone?
Re: [PEDA] multi sheet problems
The setup you described sounds ok. Sorry if these suggestions seem obvious, but I do not know your level of experience with Protel. Do you have the "Sheets to Netlist" scope set to "Active Project" (not Active Sheet or Active Sheets and Subsheets)? Do the sheets show up underneath the Project file in the Explorer Window? If not, Protel has not associated the SCH files to the PRJ file. That's about all can think of. Hope it was of some help. Cliff ~~ Cliff Gerhard, P.E. Director - EE Group E-M Designs, Inc. 32122 Camino Capistrano Suite 200 San Juan Capistrano, CA 92675 PH 949.661.3016 x 501 FX 949.661.3017 www.GerhardEng.com www.emdesigns.com www.emmanufacturing.com -Original Message- From: Steve Pfeifenroth [mailto:[EMAIL PROTECTED]] Sent: Thursday, December 20, 2001 1:41 AM To: Protel EDA Forum Subject: [PEDA] multi sheet problems I bypassed the web site posting because it just hangs on me (Never goes through). Hope this is ok and I am not getting into trouble. I just have an urgent question because my boards need to be at the board house tomorrow otherwise I won't get them until Jan 3. [EMAIL PROTECTED] I have created a project file with two sheet symbols on it referencing two .sch files (both are open and active). I am using simple "flat design" for linking two .sch together sharing only net labels and power ports. When I select the .prj file and try an ERC there are no warnings. When I select the .prj and try to create a Netlist the net list file is completely empty. I am selecting the scope of the net identifiers to "global nets/ports". What am I doing wrong. I have no problem doing it on each individual file. How do I link all the files so that I create 1 netlist and 1 ERC? The files display correctly in the file viewer so I know at least Protel understands my setup it just isn't producing any output. Thank you Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Altium preps topological autorouter
Oh, well. Bad ideas never die. They just get recycled :-(Or reborn. Hey, maybe that's why they call it "Phoenix"! IMO, most all-in-one files suck. Does the Windows registry come to mind? Corruption of a single file can ruin the whole system and it's applications. The all-in-one file concept has been refuted long ago. Look at the Unix/Linux system: lots of little configuration files. It's hard to remember where they are, but at least you don't have to search through unrelated stuff inside the file, and corruption of that one file won't ruin the entire system. However, I do like Protel's DDB file, for the most part. The only thing I can't stand about it is that if you merely open it to look at what's inside, it updates the file date and time. Ridiculous! Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: "Bob Fearon" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Thursday, December 20, 2001 1:41 PM Subject: Re: [PEDA] Altium preps topological autorouter > Mike > You are right. But does this "Integrated" library sound like a "copy" of Pads? > You know the "all-in-one library", that can"t be used. > Of course the "Manager" concept comes from Accel, oh yeah. > Sounds like a staight marketing scheme. > > Bob Fearon > > > Mike Reagan wrote: > > > Great! They are also integrating the library probably like the integration > > nightmare in ACCEL.Right now I can create a part, store it, create and > > copy separate customer libraries, import netlist from other programs, with > > or without a part assignment. Somehow one of these features will be > > lost with the new "INTEGRATED" library.They are attempting to sell > > software to managers instead of designers. Someone got a bug somewhere > > along the line that integrated libs are best. Oh did I mention the > > simplicity of creating a part and not having to play and dick with all of > > the silly worthless menus afterwards. Like assigning it to CON, or IC like > > PADS. or stupid prefixes like R or C, U etc like Accel. It means more time > > to create a part. > > > > What could be simpler and faster than create a part, import a netlist that > > associates the part, the netlist assigns the Ref designator? I don't get > > it. I'm just a simpleton. > > The autorouter is welcomed! The lib manager is overhead.That right the > > name is lib MANAGER, that's all I need is to spend more time managing. > > > > Mike Reagan > > EDSI > > Frederick MD > > > > - Original Message - > > From: Jim Labrecque <[EMAIL PROTECTED]> > > To: Protel EDA Forum <[EMAIL PROTECTED]> > > Sent: Thursday, December 20, 2001 12:17 PM > > Subject: [PEDA] Altium preps topological autorouter > > > > > Press release in EE Times- > > > > > > http://www.eetimes.com/story/design/OEG20011210S0059 > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Altium preps topological autorouter
Mike You are right. But does this "Integrated" library sound like a "copy" of Pads? You know the "all-in-one library", that can"t be used. Of course the "Manager" concept comes from Accel, oh yeah. Sounds like a staight marketing scheme. Bob Fearon Mike Reagan wrote: > Great! They are also integrating the library probably like the integration > nightmare in ACCEL.Right now I can create a part, store it, create and > copy separate customer libraries, import netlist from other programs, with > or without a part assignment. Somehow one of these features will be > lost with the new "INTEGRATED" library.They are attempting to sell > software to managers instead of designers. Someone got a bug somewhere > along the line that integrated libs are best. Oh did I mention the > simplicity of creating a part and not having to play and dick with all of > the silly worthless menus afterwards. Like assigning it to CON, or IC like > PADS. or stupid prefixes like R or C, U etc like Accel. It means more time > to create a part. > > What could be simpler and faster than create a part, import a netlist that > associates the part, the netlist assigns the Ref designator? I don't get > it. I'm just a simpleton. > The autorouter is welcomed! The lib manager is overhead.That right the > name is lib MANAGER, that's all I need is to spend more time managing. > > Mike Reagan > EDSI > Frederick MD > > - Original Message - > From: Jim Labrecque <[EMAIL PROTECTED]> > To: Protel EDA Forum <[EMAIL PROTECTED]> > Sent: Thursday, December 20, 2001 12:17 PM > Subject: [PEDA] Altium preps topological autorouter > > > Press release in EE Times- > > > > http://www.eetimes.com/story/design/OEG20011210S0059 > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Altium preps topological autorouter
Great! They are also integrating the library probably like the integration nightmare in ACCEL.Right now I can create a part, store it, create and copy separate customer libraries, import netlist from other programs, with or without a part assignment. Somehow one of these features will be lost with the new "INTEGRATED" library.They are attempting to sell software to managers instead of designers. Someone got a bug somewhere along the line that integrated libs are best. Oh did I mention the simplicity of creating a part and not having to play and dick with all of the silly worthless menus afterwards. Like assigning it to CON, or IC like PADS. or stupid prefixes like R or C, U etc like Accel. It means more time to create a part. What could be simpler and faster than create a part, import a netlist that associates the part, the netlist assigns the Ref designator? I don't get it. I'm just a simpleton. The autorouter is welcomed! The lib manager is overhead.That right the name is lib MANAGER, that's all I need is to spend more time managing. Mike Reagan EDSI Frederick MD - Original Message - From: Jim Labrecque <[EMAIL PROTECTED]> To: Protel EDA Forum <[EMAIL PROTECTED]> Sent: Thursday, December 20, 2001 12:17 PM Subject: [PEDA] Altium preps topological autorouter > Press release in EE Times- > > http://www.eetimes.com/story/design/OEG20011210S0059 > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Altium preps topological autorouter
Press release in EE Times- http://www.eetimes.com/story/design/OEG20011210S0059 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Laptop recommendations anyone?
Steve: Windows XT, what's that? Yet another permutation of Windows ;-) All the new laptops use XP (ugh!). You might be able to wipe it from the hard drive and install Windows 2000 if you don't like XP. But Bill Gates will get your money for XP regardless - you can't buy a [mainstream] laptop without it. In spite of the DOJ rhetoric the Microsoft tax still stands. I have been looking at the Sony Vaio FXA36 or FX370. I still haven't bought one, but my research led me to it. One of my customers is a software consultant who has had several Sony laptops and he likes them. Of course, he gets his clients to buy them for him for a project. When the project is over, he hands over the laptop to them. And he tells the next customer to buy him a brand new Sony. So he always stays current! Just make the laptop you get has the "standard" ports - parallel, serial. Some don't. And I personally like all the drives (floppy, DVD/CDRW, etc.) built in - no external drives or docking stations need apply. If you want to use the laptop with a video camera, make sure the laptop has a Firewire port. The Sonys do. For video, stay away from cheaper models with unified video RAM. Never mind claims of battery life - they are all bogus. Any CAD job you do is likely going to take more time than a battery charge anyway. Laptop batteries are really only good as a UPS - to prevent you from losing your data during a power failure. When the technology has gotten to where a 12-hour work day can be done on one charge while running at full CPU speed and hard drive thrashing, I'll change my mind. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Thursday, December 20, 2001 11:16 AM Subject: [PEDA] Laptop recommendations anyone? > Hi, > > I'm thinking about buying a laptop for personal and professional use. I'll > be running a wide variety of applications, but my most resource intensive > application is Protel 99se so I want to make a choice that supports it well. > > Here are my questions: > 1. What OS is best? I think Win XT professional? (I'll refrain from > ranting.) > 2. How much memory? > 3. Which processor? > 4. What video hardware do I need to look for? > 5. Do any of you have specific brand/model recommendations? > > > Thanks for the help > > Steve > Kennewick, WA > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Laptop recommendations anyone?
Re: [PEDA] Intelligent SCH and PCB components
Sounds like way to much confusion to me. This might be great for a one
person operation, but trying to get a whole group of engineers to follow
that strict regiment would be almost impossible.
Do your production boards change that drastically from the proto? Our's
certainly don't.
-Original Message-
From: Aalt Lokhorst [mailto:[EMAIL PROTECTED]]
Sent: Thursday, December 20, 2001 3:39 AM
To: Protel EDA Forum
Subject: [PEDA] Intelligent SCH and PCB components
Hello All,
Dave wrote:
> I do have a need to make seperate dbs for particular groups of lib files.
> I will use one db for production board layout while another is set for
> breadboard layout (ie. 100mil center pads for vector boards). This is
> convienent since the same schematic can be used without any changes to do
> both types of layout just by swapping out the lib db files. This is
> actually be a tad easier in p99se whereas in p98 I had to selectively
prune
> my lib file pointer list.
What we need is the option of using formulas and expressions in the
attributes of components.
Somewhere in the schematic of pcb file we need to add some 'Special Defines'
like PROTO=True or MAINS=220.
In the component attributes we could use:
Example1:
If (PROTO = True) then
FOOTPRINT = "DIP16"
Else
FOOTPRINT = "SSOP16"
EndIf
Example2:
If (MAINS = '220')
FuseType = "1 Amp"
Else
FuseType = "2 Amp"
EndIf
There is another advantage of using formulas. In the past I have designed
some circular boards with a lot of leds. The leds were placed in circles on
the board. I was happy with the rotate function and the job was easy to do.
But every time when the mechanical engineers decided to make minor changes
in the ring diameters I needed to reposition the leds. The leds were
numbered with a two digit number. The first digit was the ring number and
the second digit was the sector number inside that ring. If there was the
option of using formulas in the attribute fields, it would be possible to
use some Sine and Cosine calculations to calculate the X, Y and rotation
based on the led number and one global 'DIAMETER' define.
It would also be possible to have a lot more flexibility in creating the
BOM. If each component could add lines to the BOM, based on some simple
programming in a component formula field, it would be possible to create the
BOM for different product builds. It would also be possible to add extra
parts which are needed for specific components
Example:
If (PRODUCTBUILD = 'industrial')
AddToBom(LargeHeatSink)
AddToBom("Heavy Mounting screws")
Else
AddToBom(SmallHeatSink)
AddToBom("low cost mounting clip")
End if
The examples are just to give you an idea of what I mean. I am thinking of a
kind of Client Basic local to a component to give it more intelligence. The
next step could be to add programming options to library components. Why
should we use a lot of different footprints for radial components with
different diameters if it could be one footprint with some extra parameters?
*<-<-x
PS, this is a christmas tree.
Greetings from,
Aalt Lokhorst (e-mail [EMAIL PROTECTED])
address:
Schut Geometrische Meettechniek bv
Duinkerkenstraat 21
9723 BN Groningen, The Netherlands
tel. +31 50-5877877
fax. +31 50-5877899
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[PEDA] special board requirements ??
hello, the board shop that i've been using has been doing an excellent job for me, but i've got a board now that they can't do. its extra fat and it needs some milling done on it. can anyone recommend a shop that will do it for me? i need a 330mil thick board with 70mil taken off of mirrored sections on both sides. i'm thinking a 100mil radius tolerance on the inside of the milled corners, and probably +/- 5 or 10 mil on the milled edges. the size of the board is 12"x7". and merry christmas and happy holidays to everybody! thank you, miker * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Antwort: 1206 4xresistor network footprint in downloaded libraries. Where?
Hi, I can only warn you to use "standard" footprints without thorough check. Many of them are just useless without modification and should only be taken as examples. E.g. almost all QFP footprints have much too wide pads, and all DSUB and RJ connectors look nice, but do most probably not match the dimensions of the parts you use, as almost every supplier does them with (slightly) different dimensions. Do your own footprints wherever possible, that's the only safe method, even if it causes some work you want to avoid. Regards, Gisbert Auge N.A.T. GmbH "Blandford, Simon \[BSS Audio UK\]"An: "'Protel EDA Mailing List'" <[EMAIL PROTECTED]> Thema: [PEDA] 1206 4xresistor network footprint in downloaded libraries. Where? 20.12.2001 10:25 Bitte antworten an "Protel EDA Forum" Hi, Does anyone know which library the footprint for a 1206 size 4x resistor network is in and what it is called. I have downloaded just about every Protel library I can find, done text searches in the library spreadsheet for keywords "network, "array" and "resistor" and still can't for the life of me find it. We want to avoid making custom footprints if we can and go with "standard" footprints as much as possible. Regards, Simon B. The comments expressed in this email are my own and not necessarily those of my employer. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 1206 4xresistor network footprint in downloaded libraries. Where?
I created what you need for 4x0603 (1206) a few weeks back using a manufacture's guide drawing for pad details. I am at home and it's late. If you drop me a message requesting same at [EMAIL PROTECTED] I will send off 1'st thing tomorrow morning (about 9 hours from time of this posting). Will also attach the schematic counterpart for it as it is easier to deal with this sort of multipart component as a device of 4 parts in schematic. 'Annotate' sorts out the details as you are probably already aware. Regards, Jim Parr - Original Message - From: Blandford, Simon [BSS Audio UK] <[EMAIL PROTECTED]> To: 'Protel EDA Mailing List' <[EMAIL PROTECTED]> Sent: Thursday, 20 December 2001 22:25 Subject: [PEDA] 1206 4xresistor network footprint in downloaded libraries. Where? > Hi, > > Does anyone know which library the footprint for a 1206 size 4x resistor > network is in and what it is called. I have downloaded just about every > Protel library I can find, done text searches in the library spreadsheet for > keywords "network, "array" and "resistor" and still can't for the life of me > find it. > > We want to avoid making custom footprints if we can and go with "standard" > footprints as much as possible. > > Regards, > Simon B. > > > The comments expressed in this email are my own and not necessarily those of > my employer. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Intelligent SCH and PCB components
Hello All,
Dave wrote:
> I do have a need to make seperate dbs for particular groups of lib files.
> I will use one db for production board layout while another is set for
> breadboard layout (ie. 100mil center pads for vector boards). This is
> convienent since the same schematic can be used without any changes to do
> both types of layout just by swapping out the lib db files. This is
> actually be a tad easier in p99se whereas in p98 I had to selectively
prune
> my lib file pointer list.
What we need is the option of using formulas and expressions in the
attributes of components.
Somewhere in the schematic of pcb file we need to add some 'Special Defines'
like PROTO=True or MAINS=220.
In the component attributes we could use:
Example1:
If (PROTO = True) then
FOOTPRINT = "DIP16"
Else
FOOTPRINT = "SSOP16"
EndIf
Example2:
If (MAINS = '220')
FuseType = "1 Amp"
Else
FuseType = "2 Amp"
EndIf
There is another advantage of using formulas. In the past I have designed
some circular boards with a lot of leds. The leds were placed in circles on
the board. I was happy with the rotate function and the job was easy to do.
But every time when the mechanical engineers decided to make minor changes
in the ring diameters I needed to reposition the leds. The leds were
numbered with a two digit number. The first digit was the ring number and
the second digit was the sector number inside that ring. If there was the
option of using formulas in the attribute fields, it would be possible to
use some Sine and Cosine calculations to calculate the X, Y and rotation
based on the led number and one global 'DIAMETER' define.
It would also be possible to have a lot more flexibility in creating the
BOM. If each component could add lines to the BOM, based on some simple
programming in a component formula field, it would be possible to create the
BOM for different product builds. It would also be possible to add extra
parts which are needed for specific components
Example:
If (PRODUCTBUILD = 'industrial')
AddToBom(LargeHeatSink)
AddToBom("Heavy Mounting screws")
Else
AddToBom(SmallHeatSink)
AddToBom("low cost mounting clip")
End if
The examples are just to give you an idea of what I mean. I am thinking of a
kind of Client Basic local to a component to give it more intelligence. The
next step could be to add programming options to library components. Why
should we use a lot of different footprints for radial components with
different diameters if it could be one footprint with some extra parameters?
*<-<-x
PS, this is a christmas tree.
Greetings from,
Aalt Lokhorst (e-mail [EMAIL PROTECTED])
address:
Schut Geometrische Meettechniek bv
Duinkerkenstraat 21
9723 BN Groningen, The Netherlands
tel. +31 50-5877877
fax. +31 50-5877899
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Re: [PEDA] 1206 4xresistor network footprint in downloaded librar ies. Where?
Hi, I think you are going to be disappointed. In simple terms there is no such thing as a 'standard' component footprint. Several factors define the footprint used for any single component. Potentially there are an infinite number of PCB footprints, I don't think anybody has hade time to make them yet. Its best to collect a library of footprints that you know are correct for your purposes. Build on that over time. Look at the manufacturers data for each component and see what they recommend for the PCB assembly process that you are using, verify that your footprint matches that data and that's its pins match the component symbol in the schematic, record the results of each check. Doing this methodically is much better than relying on someone else to get it right. There are 'rules of thumb' generated mainly by experience and experimentation, but they are only guides. For instance two 0.5mm pitch components with the same lead size may require different pad sizes depending on their thermal mass, this is usually only found through trial and error. Try the IPC website - can't remember the address, though a search engine should find it. They have a useful online calculator for land patterns. I expect someone on this group will offer you some footprints that may meet your needs, though check their work carefully against manufactures data. Jason. -Original Message- From: Blandford, Simon [BSS Audio UK] [mailto:[EMAIL PROTECTED]] Sent: 20 December 2001 09:26 To: 'Protel EDA Mailing List' Subject: [PEDA] 1206 4xresistor network footprint in downloaded libraries. Where? Hi, Does anyone know which library the footprint for a 1206 size 4x resistor network is in and what it is called. I have downloaded just about every Protel library I can find, done text searches in the library spreadsheet for keywords "network, "array" and "resistor" and still can't for the life of me find it. We want to avoid making custom footprints if we can and go with "standard" footprints as much as possible. Regards, Simon B. The comments expressed in this email are my own and not necessarily those of my employer. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 1206 4xresistor network footprint in downloaded libraries. Where?
My experience has lead me to do my own footprints for *everything* - no 'standard' libraries, no Wizard! It saves hassle in the long run and is relatively quick, certainly quicker than searching the standard libraries and checking footprints. Quite a few manufacturers put recommended footprints in data sheets (I think Philips/BC have one for the SMT resistor networks - which one are you using? I may have done a footprint for it already), although these often get modified based on feedback from our assembly people. Regards Andy Gulliver > -Original Message- > From: Blandford, Simon [BSS Audio UK] [mailto:[EMAIL PROTECTED]] > Sent: 20 December 2001 09:26 > To: 'Protel EDA Mailing List' > Subject: [PEDA] 1206 4xresistor network footprint in downloaded > libraries. Where? > > > Hi, > > Does anyone know which library the footprint for a 1206 size 4x resistor > network is in and what it is called. I have downloaded just about every > Protel library I can find, done text searches in the library > spreadsheet for > keywords "network, "array" and "resistor" and still can't for the > life of me > find it. > > We want to avoid making custom footprints if we can and go with "standard" > footprints as much as possible. > > Regards, > Simon B. > > > The comments expressed in this email are my own and not > necessarily those of > my employer. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] multi sheet problems
I bypassed the web site posting because it just hangs on me (Never goes through). Hope this is ok and I am not getting into trouble. I just have an urgent question because my boards need to be at the board house tomorrow otherwise I won't get them until Jan 3. [EMAIL PROTECTED] I have created a project file with two sheet symbols on it referencing two .sch files (both are open and active). I am using simple "flat design" for linking two .sch together sharing only net labels and power ports. When I select the .prj file and try an ERC there are no warnings. When I select the .prj and try to create a Netlist the net list file is completely empty. I am selecting the scope of the net identifiers to "global nets/ports". What am I doing wrong. I have no problem doing it on each individual file. How do I link all the files so that I create 1 netlist and 1 ERC? The files display correctly in the file viewer so I know at least Protel understands my setup it just isn't producing any output. Thank you Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] 1206 4xresistor network footprint in downloaded libraries. Where?
Hi, Does anyone know which library the footprint for a 1206 size 4x resistor network is in and what it is called. I have downloaded just about every Protel library I can find, done text searches in the library spreadsheet for keywords "network, "array" and "resistor" and still can't for the life of me find it. We want to avoid making custom footprints if we can and go with "standard" footprints as much as possible. Regards, Simon B. The comments expressed in this email are my own and not necessarily those of my employer. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Highlighting sections for BOM assistance
Like Jaurique, we draw a dashed line around the items on the schematic and notes etc. I also use the editable (from schematic) part fields. i have 10,11,12, for company specific data (from a database) and 13>16 for different build options. You can just highlight the parts you want different on say Build A, and globally edit part 13 (with selected objects only) to give details eg, miss out on build A. Do the same for the other build options and these can be included on the main BOM output. And it will group them nicely as well on the BOM. Works well for us. Rich > -Original Message- > From: Jaurique, Brad [SMTP:[EMAIL PROTECTED]] > Sent: 19 December 2001 19:16 > To: 'Protel EDA Forum' > Subject: Re: [PEDA] Highlighting sections for BOM assistance > > The usual thing to do is to create assemblies (or sub-assemblies) > for each stuffing option. Draw a dotted box around the parts with a note > that states the option. On the first page of the schematic create a box > with each of the assemblies and what to stuff (or not to stuff) for each > one. > If you highlight you will most likely have to print in color. There are > other ways but this seems to be easiest for me. > > Brad Jaurique > Pelco > Clovis, Ca > > -Original Message- > From: Afshin Salehi [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, December 19, 2001 11:02 AM > To: Protel Forum > Subject: [PEDA] Highlighting sections for BOM assistance > > > Hello all, > I was wondering if its possible to highlight sections of a schematic > for a > specific build of a product that's configurable. Our application would be > to either highlight resistors that should be inserted or chips that should > be inserted for that specific build. > > Afshin Salehi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
