Re: [casper] Problem running tutorial 2

know if you have any problems, Jack On 11 August 2014 11:20, Geelen, T.F.G. t.f.g.gee...@student.tue.nl wrote: Hi Jack, Thank you, I'll be waiting for the new push on the repository. Thanks already! Groetjes, Tom Geelen Jack Hickish jackhick...@gmail.com wrote: Hi Tom

Re: [casper] Network Switches

...@ssl.berkeley.edu wrote: hi john, jack hickish tested a mellanox SX1012 (12x40Gbe, or 48x10Gbe, or mixture), when he was visiting berkeley. the SX1012 worked beautifully on roach2, after jack upgraded the switch firmware. and it's a great price. ($6K) i think jason has also tested this switch

Re: [casper] Network Switches

look forward to discussion people may have with Jonathon (Cc me if not conducted via the Casper list). Best, Lincoln On 9/2/14, 11:54 AM, Jack Hickish wrote: Hi John, As Dan said I've tested (to some extent) the SX1012. I just used one ROACH2 and corner turned data through 8 x 10GbE

Re: [casper] Spectrometer ASIAA ADC

Hi Katty, We've already spoken about this, but I thought I'd reply to the maillist in case others with the same problem land here -- I've had this problem once before, after checking the potential things Dave mentioned, I tried restarting Matlab and the problem disappeared. Not really a solution,

Re: [casper] errors of casper_xps on tut3

Hi, If you look in the opb_v20 mpd file -- https://github.com/jack-h/mlib_devel/blob/master/xps_base/XPS_ROACH2_base/pcores/opb_v20_v1_10_c/data/opb_v20_v2_1_0.mpd -- you should see an option OPTION ARCH_SUPPORT_MAP which defines the FPGA types supported by the core. If you add

Re: [casper] QDR error

Hi Raul, Few questions -- Which mlib_devel repository are you using? Which board are you compiling for? What are you clocking your design from (what have you set the MSSGE block clock source to, and do you have the corresponding blocks in your model if you've selected an ADC?) Cheers, Jack On

Re: [casper] QDR error

-23 10:27 GMT-03:00 Jack Hickish jackhick...@gmail.com: Hi Raul, Few questions -- Which mlib_devel repository are you using? Which board are you compiling for? What are you clocking your design from (what have you set the MSSGE block clock source to, and do you have the corresponding blocks

Re: [casper] OS for development: Ubuntu 14.04?

Hi Adam, I'm using Ubuntu 14.04 and things seem to work as they should, as long as you follow the instructions on that wiki page. Though not used by the toolflow, Vivado 2014.3 officially supports ubuntu 14.04, if that's a concern to you. Having said that, I think if I were to go through the

Re: [casper] Problem about the adc frequency in PAPER model.

Hi Richard, I've just had a very brief look at the design / software, so take this email with a pinch of salt, but on the off-chance you haven't checked this It looks like the PAPER F-engine setup on running the start script for software / firmware out of the box is -- 1. Disable all

Re: [casper] Problem about the adc frequency in PAPER model.

the 10-GbE cores for another second to fix it? This might be a quick way to test that theory, but please correct me if I've misunderstood. Richard Black On Mon, Oct 27, 2014 at 11:05 AM, Jack Hickish jackhick...@gmail.com wrote: Hi Richard, I've just had a very brief look at the design

Re: [casper] spectrometer implementation using LX110T instead of SX95T

Hi louis, I've just checked the spec sheet - 64 multipliers!! I'm guessing you ran out of slices when you (or maybe the compiler) pushed lots of multipliers into logic? (the lx has more slices than the sx) Maybe send around your utilisation summary tomorrow - it sounds like you might need to find

Re: [casper] spectrometer implementation using LX110T instead of SX95T

Hi Louis, You can grab the report from the terminal, but it's also at the top of the map report file, at compile-directory/XPS_ROACH_base/implementation/system_map.mrp Cheers, Jack On 29 October 2014 03:31, Louis Dartez louisdar...@gmail.com wrote: Hi Dan, I cut the number of frequency

Re: [casper] Starburst, an open-source 10gsps low-N correlator for ROACH2

Hey Ryan, This sounds great. I've just got a 312mhz design for a project in Cambridge to meet timing (broadly similar to what you're describing, but 10 single pol antennas and only 4k channels over 5ghz bw). Whilst I don't have any particular requests, I would be very interested in hearing about

Re: [casper] wide_band_real fft simulation problem of tut3

Can I add to this - do you simulate a sync pulse input, and wait an adequate time to see it show up on the block output? Jack On 2 Nov 2014 12:50, G Jones glenn.calt...@gmail.com wrote: When you are simulating, do you have the fftshift set appropriately? A pure sine wave will be the worst case

[casper] ROACH2 power on boot

Howdy Casperites, Maybe my searching ability has failed me, but surprisingly I couldn't find this in the mail archive -- What does one have to do to get a ROACH2 to boot immediately when power is applied? Thanks, and happy Thanksgiving to those celebrating such a thing, Jack

Re: [casper] ROACH2 power on boot

Sigh. Thanks! On Fri Nov 28 2014 at 16:34:11 John Ford jf...@nrao.edu wrote: I think this is the thread you seek. Your searching powers are clearly compromised by Thanksgiving dinner. https://www.mail-archive.com/casper%40lists.berkeley.edu/msg03727.html :) Howdy Casperites,

Re: [casper] NFS setup: TFTP permissions problem

Hi Michael, Do you have SELinux running? I've just checked and I get a similar permissions error if I reactivate SELinux on my Centos 6 server. On Tue Dec 02 2014 at 14:07:45 Michael D'Cruze michael.dcr...@postgrad.manchester.ac.uk wrote: Hi everyone I'm following the NFS setup guide,

[casper] Compiler merging SRLs -- Timing performance

Hi all, This is something I've been fighting with for a while now, and I wonder if anyone on this maillist has any insight (because I'm pretty sure I may just be doing something wrong with the tools). The problem: I'm playing with a ROACH2 design that (sometimes) compiles at 312 MHz. However,

Re: [casper] Compiler merging SRLs -- Timing performance

-synthesize the entire netlist. Dave On Dec 4, 2014, at 10:48 AM, Jack Hickish wrote: Hi all, This is something I've been fighting with for a while now, and I wonder if anyone on this maillist has any insight (because I'm pretty sure I may just be doing something wrong with the tools

Re: [casper] Compiler merging SRLs -- Timing performance

timing closure. Hope this helps. HK On Thu, Dec 4, 2014 at 9:37 PM, Jack Hickish jackhick...@gmail.com wrote: Hey Mark, Yeah, I guess I could manually force the locations of the two offending shift-regs to stop the combination, but the problem SRLs seem to be a fairly arbitrary

Re: [casper] inverse PFB

Hey Laura, Have you tried the vanilla complex 'fft' block? If you generate the full spectra including negative frequencies before inputting (I think there's a mirror_spectrum block that might do this(?)), I would have thought you could add two input streams together, as streamA + j*streamB. Since

Re: [casper] Mkid DAC error

Hi Matt, I'll push these into the main casper-astro github. Cheers Jack PS. Anyone else with rogue yellow blocks / cool new features / other stuff which folk might benefit from, feel free to email me patches or files, or raise github pull requests. Some of the major mlibdevel forks (like

Re: [casper] Roach2 QDR

and the other in fabric, the two 32 bit words get swapped, and the sequence is offset by one value. I actually see the same offset in a Roach1 version of the design as well. It all seems consistent, not intermittent. Thanks, Matt On Mon, Mar 9, 2015 at 10:42 AM, Jack Hickish jackhick

Re: [casper] Roach2 QDR

Hi Matt, The qdr_cal routine calibrates the relationship of clock and data signals in the link between the FPGA and QDR signals. Basically it writes test patterns and reads them back looking for glitches. It then changes the delay of IODELAY blocks so that data read from the QDR is captured

Re: [casper] How to use the qdr_transpose and qdr_ct blocks?

Hi Chenwei, I'm not sure about the qdr corner turn block, but the qdr transpose is fairly simple. It has two parameters, input block size, and output block size. The first is the number of channels in the fft input stream, the second is the number of spectra you want to buffer and transpose. I.e.

[casper] Netfpga

Hi all, Today I had a fun meeting with Andrew Moore at Cambridge university, who does some great stuff as part of netfpga (netfpga.org). By the end of it, I wanted some new toys, namely their latest virtex 7 board -

Re: [casper] sync ADCs in ROACH2

Hi Franco, The sync inputs are usually used to synchronise multiple boards. If you feed an lvttl signal into the sync input of the adc5g, it will emerge from the sync output of the yellow block. Usually people drive this signal with a pulse per second signal from a GPS, and use the resulting

Re: [casper] Regarding dram: Moving from ROACH1 to ROACH2

works but I don't want to post a buggy design. Also, how does one update the wiki on this? Perhaps add an app note? Tim From: Brad Dober [do...@sas.upenn.edu] Sent: Monday, April 20, 2015 10:07 AM To: Madden, Timothy J. Cc: Jack Hickish; casper

Re: [casper] cross_multiplier block can't find cram_init function

Hi James, I think this commit -- https://github.com/jack-h/mlib_devel/commit/c34d3e539552b2f75a5e0452a72b0669b66a187b -- should solve your problem. Cheers, Jack On Tue, 28 Apr 2015 at 04:59 G Jones glenn.calt...@gmail.com wrote: Cram was my old version of the new bus creation utilities. The

Re: [casper] cross_multiplier block can't find cram_init function

-- *From:* Jack Hickish [jackhick...@gmail.com] *Sent:* Tuesday, April 28, 2015 10:27 PM *To:* G Jones; James Gowans *Cc:* casper@lists.berkeley.edu *Subject:* Re: [casper] cross_multiplier block can't find cram_init function Hi James, I think this commit

Re: [casper] cross_multiplier block can't find cram_init function

a compile now but I don't foresee any problems. I've made a pull request against ska-sa for your change. James -- *From:* Jack Hickish [jackhick...@gmail.com] *Sent:* Thursday, April 30, 2015 8:33 PM *To:* James Gowans; G Jones *Cc:* casper@lists.berkeley.edu

Re: [casper] Timing distribution over fiber

Hi John, Thanks for the info. I'll add Litelink to my list of suppliers to investigate. We have no particular urge to multiplex the signals on to the fiber unless there's a particularly neat/cheap solution to do that. There's no great appetite to go custom. We've got about ~30 nodes, and my first

Re: [casper] casper Digest, Vol 90, Issue 10

... Today's Topics: 1. Re: Timing distribution over fiber (Jack Hickish) -- Message: 1 Date: Wed, 06 May 2015 23:45:53 + From: Jack Hickish jackhick...@gmail.com Subject: Re: [casper] Timing distribution over fiber

Re: [casper] Timing distribution over fiber

but with considerable development time. Bob Stricklin On May 4, 2015, at 10:02 PM, Jack Hickish jackhick...@gmail.com wrote: Hi John, Thanks for the info. I'll add Litelink to my list of suppliers to investigate. We have no particular urge to multiplex the signals

Re: [casper] Timing distribution over fiber

to maintain good phasing between channels. The analog devices chip is $50 so a custom solution should be $500/reference but with considerable development time. Bob Stricklin On May 4, 2015, at 10:02 PM, Jack Hickish jackhick...@gmail.com wrote: Hi John, Thanks for the info. I'll add Litelink

Re: [casper] Timing distribution over fiber

, at 10:02 PM, Jack Hickish jackhick...@gmail.com wrote: Hi John, Thanks for the info. I'll add Litelink to my list of suppliers to investigate. We have no particular urge to multiplex the signals on to the fiber unless there's a particularly neat/cheap solution to do that. There's

Re: [casper] Regarding dram: Moving from ROACH1 to ROACH2

Hi Tim, If you don't mind sharing your design, I'll put it up on the Casper wiki, where i think it would be useful for others trying to use the dram. Cheers, Jack On Thu, 16 Apr 2015 7:19 am Madden, Timothy J. tmad...@aps.anl.gov wrote: Folks After reverse engineering the dram on ROACH2

Re: [casper] How to use the qdr_transpose and qdr_ct blocks?

. Thanks for your help! On Sat, Jun 6, 2015 at 3:43 AM, Jack Hickish jackhick...@gmail.com wrote: no rush - let me know how the compile goes! cheers jack On 5 June 2015 at 23:24, Chenwei Cai caichenwei1...@gmail.com wrote: Sure Jack, but I have to send that to you on Monday, because

Re: [casper] How to use the qdr_transpose and qdr_ct blocks?

such a problem before or has some ideas about that? Thanks! On Mon, Apr 27, 2015 at 4:06 PM, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, A couple of general comments -- 1. strictly speaking you should have xilinx gateway out blocks between the slice blocks and the scope, since

Re: [casper] How to use the qdr_transpose and qdr_ct blocks?

your toolflow for this reason alone. Cheers, Jack On Fri, 5 Jun 2015 at 12:57 Chenwei Cai caichenwei1...@gmail.com wrote: Hi Jack, I am using Xilinx 14.5. On Fri, Jun 5, 2015 at 4:55 PM, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, What version of the Xilinx tools are you using

Re: [casper] How to use the qdr_transpose and qdr_ct blocks?

suggestions and help. I will try to calibrate qdr with the script you provided in my next step. Best Regards Chenwei CAI Email: caichenwei1...@pku.edu.cn On Tue, Jun 9, 2015 at 4:24 AM, Jack Hickish jackhick...@gmail.com wrote: Hi Chenwei, I had a look at your model - the error will go away

Re: [casper] System Compatibility

Hi Victor, I strongly recommend using Xilinx's 14.7 release. Some people use Ubuntu 12.04 -- see https://casper.berkeley.edu/wiki/MSSGE_Setup_with_Xilinx_14.x_and_Matlab_2012b -- but as Dan says, life might be easier with a supported operating system... Cheers, Jack On Tue, 23 Jun 2015 at 13:01

Re: [casper] Call for awesome commits

On Wed, 27 May 2015 at 21:35 Jack Hickish jackhick...@gmail.com wrote: Hi All, I believe I have a version of the QDR block / software that works at every conceivable clock frequency anyone could want. Tomorrow (Berkeley time), I'm going to merge this into the main casper-astro github repository

[casper] Call for awesome commits

Hi All, I believe I have a version of the QDR block / software that works at every conceivable clock frequency anyone could want. Tomorrow (Berkeley time), I'm going to merge this into the main casper-astro github repository. This seems like as good a time as any to ask: does anyone have any

Re: [casper] System Compatibility

Hi Vishwa, To add to what Danny said, while there will never be a Vivado flow for ROACH1/ROACH2, I've been using a vivado-based flow for the SNAP board, which is a kintex-7 platform. Some very limited information about how to obtain and run the flow, aimed at our local (in berkeley) SNAP users is

Re: [casper] QDR ROACH2: clocking at 145 MHz

Hi JP, What mlib_devel are you using? Did you actually build against commit 72d879c? I noticed you emailed a link to my repository which I specifically tweaked for my higher (312MHz) work, which I'm sure breaks *everything* at 145. Cheers, Jack On Fri, 22 May 2015 at 06:41 Juan-Pierre Jansen

Re: [casper] 5GS/s ADC compile errors

-test version for fixes before they become mainstream? Cheers Michael *From:* Jack Hickish [mailto:jackhick...@gmail.com] *Sent:* 13 August 2015 19:06 *To:* Michael D'Cruze; casper@lists.berkeley.edu *Subject:* Re: [casper] 5GS/s ADC compile errors Hi Michael, This is fixed

Re: [casper] Roach-2 crashing fix

Hi all, To close out this thread, a fix is to add a mem= option to uboot's bootargs variable --- 1. Connect a PC to the ROACH2's FTDI USB port using a usb A-B cable. 2. Open a serial console on the roach 2 using minicom/picocom/your-favourite-serial-console. The interface settings are

Re: [casper] 10Gbe transmission on roach 1

Hi Kaustubh, Have you set the option in the tgev2 yellow block to enable large tx frames? Do the receive the packets with the size you're expecting (I.e. is the EOF synchronisation logic working properly) Cheers, Jack On Tue, 11 Aug 2015 6:18 am Kaustubh Rajwade rkaustub...@gmail.com wrote: Hi

Re: [casper] 5GS/s ADC compile errors

Hi Michael, This is fixed by commit 404989f. It's in the casper-astro-soak-test branch of https://github.com/casper-astro/mlib_devel There's a bunch of other fixes in this branch, so I would suggest using it. At some point in the hopefully near future it will become the standard casper-astro

Re: [casper] Roach2 aux clocking and Bram's

Hi Vereese, Adding an iadc block will (I think, having just checked the adc yellow block code) change the number or software devices on the OPB bus, so could affect the problem if Dave's first hypothesis is correct. Having said that, your test using sys_clk, as long as you left all the yellow

[casper] GNU Radio

Hi all, At the end of August there is a GNU Radio conference in Washington DC ( http://www.trondeau.com/gnu-radio-conference-2015/) which myself and a few folk from Green Bank (I believe Richard Prestage, Mark Whitehead and Joe Brandt) were going to attend. Are any CASPERites thinking of going?

Re: [casper] Migrating to Roach 2 from Roach 1

Hi Paul, The toolflow remains the same, you just get more FPGA / QDR / IO -- in principle you just change the platform from ROACH to ROACH2, recompile, and you're good to go. In practice, there's usually a few tweaks you'd need to make depending what on-board resources you have used. Eg. Gpio /

Re: [casper] startsg issue (Xilinx?)

Seconded -- http://www.xilinx.com/support/answers/17966.html suggests MATLAB 2013a and anything before ISE 14.7 (although 14.6 works on windows -- yay!) isn't a supported combination. On Sun, 15 Nov 2015 at 19:22 John Ford wrote: > > Hi all, > > > > As part of my attempts to

Re: [casper] Multicast on 10 gbe on ROACH-2?

Hi John, It works great! Transmit only is happily also the simplest use case. If you're doing stuff from the powerPC which you want multicasting, I believe you have to invoke corr.katcp_wrapper.FpgaClient.tap_multicast_add_send(). If you only want to multicast traffic from the FPGA (which is how

Re: [casper] Weird FFT Output

Hi Amit, I've hastily fixed that error regarding bram latency -- it's pushed to the master casper branch at https://github.com/casper-astro/mlib_devel.git You should be able to cherry pick that commit into your repository, but I recommend just using the casper-astro master branch rather than the

Re: [casper] xps Segmentation fault

Hi Roberto, That's an interesting one. I don't think I've ever seen xps segfault. First, are you using the latest (14.7) versions of the Xilinx tools? Second, can you compile the original yellow block OK? Other than go through the changes you've made step by step until you identify the what's

Re: [casper] Weird FFT block problem

he problem first arose I grabbed the latest casper-astro-soak-test > commit, which didn’t solve the immediate issue. > > > > Perhaps someone could confirm that bram latencies >10 causes this issue? > It’s a 2^17 point FFT with fanout 1. > > > > BW > Michael > >

Re: [casper] Weird FFT block problem

Hi Michael, If the initialisation script fails half way through drawing then often you'll be left with a bunch of blocks half connected, so I think that's (probably) a symptom rather than a cause of the issue. Are you using the latest casper-astro branch? Do you remember what FFT parameters you

Re: [casper] Mystery timing errors

Hi Michael, As one of the Xilinx timing closure documents helpfully articulates, it's very difficult to give specific recipes for solving timing problems, other than reading the timing report, looking at things in PlanAhead/FPGA Editor, iterating compiles and developing some intuition. That

Re: [casper] Problems with ADC captured data.

Hi Sharat, Are you running the adc mmcm calibration routine after programming your roach? Cheers, Jack On 31 August 2015 at 22:41, sharat varma wrote: > > Hi Casper, > > I am working as a post-doc working under guidance of Dr. Hayden So at The > University of Hong Kong. > > We

Re: [casper] Mystery timing errors

e more FIR taps ;-) > I admire your boldness. Jack PS. If your design is on github, it might be a nice reference for people trying to build models with relatively large numbers of channels > > > Best wishes > > Michael > > > > *From:* Jack Hickish [mailto:j

Re: [casper] Problems with ADC captured data.

> "/home/nfs/roach2/debian_stable_devel/boffiles/varma/adc_tests-disentangle/adc5g/tools.py", > line 253, in find_best_delay > raise Exception("Couldn't find start of eye") > Exception: Couldn't find start of eye > > > When I run > test_adc ZDOCK 0 &

Re: [casper] Problems with ADC captured data.

ch >>>> adjusts the IODELAY for each individual data line; sadly I don't have a >>>> link handy for that. >>>> >>>> Although you may not see these glitches with a sine wave, a noise-like >>>> signal will cause more transitions on e

Re: [casper] Problems with ADC captured data.

1, 2015 at 2:54 AM, sharat varma <va...@hku.hk> wrote: >> >>> Hi Jack, >>> >>> Thanks for the reply. >>> >>> I did not run mmcm calibration. Actually, we checked the ADC by feeding >>> it a low frequency sine wave from a functi

Re: [casper] Problems with ADC captured data.

> Hi Jack, > > Thank you Jack. > I am using the mlib-devel from https://github.com/sma-wideband/mlib_devel > Also, I am using ISE 14.7. > > Regards, > Sharat > > On 4 September 2015 at 12:34, Jack Hickish <jackhick...@gmail.com> wrote: > >> Hi Sharat,

Re: [casper] Spectrum issues

Hi Michael, Are you certain that 1. The snapshot bram address counters have been changed to accommodate the new deeper rams. If not they will wrap and never write to the lower part of the ram. 2. Whatever controls the valid signal to the shared brams has been modified so that valid goes high for

Re: [casper] Problems with ADC captured data.

d not figure out where is the problem. > > Regards, > Sharat > > On 7 September 2015 at 23:47, David MacMahon <dav...@astro.berkeley.edu> > wrote: > >> Hi, Sharat, >> >> On Sep 6, 2015, at 11:02 PM, Jack Hickish wrote: >> >> > As the code s

Re: [casper] Unconnected output block warnings when compiling with dac_mkid

Hi Richard, I've just modified the dac yellow blocks so that they don't try to call the initialisation script for the now non-existent parallel_to_serial block. The interface should still work -- essentially it's now frozen with the parameters originally set by the dac yellow block, which I

Re: [casper] Error with snapshot block

Hi Roberto, I think if you tie the external sync to 1 (so it has no edges), you have to issue a software sync. You can do this with the man_trig optional argument of snapshot_get(): roach.snapshot_get('snap_name', man_trig=True) Hope that helps, Jack On Thu, 17 Dec 2015 at 18:58 Roberto F.

Re: [casper] building 300-receiver channel cross-correlator

c.uk/). I have to say I'm not entirely sure what's available in the board design realm. Jack > Many thanks, > > Neil > > > > *From:* Jack Hickish [mailto:jackhick...@gmail.com] > *Sent:* 18 December 2015 17:26 > *To:* Neil Salmon; James Smith > > > *Cc:* ca

Re: [casper] building 300-receiver channel cross-correlator

Hi Neil, A bit more information would be useful, but it sounds like if you could construct a ZDOK card that interfaced some (40, one per differential pair?) of your digitizers to a ROACH board you could use a handful of ROACH boards to perform all of the cross multiplication and accumulation and

Re: [casper] Interfacing 64-channel ADC with ROACH-2

Hi Kaushal, cc. CASPER, All good here (Berkeley), thanks. Hope you are well too. It's been a long time since I've used that ADC, but from what I remember... - Yes, you need to appropriately drive the ADC's reset through the jumper. If things aren't working and you're debugging with a probe,

Re: [casper] Error in Simulating Roach 2 Tutorial 1 .mdl file

Hi Christopher, Which scope outputs are you not able to reproduce from the wiki? What outputs did you see? Cheers Jack On Tue, 14 Jun 2016 at 10:21 Christopher Barnes wrote: > Hello, > > My name is Christopher Barnes, and I'm a graduate student at the > University of

Re: [casper] Error in Simulating Roach 2 Tutorial 1 .mdl file

e correct. > > For the counter, the settings are correct; I just checked them again. Do > you have any more ideas on this? > > On Tue, Jun 14, 2016 at 2:04 PM, Jack Hickish <jackhick...@gmail.com> > wrote: > >> For the adder, have you clicked the icon at the top m

Re: [casper] Error in Simulating Roach 2 Tutorial 1 .mdl file

ine at 0 for the counter output and then just an empty > set of axes for the adder output. > > On Tue, Jun 14, 2016 at 1:56 PM, Jack Hickish <jackhick...@gmail.com> > wrote: > >> Hi Christopher, >> >> Which scope outputs are you not able to reproduce f

Re: [casper] ASIAA adc5g downsampling

Hi Amit, That's correct, assuming you are operating the adc in single input mode. It also has a dual-input mode, where the first 8 outputs are one input, and the second 8 are the other. Don't forget that the input clock in single input (aka interleaved) mode should be half the total sample rate.

Re: [casper] VHDL for ROACH2

erilog source yourself. > > Good luck! > > > Kind Regards, > > Adam > > On Tue, Jun 21, 2016 at 11:47 PM, Jack Hickish <jackhick...@gmail.com> > wrote: > >> Hi Andrea, cc-ing maillist, since I don't think you're the only one to do >> (or want to

Re: [casper] SNAP orders

(at $280), not including enclosure or 12v power supply. Cheers Jack On Sat, 18 Jun 2016, 15:15 Jack Hickish, <jackhick...@gmail.com> wrote: > Hi all, > > SNAP revision 2 is (finally) about to finish being tested. Various folk > expressed interest in purchasing them once

Re: [casper] ADC 5g testing

Hi Amit, For what it's worth, you can always just run the ADC faster, but only use a subset of the yellow block outputs. Eg., clock the ADC at 1280MHz, and use every 8th yellow block output. This can be handy because 1. You get to avoid whatever edge cases exist which cause various blocks to

Re: [casper] 32 parallel inputs to fft_wideband_real

Hi Homin, What total size of FFT are you trying to do? How does the FFT fail? Cheers, Jack On Mon, 11 Jan 2016 at 00:35 Homin Jiang wrote: > Hello: > > Does anyone have the experience of the 32 simultaneous inputs to the > fft_wideband_real ? I have tried that for

Re: [casper] 32 parallel inputs to fft_wideband_real

_gen blocks. > > > regards > homin > > On Tue, Jan 12, 2016 at 12:38 AM, Jack Hickish <jackhick...@gmail.com> > wrote: > >> Hi Homin, >> >> What total size of FFT are you trying to do? How does the FFT fail? >> >> Cheers, >> Ja

Re: [casper] ROACH2 spectrum zeroes: request to verify my results

d also on a ROACH1. > > > > https://dl.dropboxusercontent.com/u/38103354/r2_spectra.zip > > > > BW > Michael > > > > *From:* Jack Hickish [mailto:jackhick...@gmail.com] > > *Sent:* 12 January 2016 21:28 > > *To:* Michael D'Cruze > *Subject:* R

Re: [casper] PlanAhead to a working bof

There's also a UCF yellow block that lets you add ucf files to your design (much like the PCORE yellow block). I think there's also a method to inject ucf constraints via an environment variable (I think you could find this in the git log somewhere). Cheers, Jack On Wed, 3 Feb 2016 at 10:31

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

Hi Vishwa, Is the syntax definitely -demux=1 andnot either --demux=1 or -d 1 ? Jack On Wed, 3 Feb 2016, 12:39 a.m. Vishwa Seneviratne wrote: > Hi, > > I am working on how to work with different operating of the 'ADC16x250-8 > coax rev 2' for a very simple design to

Re: [casper] Compiler merging SRLs

Ha, I just read my email in the thread you linked. I guess turning off behavioural hdl isn't (ever? always?) the solution. On Mon, 25 Jan 2016 5:14 pm Jack Hickish <jackhick...@gmail.com> wrote: > Hi Matt, > > You can resynthesize the "main" simulink netlist, but off the

Re: [casper] Compiler merging SRLs

Hi Matt, You can resynthesize the "main" simulink netlist, but off the top of my head I don't know the exact way to go about this. I think you can dig out the netlist from the sysgen build directory and use the resynth script on that. Perhaps Dave MacMahon (who I believe wrote that script) could

Re: [casper] Leuschner Spectrometer

Hi Rolando, This is wrong -- the User IP clock source should be adc0_clk, at 24 MHz. If you see a design with an ADC, but the clock source is set to to sys_clk, this is *almost always* a mistake. Jack On Sat, 20 Feb 2016 at 19:04 Rolando Paz wrote: > Hi > > I have a question

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

during optimization... Jack On Fri, 11 Mar 2016 at 00:18 Jack Hickish <jackhick...@gmail.com> wrote: > Hi Nilan, > > It looks like there's a block called (something like) ppcm12/block_t_z2 > with a huge logic delay -- from line 135 of the failing twr file -- > > Dat

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

>> >> Since, ADCs need to be clocked at 480 MHz for the demux=2 mode, how does >> the FPGA clock at 240 MHz? does it use a clock divider internally? >> >> Is there any maximum operating frequency for the FPGA, when we use the >> adc16 block? >>

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

gt; Nilan Udayanga. > > On Thu, Mar 10, 2016 at 8:38 PM, Jack Hickish <jackhick...@gmail.com> > wrote: > >> Hi Nilan, >> >> Yeah, I figured that would be a problem... :) >> Does something like this (which i confess I haven't read, but Fig 14 >> looks

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

ay. > > Regards, > Nilan Udayanga. > > On Thu, Mar 10, 2016 at 7:18 PM, Jack Hickish <jackhick...@gmail.com> > wrote: > >> Hi Nilan, >> >> It looks like there's a block called (something like) ppcm12/block_t_z2 >> with a huge logic delay -- from line 13

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

elays. But, I don't know whether it may change the > critical path delay. > > Regards, > Nilan Udayanga. > > On Thu, Mar 10, 2016 at 8:02 PM, Jack Hickish <jackhick...@gmail.com> > wrote: > >> I think if you can add latency in those multipliers / adders you'll >>

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

udent* >>> >>> *Dept. of Electrical and Computer Engineering* >>> *University of Akron* >>> >>> On Wed, Feb 3, 2016 at 11:02 AM, Vishwa Seneviratne < >>> mp...@zips.uakron.edu> wrote: >>> >>>> Hi Jack, >>>> >>&

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

; > Since, ADCs need to be clocked at 480 MHz for the demux=2 mode, how does > the FPGA clock at 240 MHz? does it use a clock divider internally? > > Is there any maximum operating frequency for the FPGA, when we use the > adc16 block? > > Regards, > Nilan Udayanga.

Re: [casper] Roach1!

Hi Rolando, CASPER, The ROACH should still be supported by all the CASPER tutorials which are on the wiki -- https://casper.berkeley.edu/wiki/Tutorials Cheers, Jack On Wed, 6 Apr 2016 at 16:48 Rolando Paz wrote: > Hi Jack > > The next Friday I will travel to Mexico to pick

Re: [casper] Roach1!

> > > 2016-04-06 23:07 GMT-06:00 Jack Hickish <jackhick...@gmail.com>: > >> Hi Rolando, CASPER, >> >> The ROACH should still be supported by all the CASPER tutorials which are >> on the wiki -- https://casper.berkeley.edu/wiki/Tutorials >> >> Ch

Re: [casper] Roach1!

ith many ROACH board. > > b) The third roach has password, and could not find it is. How we can > change the user and password? > > The most straightforward way is probably to just copy the SD card image from one of your working ROACH boards, or from the svn links you found.

Re: [casper] yellow block for 2Gsps adc/dac

Hi Matt, The usual way to deal with this is IODELAY blocks as you suggest. The adc5g core has an example of the correct instantiation of the IODELAY primitive and some controller code to talk to them. IIRC, the delay goes straight after the input buffer, prior to the SERDES (or presumably

[casper] Valon Synth python interface

Howdy all, I'm trying to program a Valon 5008 synth with the ValonSynth nrao python API -- https://github.com/nrao/ValonSynth (master branch) -- running on a raspberry pi 3. Does anyone know if this code actually works with a 5008 -- it's advertised for a 5007 and I get some fun results when I

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