Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
it may have to do with having auto junction turned off if so then i guess yes it is a serious bug i have never seen this, but i have never turned auto junction off either Dennis Saputelli John Branthoover wrote: Hello All, I have a schematic of a board that I just had fabricated. When I drew the schematic, I did so with the Auto-Junction feature turned off. I always draw schematics like this because of problems that I have had in the past with the Auto-Junction feature placing junctions where I don t want them. During testing of the new board, my boss brought me the schematics asking why I failed to attach one end of a pull-up resistor to the +5 volt supply. I had simply forgot to place a junction at the point where the wires intersected. My mistake. In looking at the board, the connection was made. I ran a netlist. It showed that the connection was made. How can this be? I added the junction, created another netlist. The netlist showed that the connection was still made, as expected. I then deleted the dot, created another netlist. The connection was still there. The only way that I could remove the connection was to delete the wires and redraw them. After that the schematic started to behave as expected. No junction, no connection. I also tried the procedure on other junctions on the same schematic page. I could not reproduce the error. I have no idea how this error (bug) originally happened. It has made me loose all faith in Protel s schematic capture side. Has anyone else seen this behavior? How can I deal with this problem without checking the entire netlist before I bring it over to the PCB? Argh! Looks like it is time to start looking for a new PCB design software. Beware and good luck. John Branthoover: Electrical Design Engineer : Acutronic R D:Phone (412) 968-1051 640 Alpha Drive :Fax(412) 963-0816 Pittsburgh PA 15238 :Email [EMAIL PROTECTED] USA :WEBhttp://www.acutronic.com -- Dennis Saputelli = send only plain text please! - no HTML == ___ Integrated Controls, Inc. www.integratedcontrolsinc.com 2851 21st Streettel: 415-647-0480 San Francisco, CA 94110 fax: 415-647-3003 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
John, could the difference come in with which point you started drawing your wire? Starting at the resistor pin or starting from the other connection first? Just a thought. One would have to see exactly how you wired to or past that pin to understand exactly how you are getting the results that you got. As well I always work with the auto junction on and have never turned it off. But doesn't the autojunction just aid in making junctions, it doesn't exclude making junctions. Using ERC is still the only way to check a schematic, especially for missed/misplaced pin connections. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com -Original Message- From: John Branthoover [mailto:[EMAIL PROTECTED] Sent: Wednesday, August 13, 2003 11:10 AM To: Protel EDA Forum Subject: [PEDA] Unacceptable Bug in Protel 99 SE SP6..! Hello All, I have a schematic of a board that I just had fabricated. When I drew the schematic, I did so with the Auto-Junction feature turned off. I always draw schematics like this because of problems that I have had in the past with the Auto-Junction feature placing junctions where I don t want them. During testing of the new board, my boss brought me the schematics asking why I failed to attach one end of a pull-up resistor to the +5 volt supply. I had simply forgot to place a junction at the point where the wires intersected. My mistake. In looking at the board, the connection was made. I ran a netlist. It showed that the connection was made. How can this be? I added the junction, created another netlist. The netlist showed that the connection was still made, as expected. I then deleted the dot, created another netlist. The connection was still there. The only way that I could remove the connection was to delete the wires and redraw them. After that the schematic started to behave as expected. No junction, no connection. I also tried the procedure on other junctions on the same schematic page. I could not reproduce the error. I have no idea how this error (bug) originally happened. It has made me loose all faith in Protel s schematic capture side. Has anyone else seen this behavior? How can I deal with this problem without checking the entire netlist before I bring it over to the PCB? Argh! Looks like it is time to start looking for a new PCB design software. Beware and good luck. John Branthoover: Electrical Design Engineer : Acutronic R D:Phone (412) 968-1051 640 Alpha Drive :Fax(412) 963-0816 Pittsburgh PA 15238 :Email [EMAIL PROTECTED] USA :WEBhttp://www.acutronic.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
In a message dated 8/13/2003 4:33:41 PM Eastern Daylight Time, [EMAIL PROTECTED] writes: Just some ideas, I would not lose faith in Protel over this one instance I wholeheartedly agree. I always keep autojunction turned on, and I've learned (the hard way at times) that if autojunction does something unexpected, it's time to cease work, pencils down, and go back and figure out why. Either an unexpected dot, or a missing dot where I expected one, is ALWAYS trying to tell me that something bad is happening. Lots of possible causes - wires that were broken and then resumed in the middle of nowhere, a part that was built with the pins inside-out, a part that was built with lines and text to pretend they're pins, even a schematic that had been wired with lines rather than wires. I've seen all of those - had to clean up some rather badly munged schematics along the way. But autojunctioning is very good at pointing out such problems - leave it turned on!! YMMV. Steve Hendrix * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Unacceptable Bug in Protel 99 SE SP6..!
Hello All, I have a schematic of a board that I just had fabricated. When I drew the schematic, I did so with the Auto-Junction feature turned off. I always draw schematics like this because of problems that I have had in the past with the Auto-Junction feature placing junctions where I don t want them. During testing of the new board, my boss brought me the schematics asking why I failed to attach one end of a pull-up resistor to the +5 volt supply. I had simply forgot to place a junction at the point where the wires intersected. My mistake. In looking at the board, the connection was made. I ran a netlist. It showed that the connection was made. How can this be? I added the junction, created another netlist. The netlist showed that the connection was still made, as expected. I then deleted the dot, created another netlist. The connection was still there. The only way that I could remove the connection was to delete the wires and redraw them. After that the schematic started to behave as expected. No junction, no connection. I also tried the procedure on other junctions on the same schematic page. I could not reproduce the error. I have no idea how this error (bug) originally happened. It has made me loose all faith in Protel s schematic capture side. Has anyone else seen this behavior? How can I deal with this problem without checking the entire netlist before I bring it over to the PCB? Argh! Looks like it is time to start looking for a new PCB design software. Beware and good luck. John Branthoover: Electrical Design Engineer : Acutronic R D:Phone (412) 968-1051 640 Alpha Drive :Fax(412) 963-0816 Pittsburgh PA 15238 :Email [EMAIL PROTECTED] USA :WEBhttp://www.acutronic.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autoreply: ---- someone set this thing to stop rebroadcasting Au to replies ------
It seems Mr. Watts has invented an e-mail oscillator ;-) Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Brooks,Bill [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Friday, August 08, 2003 2:08 PM Subject: [PEDA] Autoreply: someone set this thing to stop rebroadcasting Au to replies -- The moderator of this e-mail news/discussion group needs to filter out Auto replies from getting re-broadcast to all of us... this guys piers is in some sort of loop repeating over and over with each e-mail his auto reply sends it auto replies to itself... Bill Brooks * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Rule confusion
-Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED] Sent: Tuesday, August 05, 2003 1:02 PM To: Protel EDA Forum Subject: Re: [PEDA] Rule confusion On 01:02 PM 5/08/2003, Sanders, Dave said: I need a little help. I am using DXP SP2 on a very simple pcb, but I can't set up the clearance rules to do what I require. The general clearance rule is .25mm min between all items.This is fine for most of the board. I want to set up a second clearance rule that specifies a clearance of .5mm between polygon pours and all other items. So I set a second clearance rule where the 1st object is a poly, and the second object is all, a clearance of .5mm, and priority 1. But when I pour the poly, the general clearance rule (priority 2)is followed instead. Why??? Can anyone out there assist me on this one, tell me what I'm doing wrong. Dave Sanders This issue is the most commonly asked Q I think. There is a Protel KB article about it. You need to use InPolygon (or InPoly) rather than IsPolygon (or IsPoly). You need to test against the member tracks of the poly (InPoly) rather than the polygon itself. Ian I don't understand! There's no mention of InPoly in the PCB Rules and Constraints Editor. Can you point me at the relevant KB article. All my searches turn up nothing. Dave Sanders [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autoreply: Autoreply: How to make Component Height Rules
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
The trick to avoid auto-junctions where you don't want them is to make sure that endpoints of wires (and pins) don't intersect with any point on another wire. This means you have to be careful about how you place wires. Once you learn this behavior, it's not a problem. The problem with turning auto-junction off is that next time the schematic is opened in a Protel window with auto-junction turned on, the junctions get added, even if the schematic was created with auto-junction off. This is one case where it's Protel's way or the highway (for you)! I use auto-juntion turned ON. The reason is that if I turn it off, and later turn it back on (or Protel turns it back on) then junctions might be placed where they hadn't been before. By having it turned on, I can get instant feedback if any auto-junction nastiness happens. You might be longing for ye olde days of OrCAD SDT III for DOS, where junctions had to be explicitly placed by you... Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: John Branthoover [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, August 13, 2003 2:10 PM Subject: [PEDA] Unacceptable Bug in Protel 99 SE SP6..! Hello All, I have a schematic of a board that I just had fabricated. When I drew the schematic, I did so with the Auto-Junction feature turned off. I always draw schematics like this because of problems that I have had in the past with the Auto-Junction feature placing junctions where I don t want them. During testing of the new board, my boss brought me the schematics asking why I failed to attach one end of a pull-up resistor to the +5 volt supply. I had simply forgot to place a junction at the point where the wires intersected. My mistake. In looking at the board, the connection was made. I ran a netlist. It showed that the connection was made. How can this be? I added the junction, created another netlist. The netlist showed that the connection was still made, as expected. I then deleted the dot, created another netlist. The connection was still there. The only way that I could remove the connection was to delete the wires and redraw them. After that the schematic started to behave as expected. No junction, no connection. I also tried the procedure on other junctions on the same schematic page. I could not reproduce the error. I have no idea how this error (bug) originally happened. It has made me loose all faith in Protel s schematic capture side. Has anyone else seen this behavior? How can I deal with this problem without checking the entire netlist before I bring it over to the PCB? Argh! Looks like it is time to start looking for a new PCB design software. Beware and good luck. John Branthoover: Electrical Design Engineer : Acutronic R D:Phone (412) 968-1051 640 Alpha Drive :Fax(412) 963-0816 Pittsburgh PA 15238 :Email [EMAIL PROTECTED] USA :WEBhttp://www.acutronic.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autoreply: Autoreply: Autoreply: Autoreply: PCB Copper thickness VS mounted rails.
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE, PCB, disapearing connectionlines
Hi Waldemar,
You seem to have got a really strange problem.
Just one idea. This trick usually helps if the Pcb have become corrupt. If
I read your first mail correctly you do have a schematic. If so I would try
to select all in the Pcb and copy it to new Pcb. This will usually flush
any invalid objects and problems. You will lose rules and the netlist, but
that is the good thing about this. Then try to update from the new Pcb from
the schematic and update the free primitives to get the tracks connected to
the pads. This usually helps.
I hope this trick can help.
/Mattias
Mattias Ericson
Omnisys Instruments AB
Gruvgatan 8
SE-421 30 Västra Frölunda, SWEDEN
Phone: +46 31 734 34 08
Fax: +46 31 734 34 29
http://www.omnisys.se
Kulajew
Waldemar
waldemar.kulajew To
@kuebler.com Protel EDA Forum
[EMAIL PROTECTED]
2003-08-05 11:13 cc
Subject
Please respond to Re: [PEDA] 99SE, PCB, disapearing
Protel EDAconnectionlines
Forum
[EMAIL PROTECTED]
echservinc.com
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]
Is the PCB routed or unrouted?
Ian,
we got it routed, but for a redesign we unrouted some nets and,
after the problem apeares, we unrouted all nets for test.
So yes, all nets are unrouted.
But while you ask. The first version of the PCB (the converted)
did not show any pads for some reason. They apeared after we
replaced the old footprint by our new ones.
Thanks for fighting by my side still fighting
Waldemar
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Re: [PEDA] 99SE, PCB, disapearing connectionlines
Hi, Check that you have the Connections layer enabled under DesignOptions and the layer setup. An other thing to test is DesignNetlist manager and chose Optimize all nets from the menu. This forces a redraw of all connections. Hope that helps. Best Regards Mattias Mattias Ericson Omnisys Instruments AB Gruvgatan 8 SE-421 30 Västra Frölunda, SWEDEN Phone: +46 31 734 34 08 Fax: +46 31 734 34 29 http://www.omnisys.se Kulajew Waldemar waldemar.kulajew To @kuebler.com ProtelForum (E-Mail) [EMAIL PROTECTED] 2003-08-05 10:00 cc Subject Please respond to [PEDA] 99SE, PCB, disapearing Protel EDAconnectionlines Forum [EMAIL PROTECTED] echservinc.com Hello Everybody out there, Hope you are able to read my engliSCH and understand my Problem. Using 99SE SP6 we discovered a strange behaviour in the PCB-Editor. One of my Colleagues has got an old Eagle design, that was converted by a profesional converter we found by lurking these list for a while. There was some problems because theguys who converted the PCB did not have our original Footprints, so we have to replace them (the Foot- prints, not the guys g) After that we found everything in its place except the connction-lines. Al pads seames to have the Right nets, but only _some_ of this nets are showed by the usual Lines. After plaing around for a whilewe desided to ask somebody who have more experience, you! Here is what we tried: -searchin knowledge-base (found nothing !?) -al commands under the submenu view/connections -updatet PCB-netlist from schematic. (well the Nets where still there ..but we thought it may Help...) -doubleclicking on the netnam in the left panel and have a look on the ..Hide button (it was turned of) -the buttons in the Options/preferences/display-tab -changing the Layer drawing order (the way that Connect Layer is the ..First to be drawn) -looking in the Mailarchiv by searching Ratsnest And connections ..hide (found nothing relevant) So here is our ask for help to everybody. Any hint appreciated. Regards Waldemar Kulajew __ Fritz Kuebler GmbH Tel.: +49-7720-3903-44 Schubertstrasse 47 Fax: +49-7720-811709 78054 Villingen-Schwenningenhttp://www.kuebler.com mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Nh²Ö¦zËé[h¦º-zWiú+ºk^r ®ø§qÊN^j÷+%ËoÈÛiÿü0Â×Ç«¾)Ür¿¦º-z[¬z»?æ¯zf*'µ§-¶¥Ëfjv z¹[hîfx¬¶¶¢´Þr®ò'qÊîk¢uébëºW¬Ûiÿü0Â×Ç«¾)Ür¿¦º-z[¬z»?~zÈmPk£ ¢´j·!¦·¯¬¦-x,Ûiÿü0Âf¢ªÜ+Þr¿¦º-zWiú+ºk^r ®ø§qÊ
Re: [PEDA] Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: PCB Copper thickness VS mounted rails.
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Robert Gillatt is on holiday.
I will be out of the office starting 08/08/2003 and will not return until 18/08/2003. I will respond to your message when I return. Try calling John Mather on 01752 693908 if you have something which just can't wait. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE, PCB, disapearing connectionlines
-Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED] Is the PCB routed or unrouted? Ian, we got it routed, but for a redesign we unrouted some nets and, after the problem apeares, we unrouted all nets for test. So yes, all nets are unrouted. But while you ask. The first version of the PCB (the converted) did not show any pads for some reason. They apeared after we replaced the old footprint by our new ones. Thanks for fighting by my side still fighting Waldemar * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Rule confusion
On 02:15 PM 5/08/2003, Sanders, Dave said: I don't understand! There's no mention of InPoly in the PCB Rules and Constraints Editor. Can you point me at the relevant KB article. All my searches turn up nothing. http://www.protel.com.au/resources/kb/default.asp#results and then search for InPolygon (or IsPolygon). The direct link will be: http://www.protel.com/resources/kb/kb_item.asp?ID=3678 In the Rules and Constraints editor edit your poly clearance rule and choose the Advanced (Query) radio button, then use the Query Helper. The secret trick is that InPolygon is not listed in the Membership Checks as you would expect. But if you hit F1 you should be able to get to all the PCB Functions (in the Query Reference) - it is listed there. This issue has been discussed many times on the DXP forum. If you are using DXP you may find it worth monitoring that forum as well as PEDA. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Footprints for High power Snap-In type caps.
the two lead kind? they're pretty easy i imagine it would take about as long to verify one as to make one and of course if you found some you would *have* to verify them :) ds Brian Guralnick wrote: Hi, I'm looking for generic footprints for an assortment of High Power, Large can - Snap-In type capacitors. Where should I look? _ Brian Guralnick [EMAIL PROTECTED] -- Dennis Saputelli = send only plain text please! - no HTML == ___ Integrated Controls, Inc. www.integratedcontrolsinc.com 2851 21st Streettel: 415-647-0480 San Francisco, CA 94110 fax: 415-647-3003 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PDF Files from Protel 99SE
pdfwriter and distiller work differently regarding paths, at least for me using acrobat 4.0 PDFwriter will go to a specified path distiller is broken and will only go reliably to the sub folder PDF OUTPUT under adobe program distiller produces noticeably better output though so we put up with that for proof of the better output see: http://www.integratedcontrolsinc.com/SNAKEO/ (note: case sensitive path) look at the line spacing and the 'circle' in the middle if your results vary it may be because of a newer version than mine Dennis Saputelli Jeff Adolphs wrote: Note: I am using only PDF Writer. For getting the PDF files to go to the folder you want: change the path to the folder even if the correct path looks chosen. I think I have seen the files go to the last folder used instead of what is showing. Acrobat works much better with Protel than AutoCAD. For AutoCAD the problem is worse the plot record files go to the path chosen and the actual PDF files go to the last folder saved to or something like that. I often have to use file search to find the files. Additionally, if you don't look at the printer properties the plot file will be rotated the wrong way more than half the time. Jeff Adolphs Lake Shore Cryotronics, Inc. Westerville, Ohio -- Dennis Saputelli = send only plain text please! - no HTML == ___ Integrated Controls, Inc. www.integratedcontrolsinc.com 2851 21st Streettel: 415-647-0480 San Francisco, CA 94110 fax: 415-647-3003 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] How to make Component Height Rules
Hello All, I have cracked into how to make component height rules, here is how I did it for99SE sp6 I have created virtual components. The virtual component outlines consist of lines drawn on any Mech layer. The first component is as large as my work area. For the first component it is as lage as a C size sheet. This component is named Height 0-100 (HT1). I do the same for more components but the rest may be smaller size ( sometimes custom sizes are required) The next compont is called Height200 (HT2) then next is hieght300 (HT3), etc. This gives me a range to work with, Height 200 allows for a component up to 200 mils.I place these components in the areas that have height restrictions ie bottom side. I use a hybrid naming convention for ICs, Instead of using SOIC-8 my names consist of SO8P1.27W6.2H.42 where Pitch, Max width, and Height information is contained in the footprint information. This allows me to id parts easily. I create several component classes, Class 1 may contain SMD resistors, class2 may contain SO8P1.27W6.2H.42 (SOICs) , Now go into design rules and create placement rules not allowing components classes to overlay virtual components, HT1, HT2, HT3.you need to check the box (multilayer check). It works, another non feature in DXP Did I confuse everyone? Mike Reagan EDSI * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Using DXP with a networked library.
It could also be possible that you actually had two wires going to the same connection location, in which one was right on top of the other for part of the distance. JaMi - Original Message - From: Kiba Dempsey [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Thursday, July 31, 2003 6:13 AM Subject: Re: [PEDA] Using DXP with a networked library. Thanks for your email; this system seems to work well, although it will still take some time to get used to the differences between Protel libraries and DXP. Cheers Kiba -Original Message- From: JaMi Smith [mailto:[EMAIL PROTECTED] Sent: 21 July 2003 09:47 To: Protel EDA Forum Cc: JaMi Smith Subject: Re: [PEDA] Using DXP with a networked library. Kiba This problem has been around for as long as there have been people using CAD Systems to design things. The first part of the answer to the problem is to make sure that everyone references the same Master Library, as opposed to a copy of it which may be residing on a local disk (this eliminates people using obsoleted symbols / parts). The second part of the answer to the problem is not to allow anyone to access the Master Library in anything other than read only mode, excepting the one person who is in charge of keeping the Master Library updated. I would propose that you consider something along the following lines: No one should be able to go into your Master Library at his leisure and add things, or even more worse, edit things. Make the Master Library read only, and set up an Interim Library which can be accessed by anyone, but which contains only new or edited symbols / parts, which need to be checked and approved before being added to the Master Library. New symbols / parts, or editing of existing symbols / parts (which should be accompanied with an appropriate renaming of the part (minimally with a modifier of some type added to the original name, or a totally new name)), should be done in a Local Library (local, as within the database of the design where it is needed), and then submitted to (copied into) the Interim Library for everyone's review, and then when approved they can be placed / replaced in the Master Library by the one person who has control of the it. In this scenario, all work is done in Local Libraries, and the Interim Library is only accessed for as long as people need to copy finished symbols /parts into it from their Local Lobraries (or review symbols / parts copied there by others), and the Master Library only gets accessed by the one person in charge of it, and then only long enough to add what ever needs to be added (or overwrite the old file with an updated version). A Local Library can be easily created within a design database by using the Make Library function in the Design menu. If you delete all symbols / parts from this Local Library excepting that which will become the new ones, the Local Library will be very small and only contain those items which are pending approval. An easy way to make a new symbol / part (or edit an existing one), is to place a similar symbol / part into the design from either the Master Library or the original Altium / Protel Libraries, and then create a Local Library with the Design Make Library function, and then edit that symbol / part as required, including renaming it, and then deleting the original symbol / part from the design, and replacing it with the new symbol / part. Once the symbol / part is placed into the Interim Library, and then finally into the Master Library (after approval), it may be necessary to replace the symbol / part once again with the final version from the Master Library, at which time the Local Library within the database can be deleted. Additionally, you might find it helpful to make all of your standard Altium / Protel Libraries read only (especially where they may reside on users local disks), so that they can not be edited by anyone, and set up a Master Library for your company, and copy things out of the Altium / Protel Libraries and place them into your Master Library for the company on an as you need them basis. This allows you to keep the original Libraries as delivered, and make any appropriate changes you to a symbol / part as you deem necessary for your company's uses, which may include renaming the symbol / part to meet your company's specific needs. This will also allow your company Master Library grow very quickly on an as used basis, with very little extra work. When coupled with a 'look in the Master Library first' policy, this can help create a well organized Master Library which contains only the symbols / parts you have actually used in your designs, and which by default can become your Preferred symbols / parts Library While there are many variations to the above, hopefully the it will give you some food for thought. JaMi - Original Message - From: Kiba Dempsey [EMAIL
[PEDA] Autoreply: How to make Component Height Rules
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Trouble with printing on Acrobat Distiller
Schematic printout in Acrobat save as Protel Schematic.pdf . Se in the same directory you may find that file and then you may rename this. - Original Message - From: Adeel Malik [EMAIL PROTECTED] To: 'Protel EDA Forum' [EMAIL PROTECTED] Sent: Tuesday, August 05, 2003 7:57 AM Subject: [PEDA] Trouble with printing on Acrobat Distiller Hi All, I am having trouble in creating PDF Schematics for the protel 99SE Schematics. When I select Acobat Distiller printer in the 'Print Document' Dialogue, and click on the 'Properties' button to see the path 'where' to save files, I see the path as C:\DocumentSettings\AllUsers\Desktop\*.pdf. But the files don't get copied into this folder. How can I get the files copied into my folder of choice. ? Regards, ADEEL MALIK, * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autoreply: ---- someone set this thing to stop rebroadcasting Au to replies ------
The moderator of this e-mail news/discussion group needs to filter out Auto replies from getting re-broadcast to all of us... this guys piers is in some sort of loop repeating over and over with each e-mail his auto reply sends it auto replies to itself... Bill Brooks The person who says it cannot be done should not interrupt the person doing it. --Chinese Proverb -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: Friday, August 08, 2003 10:52 AM To: [EMAIL PROTECTED] Subject: Re: [PEDA] Autoreply: Autoreply: PCB Copper thickness VS mounted rails. Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PDF Files from Protel 99SE
At 03:13 PM 8/5/2003, Dennis Saputelli wrote: distiller produces noticeably better output though so we put up with that for proof of the better output see: http://www.integratedcontrolsinc.com/SNAKEO/ (note: case sensitive path) look at the line spacing and the 'circle' in the middle if your results vary it may be because of a newer version than mine The PDF Writer version looks bad, *but* I think it is likely that it is a resolution problem. This will be affected to some degree by the PDF Writer settings, as well as, I think, the scale setting when the Protel print process is run. If you set the display for 100% in Acrobat, you can see that the area being examined is quite small. When I pulled the file up, the magnification was over 700%. I don't expect a PDF-Writer file to look accurate at that magnification. Curious, I made a test file with a series of 10 mil tracks, about space 19 mils center-to-center. Not that it matters, the tracks were 171 mils long. If the PDF resolution is set at 300 dpi, I'd expect to see some aliasing, and, sure enough, the print had serious irregularity in the apparent track spacings. The output scale was set at 100%, however, i.e., 1.000. When I set the output scale to 10.000 and viewed the output file, it looked perfect, even at high magnification. So if you are going to use a PDF file, written by PDF writer, and you want to be able to examine fine-scale features, where a grid of 3.33 mils (i.e., 300 dpi) would be a problem, as it will be with most circuit board detail, be sure that the output scale is appropriate to give you output that is not visibly distorted by grid effects. I'd expect that Distiller might have a similar problem, but it might have been set differently. It's also possible that Distiller can generate vector files that Acrobat can read, but that's pure speculation. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: How to make Component Height Rules
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autoplace Issues
Can any one address autoplace settings and/or required rules for a successful autoplacement of a dense population of components on a small footprint. I am having issues with components stacking on each other and/or placing outside boundaries. Any help will be greatly appreciated. Thank you, Tom Sprunger Product Design/ PCB Designer CTS Resistor/Electro 406 Parr Road Berne, IN 46711 (260)589-7191 Fax: (260)589-7591 === Notice: This message is intended solely for the person to whom it is addressed. Unintended recipients will be legally responsible for unauthorized use, disclosure, copying or distribution. If you have received this message in error, please notify the sender immediately by replying to this message. Then delete this message from your system. Thank you. CTS Resistor/Electrocomponents (260) 589-3111 Phone 406 Parr Road (260) 589-3243 Fax Berne, IN 46711 www.ctscorp.com === * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Analysing...
1) You may have a boot sector virus, or perhaps some other wacky software has installed data or code in your master boot record (on the C: drive). Correct, but if you don't have fdisk, the other way to fix the MBR: Install Win right from the CD, when your are given the chance to select a drive to install on, select 'delete partition', create partition, then do a full format, not a quick one. Note: this will KILL everything on your drive. _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: Bagotronix Tech Support [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, August 11, 2003 11:11 AM Subject: Re: [PEDA] Analysing... Choong: My suggestions: 1) You may have a boot sector virus, or perhaps some other wacky software has installed data or code in your master boot record (on the C: drive). Some programs use copy protection schemes that do this - recent versions of Intuit's TurboTax programs do this, and it's caused problems for some of their users. Unfortunately, re-formatting does not necessarily overwrite the master boot record. To do this, you need to use the fdisk.exe program like this fdisk /mbr. I can't recall if you have to supply a drive letter to the fdisk command. Be sure your data is backed up BEFORE you do this. 2) In your PC's, you may have mismatched RAM types. With so many BIOS settings, speeds and types of RAM out there, it's easy to get RAM that is not really the correct type or speed for your PC. I've seen RAM that is marked as PC133 that would not work in PC133 slots, but worked fine in PC100 slots. The memtest86 program (it's free) will tell you how reliable your PC's RAM is. Get it at www.memtest86.com I've used memtest86 to find problems in several PCs that people assumed were software problems. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Choong Keat Yian [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, August 09, 2003 3:50 PM Subject: Re: [PEDA] Analysing... Been there,done that.I even formatted my pc and reinstall it and it still come with those random Error and Fatal Attraction dialoque.Been done with fresh installed WinXP on 3 other different machine too,its all the same.I have tried to use RegClean to do the job too,its all the same.There is no guarantee of the same nature but the style of the problem of crash is the same.I believe in my last call when i reformat my own pc and then run Protel 99SE,well its all the same and i consider my lucky only when for somehow it work till my job finished. Choong [EMAIL PROTECTED] wrote: I would definitely try running Regclean to clean up your windows registry - seems to alleviate most random crashing. You can find it using an internet search. David Watling __ McAfee VirusScan Online from the Netscape Network. Comprehensive protection for your entire computer. Get your free trial today! http://channels.netscape.com/ns/computing/mcafee/index.jsp?promo=393397 Get AOL Instant Messenger 5.1 free of charge. Download Now! http://aim.aol.com/aimnew/Aim/register.adp?promo=380455 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] DRC = disfunctional rule concoction?
Hello fellow designers, I just ran (again) into asomething weird concerning the online DRC of P98SE/SP6. It may I have a general rule stating that the minimum distance between a hole (via or pad) and an SMD-pad must be 8 mils, regardless of net. Handy rule, prevents solder loss during reflow. It even works.:) Now I have a few (SMD) programming pads on the board, to be used with a special connector. No SMD component will ever be fitted onto those pads, so solder loss is no problem. I want to be able to put vias in those pads, so I made a special pad class non-SMD and made all the programming pads a member of that class. Next I made a rule stating that members of pad class non-SMD do not need any clearance to holes (min clearance = 0). Alas, the via and program pad both get a clearance violation ON THE RULE THAT STATES ZERO CLEARANCE ! I know it is that rule, because all other rules (including the solder loss prevention rule) are switched off. Even negative clearances (great or small) produce a violation When I ask what rules apply to these primitives I find that the non-SMD rule DOES apply Clearly there must be something wrong with the understanding or interpretation odf rules, be it mine, Protels' or both. Is there anyone among the expert users who can explain this? As always, any help or insight is greatly appreceated. Leo Potjewijd hardware designer IE Keyprocessor bv. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB Copper thickness VS mounted rails.
Brian, Sorry for the late response, but here goes. The problem with calling out 4 oz. Cu, or even 2 oz. for that matter, is that the board house will probably pattern plate the Cu, and it may not be uniform. There is additionally the problem of etching small traces in the same layer, due to the thickness. Solder, or solder plate (with or without soldermask so that you can put more on), as brought out in an earlier post, is a very very poor design choice, simply because solder will only carry about 16 percent of the current that copper will. You should never rely on solder to carry any current whatsoever. This is why solder is always excluded in any current carrying capacity calculations, whether they be the old MIL STD 275 calculations or charts, or any of the numerous newer ones (the IPC charts are the same as the old 275 charts). Bus bars do offer a solution, as does plain old wire. I would opt for the wider traces, as brought out in one earlier post, and I would distribute the copper on both sides of the board, and stitch it together with a very liberal sprinkling of vias, which should allay your fears about the connections that you bring up below. Remember to account for the size of the vias in your trace width calculations (subtract out the hole size(s) from the width of the trace)). Is it possible that the caps are large enough to have screw type terminals? If so, you could possibly use a wire with a terminal, in addition to the copper traces. Someone also mentioned a 10 - 15 degree C rise in conductor temperature in an earlier post. That is one problem with most current capacity calculators today, is that they start at 10 degrees C, and the fact is that you really do not want to design in a 10 degree C rise in temperature to your product, not to mention 15 degrees C or anything higher. In reality, unless you have a lot of airflow and lots of extra cooling capacity, you really should be designing for something mush less than 10 degrees C for the normal operation of the product. If you get large surges in current that last for any considerable length of time, and you get them often, then maybe it is time to increase your nominal / normal current rating a bit. JaMi - Original Message - From: Brian Guralnick [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, August 08, 2003 10:26 AM Subject: Re: [PEDA] PCB Copper thickness VS mounted rails. One other possibility is to make the board double sided, with 3 Oz foil on each side. This will be easier for them to etch/plate, and paralleling the high current traces on two layers gives the same resistance. I guess this won't work if this is a thermal board to be bonded to a heat sink. Jon I don't like making power supply PCBs with power traces on both sides. Especially with large snap-in caps. It is too difficult to ensure that the top of the PCB under the cap has a good solder to the huge fat traces just like the bottom. I've experienced such designs where power supply sections get a fine odd crackling type noise, which may be mistaken for a bad caps, but it really was fine cracks in the solder on the top layer just under the cap. With a 1 layer board, such a problem is easily caught. _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: Jon Elson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, August 04, 2003 1:59 PM Subject: Re: [PEDA] PCB Copper thickness VS mounted rails. Brian Guralnick wrote: I'm designing a power supply with will have a large ripple current. This power supply will be on it's own PCB and it's 1 layer. Am I better off mounting high current rails, or, increasing the PCB copper thickness from 1oz to something like 4-6oz? The power supply will be 90 vdc, continuous dc current of 4 amps, with current surges ripple current above 15 amps. Check with your PCB vendor on how much the extra thickness of copper will cost you. Then, compare with the rails, including the cost of having the assemblers deal with it. If the 4 or 6 Oz foil will carry the current with acceptable electrical characteristics, it sounds like the best solution, unless the extra cost is prohibitive. My guess is the extra foil thickness will be cheaper than all the extra handling to assemble the whole thing. One other possibility is to make the board double sided, with 3 Oz foil on each side. This will be easier for them to etch/plate, and paralleling the high current traces on two layers gives the same resistance. I guess this won't work if this is a thermal board to be bonded to a heat sink. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum
Re: [PEDA] Analysing...
Mouse software? Choong JaMi Smith [EMAIL PROTECTED] wrote: Not to beat a dead horse, but what are you using for mouse software? - Original Message - From: Choong Keat Yian [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, August 02, 2003 5:49 AM Subject: Re: [PEDA] Analysing... You know , i have have my own confusion both self afflicted and for using Protel.,Since i join this company i has been told to use Protel but the fact is that it seem to me Protel's old and new version do not alleviate anything much other than cosmetic and workaround change as the main sunject matter.Imagine all the feature it got but some is quite unusable for what it intended to be,and i still didnt know why my Protel 99SE with service pack 6 still crash even thought i have 256 mb ram on a Asus board with Pentium 4 at 2.4Ghz.It happen on multiple machines both new and old and i dont think the problem is with the Nvidia's graphic engine. Choong __ McAfee VirusScan Online from the Netscape Network. Comprehensive protection for your entire computer. Get your free trial today! http://channels.netscape.com/ns/computing/mcafee/index.jsp?promo=393397 Get AOL Instant Messenger 5.1 free of charge. Download Now! http://aim.aol.com/aimnew/Aim/register.adp?promo=380455 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE, PCB, disapearing connectionlines
Only unrouted nets are shown. A net that is routed is does not have its ratsnest shown Is the PCB routed or unrouted? Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Analysing...
All were use and tested on Win98 and WinXP.Btw i found out some problem with Protel 99SE Autorouter too this few days for the result is that it isnt working to way it should be.Imagine when i purposely use it to route a double sided high density small PCB and when i change its rules to route the same board in single sided mode,the copper tracks got shorted and crossed to each other and yet it said this is 100% routed! ,this is not something that should happen as our work is quite tedious and confusing at times so its like adding salt to wound. Choong Brad Velander [EMAIL PROTECTED] wrote: Still running Win98 as you had stated in your earlier messages? That would be the most common reason for your crashes if you are still running Win98. 99SE SP6 will run quite stably on WIN2000 Pro. Pretty stable NT4. Sincerely, Brad Velander -Original Message- From: Choong Keat Yian [mailto:[EMAIL PROTECTED] Sent: Sat 02/08/2003 5:49 AM To: Protel EDA Forum Cc: Subject: Re: [PEDA] Analysing... You know , i have have my own confusion both self afflicted and for using Protel.,Since i join this company i has been told to use Protel but the fact is that it seem to me Protel's old and new version do not alleviate anything much other than cosmetic and workaround change as the main sunject matter.Imagine all the feature it got but some is quite unusable for what it intended to be,and i still didnt know why my Protel 99SE with service pack 6 still crash even thought i have 256 mb ram on a Asus board with Pentium 4 at 2.4Ghz.It happen on multiple machines both new and old and i dont think the problem is with the Nvidia's graphic engine. Choong __ McAfee VirusScan Online from the Netscape Network. Comprehensive protection for your entire computer. Get your free trial today! http://channels.netscape.com/ns/computing/mcafee/index.jsp?promo=393397 Get AOL Instant Messenger 5.1 free of charge. Download Now! http://aim.aol.com/aimnew/Aim/register.adp?promo=380455 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 99SE, PCB, disapearing connectionlines
On 07:13 PM 5/08/2003, Kulajew Waldemar said: -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED] Is the PCB routed or unrouted? Ian, we got it routed, but for a redesign we unrouted some nets and, after the problem apeares, we unrouted all nets for test. So yes, all nets are unrouted. But while you ask. The first version of the PCB (the converted) did not show any pads for some reason. They apeared after we replaced the old footprint by our new ones. Thanks for fighting by my side still fighting Waldemar Try Saving-As an ASCII file and then re-loading. This can clear some issues, don't know about this one though. If you like you can email me the (zipped DDB) and I will see what I make of it. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autoreply: Autoreply: Autoreply: Discovery - LAN Network pasue hiccup patch.
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Out of Office Notice
From 11.8.2003 to 28.8.2003 i'm on holidays. I will be back on Friday the 29.8.2003. Andreas Lipowsky Lipowsky Industrie-Elektronik GmbH 64291 Darmstadt, Roemerstr. 57 Telefon: +49-(0)6151-93591-0 Telefax: +49-(0)6151-93591-28 Homepage: http://www.lipowsky.de DIN EN ISO 9001:2000 certified by DQS * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autoreply: Discovery - LAN Network pasue hiccup patch.
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Discovery - LAN Network pasue hiccup patch.
-Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED] Sent: Friday, August 08, 2003 7:16 PM To: Protel EDA Forum Subject: Re: [PEDA] Discovery - LAN Network pasue hiccup patch. As far as I am aware the 'free' version of ZA is only licenced for 'home' or 'non' commercial use. At my last SW audit I had to remove it from several machines at work and replace it with ZA pro [paid] licenses. The choice is yours but i would read the SLA. @'!#%$'[EMAIL PROTECTED]'#!#* --- Thanks a million... Ok, are there any good freeware firewalls which actually are freeware. Brian If you only want to use it to stop Protel broadcast traffic you can also use the ip policies within W2k to block the ports its uses (get info from ZA before you de-install it) Did you try the setting sin the ini file to stop the traffic? If you need it for other purposes I do not know any good freebies for commercial use. But ZA or Sygate are not that expensive to deploy on one workstation. Gateways or bridges are a different matter ... Best Regards John A. Ross RSD Communications ltd Email [EMAIL PROTECTED] WWWhttp://www.rsd.tv == _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: John Ross [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Monday, August 04, 2003 6:50 PM Subject: Re: [PEDA] Discovery - LAN Network pasue hiccup patch. From: Brian Guralnick [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Subject: [PEDA] Discovery - LAN Network pasue hiccup patch. Date: Mon, 04 Aug 2003 13:22:58 -0400 I found a surprising fix for my Protel's occasional LAN network pause hiccups. I now use the firewall freeware version of ZoneAlarm on all of my PC on my network. ZoneAlarm's web site - www.zonelabs.com ZoneAlarm's freeware version - http://www.zonelabs.com/store/content/company/products/znalm/ freeDownlo ad.j sp?lid=zadb_zadown CAREFUL, not the trial version, the free version. The trial version has 2-3 added features over the freeware version, but it will die, or you'll need to pay for it. The free version works indefinitely. Brian As far as I am aware the 'free' version of ZA is only licenced for 'home' or 'non' commercial use. At my last SW audit I had to remove it from several machines at work and replace it with ZA pro [paid] licenses. The choice is yours but i would read the SLA. Also as someone pointed out before on these lists (not me, just cannot remeber who) there is an option in the client99se.ini file for Broadcast Access Code = True/False Receive Access Code = True/False I assume setting these to false will kill the need for network traffic (if the executables take any notice of these lines in the ini anyway), unless the wise developers at Protel do not want this feature disabled, which IMO was the reason to remove the user selectable check boxes in Licencing for broadcast/receive from the earlier 99SE builds (sp3 and later). Best regards John _ Stay in touch with absent friends - get MSN Messenger http://www.msn.co.uk/messenger * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Analysing...
I think I might know what's going on. Can you try something for me? Make your .swp file 3080mb and see what happens. _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: Choong Keat Yian [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, August 09, 2003 3:45 PM Subject: Re: [PEDA] Analysing... Mouse software? Choong JaMi Smith [EMAIL PROTECTED] wrote: Not to beat a dead horse, but what are you using for mouse software? - Original Message - From: Choong Keat Yian [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, August 02, 2003 5:49 AM Subject: Re: [PEDA] Analysing... You know , i have have my own confusion both self afflicted and for using Protel.,Since i join this company i has been told to use Protel but the fact is that it seem to me Protel's old and new version do not alleviate anything much other than cosmetic and workaround change as the main sunject matter.Imagine all the feature it got but some is quite unusable for what it intended to be,and i still didnt know why my Protel 99SE with service pack 6 still crash even thought i have 256 mb ram on a Asus board with Pentium 4 at 2.4Ghz.It happen on multiple machines both new and old and i dont think the problem is with the Nvidia's graphic engine. Choong __ McAfee VirusScan Online from the Netscape Network. Comprehensive protection for your entire computer. Get your free trial today! http://channels.netscape.com/ns/computing/mcafee/index.jsp?promo=393397 Get AOL Instant Messenger 5.1 free of charge. Download Now! http://aim.aol.com/aimnew/Aim/register.adp?promo=380455 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autoreply: Autoreply: Autoreply: ---- someone set this thing to stop rebroadcasting Au to replies ------
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Analysing...
No, i dont think that its the mouse as my experience with 99SE is from Win98SE fresh installation and other existing pcs and also with original licensed WinXP,none of them use tablets but only normal mouse of differing brands,so i am still waiting for some miracle answer to this mystery. Choong [EMAIL PROTECTED] wrote: I can confirm that some mouse software will screw things. I removed the Alps touchpad mouseware from my laptop and got much better behaviour, not only from Protel. It was so bad that on occasions the mouse cursor would just fly about the screen on its own, opening applications as it went... like something from the Exorcist! Robert __ McAfee VirusScan Online from the Netscape Network. Comprehensive protection for your entire computer. Get your free trial today! http://channels.netscape.com/ns/computing/mcafee/index.jsp?promo=393397 Get AOL Instant Messenger 5.1 free of charge. Download Now! http://aim.aol.com/aimnew/Aim/register.adp?promo=380455 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
Brad Velander wrote: John, could the difference come in with which point you started drawing your wire? Starting at the resistor pin or starting from the other connection first? Just a thought. One would have to see exactly how you wired to or past that pin to understand exactly how you are getting the results that you got. Well, the problem is that breaks in an otherwise straight line are not displayed in a schematic. If you lay a crossing wire directly across a break in a wire, it forms a connection. With auto-junction on, a dot appears to warn you of that connection. But, the junction dot is not what CAUSES the connection, it is just a flag that a connection has been made. Some other software automatically REMOVES any breaks in straight lines as they are laid down. Protel doesn't. As well I always work with the auto junction on and have never turned it off. But doesn't the autojunction just aid in making junctions, it doesn't exclude making junctions. It really doesn't aid in making junctions, it MARKS them. The only place it actually makes a connection is when you manually place a dot on two intersecting and unbroken wire lines. Using ERC is still the only way to check a schematic, especially for missed/misplaced pin connections. Yes, but the ERC may not pick up all cases of unintended crossed nets. If one of them is unnamed, and doesn't violate an input/output rule (passive, perhaps) it would not cause an error. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autoreply: Autoreply: Autoreply: How to make Component Height Rules
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DRC = disfunctional rule concoction?
Leo, to the best of my knowledge or recollection P99SE does not support negative clearances in rules. As well, a zero clearance will allow for everything up to but not including touching. So in P99SE there is no manner by which you can do a rule that allows overlap or touching without generating a violation. The only option would to have no rule but this will only work in some limited cases as well. Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com -Original Message- From: Leo Potjewijd [mailto:[EMAIL PROTECTED] Sent: Wednesday, August 13, 2003 9:12 AM To: [EMAIL PROTECTED] Subject: [PEDA] DRC = disfunctional rule concoction? Hello fellow designers, I just ran (again) into asomething weird concerning the online DRC of P98SE/SP6. It may I have a general rule stating that the minimum distance between a hole (via or pad) and an SMD-pad must be 8 mils, regardless of net. Handy rule, prevents solder loss during reflow. It even works.:) Now I have a few (SMD) programming pads on the board, to be used with a special connector. No SMD component will ever be fitted onto those pads, so solder loss is no problem. I want to be able to put vias in those pads, so I made a special pad class non-SMD and made all the programming pads a member of that class. Next I made a rule stating that members of pad class non-SMD do not need any clearance to holes (min clearance = 0). Alas, the via and program pad both get a clearance violation ON THE RULE THAT STATES ZERO CLEARANCE ! I know it is that rule, because all other rules (including the solder loss prevention rule) are switched off. Even negative clearances (great or small) produce a violation When I ask what rules apply to these primitives I find that the non-SMD rule DOES apply Clearly there must be something wrong with the understanding or interpretation odf rules, be it mine, Protels' or both. Is there anyone among the expert users who can explain this? As always, any help or insight is greatly appreceated. Leo Potjewijd hardware designer IE Keyprocessor bv. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Analysing...
Choong: My suggestions: 1) You may have a boot sector virus, or perhaps some other wacky software has installed data or code in your master boot record (on the C: drive). Some programs use copy protection schemes that do this - recent versions of Intuit's TurboTax programs do this, and it's caused problems for some of their users. Unfortunately, re-formatting does not necessarily overwrite the master boot record. To do this, you need to use the fdisk.exe program like this fdisk /mbr. I can't recall if you have to supply a drive letter to the fdisk command. Be sure your data is backed up BEFORE you do this. 2) In your PC's, you may have mismatched RAM types. With so many BIOS settings, speeds and types of RAM out there, it's easy to get RAM that is not really the correct type or speed for your PC. I've seen RAM that is marked as PC133 that would not work in PC133 slots, but worked fine in PC100 slots. The memtest86 program (it's free) will tell you how reliable your PC's RAM is. Get it at www.memtest86.com I've used memtest86 to find problems in several PCs that people assumed were software problems. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: Choong Keat Yian [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Saturday, August 09, 2003 3:50 PM Subject: Re: [PEDA] Analysing... Been there,done that.I even formatted my pc and reinstall it and it still come with those random Error and Fatal Attraction dialoque.Been done with fresh installed WinXP on 3 other different machine too,its all the same.I have tried to use RegClean to do the job too,its all the same.There is no guarantee of the same nature but the style of the problem of crash is the same.I believe in my last call when i reformat my own pc and then run Protel 99SE,well its all the same and i consider my lucky only when for somehow it work till my job finished. Choong [EMAIL PROTECTED] wrote: I would definitely try running Regclean to clean up your windows registry - seems to alleviate most random crashing. You can find it using an internet search. David Watling __ McAfee VirusScan Online from the Netscape Network. Comprehensive protection for your entire computer. Get your free trial today! http://channels.netscape.com/ns/computing/mcafee/index.jsp?promo=393397 Get AOL Instant Messenger 5.1 free of charge. Download Now! http://aim.aol.com/aimnew/Aim/register.adp?promo=380455 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
At 05:09 AM 8/14/2003, Edi Im Hof wrote: It's also a good idea to set the ERC a bit tighter. [...] On intentionally left open pins, I place a no erc mark on it. Keystrokes p-i-n, witch is easy to remember because you'll place them on a pin. I have found quite a lot of schematic errors this way. I'd like to underscore this. Especially when one is new to Protel, and is faced with a host of mostly phoney errors, it's tempting to set the ERC to tolerate open pins and type incompatibilities. And it's a bad idea. As to unconnected pins, when you deliberately leave a pin open, it is very simple to place a No-ERC directive on it. You'll never have to look at it again. And if you forget to do this, you'll get a warning and you can quickly and easily fix it. The large majority of schematic errors leave an unconnected pin. Years ago, designing with mylar and tape, I had an engineer who used to take a design and quickly go over it for unconnected pins. Even on a complex multilayer design (complex for those days might have meant 6 layers), it was easy to see this. And then he'd make sure that they were all properly unconnected. He'd find the bulk of errors very quickly with this As to other errors, many types of pin type combinations will generate an error with the default matrix. The best solution may be to fix the pin types, i.e., make, for example, a connector pin be an input or an output or passive instead of I/O, which doesn't like to be connected to an output. But this is not always practical. so, once again, it's simple to place No-ERC directives, though in this case I'd wait until running the first ERC. If it is easy to understand why an error is popping up, it may be relatively safe to suppress it with No-ERC, but if it is at all unclear, the safe path is to figure out why the error is happening. You might just find an error. And once you know, and it is not practical to fix it -- i.e., the error is purely formal -- then it should be suppressed. It only takes minutes at most to deal with even a host of connector pins. The goal is to generate a clean ERC report. Ideally, No-ERC markers would not be used, but practical reasons make us very glad that the primitive exists: at least we have made a conscious decision that a particular error or warning can be disregarded, and the markers allow us to avoid having to make this decision with every revision of the schematic. The cost of a schematic error can be very high, both in terms of money and in time-to-market, so it's worth the effort to learn to use the error-checking tools to best advantage. In the end, it's easy, the difficulty is only in the beginning It's too bad that Protel 99SE does not have editable pin types at the schematic level: Tango DOS allowed this (In Protel, pin types are only editable in the Library editor.) What I'd have liked to see would have been a symbol attribute that is Allow Pin Electrical Type Edits. If checked in the library, the pin types would be editable at the schematic level. If not, they'd be locked. So a connector symbol, generally, would have editable pin types. And then the error checking could get even better. I'd also like to have a way to quickly see the pin type of a pin. (Again, this was easy in Tango DOS). Has any of this been done in DXP? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Non standard pad shapes in 99se
I am creating a pcb foot-print for an MLP-11 package. The '11'th pin is defined as a large area under the package with 4 contact pads on the edge. What is the procedure for creating the irregular shaped area as a pin?? Thanks Ralph Garvin Design Engineer Rycom Instruments, Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Non standard pad shapes in 99se
At 05:34 PM 8/14/2003, Ralph Garvin wrote: I am creating a pcb foot-print for an MLP-11 package. The '11'th pin is defined as a large area under the package with 4 contact pads on the edge. What is the procedure for creating the irregular shaped area as a pin?? Protel doesn't directly support more than a very few shapes for pads. The workaround is to create a complex pad shape by adding line or fill primitives to a pad in the footprint. You can use pretty much any size pad as the pad itself, as long as it is smaller than the desired final area; it will be buried in that area. Since it is a surface mount part, there is no complication involving hole location. You also need to add primitives to the solder mask layer, if the pad is to be free of solder mask. There is a small complication in that the additional copper may not be assigned its net properly, if this is so, you'll see it with error indicators or in a DRC. It may be necessary to run the tool that assigns nets to primitives by connection to pads, or to manually edit the primitives to the net, possibly with a global edit -- and for this, the footprint may need to be unlocked temporarily (never leave footprints unlocked!). * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
At 11:44 13.08.2003 -0700, you wrote: John, could the difference come in with which point you started drawing your wire? Starting at the resistor pin or starting from the other connection first? Just a thought. One would have to see exactly how you wired to or past that pin to understand exactly how you are getting the results that you got. As well I always work with the auto junction on and have never turned it off. But doesn't the autojunction just aid in making junctions, it doesn't exclude making junctions. Using ERC is still the only way to check a schematic, especially for missed/misplaced pin connections. It's also a good idea to set the ERC a bit tighter. I marked all unconnected pins as a warning, except for the power pin, witch is an error. On intentionally left open pins, I place a no erc mark on it. Keystrokes p-i-n, witch is easy to remember because you'll place them on a pin. I have found quite a lot of schematic errors this way. This would have found your unconnected passive pin of the pullup. Do you have other things connected to the power port witch should be connected to the pull up? If no, this should definitly be marked as an error. Edi Im Hof Sincerely, Brad Velander. Lead PCB Designer Norsat International Inc. Microwave Products Tel (604) 292-9089 (direct line) Fax (604) 292-9010 email: [EMAIL PROTECTED] http://www.norsat.com -Original Message- From: John Branthoover [mailto:[EMAIL PROTECTED] Sent: Wednesday, August 13, 2003 11:10 AM To: Protel EDA Forum Subject: [PEDA] Unacceptable Bug in Protel 99 SE SP6..! Hello All, I have a schematic of a board that I just had fabricated. When I drew the schematic, I did so with the Auto-Junction feature turned off. I always draw schematics like this because of problems that I have had in the past with the Auto-Junction feature placing junctions where I don t want them. During testing of the new board, my boss brought me the schematics asking why I failed to attach one end of a pull-up resistor to the +5 volt supply. I had simply forgot to place a junction at the point where the wires intersected. My mistake. In looking at the board, the connection was made. I ran a netlist. It showed that the connection was made. How can this be? I added the junction, created another netlist. The netlist showed that the connection was still made, as expected. I then deleted the dot, created another netlist. The connection was still there. The only way that I could remove the connection was to delete the wires and redraw them. After that the schematic started to behave as expected. No junction, no connection. I also tried the procedure on other junctions on the same schematic page. I could not reproduce the error. I have no idea how this error (bug) originally happened. It has made me loose all faith in Protel s schematic capture side. Has anyone else seen this behavior? How can I deal with this problem without checking the entire netlist before I bring it over to the PCB? Argh! Looks like it is time to start looking for a new PCB design software. Beware and good luck. John Branthoover: Electrical Design Engineer : Acutronic R D:Phone (412) 968-1051 640 Alpha Drive :Fax(412) 963-0816 Pittsburgh PA 15238 :Email [EMAIL PROTECTED] USA :WEBhttp://www.acutronic.com + IH electronic+ Phone: ++41 52 320 90 00 + + Edi Im Hof + Fax: ++41 52 320 90 04 + + Doernlerstrasse 1, Sulz + URL: http://www.ihe.ch + + CH-8544 Rickenbach-Attikon + E-Mail: [EMAIL PROTECTED] + + Switzerland + + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
I have been designing some bus-based cards (with a processor card, and other peripheral cards), and have the problem that on many of the other cards, the address signals (in particular) have no outputs (they come from the processor card). This causes lots of Unconnected Input Pin type errors (I can't remember the exact wording). While I can live with that, I worry that I'll miss a _real_ error in the mass of spurious ones. Any suggestions on a robust solution, not based on No-ERC directives? Cheers, Damon Kelly Hardware Engineer -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED] Sent: Friday, 15 August 2003 07:03 To: Protel EDA Forum Subject: Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..! At 05:09 AM 8/14/2003, Edi Im Hof wrote: It's also a good idea to set the ERC a bit tighter. [...] On intentionally left open pins, I place a no erc mark on it. Keystrokes p-i-n, witch is easy to remember because you'll place them on a pin. I have found quite a lot of schematic errors this way. I'd like to underscore this. Especially when one is new to Protel, and is faced with a host of mostly phoney errors, it's tempting to set the ERC to tolerate open pins and type incompatibilities. And it's a bad idea. As to unconnected pins, when you deliberately leave a pin open, it is very simple to place a No-ERC directive on it. You'll never have to look at it again. And if you forget to do this, you'll get a warning and you can quickly and easily fix it. The large majority of schematic errors leave an unconnected pin. Years ago, designing with mylar and tape, I had an engineer who used to take a design and quickly go over it for unconnected pins. Even on a complex multilayer design (complex for those days might have meant 6 layers), it was easy to see this. And then he'd make sure that they were all properly unconnected. He'd find the bulk of errors very quickly with this As to other errors, many types of pin type combinations will generate an error with the default matrix. The best solution may be to fix the pin types, i.e., make, for example, a connector pin be an input or an output or passive instead of I/O, which doesn't like to be connected to an output. But this is not always practical. so, once again, it's simple to place No-ERC directives, though in this case I'd wait until running the first ERC. If it is easy to understand why an error is popping up, it may be relatively safe to suppress it with No-ERC, but if it is at all unclear, the safe path is to figure out why the error is happening. You might just find an error. And once you know, and it is not practical to fix it -- i.e., the error is purely formal -- then it should be suppressed. It only takes minutes at most to deal with even a host of connector pins. The goal is to generate a clean ERC report. Ideally, No-ERC markers would not be used, but practical reasons make us very glad that the primitive exists: at least we have made a conscious decision that a particular error or warning can be disregarded, and the markers allow us to avoid having to make this decision with every revision of the schematic. The cost of a schematic error can be very high, both in terms of money and in time-to-market, so it's worth the effort to learn to use the error-checking tools to best advantage. In the end, it's easy, the difficulty is only in the beginning It's too bad that Protel 99SE does not have editable pin types at the schematic level: Tango DOS allowed this (In Protel, pin types are only editable in the Library editor.) What I'd have liked to see would have been a symbol attribute that is Allow Pin Electrical Type Edits. If checked in the library, the pin types would be editable at the schematic level. If not, they'd be locked. So a connector symbol, generally, would have editable pin types. And then the error checking could get even better. I'd also like to have a way to quickly see the pin type of a pin. (Again, this was easy in Tango DOS). Has any of this been done in DXP? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
I have read all the replies on this topic and though I do follow the same practice as Edi Im Hof, and, like, many others, I leave auto-junction on, I have some sympathy to John Branthoover. The interactions between autojunction and abutted co-linear lines has always been a problem in P99SE - it leaves stray autojunction hot spots around the design. But John seems to have a different problem. If as John Elson points out, the presence of the auto-junction is essentially visual where you have a wire crossing abutted wire - then this is a problem. If I understand John E. correctly he is saying that if you have the conditions for an autojunction but you don't have the autojunction there (either autojunction is not enabled or you delete the junction), you may still have the connection in some circumstances. This is a pretty dangerous situation - it is interesting though that it has not come up a lot over the last 4 year. Leaving autojunction enabled will help. At least then you may see stray connections - if you or a reviewer happens to notice them. (DXP comment - DXP offers some help here. Firstly wire segments have little graphical details to show where they end. So if you do have two abutting wire segments you can see this little detail. Secondly, there is an option to optimise wires - this option will merge co-linear abutted line segments. This optimise option also offers a nice feature where is you drop a two wire component onto a wire the wire will be split into two nets at the two pins (you can drop in a series resistor, for example easily. As near as I can figure, after discussing this issue of merging line segments for years, the optimise function was added to DXP after I pointed out that you could draw a wire on a DXP sample schematic between two particular points and end up with stray auto-junction hot spots. I am not sure why but it seemed that the discussion in PEDA about this issue for years had not quite managed to make it into the required DXP feature list. Only after the problem was easily demonstrated in a Altium sample Sch did it become apparent why something should be done.) Hey John B. - if you do evaluate alternative packages why don't you report here. Especially after a few projects on the new one. Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
John I have never seen the behaviour you describe with autojunction. I always have it turned on, never a problem. Only issues I can remember seeing in the list was a large thread on the issue of 4 point connections (bad practice anyway). This was not directly related to having a 4 point connection, but the issue was raised where the actual correct behaviour of the autojucntion feature caused a connectivity issue (but a short, not an open as in your case) where a wire has been drawn so far then stopped, then an additional wire had been added from its endpoint to its destination. Technically there is a junction there at the end nodes of where the 2 wires meet, but no need to see it, so Protel keeps it hidden, just like the connection from your wire or power port to the pull-up. But another wire placed across that node at 90 deg WILL create an autojunction (short). So a very rare case for having autojunction disabled, but only to enable the use of a bad practice anyway. In any event the ERC has always flagged this as an error, if the nets have been named, or the pin types are incompatible, but if all the pins were drawn passive, and no nets named, then it's a problem.. But with what you describe below I do not think that your SCH is the issue as you have seen the generated netlist for yourself and it was correct. Perhaps an import to PCB or synchroniser issue in this case where your PCB netlist was not updated correctly is more likely, hence the reason you cannot reproduce it while working on the SCH area alone. Did you run a batch DRC after completing the board? Just some ideas, I would not lose faith in Protel over this one instance. Best Regards John A. Ross RSD Communications Ltd 8 BorrowMeadow Road Springkerse Industrial Estate Stirling, Scotland FK7 7UW Tel +44 [0]1786 450572 Ext 225 (Office) Tel +44 [0]1786 450572 Ext 248 (Lab) Fax +44 [0]1786 474653 GSM +44 [0]7831 373727 Email [EMAIL PROTECTED] WWW http://www.rsd.tv == -Original Message- From: John Branthoover [mailto:[EMAIL PROTECTED] Sent: Wednesday, August 13, 2003 7:10 PM To: Protel EDA Forum Subject: [PEDA] Unacceptable Bug in Protel 99 SE SP6..! Hello All, I have a schematic of a board that I just had fabricated. When I drew the schematic, I did so with the Auto-Junction feature turned off. I always draw schematics like this because of problems that I have had in the past with the Auto-Junction feature placing junctions where I don t want them. During testing of the new board, my boss brought me the schematics asking why I failed to attach one end of a pull-up resistor to the +5 volt supply. I had simply forgot to place a junction at the point where the wires intersected. My mistake. In looking at the board, the connection was made. I ran a netlist. It showed that the connection was made. How can this be? I added the junction, created another netlist. The netlist showed that the connection was still made, as expected. I then deleted the dot, created another netlist. The connection was still there. The only way that I could remove the connection was to delete the wires and redraw them. After that the schematic started to behave as expected. No junction, no connection. I also tried the procedure on other junctions on the same schematic page. I could not reproduce the error. I have no idea how this error (bug) originally happened. It has made me loose all faith in Protel s schematic capture side. Has anyone else seen this behavior? How can I deal with this problem without checking the entire netlist before I bring it over to the PCB? Argh! Looks like it is time to start looking for a new PCB design software. Beware and good luck. John Branthoover: Electrical Design Engineer : Acutronic R D:Phone (412) 968-1051 640 Alpha Drive :Fax(412) 963-0816 Pittsburgh PA 15238 :Email [EMAIL PROTECTED] USA :WEBhttp://www.acutronic.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
On 07:02 AM 15/08/2003, Abd ul-Rahman Lomax said: It's too bad that Protel 99SE does not have editable pin types at the schematic level: Tango DOS allowed this (In Protel, pin types are only editable in the Library editor.) What I'd have liked to see would have been a symbol attribute that is Allow Pin Electrical Type Edits. If checked in the library, the pin types would be editable at the schematic level. If not, they'd be locked. So a connector symbol, generally, would have editable pin types. And then the error checking could get even better. I'd also like to have a way to quickly see the pin type of a pin. (Again, this was easy in Tango DOS). Early versions of Protel did. It was removed as part of a push to make more robust library management I think. Can't recall the details. DXP allows the pin types to be edited on the Sch (per instance). This is very useful for FPGA and large CPLDs and micros where the pins are programmable and you don't know the use when designing the symbol in the Sch Lib. Editing a component (dbl clicking to bring up the Component Properties dialog, has an Edit Pins button that bring up a grid showing details of all the pins, can sort by columns etc. Also the List panel will show pin details if a suitable selection is current.) Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
John Branthoover wrote: Hello All, I have a schematic of a board that I just had fabricated. When I drew the schematic, I did so with the Auto-Junction feature turned off. I always draw schematics like this because of problems that I have had in the past with the Auto-Junction feature placing junctions where I don t want them. During testing of the new board, my boss brought me the schematics asking why I failed to attach one end of a pull-up resistor to the +5 volt supply. I had simply forgot to place a junction at the point where the wires intersected. My mistake. In looking at the board, the connection was made. I ran a netlist. It showed that the connection was made. How can this be? This is an artifact of the schematic rules. In fact, that's why the auto-junction feature is there, I think. Any time there is a wire segment with vertices on some point, and another wire segment that either passes through the same point, or has a vertex at that point, these are considered connected, whether there is a junction dot shown or not. The rules are this way so that two wire segments that are in a straight line are connected, as you'd have no way to tell there was a break in the wire. The auto-junction only places a junction dot where a wire segment terminates ON another wire, so it is really just an INDICATOR of the connection, not the thing that CAUSES the connection. The real usefulness of the auto-junctions is that it SHOWS were an unintended connection may have been made. And, clicking and deleting the junction dot will NOT remove the connection, except in one special case. If you have two wires that cross without there being any vertex at the crossing point, and you place or remove a junction dot there, the dot DOES control the connectivity. I added the junction, created another netlist. The netlist showed that the connection was still made, as expected. I then deleted the dot, created another netlist. The connection was still there. The only way that I could remove the connection was to delete the wires and redraw them. After that the schematic started to behave as expected. No junction, no connection. I also tried the procedure on other junctions on the same schematic page. I could not reproduce the error. Yes, you need to have a break in the wire segments at the crossing point. That break, without auto-junction, is totally INVISIBLE - and, of course, that IS the danger there! I have no idea how this error (bug) originally happened. It has made me loose all faith in Protel s schematic capture side. Has anyone else seen this behavior? How can I deal with this problem without checking the entire netlist before I bring it over to the PCB? Argh! No, don''t lose faith in the package. Protel (and Accel's Tango) has ALWAYS behaved this way, it has worked like this for 15 years or more. The auto-junction feature, when left on, almost removes the danger of this. But, you have to understand the behavior of every program you use, and know the pitfalls. EVERY program has a few pitfalls. This particular one is something I've known about for many years, and since the auto-junction feature, it is not really a problem. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB Copper thickness VS mounted rails.
The problem with calling out 4 oz. Cu, or even 2 oz. for that matter, is that the board house will probably pattern plate the Cu, and it may not be uniform. There is additionally the problem of etching small traces in the same layer, due to the thickness. My PCB house says that their process is a positive growth of copper, not an etch process. Is this your described pattern plate? When you say not uniform, how much error can I expect? Will it matter with traces from 50 mil to 500 mil. My PCB does not have any fine traces. It's a pure CMOS class A audio amp and power supply. 3-4 traces are 25 mil wide (audio in), everything else is at least 50 mil wide, mostly 250 mil wide. _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: JaMi Smith [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Cc: JaMi Smith [EMAIL PROTECTED] Sent: Thursday, August 14, 2003 2:44 PM Subject: Re: [PEDA] PCB Copper thickness VS mounted rails. Brian, Sorry for the late response, but here goes. The problem with calling out 4 oz. Cu, or even 2 oz. for that matter, is that the board house will probably pattern plate the Cu, and it may not be uniform. There is additionally the problem of etching small traces in the same layer, due to the thickness. Solder, or solder plate (with or without soldermask so that you can put more on), as brought out in an earlier post, is a very very poor design choice, simply because solder will only carry about 16 percent of the current that copper will. You should never rely on solder to carry any current whatsoever. This is why solder is always excluded in any current carrying capacity calculations, whether they be the old MIL STD 275 calculations or charts, or any of the numerous newer ones (the IPC charts are the same as the old 275 charts). Bus bars do offer a solution, as does plain old wire. I would opt for the wider traces, as brought out in one earlier post, and I would distribute the copper on both sides of the board, and stitch it together with a very liberal sprinkling of vias, which should allay your fears about the connections that you bring up below. Remember to account for the size of the vias in your trace width calculations (subtract out the hole size(s) from the width of the trace)). Is it possible that the caps are large enough to have screw type terminals? If so, you could possibly use a wire with a terminal, in addition to the copper traces. Someone also mentioned a 10 - 15 degree C rise in conductor temperature in an earlier post. That is one problem with most current capacity calculators today, is that they start at 10 degrees C, and the fact is that you really do not want to design in a 10 degree C rise in temperature to your product, not to mention 15 degrees C or anything higher. In reality, unless you have a lot of airflow and lots of extra cooling capacity, you really should be designing for something mush less than 10 degrees C for the normal operation of the product. If you get large surges in current that last for any considerable length of time, and you get them often, then maybe it is time to increase your nominal / normal current rating a bit. JaMi - Original Message - From: Brian Guralnick [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Friday, August 08, 2003 10:26 AM Subject: Re: [PEDA] PCB Copper thickness VS mounted rails. One other possibility is to make the board double sided, with 3 Oz foil on each side. This will be easier for them to etch/plate, and paralleling the high current traces on two layers gives the same resistance. I guess this won't work if this is a thermal board to be bonded to a heat sink. Jon I don't like making power supply PCBs with power traces on both sides. Especially with large snap-in caps. It is too difficult to ensure that the top of the PCB under the cap has a good solder to the huge fat traces just like the bottom. I've experienced such designs where power supply sections get a fine odd crackling type noise, which may be mistaken for a bad caps, but it really was fine cracks in the solder on the top layer just under the cap. With a 1 layer board, such a problem is easily caught. _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: Jon Elson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, August 04, 2003 1:59 PM Subject: Re: [PEDA] PCB Copper thickness VS mounted rails. Brian Guralnick wrote: I'm designing a power supply with will have a large ripple current. This power supply will be on it's own PCB and it's 1 layer. Am I better off mounting high current rails, or, increasing the PCB copper thickness from 1oz to something like 4-6oz? The power supply will be 90 vdc, continuous dc current of 4 amps, with current surges ripple current above 15
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
This is very good practice. I do exactly the same thing. You can set up your printing not to print the ERC directive markers. It provides a very robust check for unintentionally unconnected pins. I also keep the autojunction turned on, but that does mean that I have to be careful not to run wires across valid connection nodes. Phil. -Original Message- From: Edi Im Hof [mailto:[EMAIL PROTECTED] Sent: Thursday, 14 August 2003 6:40 PM To: Protel EDA Forum Subject: Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..! It's also a good idea to set the ERC a bit tighter. I marked all unconnected pins as a warning, except for the power pin, witch is an error. On intentionally left open pins, I place a no erc mark on it. Keystrokes p-i-n, witch is easy to remember because you'll place them on a pin. I have found quite a lot of schematic errors this way. This would have found your unconnected passive pin of the pullup. Do you have other things connected to the power port witch should be connected to the pull up? If no, this should definitly be marked as an error. Edi Im Hof * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..!
Don't you show the connectors leading to the bus? Wouldn't they be the source of the address on your peripheral cards and therefore you shouldn't have any Unconnected Input Pins? On Fri, 15 Aug 2003 08:49:02 +1000, Damon Kelly wrote: I have been designing some bus-based cards (with a processor card, and other peripheral cards), and have the problem that on many of the other cards, the address signals (in particular) have no outputs (they come from the processor card). This causes lots of Unconnected Input Pin type errors (I can't remember the exact wording). While I can live with that, I worry that I'll miss a _real_ error in the mass of spurious ones. Any suggestions on a robust solution, not based on No-ERC directives? Cheers, Damon Kelly Hardware Engineer -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED] Sent: Friday, 15 August 2003 07:03 To: Protel EDA Forum Subject: Re: [PEDA] Unacceptable Bug in Protel 99 SE SP6..! At 05:09 AM 8/14/2003, Edi Im Hof wrote: It's also a good idea to set the ERC a bit tighter. [...] On intentionally left open pins, I place a no erc mark on it. Keystrokes p-i-n, witch is easy to remember because you'll place them on a pin. I have found quite a lot of schematic errors this way. I'd like to underscore this. Especially when one is new to Protel, and is faced with a host of mostly phoney errors, it's tempting to set the ERC to tolerate open pins and type incompatibilities. And it's a bad idea. As to unconnected pins, when you deliberately leave a pin open, it is very simple to place a No-ERC directive on it. You'll never have to look at it again. And if you forget to do this, you'll get a warning and you can quickly and easily fix it. The large majority of schematic errors leave an unconnected pin. Years ago, designing with mylar and tape, I had an engineer who used to take a design and quickly go over it for unconnected pins. Even on a complex multilayer design (complex for those days might have meant 6 layers), it was easy to see this. And then he'd make sure that they were all properly unconnected. He'd find the bulk of errors very quickly with this As to other errors, many types of pin type combinations will generate an error with the default matrix. The best solution may be to fix the pin types, i.e., make, for example, a connector pin be an input or an output or passive instead of I/O, which doesn't like to be connected to an output. But this is not always practical. so, once again, it's simple to place No-ERC directives, though in this case I'd wait until running the first ERC. If it is easy to understand why an error is popping up, it may be relatively safe to suppress it with No-ERC, but if it is at all unclear, the safe path is to figure out why the error is happening. You might just find an error. And once you know, and it is not practical to fix it -- i.e., the error is purely formal -- then it should be suppressed. It only takes minutes at most to deal with even a host of connector pins. The goal is to generate a clean ERC report. Ideally, No-ERC markers would not be used, but practical reasons make us very glad that the primitive exists: at least we have made a conscious decision that a particular error or warning can be disregarded, and the markers allow us to avoid having to make this decision with every revision of the schematic. The cost of a schematic error can be very high, both in terms of money and in time-to-market, so it's worth the effort to learn to use the error-checking tools to best advantage. In the end, it's easy, the difficulty is only in the beginning It's too bad that Protel 99SE does not have editable pin types at the schematic level: Tango DOS allowed this (In Protel, pin types are only editable in the Library editor.) What I'd have liked to see would have been a symbol attribute that is Allow Pin Electrical Type Edits. If checked in the library, the pin types would be editable at the schematic level. If not, they'd be locked. So a connector symbol, generally, would have editable pin types. And then the error checking could get even better. I'd also like to have a way to quickly see the pin type of a pin. (Again, this was easy in Tango DOS). Has any of this been done in DXP? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To
Re: [PEDA] Analysing...
do you mean single layer of routed copper ?
('single sided board')
or do you mean parts only on one side and 2 or more layers of copper?
if you mean the first then the autorouter will probably not work for you
as far as crashing that is really a shame
using P6 w/ windows 2000 i find it to be very stable
with WIN98 (a few years ago) i found it to be less stable but not too
bad if you reboot once or twice a day (before it crashed!)
256m ram is not a whole lot, but it should be enough i think
since you have tried several machines i think it is time to try a
generic mouse and mouse driver ( :) )
other than that i don't know what to suggest
have you talked to Protel?
Dennis Saputelli
Choong Keat Yian wrote:
All were use and tested on Win98 and WinXP.Btw i found out some problem with Protel
99SE Autorouter too this few days for the result is that it isnt working to way it
should be.Imagine when i purposely use it to route a double sided high density small
PCB and when i change its rules to route the same board in single sided mode,the
copper tracks got shorted and crossed to each other and yet it said this is 100%
routed! ,this is not something that should happen as our work is quite tedious and
confusing at times so its like adding salt to wound.
Choong
Brad Velander [EMAIL PROTECTED] wrote:
Still running Win98 as you had stated in your earlier messages? That would be the
most common reason for your crashes if you are still running Win98. 99SE SP6 will
run quite stably on WIN2000 Pro. Pretty stable NT4.
Sincerely,
Brad Velander
-Original Message-
From: Choong Keat Yian [mailto:[EMAIL PROTECTED]
Sent: Sat 02/08/2003 5:49 AM
To: Protel EDA Forum
Cc:
Subject: Re: [PEDA] Analysing...
You know , i have have my own confusion both self afflicted and for using
Protel.,Since i join this company i has been told to use Protel but the fact is
that it seem to me Protel's old and new version do not alleviate anything much
other than cosmetic and workaround change as the main sunject matter.Imagine all
the feature it got but some is quite unusable for what it intended to be,and i
still didnt know why my Protel 99SE with service pack 6 still crash even thought i
have 256 mb ram on a Asus board with Pentium 4 at 2.4Ghz.It happen on multiple
machines both new and old and i dont think the problem is with the Nvidia's
graphic engine.
Choong
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Re: [PEDA] Non standard pad shapes in 99se
You also need to add primitives to the solder mask layer, if the pad is to be free of solder mask. And you also need to add primitives to the paste mask if you are using a stencil. Pay attention to the hole size in the stencil too. If it is getting large you may have to make paste sections avoid scooping. Brock Russell * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: ---- someone set this thing to stop rebroadcasting Au to replies ------
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [dxp] DXP License Nonsense
-Original Message- From: Duane Brown [mailto:[EMAIL PROTECTED] Sent: Thursday, August 07, 2003 10:55 PM To: DXP Technical Forum Subject: Re: [dxp] DXP License Nonsense I've been called twice with same nonsense Duane, Harry Its not nonsense, its for real. I was made the same offer from the UK VAR but was informed that the maintenance cover WAS optional, it covered major releases and 'priority' telephone support. SP, add-ons would always be free for current major release only. But, my understanding, is that it is very misunderstood. After all the backlash against ATS it is still actually around in principle under a different name guise and now 'optional'. I brought this up around April this year on this list, but it seems that no-one had an issue with this at the time, and quite OK about it, unlike the ATS revolt. I tried to push for an official comment from Altium but none was forthcoming, all communication was via the VAR. To the UK VARs credit (thanks, I know she monitors this list), they did assure me that they would offer technical support (inc telephone) for the product to the best of their ability regardless of my choice to accept or decline the Altium maintenance option. This may differ from other VARS in other countries. The Uk VAR was even prepared to supply a slide detailing how they deal worked how they would be prepared to 'fill the breach' left for telephone support if I 'opted out' from the Altium maintenance offer. You can download the slide (looks like an Altium slide branded with the VARs name) from http://www.proteluser.com/download/ and the file is called 'Protel DXP maintenance policy slide.zip' as it explains the deal. But, the slide is a little obtuse in the way it was worded and pitched, to the point that if no verbal backup conversation accompanied it, or it was not interpreted correctly, it could be read either as an offer to customers wanting to have a 'flat' annual cost of ownership model (some people do), or by EXCLUDING priority telephone support from Altiums obligations, implying something a little more sinister. The fact that DXP is over a year old now and still being shaken down, in some respects not lived up to its hype and customers expectations, does not help. Perhaps that is what has been pitched incorrectly to you by your own VAR. I had exactly the same initial reaction as Harry, it was made worse by the fact I could find NO official policy on any Altium web site about this at the time (paranoia) to match up with the VARs offer. I still cannot find any. But at least the UK VAR did not avoid the issue, and took the time to suppress my fears and explain it better, even after I had already said I was unwilling to upgrade any of my other P99SE seats to DXP as I did not consider it a good commercial risk to use yet, over 99SE. As most people will have had their DXP copy for around a year now I guess this issue will crop up more, in different flavours, perhaps some additions to the FAQ or a statement on Altiums own sites on this policy would clear the air in advance. Best Regards John A. Ross RSD Communications Ltd 8 BorrowMeadow Road Springkerse Industrial Estate Stirling, Scotland FK7 7UW Tel +44 [0]1786 450572 Ext 225 (Office) Tel +44 [0]1786 450572 Ext 248 (Lab) Fax +44 [0]1786 474653 GSM +44 [0]7831 373727 Email [EMAIL PROTECTED] WWW http://www.rsd.tv == -Original Message- From: Harry Selfridge [mailto:[EMAIL PROTECTED] Sent: Thursday, August 07, 2003 4:21 PM To: DXP Technical Forum Subject: [dxp] DXP License Nonsense I just got off the phone after an interesting call from Altium (San Diego). A young man called to tell me, your Protel license is expiring next month. He went on to ask if I wanted to renew. Since I am under the impression that a Protel license is not a year-to-year deal, my composure slipped somewhat. I told him that I thought Altium had cancelled the yearly fee nonsense last year. I further told him that DXP was still not a stable, mature, product, and we couldn't trust it for a big project just yet. Even if there were a yearly fee, I wouldn't spend it on a program I couldn't completely trust to be as good and as stable as the previous version. He looked up my record, and decided that I had received a one year complementary service agreement with DXP, and that was what I could pay to renew if I wished. He said it included phone help and any new releases of Protel that might come out within the service agreement period. I declined his generous offer. Good grief!! I hope they have a training program planned for their salesmen. --- You are currently subscribed to dxp For details about using the list, including how to un-subscribe, please refer to http://forums.altium.com/cgi-bin/info.asp --- You are currently subscribed to dxp For details about using the list, including how to un-subscribe, please refer to
Re: [PEDA] PCB Copper thickness VS mounted rails.
One other possibility is to make the board double sided, with 3 Oz foil on each side. This will be easier for them to etch/plate, and paralleling the high current traces on two layers gives the same resistance. I guess this won't work if this is a thermal board to be bonded to a heat sink. Jon I don't like making power supply PCBs with power traces on both sides. Especially with large snap-in caps. It is too difficult to ensure that the top of the PCB under the cap has a good solder to the huge fat traces just like the bottom. I've experienced such designs where power supply sections get a fine odd crackling type noise, which may be mistaken for a bad caps, but it really was fine cracks in the solder on the top layer just under the cap. With a 1 layer board, such a problem is easily caught. _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: Jon Elson [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Monday, August 04, 2003 1:59 PM Subject: Re: [PEDA] PCB Copper thickness VS mounted rails. Brian Guralnick wrote: I'm designing a power supply with will have a large ripple current. This power supply will be on it's own PCB and it's 1 layer. Am I better off mounting high current rails, or, increasing the PCB copper thickness from 1oz to something like 4-6oz? The power supply will be 90 vdc, continuous dc current of 4 amps, with current surges ripple current above 15 amps. Check with your PCB vendor on how much the extra thickness of copper will cost you. Then, compare with the rails, including the cost of having the assemblers deal with it. If the 4 or 6 Oz foil will carry the current with acceptable electrical characteristics, it sounds like the best solution, unless the extra cost is prohibitive. My guess is the extra foil thickness will be cheaper than all the extra handling to assemble the whole thing. One other possibility is to make the board double sided, with 3 Oz foil on each side. This will be easier for them to etch/plate, and paralleling the high current traces on two layers gives the same resistance. I guess this won't work if this is a thermal board to be bonded to a heat sink. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: Autoreply: How to make Component Height Rules
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DXP License Nonsense
At 11:55 PM 8/7/03 +0100, you wrote: Duane, Harry Its not nonsense, its for real. I was made the same offer from the UK VAR but was informed that the maintenance cover WAS optional, it covered major releases and 'priority' telephone support. SP, add-ons would always be free for current major release only. But, my understanding, is that it is very misunderstood. After all the backlash against ATS it is still actually around in principle under a different name guise and now 'optional'. I brought this up around April this year on this list, but it seems that no-one had an issue with this at the time, and quite OK about it, unlike the ATS revolt. SNIP John A. Ross SNIP John - The phrase from the salesman that peaked my attention, and raised my hackles, was your license is about to expire. There is no annual license requirement for Protel. Regarding ATS, below is the message that was sent to me from Altium on 26 September 2002 - it is consistent with the slide that you reference in your posting: Quote - As a result of listening to extensive customer feedback, we would like to inform you that the Altium Total Support (ATS) maintenance program has been discontinued, and all published Service Packs for Protel products will be made freely available to all Protel customers. We have taken this step to reaffirm the core values of our company - that of providing easy access for all engineers, designers and developers to the best possible design technologies - and to preserve the key benefits and advantages that you have enjoyed as a Protel designer. Service packs not only address issues with the software, they also include enhanced features and functionality, ensuring you get the most out of your Protel design system. Forcing customers to pay for product fixes and technology updates does not fit with the spirit in which Altium was founded, nor is it in harmony with the Protel product development philosophy. Options will be available for Protel customers that wish to have direct phone support and/or to annualize the cost of upgrades. The availability of these options will not disadvantage customers who wish to maintain their products on an upgrade-by-upgrade basis. All current ATS members will continue to receive all benefits entitled to them. If you would like any further information on these changes, please don't hesitate to contact your local Altium Sales and Support Center. A press release regarding the changes is available at http://www.protel.com/news.htm. For information on the latest Protel service packs available for download visit: http://www.protel.com/resources/downloads/. If you would like more product information on Protel or would like to download the Protel DXP Trial Version visit http://www.protel.com. Best regards, Phil Loughhead Protel Product Manager Altium Limited - End Quote * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autoreply: Autoreply: Autoreply: PCB Copper thickness VS mounted rails.
Hi, I am afraid that I am on annual leave until Tuesday 19th August. In my absence please direct any enquiries to Aiden Dalley, [EMAIL PROTECTED], who will be able to assist. If you wish to speak to me directly, please call 0413 528 152. Thanks and regards, Piers Watts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Discovery - LAN Network pasue hiccup patch.
As far as I am aware the 'free' version of ZA is only licenced for 'home' or 'non' commercial use. At my last SW audit I had to remove it from several machines at work and replace it with ZA pro [paid] licenses. The choice is yours but i would read the SLA. @'!#%$'[EMAIL PROTECTED]'#!#* --- Thanks a million... Ok, are there any good freeware firewalls which actually are freeware. _ Brian Guralnick [EMAIL PROTECTED] - Original Message - From: John Ross [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: Monday, August 04, 2003 6:50 PM Subject: Re: [PEDA] Discovery - LAN Network pasue hiccup patch. From: Brian Guralnick [EMAIL PROTECTED] Reply-To: Protel EDA Forum [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Subject: [PEDA] Discovery - LAN Network pasue hiccup patch. Date: Mon, 04 Aug 2003 13:22:58 -0400 I found a surprising fix for my Protel's occasional LAN network pause hiccups. I now use the firewall freeware version of ZoneAlarm on all of my PC on my network. ZoneAlarm's web site - www.zonelabs.com ZoneAlarm's freeware version - http://www.zonelabs.com/store/content/company/products/znalm/freeDownload.j sp?lid=zadb_zadown CAREFUL, not the trial version, the free version. The trial version has 2-3 added features over the freeware version, but it will die, or you'll need to pay for it. The free version works indefinitely. Brian As far as I am aware the 'free' version of ZA is only licenced for 'home' or 'non' commercial use. At my last SW audit I had to remove it from several machines at work and replace it with ZA pro [paid] licenses. The choice is yours but i would read the SLA. Also as someone pointed out before on these lists (not me, just cannot remeber who) there is an option in the client99se.ini file for Broadcast Access Code = True/False Receive Access Code = True/False I assume setting these to false will kill the need for network traffic (if the executables take any notice of these lines in the ini anyway), unless the wise developers at Protel do not want this feature disabled, which IMO was the reason to remove the user selectable check boxes in Licencing for broadcast/receive from the earlier 99SE builds (sp3 and later). Best regards John _ Stay in touch with absent friends - get MSN Messenger http://www.msn.co.uk/messenger * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PDF Files from Protel 99SE
Note: I am using only PDF Writer. For getting the PDF files to go to the folder you want: change the path to the folder even if the correct path looks chosen. I think I have seen the files go to the last folder used instead of what is showing. Acrobat works much better with Protel than AutoCAD. For AutoCAD the problem is worse the plot record files go to the path chosen and the actual PDF files go to the last folder saved to or something like that. I often have to use file search to find the files. Additionally, if you don't look at the printer properties the plot file will be rotated the wrong way more than half the time. Jeff Adolphs Lake Shore Cryotronics, Inc. Westerville, Ohio * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Trouble with printing on Acrobat Distiller
Hi All, I am having trouble in creating PDF Schematics for the protel 99SE Schematics. When I select Acobat Distiller printer in the 'Print Document' Dialogue, and click on the 'Properties' button to see the path 'where' to save files, I see the path as C:\DocumentSettings\AllUsers\Desktop\*.pdf. But the files don't get copied into this folder. How can I get the files copied into my folder of choice. ? Regards, ADEEL MALIK, * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB Copper thickness VS mounted rails.
i've seen some people mask out the solder mask from these traces and let the wave solder build them up not very controlled though personally i have never asked for 4oz or 6oz starting weight or seen much reference to those 2oz is pretty common though bus bars are pain , but they could work if it came to that i would look at just soldering in 18ga or 16ga jumper wires besides they can cross over! why is it single sided? - very (very) high volume? thru plates are much more reliable solder joints for those big heavy high current caps ds Frank Gilley wrote: Brian, Gosh, I would go for the fat copper if at all possible. This is not that much amperage. Are you under some sort of space constrained situation where you can't afford 500 mil traces? 500 mil traces outta get you a 10-15 C rise with only 2 oz copper at 19 amps continuous. I should think that the capacitor(s) you are going to be installing to handle this kind of ripple is/are gonna be huge, so you should have the room. Not to mention the heat those puppies are going to generate. -Frank At 02:41 PM 8/4/2003 -0400, you wrote: I'm designing a power supply with will have a large ripple current. This power supply will be on it's own PCB and it's 1 layer. Am I better off mounting high current rails, or, increasing the PCB copper thickness from 1oz to something like 4-6oz? The power supply will be 90 vdc, continuous dc current of 4 amps, with current surges ripple current above 15 amps. _ Brian Guralnick [EMAIL PROTECTED] Frank Gilley Dell-Star Technologies (918) 838-1973 Phone (918) 838-8814 Fax [EMAIL PROTECTED] http://www.dellstar.com -- Dennis Saputelli = send only plain text please! - no HTML == ___ Integrated Controls, Inc. www.integratedcontrolsinc.com 2851 21st Streettel: 415-647-0480 San Francisco, CA 94110 fax: 415-647-3003 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
