Tony, JaMi,
Partly I have to agree with Joey.
First of all, the bugs that are really annoing mostly happen if I don't have
the time. I need to finish a certain job, and now even the file is gone.
Hopefully the backup is OK. Then I realize the autobackup has ceased to work
two hours ago. Happened
- Original Message -
From: Tony Karavidas [EMAIL PROTECTED]
~ ~ ~
Not to jump all over you, but how do you suppose Altium is supposed to
fix bugs if we don't report them?
Excellent point Tony,
But I think that there are actually some other priorities too!
I think that the first
I was thinking about this a bit more today. This evening Terry Creer
discovered a 'new' bug. Subsequently, a few of us confirmed it in DXP.
Here's an interesting perspective: It's probably clear that DXP has some
if not a lot of code reuse from 99SE. If we find a bug in DXP, you know
it will have
Hello Gary,
this is a VERY late reply, but I had a similar
problem today,
so maybe this helps you and anyone who doesn't
get JEDEC.
I found out that at least one problem was, that
the JEDEC file
generator uses the Name entry in the CUPL
source file to
create the base name of the JEDEC
Hello everybody!
This is not the same as the old AUTOTRAX.
I have tryed it and it has som greate things like 3D editor ( that 99SE have
missed ).
The price 195$ ?? is wery nice!! And it`s also freeware!!
The speed is amaizing!!
Try it, and continue the discussion here , it will maybe help too
Terry, All,
It doesn't crash for me, it seems I'm the lucky one.
My setup is:
Protel 99SE SP6
Windows 2000 SP2 + some Pre-SP3 Hotfixes,
AMD Athlon 1600+, 256MB DDR RAM, Matrox G450
At the same time I have open Netscape Mail and browser.
I tried it in 2 combinations:
1. Mech Layers 1 and 4
On 10:53 AM 11/09/2002 +0200, Wojciech Oborski said:
Terry, All,
It doesn't crash for me, it seems I'm the lucky one.
Based on reports elsewhere it may be file related. Should check a number
of different files. I don't have the P99SE example file installed so I
can't test those and I happen
AH ha My brain ain't mush!!!
- Original Message -
From: Tony Karavidas [EMAIL PROTECTED]
To: 'Protel EDA Forum' [EMAIL PROTECTED]
Sent: Tuesday, September 10, 2002 11:32 PM
Subject: Re: [PEDA] Protel clone on the way?!?!?!
Yeah, 1989. Red box, Protel Autotrax. (I still have a box
- Original Message -
From: Terry Creer [EMAIL PROTECTED]
To: Protel EDA Forum (E-mail) [EMAIL PROTECTED]
Sent: Wednesday, September 11, 2002 3:21 AM
Subject: [PEDA] GTC - Guaranteed To Crash
I just discovered this.
I had all copper layers turned off, and only 2 Mechanical Layers and
On 12:26 PM 11/09/2002 +0100, John A. Ross \[Design\] said:
Terry
Tried my best, cannot get it to crash on W2k SP3
I left mech 1 (my board outline) mech 2 (dimensions annotation) and
multilayer.
Toggling between the 3 layers using + / - / * works fine.
Board I used has approx 380 parts.
Ian Wilson wrote:
snip
So it seems that the subject should be NQGTC.
snip
Ian,
What does NQ in your acronym mean ?
Sorry for asking, but english is not my native language,
so I have difficulties in guessing such things :)
As to your suggestion - I checked the behaviour with
several of
Yea Ive had noticed that about a year ago and might have reported it, It
happens if when turn off all of the signal/plane layers. I just figured
if I never use it that mode it never crashes. Also if you turn off of all
the clearance rules it will cause a crash. There are a few other
From: Mike Ingle [mailto:[EMAIL PROTECTED]]
I purchased Auto-Trax from Protel along with The initial
windows schematic
software. Way back when they were in Santa Clara Ca.
Protel has always been an Aussie company, though they did have a
sales/support group here in the states.
aj
From: Bagotronix Tech Support [mailto:[EMAIL PROTECTED]]
Wasn't AutoTrax the predecessor to Protel?
Yes. I was surprised to see that the name was being used. 'Suppose someone
will make issue. Didn't want to be the one. My understanding is that the
original code had been sold to a third party
Warning
Unable to process data:
multipart/mixed; boundary==_NextPartTM-000-8e19bc73-068a-4491-9eb4-2d5eef535ff3
So is there nobody who knows how to do this?
Tim
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, September 10, 2002 11:17 AM
To: Protel EDA Form
Subject: [PEDA] GND Plane Neck
I have 3 GND planes (3 different net names on the sch) I need to neck
together
Matt,
Yes - I had this about 2 months ago - I sent narinder a mail about it, and
it stopped. They must be infected again.
Klez is a very persistent virus!
Steve.
Anyone getting possible KLEZ spam from the originating IP
64.229.233.168 and
with a return path only in the headers from
Hi,
In the design rules 'Other' section, you can allow short circuits between
different nets. This should allow you to join the planes together wihtout
creating errors.
Hope this helps.
Paul
-Original Message-
From: Tim Fifield [mailto:[EMAIL PROTECTED]]
Sent: 11 September 2002 13:31
Warning
Unable to process data:
multipart/mixed; boundary==_NextPartTM-000-662d5a2a-7bb9-4420-9b93-37f2b78145ed
I got one yesterday.
-Original Message-
From: Matt Daggett [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, September 11, 2002 7:33 AM
To: Protel EDA Forum
Subject: [PEDA] Possible Spam...
Anyone getting possible KLEZ spam from the originating IP 64.229.233.168 and
with a return path only
Rene said:
It is not only the price that matters. I'd rather have one
that thinks a bit for itself. I once had an urgent pcb and
sent the data to a boardhouse before going to vacation,
intending to proceed when I'm back. There were a few unplated
holes and even they knew it was in a hurry they
Jon Elson said:
We used to use Imagineering, aka www.pcbnet.com, as they
were cheaper than Advanced Circuits a few years ago. Beware,
though, that they charge for electrical test but may not actually
do the test. We had a 6-layer board that they did for us, it had the
ET stamp on it, but a
11/09/2002 01:38:15, Damon Kelly [EMAIL PROTECTED] wrote:
Can I have a 3 pad PCB footprint and only load a 2 terminal part? Will the
PnP generator get confused?
I've been known to cheat and place a zero-ohm resistor on top of the (no-
fitted) 3-pin jumper. It can be fully described in the
Put me in for SP7. I will not go to DXP.
Dave Adams
Electronics Design Engineer
Safco Corporation
5404 Touhy
Skokie, Il 60077
(847)677-3204
-Original Message-
From: JaMi Smith [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, September 11, 2002 2:25 AM
To: Protel EDA Forum
Cc: JaMi Smith
- Original Message -
From: Matt Daggett [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Wednesday, September 11, 2002 1:32 PM
Subject: [PEDA] Possible Spam...
Anyone getting possible KLEZ spam from the originating IP 64.229.233.168 and
with a return path only in the
Hi,
I cannot confirm this behaviour. The given procedure works absolutely fine
here, just toggles the 3 layers.
W2K SP3, 99SE SP6, but not all the other processes you mentioned, just
Lotus.
Mit freundlichem Gruß
Kind regards
Gisbert Auge
N.A.T. GmbH
www.nateurope.com
Hi group,
since this SP7 stuff is being discussed, I typically have 100+ emails from
the forum every day, instead of 10-30 before. Yes, I also would like to
have SP7, but I suggest going back to normal. If someone wants to add
JaMi's Ceterum censeo ... to every mail as a reminder for Altium,
A simple method I've used several times is to indicate on the schematic
the two select resistors, calling them out as 0805s, then simply placed
them such that the ends which are commoned on the schematic physically
lie on top of each other with their bodies in-line. Selection is by loading
one or
Paul, Emanuel,
I like both of those ideas! I have a few questions.
1. With regards to the design rule. If I allow the nets of the three GND
planes to be able to short together, would the neck be the last thing I
place so the polygons don't completely short when repouring. (Assuming the
corners
I also got different klez variations from various adresses -none of them I
knew- in the past, too.
But no hint to the PEDA list.
Be careful with klez, it is not spam, it is a very dangerous worm.
As far as I know, it takes target adresses from everywhere,
not only -or even not at all- out of the
I have turned DRC off, at least I think I have. Autosave would not account
for my system going dead for 3-4 minutes while it re-calculates the inner-
plane connections. Something else must be eating up CPU cycles.
At 12:00 AM 9/11/02 -0700, DOLIST Server Expert 3.4 B2157 wrote:
From: [EMAIL
Everyone is probably getting this call from their fAultium sales office, but
I just found it amusing:
fAultium: (very energetically).. I was calling to see if you had gotten the
Altium DXP demo you had requested!
Me: Yes, but I didn't request it.
fAultium: Oh... ureally? Well, anyway,
even if some code was the same it doesn't mean the bug fix would be the same
. Sometimes a quick fix is modifying other portions of the software than the
faulty one, maybe even not knowing where the fault is , just patch something
until it works. For example, something hangs, we don't know why,
If bug really causes me a problem, I report it. But there are tons of
little trifles. The bug that sparked this thread is a perfect example.
Certainly, Protel would be a better product if these trifles were fixed,
but they are easy to avoid and have little impact on my use of Protel.
Honestly,
Tim Fifield wrote:
Paul, Emanuel,
snip
Well, I think I answered my own questions
Hmmyes!)
BR Emanuel
* Tracking #: 5AA09DBFCD7D564ABB2023E091BAFC1F95CD736D
*
I've had very good results with www.pcbexpress.com for small quantities or
protos .
They don't charge tooling , also no electrical test for less than 20pcs
protos .
3 days 4 layers no soldermask , ALWAYS (and I mean always) on time with zero
problems.
4 days 4 layers LPI soldermask +silkscreen
At 07:37 PM 9/10/2002 +0200, Heiko Vachek wrote:
And as far as I remember, it never happened that
they released a SP after the release of a major upgrade.
There was a final service pack for Protel 98, I don't recall the exact
timing, but I think it was simultaneous with the release of SP1 (or
Paul,
the short circuit design rule does not work, this was established
through a number of users many moons ago.
Sincerely,
Brad Velander.
Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel (604) 292-9089 (direct line)
Fax (604) 292-9010
email: [EMAIL PROTECTED]
Scott,
this sounds like a basic problem. As Steve has asked, if you supply
some more details then we could suggest some more probable causes.
First items to check, polygon net names (they must be different to
avoid each other), design rules (you must have a rule that the pours
Tony,
Protel/Altium first has to show some interest in fixing bugs and
addressing the problems in a timely fashion. In my personal experiences they
don't care and have no organized system to deal with bug reports. I have
reported several bugs to Protel, supplied files, described in detail
At 10:48 AM 9/11/2002 -0400, Watnoski, Michael wrote:
Daniel,
Just use the link that's at the bottom of the page when you receive
a message.
-Original Message-
From: Daniel Webster [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, September 10, 2002 7:39 PM
To: 'Protel EDA Forum'
Subject: Re:
Dave,
in the netlist manager, lower left corner you will find a Menu. Use
the function Update free primitives from component pads. This should
eliminate your ratsnest lines where you have already routed the connections.
I am not sure where the title of this thread came from but I
It's freeware for 15 or 30 days, right?
-Original Message-
From: Tommy Åkesson [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, September 11, 2002 1:42 AM
To: Protel EDA Forum
Subject: [PEDA] SV: Protel clone on the way?!?!?!
Hello everybody!
This is not the same as the old
If your layout is complete, you should not be seeing ratsnest. I'm not
sure of the state of your project.
-Original Message-
From: Dave Eloranta [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, September 11, 2002 7:54 AM
To: Protel EDA Forum
Subject: [PEDA] A few nets attach to blank
As steamed as most of us are, The Borgs were right
resistance is futile
You never saw the series finale of Star Trek: Voyager, eh? It proved that
resistance is far from futile.
Now, if I could just buy a tachyon generator from some Klingon dude on eBay.
I could go back in time and tell the
mariusrf wrote:
I've had very good results with www.pcbexpress.com for small quantities or
protos .
They don't charge tooling , also no electrical test for less than 20pcs
protos .
Well, when we made a manufacturing run of 10 6-layer boards with about 1000
components/board, we asked for,
I'm with Jim. Seems all I do anymore on this list is delete nontopical
messages. Guess I was too lazy to unsubscribe.
Jim, go to the link at the bottom of this posting labeled To leave this
list visit and fill out the form.
Cheers, Shawn
- Original Message -
From: Jim Weir [EMAIL
Yep - it still acts the same in DXP.
At 01:01 PM 9/11/2002 -0400, you wrote:
I am wondering if any of you can replicate this:
Start placing a series of track segments on Mech 1.
While in the process of placing track, hit the TAB key to change the track
width on the fly.
Upon changing the width
On 09:54 AM 11/09/2002 -0500, Dave Eloranta said:
I moved a completed layout so that I could add a mirrored title block on the
lower left of my parts locator drawing. All design rules pass, and I am
ready to generate gerbers. How do I get the rats nest of nets to conform to
the completely routed
At 03:08 PM 9/11/2002 +0100, John A. Ross \[Design\] wrote:
I got one containing an attachment called rock.exe which is the Klez beast
but the attachment was auto deleted by AV S/W at server
It was sent to [EMAIL PROTECTED] from [EMAIL PROTECTED] , vmadmin.com
is an e-mail marketing company. It
If you are meaning that a polygon does not see another polygon on the same
layer and then removes it as dead copper then I have seen this also.
I would suggest the easy workaround would be to stitch it at the overlap so
the polygon sees the vias as a connection to the same net.
Ed
Yes all your comments were very obvious. I will try and be a little clearer.
Using a single layer board for simplicity - place a polygon and connect to
GND. Place another polygon which overlaps the first, connect to VCC. Now
pick up and move the second polygon so that it no longer overlaps.
Thanks, Steve and Brian.
Yes, I came to the same solution late yesterday, after giving up on
cunning solutions.
I was trying to reduce the number of resistor symbols on the schematic, but
I guess I'll just have to make do...
As cunning as fox that graduated from Cunning University or words to
Now that the Forum appears to possibly be bak on line I will copy this
forum related post to the forum itself.
JaMi Smith
- Original Message -
From: JaMi Smith [EMAIL PROTECTED]
To: Forum Administrator [EMAIL PROTECTED]
Cc: [EMAIL PROTECTED]; JaMi Smith [EMAIL PROTECTED]
Sent:
Hey Rob,
I presume it's because there is no non-copper layers in the drop down box in
the interactive routing window, so it then automatically changes you to the
first cu layer... top!
Annoys the hell out of me too, and unfortunately is not a new fault so don't
expect a fix!
Ed
-Original
I haven't done a lot of boards, but why would you have overlapping polygons?
There are cases where Protel will (must?) repour all the polygons -- what
order should it use then? (And will some other designer looking at this be
able to figure it out?)
-Original Message-
From: Scott Ellis
One other thing about Sierra Proto Express (link below), they have some
fairly sophisticated software checking the Gerber. On one design we sent
them they caught that 2 track segments, while touching, only BARELY
overlapped -- the narrowest point of overlap (of the rounded track ends) was
much
this is not a bug
you are just using the wrong command
use P L
place line for mech layers
when you hit TAB a different dialog will pop and it won't swap you back
to a copper layer
P T is for electrical tracks
if you think about it, it is not bad
also the last used width will stick for each
i have seen this problem a few times myself
it is pretty mysterious and difficult to resolve
i chased it for a while and got nowhere
i sent such a file to protel and they reported that they could not see
it
(they did not report that it was a known bug)
when i opened the file on a different
Rob,
I think the problem is that you should use place line,
this doesn't have the same issue as you are using place
interactive routing which of course could not work on
a layer that is not copper as Shane says below.
Darren
-Original Message-
From: Shane Edwards [mailto:[EMAIL
For interest only, Protel is running a P99SE training course on simulation in
Sydney and Melborne . The course outline only covers the schematic side and does
not include anything on Signal Integrity or other good stuff like PLD, 3D view
or autorouting.
BR Clive Broome
Thanks Dennis,
I never realized they snuck the P L command in there! It works like it
should now. I guess that is one problem with being a long-time user and
using only the hot keys. I wonder what release started the Place Line
command? I learn something new everyday...
Rob
-
You can use Tools | Convert | Explode Polygon to free Primitives to
accomplish that.
-Original Message-
From: Scott Ellis [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, September 11, 2002 5:33 PM
snip
My next approach is to edit the text version of the PCB file, grab all the
track
Yes PL is the correct comand.
Ever notice how the place electrical wire in schematic icon is the same as
the place line icon in PCB!
This helps with my confusion :-)
Shouldn't Protel know when it's placing a mechanical line, that to me is a
bug!
Ed
-Original Message-
From: Dennis
Thanks Dwight.
I got it working by removing the polygon definition in the ascii file. -
Your way is much better!
Scott Ellis
Manager
Novatex Research - Excellence in Electronic Research Development
[EMAIL PROTECTED]
41 Yule Road, Merewether, Newcastle, NSW 2291, Australia
Ph 0412 988408 Fax
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