On 07:00 AM 30/07/2002 +0100, Terry Harris said:
..SNIP..I'm sure - but it isn't going to change anything soon - the only
question
for most of us is do we want DXP instead of 99SE and if so do we want it as
much as the upgrade price.
I remember some of the promises about DXP that were on the
Stefan,
I think your problem is lack of RAM - You really need 512MB of RAM, not KB!
To get Windows XP to run in half a megabyte is incredible!
Actually, I realise it's a typo, and if DXP needs more than the half a
gigabyte that you have then I'm stunned. I'd have thought that it would use
a
No need to apologise - I realised it was a typo - I should apologise for the
sarcasm!
Do you get this error when you try to install the software, or after the
install, when you run it? If it's when you try to install it, then I think
you are probably correct about the bad file. I have seen this
Hi all
I'm tweaking my Eudora.
Does this mail contains HTML?
How does it look with an no-html-client?
Thanks
Edi Im Hof
+ IH electronic+ Phone: ++41 52 320 90 00 +
+ Edi Im Hof + Fax:
Edi Im Hof wrote:
Hi all
I'm tweaking my Eudora.
Does this mail contains HTML?
How does it look with an no-html-client?
It seems that it's plain text e-mail and looks OK.
Wojciech Oborski
* Tracking #:
Hi Edi,
The email I received is plan text, I'm using Outlook 2002.
Darren Moore
-Original Message-
From: Edi Im Hof [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, 30 July 2002 23:02
To: Protel EDA Forum
Subject: [PEDA] OT: HTML
Hi all
I'm tweaking my Eudora.
Does this mail
Warning
Unable to process data:
multipart/mixed;boundary==_NextPart_000_000D_01C237B5.A74B3F90
Ian wrote,
Just a brief comment before the discussion really hots up.
My comments: Ian,follow the context of the messages on this forum from
release of 99 to present. The earlier tone from these discussions was
nothing but frustration. Some of us were mad as hell at simple things not
Yes but as I mentioned I have over 40nets and want to add the net
classes in a text format so I can do it all at once (like an INI file or
the old place txt file where you could place components by XY
co-ordinates we did that for placing test points in specified locations
-- you sure didn't want
Yes I know that I can get all the information on lengths etc with the
report file (net status) I can select each net 1 at a time, I want to
add this to the rules I want to input a txt file with the net classes in
a less tedious manner
-Original Message-
From: [EMAIL PROTECTED]
Dennis,
no I didn't mean 1 oz. foil or starting copper weight, I meant 1 oz.
plating. I thought that my comment was fairly clear but I guess not. I had
also mentioned that they have an automated plating line which supposedly was
their reason for only plating one weight of copper without
I don't have a real answer here so perhaps it would be wiser to keep quiet
but maybe there's a reason this company is called Enigma ??? ;)
Like in making their specs top secret even for customers?
Best Regards,
Matt Tudor , MSEE
http://www.gigahertzelectronics.com
- Original Message -
I haven't looked into it, but I believe this could be done, by saving the pcb to
an ASCII file then editing the text there.
Rob
Frances Wheeler [EMAIL PROTECTED] on 07/30/2002 11:09:21 AM
Please respond to Protel EDA Forum [EMAIL PROTECTED]
To: 'Protel EDA Forum' [EMAIL PROTECTED]
cc:
Just downloaded DXP demo yesterday and rejoined the forum (missed any
earlier discussion).
My initial impressions:
To compare the product I choose an 8-channel amplifier board that is one of
six identical cards used in a 48 transducer system. Of course this was very
tedious to do (or tedious
Or maybe the owner's name is E. (Edward) Nigma ?
(That was the real name of one of Batman's nemeses, the Riddler).
Best regards,
Ivan Baggett
Bagotronix Inc.
website: www.bagotronix.com
- Original Message -
From: mariusrf [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent:
Warning
Unable to process data:
multipart/mixed;boundary==_NextPart_000_0003_01C237C4.0839AB30
Try removing your mouse . . .
Just kidding - just kidding . . .
JaMi
- Original Message -
From: Stephen Casey [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Monday, July 29, 2002 5:15 AM
Subject: Re: [PEDA] Altium Release Protel DXP
John,
I'm glad it works for
Jami, that was truly funny!! :)
-Original Message-
From: JaMi Smith [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, July 30, 2002 10:14 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Altium Release Protel DXP
Try removing your mouse . . .
Just kidding - just kidding . . .
JaMi
Ian,
This is really scarey, you beta'd the thing and you cant say anything more
constructive yourself?
Talk about George Orwellean 1984 doublespeak . . .
JaMi
- Original Message -
From: Ian Wilson [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Monday, July 29, 2002
Part of the beta agreement was to not disclose things that transpired during
the beta period. That would seem to imply good or bad. The comments made on
this list should be 'freshly formed' from the released demo that everyone
has access to right now, not from what beta people saw in the past.
Forum members:
I don't know how it's happening, but some of the messages posted to this
list override the default fonts on my e-mail program (Outlook Express). I
suspect that some of us have our e-mail programs set up to format message
text in HTML. While this may look neat to you, I ask that
Guys and Gals,
It looks like this list is going to get very very busy here in the next few
weeks with all of the various threads that are going to be popping up with
DXP, and the ongoing fun with 99 SE.
I was wondering whether or not we all might want to do ourselves a favor and
come up with
Tony,
Thank you for the reminder, I don't think I have disclosed anything other
than reinforcing any commentary that I have posted here for the past year
and long before dXP was a gleam in the Kangaroo's eye. I believe Andrew
Jenkins past comments on here also reflect the poor response from
Hi everybody,
I am a Graduate student and I am currently working on designing a PCB for a Xilinx
FPGA.
I have started using Protel-99-SE trial version for the same.
Recently I noticed that the support site of Protel offers 2 documents to ATS members
(altium total support) members which I
Hi Mike,
My comment was more focused on Jami's comment to Ian:
This is really scarey, you beta'd the thing and you cant say anything more
constructive yourself?
I hinted that it might be possible for Ian to not say too much because of
the NDA.
Tony
-Original Message-
From:
How about just including DXP anywhere in the Subject if it's DXP related and
not 99SE or prior?
I think most of us have some sort of mail filter that could sort it. I
current use the PEDA string to get it into a Protel mail folder, away from
my regular inbox.
I could search for DXP to subdivide
From Alan Todd (Altium) when I asked for some clarification on the NDA:
To make any comments about work arounds or techniques you have found is OK
and I would encourage you to do so if you wish as this helps spread the
collective knowledge of the application. The sort of topics that you should
I recently had a look into the subject of FPGA and Protel.
I was told the FPGA router is still taken from the manufacturer
(in your case XILINX).
Meaning you're just using Protel to draw the schematics and
send the netlist to the other tool doing the FPGA. These
tools from various manufacturers
Hi,
I didn't participate in the Beta test. However I may recall incorrectly that
the Beta test NDA applied only during the term of the test and not after. I
did the beta on 98 and I seem to recall that these were the terms. Maybe I'm
wrong, does anyone have a copy of the DXP BETA NDA handy.
Joe
Anand Kulkarni wrote:
Hi everybody,
I am a Graduate student and I am currently working on designing a PCB for a Xilinx
FPGA.
I have started using Protel-99-SE trial version for the same.
Recently I noticed that the support site of Protel offers 2 documents to ATS members
(altium total
OK,
So everything seems to be ok except that when I look at a parts attributes
after an import nothing seems to change.
This is what I'm doing.
Export
1. In Schematic Editor. FileExportExport Schematic to Database.
2. I choose Part as my selected primitive.
3. I choose X and Y Loc, Lib Ref,
i agree and i vote for #4
Dennis Saputelli
JaMi Smith wrote:
Guys and Gals,
It looks like this list is going to get very very busy here in the next few
weeks with all of the various threads that are going to be popping up with
DXP, and the ongoing fun with 99 SE.
I was wondering
One reason to get the drawing in Protel and then export it to the Xilinx
tools is that the schematic editor of Xilinx is not, how shall I put it,
particularly convenient. I myself have done some designs in it while the
rest of the board was done in Protel. This got me out of my hum on more
Does anyone know if the Protel 2002-07-29 Digest was intact. I only
received one email in the attachments. I was looking forward to reading
all the comments about the new DXP.
Maybe one of you antipodean or insomniac readers could tell me by a
personal email whether it was sent properly
Hey, I removed my CPU and RAM, and found an old Dell Mouse from 1989, and
now it's all working fine!
JaMi, I laughed out loud when I read your post. Nice sense of humour!
Steve.
-Original Message-
From: JaMi Smith [mailto:[EMAIL PROTECTED]]
Sent: 30 July 2002 18:14
To: Protel EDA
This is really scarey, you beta'd the thing and you cant say anything
more
constructive yourself?
Tony,
I felt very strong that the platform (99SE) was and is superior to anything
else in the price range. A few minor tweaks, a few lines of code taken out
to optimize long compilations, and
I was getting ready to install the DXP demo and so was 'cleaning' my system
by uninstalling some other stuff ;)
After removing several items, the windows (un)installer said:
The Windows Installer Service could not me accessed. This can occur if you
are running Windows in safe mode, or if the
You're wrong. The NDA applies for afterwards too.
The NDA covers the NDA too, I guess.
The beta was a lot of tiring work, so let's forget about
the beta and focus on the release. You do your
purchase decision on the release and not on the beta.
The beta is gone ...
Rene
Joe Sapienza wrote:
Question to smartest of smartest designers out there:
Here is the delima, we have a board appox 24 x 30 ( a very large
backplane) , many thousands of connections, every layer controlled
impedance. The boards are used for high speed tele comminications
switching and data monitoring. ( No
Brad:
I don't want to start Font Wars, having just been an innocent bystander of
Mouse Wars. But I wish there was a way for me to make these e-mails appear
My Way. I can't even control how my replies look. Your company default has
hijacked me!
Best regards,
Ivan Baggett
Bagotronix Inc.
I'm using Altera FPGAs exclusively, since the tools are an effort in
itself. I also find the handling of MaxPlus2 rather awful, Quartus2
is a bit better.
The functionality they provide is far beyond just a schematic editor.
They allow me have graphic modules ( forget the VHDL for now)
to make a
The documents that you are requesting are also included in the free trial
version of Protel DXP. Look in the DXP help menu Articles and Tutorials.
John Williams
- Original Message -
From: Anand Kulkarni [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Tuesday, July 30,
put in the win2000 cd and boot from it.
select repair when asked what you want to do
it will rumble on the disk for a while and might reboot .
if it reboots select repair again ( always specify automatic.
this will put back any missing or modified system files.
eventually it will tell you to
before pouring , switch off the online DRC , 'Pour over same net' and
'remove dead copper'
since you have only that on thse layers no need to have the pouring
algorithm look for this stuff.
that should speed it up somewhat
Michael Reagan (EDSI) wrote:
Question to smartest of smartest
Michael Reagan (EDSI) wrote:
Question to smartest of smartest designers out there:
Not sure if I qualify :-)
snip
Copper pours of this size are poured last because they are time consuming.
The pours can take 4 hours, and even longer if they are not right the first
time. Question to any
Can't you simply use a ground plane (usually internal, of course, you
probably already have one) and tell the pcb house to use it as the top
and/or bottom too?
Richard
At 04:33 PM 7/30/2002 -0700, you wrote:
Question to smartest of smartest designers out there:
Here is the delima, we have
I'd try splitting the pours: a large area pour with large track widths and
a large pour grid, plus small regional pours wherever the coarse-grained
nature of the large pour has clearances that are larger than you want.
John Haddy
-Original Message-
From: Michael Reagan (EDSI)
Thanks Vince,
We do all of your mentioned tricks, it still takes hours. As a matter of
fact anytime I layout a design I turn off DRCs when I a place parts, I turn
on only clearance constraints and hide gnd and plane nets after I start to
manually route critical lines. This allows my computer
If you set the track size to a larger value the pours take less time.
Also make the trace larger than the grid and pour vertical (or horizontal)
hatch only.
i.e. 24mil track width 20mil grid size
This is faster since the polygon does not have to generate horizontal and
vertical.
If the outer
Mike,
I don't work on boards as _humongous_ as yours but have done similar on a
smaller scale. Here are a few suggestions:
(1) Break up your pour into many smaller tiles so that any later rework
can be completed with just a local re-pour on one of the tiles.Its
pretty easy to repour a
Hi there,
The only problem with simply file swapping the top layer with an internal
plane is you would not have any pads for the components since they are
hogged out on planes. That's why you ultimately have to merge the two
layers, but thats a problem since they are oposite polarity images.
Something I forgot to mention:
If the parts are surface mount then the internal plane has no hog-outs at
all for the pads. Thats why you might be interested in using the
soldermask layer instead.
Dave Lewis
[EMAIL PROTECTED] on 07/30/2002 03:19:57 PM
Please respond to Protel EDA
Rene Tschaggelar wrote:
I recently had a look into the subject of FPGA and Protel.
I was told the FPGA router is still taken from the manufacturer
(in your case XILINX).
Meaning you're just using Protel to draw the schematics and
send the netlist to the other tool doing the FPGA. These
The file for the toolbar is at the following link:
http://groups.yahoo.com/group/protel-users/files/
Sorry, I wasn't clear about where I uploaded the
file to. The zip file includes an readme file with
details on how to install it.
Darren Moore
-Original Message-
From: Darren
Peter and All
If an internal ground plane has an appropriate copper pattern for the
outer layers, just tell the board shop to use that artwork for both the
inner layer and outer layer - just because Protel thinks the *.gtl file
is the top layer, doesn't mean you _must_ use that as the top
Mike,
100% Correct.
Bob Wolfe
Mike wrote
I disagree,This is expensive software. I purchase $49.00 software and
complain to store managers if my $49.00 package doesnt work, why shouldnt
ALTIUM receive heat from us about not correcting bugs and not meeting our
expectations. We are the
Paul,
You can go look at the archive at Protel-Users-PEDA-Archive at hahoo groups.
JaMi
- Original Message -
From: Paul Gaastra [EMAIL PROTECTED]
To: [EMAIL PROTECTED]
Sent: Tuesday, July 30, 2002 12:53 PM
Subject: [PEDA] Checking if Protel 2002-07-29 Digest intact.
Does anyone know
On 09:46 PM 30/07/2002 -0400, Robert M. Wolfe said:
Mike,
100% Correct.
Bob Wolfe
Mike wrote
I disagree,This is expensive software. I purchase $49.00 software and
complain to store managers if my $49.00 package doesnt work, why shouldnt
ALTIUM receive heat from us about not correcting
So I'm checking out the flash demos today on Altiums site and notice an
image of Palm or Handspring device flashing by, like it has something to do
with DXP. Then
I'm poking around the Innoveda site and notice an image of Palm or
Handspring device in this PDF file:
In the US, 'to bag' generally means the same thing. I think some places it
means to 'capture' or 'get lucky' but I'm not sure where...
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, July 30, 2002 7:14 PM
To: Protel EDA Forum
Subject: Re: [PEDA] DXP
Hello,
I believe this has to do with the default encoding used by the e-mail
program of the sender's original post. I have OE6 set to reply in plain
text only and I have always seen the same thing as you do, up 'till just
now.
When I click on 'View' 'Encoding' ... for this e-mail I saw the
InterestingIn my neck of the woods (NW US), to bag something is to
abandon it
as useless, but without extreme prejudice
Brian
At 07:32 PM 7/30/02 -0700, you wrote:
In the US, 'to bag' generally means the same thing. I think some places it
means to 'capture' or 'get lucky' but I'm not
Hey, I removed my CPU and RAM, and found an old Dell Mouse from 1989, and
now it's all working fine!
JaMi, I laughed out loud when I read your post. Nice sense of humour!
Steve.
Steve,
the guys in the office around me looked at me like I am crazy because I
laughed out loud when I
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