Yes,
I find that to be true also, someone helping me learn the program just used
* (Shift 8)
to place vias, I could never get this to work only the numeric keypad *
Bob
Robert M. Wolfe, C.I.D.
47 Chatfield Drive
Trumbull, CT 06611
203-261-2182
[EMAIL PROTECTED]
- Original Message -
From: "
Gary,
Very interesting, I had a similar situation, (before I found this forum)
where the autorouter
would just not run, still don't know why, it was very early in the design
stage and I was just testing
out the system so not being able to resolve it I started from scratch (it
was a simple board).
Tony,
Well (back in the old days) once film has been generated from gerber (or
hand tape) they could bomb-site the film for coordinates. However I don't
honestly know of any fab houses that still do this. I'm
sure there are, just have not delt with any in recent times.
But honestly the fab house c
e any problems.
I really want to use NT for now.
Has any one had any problems with OBDC drivers and NT ???
Thanks
Bob Wolfe
- Original Message -
From: "Andrew Moran" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Tuesday, Novem
h
had two pads touching. Then just swapped footprint to one needed. DRC would
then flag those
footprints but there where usually so few on a design they could easily be
identified and disregarded.
This second way also makes it part of the schematic. Just a little more
documentation friendly.
Bob
Terry,
Just could not stop myself from answering this post.
If you ask 10 engineers about how they would like to see power pins on a
schematic
or not (especially now that we are dealing with 5/3 volt parts) and you WILL
get 10 different
answers. I am a PCB designer who does not believe the schemat
Terry,
Thanks for the response, sorry to rant, I understand the variety of choice,
but I am dealing with a situation where the master of the Orcad schematic I
am taking in is rather reluctant to modify much
on that end which is causing me more work on my end plus the constant errors
in power conne
Abdulrahman wrote
> The bottom line is that the photoplot people can panelize in seconds,
> literally. They do it all day, every day. If you must control the panel,
> then give them a dimiensioned drawing (which can be on a mech layer on
your
> original PCB file) and then tell them to step and rep
To all,
I will second that rule to do the preview. I was in a situation where IF had
I done it I would have realized what it did to me before I just went on fat
dump an happy making changes to an existing design. The 99SE synchronizer
works very well. I have completed many designs now (being a new
Steve,
Your source for danger??? Just a question how it was determined it was
really dual proc
that causes Matrox dual head problems. Its been a while too since I have
used
dual proc and the dual head set up but we never really got ant good info out
of Dell
or Matrox back then.
Robert M. Wolfe, C
Ian,
VeriBest (now Mentor) was one that had a .pcb extension
Robert M. Wolfe, C.I.D.
[EMAIL PROTECTED]
- Original Message -
From: "Ian Wilson" <[EMAIL PROTECTED]>
To: <[EMAIL PROTECTED]>
Sent: Friday, December 21, 2001 5:03 AM
Subject: [PEDA] Want to know which program created some .PCB
don't have to use any one of these. So changing the
> footprint list in the library should NOT update all the footprints for
those
> symbols in the schematic.
> 2) Use global edit if you really want to change all of them to the same
> (new) footprint.
>
> -Original Me
Sean,
Meetings are a great idea, not just to put a face to the email, but usually
a whole lot
of great networking goes on. It is usually a wonderful forum to exchange
ideas
on using this tool. I have always come a way from these type of meetings
with great ideas
both given and taken. I would atten
ED]>
Sent: Saturday, December 22, 2001 5:51 AM
Subject: Re: [PEDA] multi sheet problems
> On 03:52 PM 21/12/2001 -0500, Bob Wolfe said:
> >Dwight,
> >I believe it is the first one on the list of footprints it will actually
put
> >on the board.
>
> The list of four foot
>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, December 27, 2001 10:57 AM
Subject: Re: [PEDA] multi sheet problems
> At 07:02 PM 12/26/2001 -0500, Bob Wolfe wrote:
> >An one more note.
> >Not only does it ONLY put down the first footprint on the list
Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]]
> > Sent: Friday, 28 December 2001 2:58 AM
> > To: Protel EDA Forum
> > Subject: Re: [PEDA] multi sheet problems
> >
> >
> > At 07:02 PM 12/26/2001 -0500, Bob Wolfe wrote:
> > >An one more note.
> > >Not
> schematic with the synchroniser).
> >
> > The only boxes I had checked in the synchroniser were,
> > 'Update footprints',
> > and 'Delete components'.
> >
> > Did you say you had SP6 installed?
> >
> > Regards,
> >
> > Tom.
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, December 27, 2001 8:41 PM
Subject: Re: [PEDA] multi sheet problems
> At 06:26 PM 12/27/2001 -0500, Bob Wolfe wrote:
> >Well Guys and Gals,
> >All I know is a while back I tried a number of times to keep an
OK Here is the scenario, I ran through this today.
Hopefully I have described it clearly enough.
I am running 99SE, SP6 on WIN98 Second Ed.
Using the Database structure.
Create 3 footprints called KP1, KP2, & KP3 that could be used for this
part in a library,
Create a part for a contact pattern f
ting the new netlist into PCB and with "Delete Components not in
> netlist" and Update Footprints" checked you would think that these two
> options would refresh the footprint association between a sch component
and
> it's footprint. It doesn't always work. I foun
[PEDA] Multisheet Problems & Updates etc.
> Bob Wolfe wrote:
> >
> > OK Here is the scenario, I ran through this today.
> > Hopefully I have described it clearly enough.
> > I am running 99SE, SP6 on WIN98 Second Ed.
> > Using the Database structure.
>
rom: "Ian Wilson" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, January 03, 2002 6:16 AM
Subject: Re: [PEDA] Multisheet Problems & Updates etc.
> On 05:18 PM 2/01/2002 -0500, Bob Wolfe said:
> >Peter,
> >
it to its fullest,
this is still seems way too much work for a large schematic.
Thanks
Bob Wolfe
- Original Message -
From: "Peter Bennett" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, January 02, 2002 6:06 PM
Subject: Re: [PE
ul-Rahman Lomax" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, January 03, 2002 4:05 PM
Subject: Re: [PEDA] Multisheet Problems & Updates etc.
> At 02:18 PM 1/3/2002 -0500, Bob Wolfe wrote:
>
> >But is it not true that you
Sean.
Yup been there done that. It worked out very well, the product is in
production now, with no problems, at least not do to the contersunk holes
anyway.
Just talk to your fab house. I was doing a quite intelligent fan tray unit
that had major
height clearance issues so the PCB became an integr
Sean,
I believe they can be plated but in previous post about fan tray a
countersink for a
flat head screws was used, and again I believe the answer was they could do
it, not as sure
about if you are looking at a countersink with verticle entry on edges.
There might be a build up of in the corner
Sam,
Thanks, for the life of me could not think of the word counter bore before,
in my last post.
Bob Wolfe
- Original Message -
From: "Samuel Cox "Sam"" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, Ja
with good library functionality to
work this way.
Thanks
Bob Wolfe
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lfe, C.I.D.
[EMAIL PROTECTED]
- Original Message -
From: "Peter Bennett" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, January 10, 2002 10:48 AM
Subject: Re: [PEDA] Multisheet Problems & Updates etc.
> Bob Wolfe
There might be other opproaches like Adobe, but you need the writer,
don' t think there is any way to view the native Protel .pcb file.
if you output gerber at least there are many free gerber viewers out here
like
Lavenir Viewmate etc. usually they just won't let you print, and may no tlet
you sa
t;Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Sunday, January 13, 2002 10:56 PM
Subject: Re: [PEDA] Multisheet Problems & Updates etc.
> At 12:25 PM 1/10/2002 -0500, Bob Wolfe wrote:
>
> >What I do really want though is on the schematic side. All I want is for
the
> &
Rene,
If you mean that it should work EXACTLY the same way as the PCB
you got my vote. That was pretty annouying to get used to.
That is one pet peave about CAD systems that most just don't
get and it really bugs me. Is the fact that all of the simple functions like
pan, zoom etc
do not use the sa
Dwight,
Unrelated to actual Router Setup but,
Just a question only .015 inch gap for Tip & Ring to all other nets,
that might be good for between Tip and Ring Or is it not the actual
Tip & Ring coming directly from CO but rather further down stream
that connects to some sort of system station
In response to Mr. Lomax,
He is absolutely 110% correct in the area of face to face
requirements in PCB design.
It is a shame that many companies have not come to realize this.
Even direct employees and companies can benefit from remote
work. I will say that I am more likely to immediately pick up
John,
You should also point out that if you are going to use alternate footprints,
that if update footprints is needed to be used during synchronization to
update
a bunch of updated or changed footprints in a board that the system will
remove
any of these alternate footprints and put the first foo
ts whatever footprint is specified in each schematic
> symbol.
>
> > -Original Message-
> > From: Bob Wolfe
> > Sent: Sunday, February 03, 2002 12:11 PM
> >
> >
> > John,
> > You should also point out that if you are going to use alternate
>
rary standpoint.
Thanks
Bob
Robert M. Wolfe, C.I.D.
[EMAIL PROTECTED]
- Original Message -
From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Monday, February 04, 2002 12:46 PM
Subject: Re: [PEDA] Component
Forum" <[EMAIL PROTECTED]>
Sent: Monday, February 04, 2002 3:47 PM
Subject: [PEDA] Bob Wolfe's Update Issue (Ex: Component partition)
> On 11:40 AM 4/02/2002 -0500, Bob Wolfe said:
> >Dwight,
> >Mr. Lomax pointed out and unless there is something wrong
> >with
ed in the SCH (whether in the list or not) is what the
> synchronizer will try to place on the PCB -- that's what it's supposed to
> do.
>
> Dwight.
>
> > -Original Message-
> > From: Bob Wolfe
> > Sent: Monday, February 04, 2002 11:12 AM
> > S
To Abdul-Rahman, Dwight & Ian, & All,
Well guys I have finally seen the light.
Actually it was Dwight's post that finally clued me in last night, and
a chat with Abdul-Rahman. I guess it was past CAD systems
that provided me a major mental block.
There is no bug and I do understand now how the foo
Lloyd,
I would whole heartily agree with you.
There was a CAD system VeriBest that was based on Bentley's
MicroStation and therefor needed it to run, there was two editors
the PCB side and the drafting side, and yes one could say that
there was great power in that combination, however the PCB sid
> Yes, fascinating. From my casual reading, I didn't see that the author
> really recognized the supreme idiocy of red/blue tape.
>
> He talked about using register pins, but nothing about the concept of
using
> a single layer padmaster with separate mylar layers for top and bottom
(and
> innerlay
> Mr. Newberry is correct about the origin of the term, except that I'd
think
> it began with CAD systems. Generating a rat's nest was simple for a
> computer but not at all simple for a manual designer, so I never saw a
> manually-done rat's nest drawing.
Unless we can consider the big pile of m
had to develope the film in total darkness? I don't
> want to go bac either!
>
> Jim McGrath
> CAD Connections, Inc.
>
> Bob Wolfe wrote:
>
> > > Yes, fascinating. From my casual reading, I didn't see that the author
> > > really recognized the sup
>my brain would not stop and I actually ended up having recurring dreams
>where I was actively doing the lay out--in the dream!
Abd ul-Rahman wrote:
You haven't earned your stripes as a professional PCB designer if this
hasn't happened to you
H Boy a truer statement has never been uttere
Jason,
I did not follow this one from the very beginning but,
I would also 100% agree that bringing a gerber file back into your
CAD system for any reason other than to use it to reproduce
a board you have no CAD data for, or copy sections into an
existing board etc. is not good. I would NOT recom
Ian,
There is an industry standard that does define these terms, the IPC.
Look at IPC-T-50 "Terms and Definitions for Interconnecting and Packaging
Electronic Circuits"
PCB & PWB have in the past (old school) been interchangeable in meaning
Printed Circuit Board & Printed Wiring Board and generall
Even if it has been talked about I would add that this is very much needed
in capability. However or if ever Altium decides to implement something like
this.
But as the software stands now it is very clunky with respect
to package info on a mechanical layer with respect to two sided assemblies.
To
I'll keep it short and not copy the other post totaly, but it pretty much
puts the issues right on the money. Especially the statement below about
dedicated assembly layers.
Robert M. Wolfe, C.I.D.
[EMAIL PROTECTED]
Abdulrahman wrote
>Yes, we should have dedicated assembly layers. This should ha
Sean,
Just like I would treat a slot basically.
Provide holes at key points to define the removed board material.
Does the hole really need to be an exact square or rectangle?
Or would a small slot do, just provide the holes at the endpoints
with hole dia as width. Put detail or notes on dwg to de
Sean,
On my installation of 99SE on Win2Kpro it does not seem to matter that I
needed to shut
down with Task Manager, it does this just shutting down Protel normaly,
every now an then the process remains running when I just close Protel only,
which of course won't let you shut down the machine, an
Tim,
It really depends on what your test group requirements are, based on
quite a few things but one would be type of probe being used, even
if the tester is capable of smaller pads and spacing, also the level at
which a fixture
is made would govern that too.
But with a newer GenRad system I would
So far I have only seen this when I have selected and moved a bunch of
parts,
if I then double-click the part the coordinates are all of a sudden out to 6
places.
I am woring im metric but also use basic increments like 0.1mm for all
grids.
I pretty much do not change between units display.
Robert
x27;t think he had any
luck. So for now I am good
but thanks very much for the offer of help.
Thanks again to all.
Bob Wolfe
- Original Message -
From: "Jon Elson" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, March 13, 2
Abdul-Rahman wrote
> Which could be quite a disaster. Files should be interchangeable between
> users, the OrCAD port setting being an example of what can go wrong.
Abdul-Rahman,
Welcome back, if you're burried no problem, the sauce got you eh?? but what
is this
OrCAD port setting issue?? Or mayb
]
- Original Message -
From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Tuesday, March 19, 2002 5:20 PM
Subject: Re: [PEDA] Re[2]: spaces in footprint names
> At 03:50 PM 3/19/2002 -0500, Bob Wolfe wrote:
>
ivity was there in OrCAD with no errors.
Bottom line I need to ERC the design after it comes over.
Thanks
Bob Wolfe
> Abdulrahman Lomax
> Easthampton, Massachusetts USA
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* To post a message: mailto:[EMAIL PROTECTED]
*
*
Also I believe there is an extra process step involved when you have pad
area on a NPT hole. Most vendors I have delt with asked if they could plate
the hole
in some cases we said yes in others we said no and they delt with it.
In most of the cases they were just mounting holes (not tooling) and t
Brad,
Just a thought,
I believe IPC docs do specify a formal Fab Dwg for complete documentation,
however whether
or not the IPC spec's defines needing one, unless one plans on providing a
very complete set of total electronic
files like IPC GenCAM or Valor to a fab house which also does provide th
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