Re: [PEDA] 99SE Print Preview problem
Remove the printer driver, and then re-install it Ted -Original Message- From: Ian Rozowsky [mailto:[EMAIL PROTECTED] Sent: Wednesday, July 07, 2004 10:41 AM To: Protel EDA Forum (E-mail) Subject: [PEDA] 99SE Print Preview problem Hi Group I've been using 99SE SP6 for years now, and all of a sudden I'm experiencing a problem with printing. After requesting a print preview, I get a system message as below: Access violation at address 0EBEE544 in module 'PCBPRINT.DLL Read of adress 0008 Exception information Exception occurred in PCBPRINT:PrintPreview I've tried repairing the installation, no luck. I then uninstalled Protel, deleted all the .INI and .cfg files, and re-installed - no dice. Any ideas? TIA Ian Rozowsky R&D Director Centurion Systems (Pty) Ltd. Box 506 Cramerview 2060 South Africa [EMAIL PROTECTED] ||Anti-spam - please remove the ** from the e-mail address before sending|| http://www.centsys.co.za - This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager. Please note that any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Centurion Systems (Pty) Ltd. Finally, while Centurion Systems attempts to ensure that all email is virus-free, Centurion Systems accepts no liability for any damage caused by any virus transmitted by this email. - This email and any files transmitted with it are confidential and intended solely for the use of the individual or entity to whom they are addressed. If you have received this email in error please notify the system manager. This message contains confidential information and is intended only for the individual named. If you are not the named addressee you should not disseminate, distribute or copy this e-mail. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Test point style
I am setting up a new design that is going to require me to use test points on the board. I would like to use .9mm (.035") for the test point size. I am trying to find a way to set up the design rules to automatically place a square test pad instead. I am running 99SE SPK6, I looked in the Protel 99SE hand book I downloaded off Protel's web sight and there is no information regarding the changing of a round test pad to a square test pad, the Protel 99 book does. Does any one know If I can change the pads so I can let Protel place them while auto routing (in the design rules)? Or am I going to have to change each one after they have been placed? Regards, Ted Tontis C.I.D. Engage Networks, Inc. 1320 N. Dr. Martin Luther King Jr. Drive River Level Milwaukee, WI 53212 PH 414-918-4267 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] flies in the archive
thank you. > That is an older archive. There is a current archive kept on [EMAIL PROTECTED] This is a normal yahoogroups archive; that list is simply an echo of the Techserv list. > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] flies in the archive
I have been trying to get some of the files that where loaded up to the list, like the QFP generator, and the spiral generator. I can not seem to find them, I do however find a message from Mr. Lomax about subscribing to protel-users-PEDA-archive. I have downloaded the two files mentioned above, but now I can not seem to find them. Have they been moved, am I looking in the wrong spot? Could someone point me in the right direction? Regards, Ted Tontis C.I.D. Engage Networks, Inc. 1320 N. Dr. Martin Luther King Jr. Drive River Level Milwaukee, WI 53212 PH 414-918-4267 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Tasking software
I have not received my copy yet. Ted, Milwaukee WI -Original Message- From: Burt Bicksler [mailto:[EMAIL PROTECTED]] Sent: Tuesday, April 02, 2002 6:40 PM To: Protel EDA Forum Subject: [PEDA] Tasking software Just wondering.. Is anyone else here in the states still waiting for the free Tasking software to show up? Not that it is of extreme value, but still it was promised and I haven't seen it appear yet. Thanks, Burt * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] .legend will not work
Thanks, Mike that was it. Do you know what originally caused this problem? Regards, Ted > >Ted, >Delete .legend from your design >Reset origin >Set Grid to 25 mils >place .legend on drill drwg layer on grid >Generate gerbers >View with gerber viewer >See if this works >Mike Reagan * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] .legend will not work
I have a old file that I am trying to generate gerber files on. I can not seem to get the .legend to work. I have confirmed I can not view it when I generate the gerber files or when I do a print preview. This is what I have done already repair the data base, repair Protel, checked that all the drill holes are really holes, confirmed that the .legend is really there, and tried it on another data base. The only thing I have not tried is to completely remove Protel and re install it. Has anyone else had the displeasure of having this happen to them? Thank you, Ted Tontis C.I.D. Engage Networks, Inc. 1320 N. Dr. Martin Luther King Jr. Drive River Level Milwaukee, WI 53212 PH 414-918-4267 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Camtastic installation
Mike, If this is just to view the files Camtastic offers a free viewer http://www.camtastic.com/en/downloads/sfiles.asp you just will not be able to edit the files. Regards, Ted -Original Message- From: Michael Reagan [mailto:[EMAIL PROTECTED]] Sent: Monday, March 11, 2002 3:06 PM To: Protel EDA Forum Subject: Re: [PEDA] Camtastic installation Thanks Matt Well appreciated Mike Reagan > -Original Message- > From: Matt Pobursky [mailto:[EMAIL PROTECTED]] > Sent: Monday, March 11, 2002 3:20 PM > To: Protel EDA Forum > Subject: Re: [PEDA] Camtastic installation > > > I don't believe so. I tried it once a few months ago on a new > machine with no Protel instal (yet) and it gave me an error > dialog box stating "No valid installation of Protel99SE found" > (or something to that effect). Closing the error box exited the > installation. > > Matt Pobursky > Maximum Performance Systems > > On Mon, 11 Mar 2002 14:25:17 -0500, Michael Reagan wrote: > >Does anyone know if Camtastic will install as a stand alone > >product ( not using the lic number from the pcb product) We > >wish to install a seat of it on our production manager's > >computer so he can inspect paste files. We have about 5 seats > >of Camtastic and only three are being used with designers. > > > > > >Mike Reagan > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel and Windows XP
I have not yet really had a chance to push protel hard under XP, but I have not had any problems yet (knock on wood). I have been running XP for two months. Ted -Original Message- From: Bob Puckette [mailto:[EMAIL PROTECTED]] Sent: Friday, February 22, 2002 2:12 PM To: Protel EDA Forum Subject: [PEDA] Protel and Windows XP I heard from a friend that Protel won't work on Windows XP. I'm setting up a new computer, and I'd like to run Windows XP if I can. Will it work? Bob Puckette [EMAIL PROTECTED] Tripod Data Systems 345 SW Avery Ave Corvallis OR, 97333 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] help with a stack ??
Mike, use this stack up non critical gnd critical -5 gnd critical +5 (better if this was ground) non critical or gnd critical non critical power gnd non critical critical gnd (if power switch critical and non critical) two reasons why I say put the critical in the center of the board. First your board vender will be able to control the thickness of the traces better, when they plate the board. Second your board will be a lot more quite. You will then only have to factor in the etch factor to keep you impedance. Regards, Ted * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] how does smt work ??
There are quite a few problems with via in pad. 1. Having a via in a pad will not give you a flat pad, possibly reducing the reliability to the solder joint, very bad for fine pitch parts. (unless this is a micro via) 2. You will be forced to plug or fill the via (again unless it is a micro via or blind via). 3. There is also a process that will cap a via during the plating process, again you will not have a flat pad. If one is trying to decide if using via in pad is use full, just remember the more processes you add to the board the more costly the design will become, along with it's complexity, check with your board vender. It is sometimes less expensive to add layers then going to a more complex design. Regards, Ted -Original Message- From: Dwight Harm [mailto:[EMAIL PROTECTED]] Sent: Wednesday, February 20, 2002 9:17 PM To: Protel EDA Forum Subject: Re: [PEDA] how does smt work ?? I'm relatively new at PCB layout, so I'd like to verify -- aren't under-the-component vias fairly common nowadays, particularly with fine-pitch ICs and BGAs? The autorouter puts 'em there all the time, so it MUST be ok! ;) > -Original Message- > From: Thomas [mailto:[EMAIL PROTECTED]] > Sent: Wednesday, February 20, 2002 3:19 PM > > The reason you may not notice the vias is that they may be tented (covered > with solder mask) or under the component (bad design practice). * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] protel schematic question..
use the select all option, deselect the fill, cut the pins, and then paste them back. Just make sure that when you paste them the curser has not moved, or you will place them off the fill. remember to deselect all after you pasted the pins back on. Regards, Ted -Original Message- From: rimas [mailto:[EMAIL PROTECTED]] Sent: Thursday, February 07, 2002 1:13 PM To: Protel EDA Forum Subject: [PEDA] protel schematic question.. quick question about creating schematic library parts. i generally like to place the pins first and then place a rectangle that encompasses them. however when i do this, the fill color of the rectangle covers the text identifying the pin. if i place the rectangle first and then place pins over it, i don't have this problem. any advice ? i've been unselecting the "draw solid" option for now... thanks, -rimas * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Re[3]: View PCB 3D
In the 50's there was a car that was also a boat. You could drive it on both land and water. I just thought it was kind of ironic that you used that particular one.:) Ted -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Thursday, February 07, 2002 12:56 PM To: Protel EDA Forum Subject: Re: [PEDA] Re[3]: View PCB 3D "Many users will not want to have to convert all their libraries to include 3-D information" This is my point exactly. Some PCB designers have no interest in the 3D world, so let's not create a proverbial white elephant inside of Protel. The functionality you request would add cost, or possibly an add-on package. Hmmm extra packagessounds like the road the PADs and Orcads have been down before. And frankly I'm not interested in going down that road again. You don't use a car in the lake nor do you use a boat on roads, but as long as you have a boat trailer to transport back and forth to the different mediums.. (perhaps a flakey analogy!?) Still disagreeing ...respectfully, Lloyd * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Auto router
I can get the auto router to route the manual fan outs, and in some locations I can get the auto router to just route the area I have selected. I can never get the auto router to route the board without it looking like it went through a skeet competition. This is why I figured I would fan out the board by hand then area route the board and do it in sections. I left just enough room to get the tracks in between the vias, trying to keep it nice neat. This is not working as well as I had hoped. Can any one share one success story with the auto router and possibly share the setup they used. I know that there a only a few design rules that are related to the auto router, maybe I am just missing one? Thank you, Ted -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] Sent: Thursday, January 24, 2002 5:15 PM To: Protel EDA Forum Subject: Re: [PEDA] Auto router it won't connect to your manual fannouts, it will route back to the smd pad and place a new fannout somewhere it does the best when it has the most to do, i.e. limited or no preroutes and then Route All if you have preroutes they should be completely routed nets and then locked i have not had it run over keepouts make sure your 'board' via size makes sense relative to your width and space and routing channel Dennis Saputelli Ted Tontis wrote: > > I have some time on my hands and I figured I would mess with the > auto router. I have been running into some problems, no surprise. I am > manually fanning out my components and trying to have the auto router route > the rest. This is the way I have been setting up the design rules. I set up > the routing layers for a net class to route on the bottom layer in a > horizontal direction, I set the top layer to not used, and a board scope of > any direction on the bottom layer with the top layer selected as not used. I > throw up some layer defined keep outs. The tracks I set up are all locked by > selecting auto routing all and only checking lock traces. I try to auto > route area, and all I get is a bunch of garbage. Protel still try's to route > over the keep out area, also Protel is not content with auto routing the > area I have selected it's under worked and starts routing everything else. > Any direction that I can get would be great. I am running Protel 99SE and > WIN2K SPK6 > > Regards, > > Ted Tontis C.I.D. > Engage Networks > 316 N. Milwaukee Street > Suite 214 > Milwaukee WI, 53202 > PH 414-273-7600 ext. 7607 > FX 414-273-7601 -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Autoroute error message
The board can still be auto routed with arcs on the keep out for the border, it just ignores them. Have you run the drc, or check to see if you have any violations on the navigation panel. What was the last trace size that you placed? If I remember right that auto router will default to the last track size you placed. Ted -Original Message- From: Mark E Witherite [mailto:[EMAIL PROTECTED]] Sent: Thursday, January 24, 2002 4:45 PM To: Protel EDA Forum Subject: Re: [PEDA] Autoroute error message Do you have any arcs in your keep out layer? At 02:13 PM 1/24/02 -0600, you wrote: >I know I have seen this error before but I can't remember how to fix it. >When I try to start the autorouter it tells me that one or more connections >cannot be routed due to design rule violations. I have checked the border of >the board and it is fine there are no gaps and the outline is on the keepout >layer. I haven't seen this in a long time and am at a loss to figure it out. >Any help would be appreciated. >Nick Cobb > Mark Witherite C.I.D. Assistant Research Engineer Astronomy & Astrophysics Penn State University 2565 Park Center Blvd Suite 200 State College, PA. 16801 email [EMAIL PROTECTED] telephone 814 865 9839 fax 814 865 9100 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Solder mask over via's
Afshin, To use the design rule go in the design rules, select manufacturing, select solder mask expansion, click add, select object kind, check via's, give the expansion a negative value, and click ok. Regards, Ted -Original Message- From: Afshin Salehi [mailto:[EMAIL PROTECTED]] Sent: Thursday, January 24, 2002 3:30 PM To: Protel Forum Subject: [PEDA] Solder mask over via's Hello all, I was wondering how I could have solder mask placed over all the via's on my PCB. Is there a design rule for the via's that allow you to select solder mask options? I saw a design rule for via size but not solder mask. All of my via's should be a different size than any pads so if it were necessary I am sure I could select them all and do a global change if that is the only way possible. Some of my via's are placed so close to pads after a route that I am afraid of bridging occurring when the PCB is soldered. Thanks to everyone for your continued help. Afshin Salehi DPS Telecom * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Auto router
I have some time on my hands and I figured I would mess with the auto router. I have been running into some problems, no surprise. I am manually fanning out my components and trying to have the auto router route the rest. This is the way I have been setting up the design rules. I set up the routing layers for a net class to route on the bottom layer in a horizontal direction, I set the top layer to not used, and a board scope of any direction on the bottom layer with the top layer selected as not used. I throw up some layer defined keep outs. The tracks I set up are all locked by selecting auto routing all and only checking lock traces. I try to auto route area, and all I get is a bunch of garbage. Protel still try's to route over the keep out area, also Protel is not content with auto routing the area I have selected it's under worked and starts routing everything else. Any direction that I can get would be great. I am running Protel 99SE and WIN2K SPK6 Regards, Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] schematic lib ?
I was afraid I was going to have to do this. Our engineers have selected a hand full of components that they are going to be using on all of our new designs. All the components picked come in three or four different package formats, which depending on the design are going to be used one time or another. So now I have to flag each component for each foot print. Thank you for the input, Ted * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] schematic lib ?
I have a component that is a 176 pin micro. I have a few choices between the types of packages I can choose from. One of the choices is a BGA, the other TQFP. Is there a way to number the schematic part to work with both the BGA alpha numeric and TQFP numeric? Or am I going to have to renumber the BGA to be numeric? Thank you, Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Design Rules
Mr. Lomax wrote: > I do not understand how using a layer 30 courtyard will help, unless you > also move the reference designators to layer 30. Perhaps Mr. Tontis will > give us further detals. However, this will, if I my expectation is correct, > check the bounds box for the text, not the actual text strokes. I do not add the designator to mid layer 30. When placing a component to close to another component the DRC picks it up right away turning it green. This now reminds me that I am to close to another component, I use this as a simple reminder to keep an eye out. There is nothing that can replace checking your work with a gerber viewer. Regards, Ted -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Wednesday, January 02, 2002 12:32 PM To: Protel EDA Forum Subject: Re: [PEDA] Design Rules * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Design Rules
The best and quickest way I have addressed this problem is to use mid layer 30, I place a courtyard around the component just outside the pads. I use a .5mm grid, it is an electrical trace now you can use the DRC to keep your spacing between your pads and overlay. The only draw back is you have to update all your library's. When you generate the gerber files just deselect that layer. Regards, Ted -Original Message- From: Ian Capps [mailto:[EMAIL PROTECTED]] Sent: Wednesday, January 02, 2002 12:25 AM To: Protel EDA Forum Subject: Re: [PEDA] Design Rules Becouse Protel is using text it is unlikely that it can differentiate between the individual tracks that make up the characters. Let's face it you can pass DRC with a hole that is larger than on dimension of a pad so long as the other dimension has adequate annular ring. I have only just rreceived the 99SE so I haven't had a chance to play much but I did notice that Camtastic will do a silkscreen clip. This will ensure that there is no overlay on pads but the result can look pretty crappy if you are not careful. If in doubt tell the fab shop that you require silk screen clipping as their software will do it without any problems. Ian Capps - Original Message - From: "Anthony Whitesell" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Saturday, December 29, 2001 12:17 AM Subject: [PEDA] Design Rules > > Does anyone know if it is possible (or how to) set a design rule to check > between the overlay and the soldermask layers? If you place a designator > over a pad or via then it does not appear correctly on the finished PCB. I > have simplified the solution to check the reference designators versus the > [inverted] soldermask of the same side and make sure they don't overlap. I > was hoping to automate the process with a design rule. Any ideas? > > Anthony Whitesell > Sunrise Labs > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fwd: Protel 99 SE Training Manual now available for do wnload
I was told that the year starts when you upgrade, so not everyone will have to make there ATS payment at the same time. Regards, Ted -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Thursday, December 13, 2001 5:21 PM To: Protel EDA Forum Subject: Re: [PEDA] Fwd: Protel 99 SE Training Manual now available for do wnload I suspect the P99SE clients that are eligdable for free support will be offered an upgrade to Pheonix. These clients are now no longer P99 clients but Pheonix clients with 1 years free support. Now this new Pheonix will be version 1 with all the bugs associated with new release. I bet the service pack for this will be delayed and released after the 1 year so to receive it you will have to pay ATS support fee. Altium is now a marketing company and no longer the engineering company that won the respect of the community. Clive B "Ted Tontis" <[EMAIL PROTECTED]> on 12/14/2001 01:25:59 AM Please respond to "Protel EDA Forum" <[EMAIL PROTECTED]> To: "'Protel EDA Forum'" <[EMAIL PROTECTED]> cc:(bcc: Clive Broome/sdc) Subject: Re: [PEDA] Fwd: Protel 99 SE Training Manual now available for do wnload * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Altium Total Support Brochure
I just talked to a sales rep. regarding the 20% discount. It is for 98 users only, they get 20% off the 99SE price and one year of ATS. They have to pay the full price for Phoenix when it is released. regards, Ted -Original Message- From: Frank Gilley [mailto:[EMAIL PROTECTED]] Sent: Thursday, December 13, 2001 3:30 PM To: Protel EDA Forum Subject: Re: [PEDA] Altium Total Support Brochure At 03:34 PM 12/13/2001 -0500, Abdulrahman Lomax wrote: >Right now upgrade from 98 to 99SE is $1595 *and it includes ATS, i.e., the >next release should be free. > >The price goes back up Jan 1 to $1995, and there are indications that it >will go up again when Phoenix is released. Do you know for a fact that upgrading from 98 to 99SE will get you the next release free due to ATS membership? Or is this speculation? Other 99SE members (us) are supposedly grandfathered ATS members, and you can bet they will charge us for the next release. Frank Frank Gilley Dell-Star Technologies (918) 838-1973 Phone (918) 838-8814 Fax [EMAIL PROTECTED] http://www.dellstar.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Fwd: Protel 99 SE Training Manual now available for do wnload
Re: [PEDA] Altium Total Support Brochure
I recently sent an e-mail to Altium regarding the Phoenix release, asking if it would support HDI designs. If you really want to laugh take a look at the response they gave me in regards to why "ATS" was started. "Protel has made this decision based on request from our current customers. Our customers and their designs are more sophisticated and so they are requesting strong support. I hope this helps." No this does not help and it still did not answer my original question, worst of all Altium is telling me that it is my fault that "ATS" is here. I did not ask for it, did anyone else ask? Personally Altium should be trying to get on our good side regarding support. Most users of Protel who know about this group, go to the group first to get answers. "ATS" can not offer better support than this list, unless Phoenix is that much of a change. If you ask me Altium is looking more like a car sales person than a software company. No one is jumping on the "ATS" ride and I think Altium is freaked, that's why the 20% discount. If no one buys into "ATS" this last Q then come Q1 it will be 50% to 60% discount. >Dear Ted, >The Altium Total Support is maintenance/support package. The ATS includes version releases, service packs, fixes. >unlimited phone, email and fax support(no maximum) with dedicated Protel product technicians as well as newly maintained and >always update libraries. >I realize that you are use to getting your support for free. With the purchase of a new license you would get 1 year of >free support. Then if you wanted to continue you would be required to purchase the support. Protel has made this decision >based on request from our current customers. Our customers and their designs are more sophisticated and so they are >requesting strong support. >I hope this helps. > Altum has not given me any information on regards to what total support is. I can not go to management and tell them "we >need to invest in Altum's Total Support to be more productive." They are going to ask me what it is that I am investing in, >what am I going to tell them "I don't know"? Awhile back some of the engineers here where pushing upper management to change >software packages, they really did not like the way Protel was working out for them. They where pushing for Cadence or >Mentor, which they feel is better than Protel. I was able to win the battle by telling management that service packs and >support was free, however this has now changed and the engineers are beating the war drum again. I have nothing to give >management in regards to buying into Total Support, I cant tell them that it is going to be a good investment because no >knows. One only needs to read the independent Protel group to see I am not the only one who feels this way, not everyone >shares the excitement that Altum is showing on the Phoenix release. With past track records regarding bugs, fixes, and >support there is no justification to make an investment in a product that has no weight. Most of Protel's existing >customers, like my self are sitting on the fence post regarding Total Support, and most can not afford to make the Total >Support jump. Without knowing what it is that we are getting I can not force management to make that investment. >Regards, >Ted Tontis C.I.D. >Engage Networks >316 N. Milwaukee Street >Suite 214 >Milwaukee WI, 53202 >PH 414-273-7600 ext. 7607 >FX 414-273-7601 >Dear Ted, >As of 12/10/01 the only thing that has been announced is the commitment to a new version release in Q1. I know the software >is still going through bata and no details have been released. >For the month of December Protel 99SE has a promotion of a 20% until 12/28/01. This is not to get rid of product but >silmply a way to get the customer into the software and prepared for the next release. The first year that you own the >product all maintenance and technical support is free. >Please let me know what you think. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] URGENT!!!
make sure that remove dead copper is not selected. Ted -Original Message- From: Sean James [mailto:[EMAIL PROTECTED]] Sent: Wednesday, December 12, 2001 2:28 PM To: Protel EDA Forum Subject: [PEDA] URGENT!!! What would keep a polygon pour from not forming if A. There are no keepouts. B. There are no areas present to create "dead" copper pours. C. I am pouring over the same net. Sean James PCB Designer Telecast Fiber Systems, Inc. 102 Grove Street Worcester, MA 01605 (TEL) 508.754.4858 x33 (FAX) 413.541.6170 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Blind and buried via's Mayhem
Have you considered using micro vias? You can place them in the pads and solder right over them, you will never see them on the top layer. Also laser drilling is less expensive than mechanical drilling. Regards, Ted -Original Message- From: Jeff Stout [mailto:[EMAIL PROTECTED]] Sent: Thursday, November 29, 2001 5:17 PM To: Protel EDA Forum Subject: Re: [PEDA] Blind and buried via's Mayhem [snip] > At 03:53 PM 11/29/2001 -0600, Jeff Stout wrote: > >1. Can I use a hole pair that goes through the prepreg, but > >does not go through the core material above or below that > >level? I just don't see how it can be manufactured. > > No. At least not to my knowledge. My understanding of the process is that > basically you can only use blind vias on cores. You may not connect cores > to one another except with full through-hole vias. > Exception: If you have 2 internal cores you can prepreg these together and > then drill through them... plate to connect these cores together, and then > prepreg more cores to the outside of that unit, through-hole drill the > whole thing and plate again, etc, etc, etc. > So if you want to connect two layers across a layer of prepreg, your stuck with having holes on the outside of the two cores surounding the prepreg. Well t'aint that shitty. So in a PCB, with a stack up like: T --C-- 1 --P-- 2 --C-- 3 --P-- 4 --C-- B It's only possible to manufacturer: T -> 1 T -> 3 T -> B 2 -> 3 2 -> B 4 -> B Without having some extra "through holes" somewhere, of course. I think I'm beginning to understand this. Jeff Stout [snip] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Windows XP
I haven't found any yet, but I really haven't had the chance to test it against a big design. Ted -Original Message- From: Wayne Trow [mailto:[EMAIL PROTECTED]] Sent: Tuesday, November 20, 2001 2:54 PM To: [EMAIL PROTECTED] Subject: [PEDA] Windows XP Hi All Just wondering if anyone uses Protel99SE on WindowsXP ? Are there any problems? Wayne Trow PCB Design Technician Gallagher Group LTD Hamilton New Zealand * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Copper Calculations
he writes articles for PCD magazine. Here is there web sight www.pcdmag.com very helpful. Ted -Original Message- From: Stephen Smith [mailto:[EMAIL PROTECTED]] Sent: Friday, November 16, 2001 9:05 AM To: Protel EDA Forum Subject: Re: [PEDA] Copper Calculations That's very helpful, thanks. But, one more thingWho is Chris Robertson? Steve -Original Message- From: Ted Tontis [mailto:[EMAIL PROTECTED]] Sent: 16 November 2001 15:06 To: 'Protel EDA Forum' Subject: Re: [PEDA] Copper Calculations Minimum Conductor Widths For PCBs Temperature Rise Above Ambient For 1/2 oz Copper Amperage Ambient Temperature Conductor Width 1 AMP 45C (113F) .013 1.5 AMP 45C (113F) .025 2 AMP 45C (113F) .033 3 AMP 45C (113F) .050 4 AMP 45C (113F) .073 5 AMP 45C (113F) .110 6 AMP 45C (113F) .125 7 AMP 45C (113F) 1.45 10 AMP 45C (113F) 2.25 This information is from Chris Robertson's web page. Hope this helps. Regards, Ted Temperature Rise Above Ambient 1 oz Copper Amperage Ambient Temperature Conductor Width 1 AMP 45C (113F) .008 1.5 AMP 45C (113F) .012 2 AMP 45C (113F) .016 3 AMP 45C (113F) .025 4 AMP 45C (113F) .040 5 AMP 45C (113F) .050 6 AMP 45C (113F) .065 7 AMP 45C (113F) .080 10 AMP 45C (113F) 1.20 Minimum Conductor Widths For PCBs Temperature Rise Above Ambient 2 oz Copper Amperage Ambient Temperature Conductor Width 1 AMP 45C (113F) .003 1.5 AMP 45C (113F) .006 2 AMP 45C (113F) .008 3 AMP 45C (113F) .013 4 AMP 45C (113F) .020 5 AMP 45C (113F) .025 6 AMP 45C (113F) .030 7 AMP 45C (113F) .040 10 AMP 45C (113F) .060 -Original Message- From: Stephen Smith [mailto:[EMAIL PROTECTED]] Sent: Friday, November 16, 2001 8:07 AM To: Protel EDA Forum (E-mail) Subject: [PEDA] Copper Calculations Does anyone know a simple way of calculating copper track size (in, mm), when you know the amount of copper (in, ounces), and the current flow (in, Amps)?? I've never had to do any high current circuits before, so any help much appreciated. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Copper Calculations
Minimum Conductor Widths For PCBs Temperature Rise Above Ambient For 1/2 oz Copper Amperage Ambient Temperature Conductor Width 1 AMP 45C (113F) .013 1.5 AMP 45C (113F) .025 2 AMP 45C (113F) .033 3 AMP 45C (113F) .050 4 AMP 45C (113F) .073 5 AMP 45C (113F) .110 6 AMP 45C (113F) .125 7 AMP 45C (113F) 1.45 10 AMP 45C (113F) 2.25 This information is from Chris Robertson's web page. Hope this helps. Regards, Ted Temperature Rise Above Ambient 1 oz Copper Amperage Ambient Temperature Conductor Width 1 AMP 45C (113F) .008 1.5 AMP 45C (113F) .012 2 AMP 45C (113F) .016 3 AMP 45C (113F) .025 4 AMP 45C (113F) .040 5 AMP 45C (113F) .050 6 AMP 45C (113F) .065 7 AMP 45C (113F) .080 10 AMP 45C (113F) 1.20 Minimum Conductor Widths For PCBs Temperature Rise Above Ambient 2 oz Copper Amperage Ambient Temperature Conductor Width 1 AMP 45C (113F) .003 1.5 AMP 45C (113F) .006 2 AMP 45C (113F) .008 3 AMP 45C (113F) .013 4 AMP 45C (113F) .020 5 AMP 45C (113F) .025 6 AMP 45C (113F) .030 7 AMP 45C (113F) .040 10 AMP 45C (113F) .060 -Original Message- From: Stephen Smith [mailto:[EMAIL PROTECTED]] Sent: Friday, November 16, 2001 8:07 AM To: Protel EDA Forum (E-mail) Subject: [PEDA] Copper Calculations Does anyone know a simple way of calculating copper track size (in, mm), when you know the amount of copper (in, ounces), and the current flow (in, Amps)?? I've never had to do any high current circuits before, so any help much appreciated. Steve * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] imported Gerber info missing
I am trying to import Gerber files into Protel, from Camtastic. I have no problems getting the files to generate, but there is a lot of information missing. The text is not complete and there are missing tracks. I have no idea what I am doing wrong. I have tried everything I could think of. Changing the export to metric, using arc's, convert polygons to vector fills, type absolute and incremental, and zero suppression. Is there some thing I am missing? Any help would be greatly appreciated. Thank you, Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel Test-point features not working
Chris, I am no expert on test points, but I have added them to existing boards. I have found that the test point grid has to match the via grid. Try setting the grid to .001 mil and see if it works, you should get more test points to show up. As for the auto router and the test points I have no clue. Regards, Ted -Original Message- From: Chris Dopp [mailto:[EMAIL PROTECTED]] Sent: Wednesday, September 19, 2001 1:25 PM To: Protel EDA Forum Subject: [PEDA] Protel Test-point features not working To all, I have a oddly shaped small PCB (approx 55mm by 54mm in size). I have designed the PCB in Advanced PCB 2.8 because of technical problems I have encountered with Protel Design Explorer "PDE" PCB package (keyboard locking related to my Microsoft mouse, now resolved by disabling the wheel in Protel). For volume production reasons I have a need to use the test-point features of PDE to insert testpoints and then hopefully back annotate the resulting test points into my schematic data base, and produce a test point report for test fixture tooling. I have manually placed all components and routed using a snap grid of .1mm. PCB is targetted for a 3mil/3mil clearances bewtween different nets. I have beed unsuccesful in getting the "Find Test Point: feature to find any of my 25mil/13.5mil hole vias as test points. After working with Protel's tech support for many emails, they said it is out of the scope of their abilities to resolve. Also the Autorouter places test point unders components even though the check box is unchecked. I believe Protel tech support says this function does not work in the auto-router. Any info or direction to help me understand if theres a solution using Protel would be of much assistance. Regards, Chris Dopp Vista Imaging, Inc. 521 Taylor Way San Carlos, CA 94070 (650) 802-9685 tel (650) 802-0322 fax [EMAIL PROTECTED] www.vistaimaging.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pad with multiple holes surrounding it.
if one was to use a hole for mounting the PCB to a fixture, they might put plated through holes around the mounting hole for reinforcement. The extra copper in the vias around the hole would support more pressure in that area. I have never implemented this in a design, but I have seen articles on it. Regards, Ted -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 18, 2001 5:52 PM To: Protel EDA Forum Subject: Re: [PEDA] Pad with multiple holes surrounding it. At 02:22 PM 9/18/01 -0500, Ted Tontis wrote: >I believe he is trying to put supporting holes around the top of the PTH. I'd like to know what a "supporting hole" is, since holes remove physical support. Holes placed for additional ground connection would be likely to make only a negligible contribution under most circumstances; the pad, if it goes to a ground plane or copper pour, should be made direct-connect unless it is to be soldered. Holes surrounding a central hole going to a plane may remove connection to the inner hole unless they are direct-connect. A .125 hole direct-connect to a ground plane is equivalent to a trace almost a half-inch wide for a distance of perhaps 30 mils at most. In any case, if the original questioner will tell us in more detail not only what he wants but why he wants it, we'll have a better idea of what recommendations to make. When a way of doing a thing is not easy in a program like Protel, it is a clue (but certainly not a proof) that perhaps the thing is not a good idea. There are, obviously, exceptions; but it is much more common to see that the thing cannot be done easily because the users did not want it, and the users did not want it because it was not a good idea. So I'm just trying to find out what is the case here. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pad with multiple holes surrounding it.
I believe he is trying to put supporting holes around the top of the PTH. Ted -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 18, 2001 5:04 PM To: Protel EDA Forum Subject: Re: [PEDA] Pad with multiple holes surrounding it. At 10:36 AM 9/18/01 -0700, Afshin Salehi wrote: > I have been having a problem trying to create a pad with a .125 hole > and .225 pad size. I am trying to place six smaller holes on the pad > area of the large hole to create a screw hole with very hood through > board connection. I'm puzzled as to what Mr. Salehi wants to do here. A screw hole is a round hole and would be made with a single drill, i.e., a single pad. If one wants a slot, we could discuss that; with such a large drill size multiple drill hits side-by-side may be practical. (With smaller holes, overlapping holes can break drill bits). If you want through-board connection, presumably the pads will be assigned a net. If they are not, that is why a DRC error is coming up. Or another rule is being violated. Every component pad assigned a net should have a corresponding pin on the schematic; to be completely explicit, these pins should all have unique names (like MH1, MH2, etc.), but if all the pads have the same name and there is only one occurrence of that name in the net list, all the pads will be assigned that name. So if you must have multiple pads, it may be sufficient to give them all the same name. Note that if one is using the old Load Netlist method of bringing the netlist into the board, there is a bug still remaining with SP6 that can cause problems. As I recall, this does not happen when using the Update PCB command from schematic. So I recommend a little more discussion of this issue, or else we might be advising Mr. Salehi how to do something which might not be such a great idea. Perhaps I have failed to understand, wouldn't be the first time :-) [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Altera 144Pin TQFP Landing Pattern
You can set the grid in the lib. to be metric and when done adjusting the part switch it to a imperial grid and save it. The translation is made when you switch the grids. Ted -Original Message- From: Jon Elson [mailto:[EMAIL PROTECTED]] Sent: Friday, September 07, 2001 2:17 PM To: Protel EDA Forum Subject: Re: [PEDA] Altera 144Pin TQFP Landing Pattern [EMAIL PROTECTED] wrote: > All, > Thanks for responding. It looks like I have several paths to explore. > > 1. I was able to get IPC's website footprint generation tool to spit out a > footprint. > 2. Brian Gurlanick's QFP generator. > 3. Michael Scmitt provided a footprint he uses for the Altera part I'm using. > > I have an additional question. It looks like QFP footprints generally are > created with metric grids. Will I run into trouble when I use metric > footprints on an imperial grid board? The autorouter (and sometimes manual routeing, too) has a problem when there are many different grids on the same board. It doesn't cause any specific problem with a metric/imperial grid, just that they are different. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Mill-Max PLCC68 socket 940-99-068-24-000000
The part is a through hole correct? and has a 2 rows of pins for all 4 sides. If you have a ohm meter and a sample part, ohm it out. The pin 1 location on the socket should have a mark on it for pin 1. If you don't have a sample I would call Mil-Max directly. Regards, Ted -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: Friday, September 07, 2001 12:36 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Mill-Max PLCC68 socket 940-99-068-24-00 Jeff, here is my thought. Isn't the answer to that question dependant on the device that you plug into it? If you plug in a device and it is numbered A/B/C/D, does it make sense that the mating Mill-Max connector pins might be numbered W/X/Y/Z? If they aren't numbered the same then you need some form of table to note the cross connections. If you are inserting more then one device type and they are pin numbered differently, then you are hooped and you need cross reference tool of some sort somewhere. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: Jeff Adolphs [mailto:[EMAIL PROTECTED]] > Sent: Friday, September 07, 2001 10:13 AM > To: Protel EDA Forum (E-mail) > Subject: [PEDA] Mill-Max PLCC68 socket 940-99-068-24-00 > > > Good Day! Anyone know the pin numbering of Mill-Max PLCC68 socket > 940-99-068-24-00 ? > The Mill-Max PCB Layout does not show the pin numbering and I > do not have a > sample part. > > Have a good weekend! > > Regards, > Jeff Adolphs > Lake Shore Cryotronics, Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] what changed
Besides me does anyone else think that it is strange that the forum administrator is cracking down on what he/she believes to be off topic? This was never an issue before, so why now? Who is the forum admin? is it Protel/Altium? or is it some other EDA co. The message sent buy Mr. Potapoff was an on topic post, Is tech serv going to be the new world order censoring everything we say and deciding weather something can be posted or not? This also brings up the recent problems from yesterday, The errors everyone was receiving where stating that we where the problem, when in fact it was a router error. I find it interesting that the admin never sent a message that there was a problem and they where working on it, that would have been off topic and not posted on the forum. Thank you for letting me vent, Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] test
Below is the first message I had bounced. I rest my error count I don't know if that had anything to do with it. Ted > I just received the same message. This is the second time I received it this year. I brought this to the attention of the group when I first received it about 6/7 months ago. Our IT guy says it is because tech serv is trying to route through our server. Our e-mail server is set not to allow routing and there for tech serv receives a error every time they try to use us as a router. I would suggest at this time to talk to your IT guys and find out what your settings are for routing through your e-mail server. This forum is too important to me, so I just deal with it now. Tech serv had no answers for me the last time I brought it up to them, they most likely have no answer this time ether. Ted -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Thursday, September 06, 2001 12:49 PM To: Protel EDA Forum Subject: Re: [PEDA] test In a message dated 9/6/01 1:42:25 PM Eastern Daylight Time, [EMAIL PROTECTED] writes: > could someone let me know if my messages are getting out? > Well, this one got out to me. But I just got one of the bounce messages that I've seen from several users today. It seems TechServ has a problem at their end. Sure would hate to get unsubscribed - this list has been a lifeline at times. Steve Hendrix * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] removed from list
Seems as though I had an e-mail bounced from the techserv. Did anyone receive the e-mail I sent in response to the "removed from proteledaforum"? Thank you, Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] test
could someone let me know if my messages are getting out? Thank you, Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Removal From List
I just received the same message. This is the second time I received it this year. I brought this to the attention of the group when I first received it about 6/7 months ago. Our IT guy says it is because tech serv is trying to route through our server. Our e-mail server is set not to allow routing and there for tech serv receives a error every time they try to use us as a router. I would suggest at this time to talk to your IT guys and find out what your settings are for routing through your e-mail server. This forum is too important to me, so I just deal with it now. Tech serv had no answers for me the last time I brought it up to them, they most likely have no answer this time ether. Ted -Original Message- From: Walter Muth [mailto:[EMAIL PROTECTED]] Sent: Thursday, September 06, 2001 10:22 AM To: Protel EDA Forum Subject: Re: [PEDA] Removal From List Hi Jim same message here Walter Muth RBW Elektronik GmbH Jim McGrath wrote: > Hi All, > > Has Anyone else received this messege? Last time I got this messege > it was not my problem. I do NOT want to be removed from this list! > I received 20 messeges this morning and others since then. > Regards, > > Jim McGrath > CAD Connections, Inc. > > RESET-ERROR proteledaforum [EMAIL PROTECTED] > > -- > > Your mail address <[EMAIL PROTECTED]> will be removed > from the "proteledaforum" mailing list if has more > errors. > > It generated an excessive amount of bounced mails. > > If you have fixed this, please send back this message > to [EMAIL PROTECTED] to fix the problem, > it will reset your error counter to 0 for the > list <[EMAIL PROTECTED]>. > > Before sending this subscription request to > the server, please ensure that this problem has been > resolved. > > When in doubt, ask your system administrator > or send mail to "postmaster" at your domain > (right part of your email address after the '@'). > > The last one of those bounced mails has been quoted below : > > -- > > Brian Guralnick wrote: > > > Use my QFP generator, just enter the dimensions provided in Altera's Device Package > > Catalog. > > > > Sites: > > Altera package specs -> http://www.altera.com/literature/ds/dspkg.pdf > > > > Just copy this link location into your internet explorer address bar: > > ftp://ftp.point-lab.com/quartus/Public/ProtelUsers/ > > Take these 2 files: > > > > QFPfootprintGeneratorScript.bas - Protel ClientBasic script. > > QFPfootprintGeneratorScript.txt - added documentation. > > > > enter: " 36, 22, 0, 36, 22, 0.5, 0.27, 0.75, 1, 2, 0.04, 0 " for Altera's 144 pin > > TQFP > > > > If you want a thinner footprint, minimal pad meat, change: > > 0.27 -> 0.22 > > 0.75 -> 0.60 > > > > Goodluck. > > > > Brian Guralnick > > > > - Original Message - > > From: <[EMAIL PROTECTED]> > > To: "Protel EDA Forum" <[EMAIL PROTECTED]> > > Sent: Wednesday, September 05, 2001 4:21 PM > > Subject: [PEDA] Altera 144Pin TQFP Landing Pattern > > > > | Hi, > > | > > | I need a landing pattern for Altera p/n EP1K30TC144-2. The package is a 144 > > | Pin TQFP package. > > | > > | I typically use the recommended landing pattern from the manufacturer; > > | however, Altera only provides the physical dimensions of the part itself. I > > | attempted to use the land pattern calculator, on the IPC website, using these > > | dimensions, but the pad size was clearly calculated incorrectly (one > > | dimension of the pad was the width of the entire part). > > | > > | At this point, I think I'll return to the IPC website to isolate my problem. > > | I'd appreciate learning how others handle this situation. > > | > > | Thanks, > > | Steve Allen > > | > > | > > | > > | > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] standard lib.
I have a few components that I have imported into Protel for that standard lib. If anyone would be interested in looking at them and give some feed back I would like to hear from them. There are only a few components nothing major, small files. Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Camtastic or Protel?
a break away tab that is made up of multiple drills. kind of looks like a mouse took a bite out of the board. | | * * * * | | Ted -Original Message- From: Darryl Newberry [mailto:[EMAIL PROTECTED]] Sent: Thursday, August 16, 2001 2:39 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Camtastic or Protel? Pardon my ignorance...What's a "mousebite"? A cute name for a break-apart slot? > I'm thinking it might be good to add the support bars and mousebites in > Protel, then panelize in Camtastic and just connect the board together... Darryl Newberry Hardware Engineer Freedom Scientific, Inc 2850 SE Market Pl Stuart FL 34997 (561) 223-6443 http://www.freedomscientific.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Importing PADS
You can not import PowerPCB V3.5 you can however import v2.0. Another member from the list helped me import some files in to Protel we worked at it for over a week. I believe the problem was that V3.5 supports centered text where as v2.0 does not. Protel does not support the centered text. That's where I believe the problem falls, some problems I have had to deal with on the import. 1. Silk screen and mechanical and some tracks all became silk screen 2. some of the PTH did not have holes 3. lost the keepout I do not know if the same happens to PCB's as I am working on importing lib. hope this helped. Ted -Original Message- From: Wolfgang [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 14, 2001 8:37 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Importing PADS www.rsi-inc.com make a PADS to Protel converter, which is fully supported. Wolfgang -Original Message- From: Owain May [mailto:[EMAIL PROTECTED]] Sent: Tue, Aug 14, 2001 02:39a To: Protel EDA Forum Subject: [PEDA] Importing PADS I'm trying to import a PADS PowerPCB V3.5 layout file into Protel, but all I get is a couple of the components and a few nets plus a load of errors. The errors I'm getting are all roughly the same, although I can't find "CRLF" in the ASCII file at all. Error Loading Footprint :CR10NR Expected number in line: 2793 at position 0 and found this: **CRLF** Expected integer in line: 2793 at position 0 Expected integer in line: 2793 at position 0 Expected integer in line: 2793 at position 0 I can import V2.1 files with no problem. The Knowledge Base says that V3.5 files should also work. Anyone got any ideas? Thanks, Owain * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel 99 cannot auto-route BGA components
What is the ball pitch? There are ways to play with both track, via, and ball size to route the board with lots of room left to run tracks from out side the BGA. Is the ball grid causing you to go to the 10 layer count? what size vias are you using, what size tracks? If the ball grid has a lage number of pads keep an eye on your power and ground you may end up taking too much copper away with poor via placement (if power and ground are located in the center). With a 1mm pitch you should be able to fit two tracks between a pad using a 4/3 set up and 20mil pads and vias. You can go three layers deep for the fist layer and two rows there after. when using a 5/5 on a 1.27mm pitch 44 signals can be routed from the 7th row. Ted -Original Message- From: Ian Wilson To: Protel EDA Forum Sent: 8/13/01 6:53 PM Subject: Re: [PEDA] Protel 99 cannot auto-route BGA components On 11:58 AM 13/08/2001 +, [EMAIL PROTECTED] said: >I have been unable to autoroute a 10 layer design which has 2 fine grid >BGA packages. Protel support has not been able to assist me and has cause >a 3 MONTH delay of this design. Protel's auto-router simply locks-up or >does not initialize. The autorouter give no reason for the problem and >Protel is either unwilling or unable to address the problem. Therefore, I >am under the impression that there is a major software problem with >respect to the autorouter and BGA components. Has anyone else seen this >problem? If any other user has had this problem or know of a fix, PLEASE >contact me ([EMAIL PROTECTED]). Thanks you for any feedback. > >Loop. >Posted from Association web site by: Gerard Vanderloop Yes the Protel 99/99SE autorouter has problems - but 3 months delay. I could hand route a pretty large board in 3 months. And I know that others could double my throughput at least. With 2 BGAs and 10 layers to play with there must be a *lot* of other stuff on it. 3 months to lay out a board - OK you professional PCB designers what sort of size must we be talking about here - 2 m x 2m? :-) Not so sure about the etiquette of requesting replies by mail - in the Usenet world this is considered bad form. This forum is a bidirectional thing - "give a bit get a lot". Others have discussed routing strategies for BGA in the past. I did try to have look through the archive (http://groups.yahoo.com/group/protel-users-PEDA-Archive) but I could not find much there. and my own more extensive archive (going back years) did not show much of relevance. I do seem to recall someone saying they were having some success with autorouting BGAs. Was it Gordon Price? Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] ddb transfer failure ??
have you tried to repair the data base? Ted -Original Message- From: Robison Michael R CNIN [mailto:[EMAIL PROTECTED]] Sent: Monday, August 13, 2001 2:54 PM To: 'Protel EDA Forum' Subject: [PEDA] ddb transfer failure ?? hi everybody, well, i'm not having a banner day here. somebody else here needs to look at a pcb of mine in protel. since i'm using ddb's (it was either ddb's or not be able to read the footprints libraries) of course, there is no actual powsup.pcb. so i emailed him a 20MB ddb. we're still hosed... he tries to open it using the protel browse and gets an "access violation at address xxx in client 99SE.exe". what do i need to do so he can use the file? thank you, miker * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Naughty bits (from Benny Hill)
They do not go away. I brought this up to Protel when they released SPK6, that's when I noticed it. I would auto route a board and when finished hit unroute and it would leave floaters in different spots across the board. At first I thought it was just a fluke but I tried it again same thing, I also thought it was happening in the same locations. To my surprise it wasn't, I took a snap shot of the board and autorouted it again. When it was done I unrouted it those little floaters popped up again but in different spots. Ted -Original Message- From: Jon Elson [mailto:[EMAIL PROTECTED]] Sent: Monday, August 13, 2001 2:42 PM To: Protel EDA Forum Subject: Re: [PEDA] Naughty bits (from Benny Hill) Evan Scarborough wrote: > I get these "naughty bits" too using the same process and I see them in many > Protel generated gerber files from other designers. > > It seems to me that the auto-router leaves extra line segments after > "cleanup" (and it seems to be worse if the routing grid and the component > pad spacing are different and worse still if the difference is not an even > multiple of the grid or pad pitch). Since the autorouter has "cleaned up" > they are no longer linked to the routers part of the database so they no > longer are subjects for the un-route process just like any other manually > added copper. HUH? I don't think this is true (the not linked to the routed net in database). I'm pretty sure they do go away if you do an unroute! Next time I'm doing an autoroute, I'll try to verify that. But, I'm pretty sure they DO go away after an unroute. I know they ARE there after the autorouting. I hit lots of them when cleaning up. > I wind up manually cleaning these up it would be nice for these to go away. I wonder if there is a particular step in your work flow that causes them to get 'un-linked'. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Compactflash socket PCB footprint
I have 10 and they are all AMP foot prints. Sorry no JST. Ted -Original Message- From: Ted Tontis [mailto:[EMAIL PROTECTED]] Sent: Thursday, August 09, 2001 1:03 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Compactflash socket PCB footprint give me the foot print number you are looking for I have a hand full. Ted -Original Message- From: Darryl Newberry [mailto:[EMAIL PROTECTED]] Sent: Thursday, August 09, 2001 12:53 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Compactflash socket PCB footprint I have a JST # ICM-MA50H-SS52-1151 Darryl Newberry Hardware Engineer Freedom Scientific, Inc 2850 SE Market Pl Stuart FL 34997 (561) 223-6443 http://www.freedomscientific.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Compactflash socket PCB footprint
give me the foot print number you are looking for I have a hand full. Ted -Original Message- From: Darryl Newberry [mailto:[EMAIL PROTECTED]] Sent: Thursday, August 09, 2001 12:53 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Compactflash socket PCB footprint I have a JST # ICM-MA50H-SS52-1151 Darryl Newberry Hardware Engineer Freedom Scientific, Inc 2850 SE Market Pl Stuart FL 34997 (561) 223-6443 http://www.freedomscientific.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Logo's for FCC, UL and CE ?
check out www.ce-mag.com Ted -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: Thursday, August 09, 2001 11:38 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] Logo's for FCC, UL and CE ? Gisbert, I am not a CE compliance expert and I do not have access to the statement from the CE group any longer (former life with a different employer). However the statement that I read clearly and specifically stated that computer PSUs and other similar PSUs could not bear the CE marking. It also stated that all such PSU manufacturers should cease putting such markings on their equipment. That is all that I can state, you can argue with it all you want but it is a pretty clear statement directly from the CE governing bodies/group. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: Thursday, August 09, 2001 5:37 AM > To: Protel EDA Forum > Subject: Re: [PEDA] Logo's for FCC, UL and CE ? > > > Not quite correct, Brad. It is not illegal, to place a CE > mark on a power > supply, it only is not necessary, as the power supply will > not work for its > own, but only together with e.g. a PC. The complete system > has to carry the > CE mark, but system designers often ask for the components > they implement > to carry a CE mark also, in order to get proved that the > single components > (boards, power supply, drives, etc.) passed an EMC test. > > Regards, > > Gisbert Auge > N.A.T. GmbH * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Signal Integrity dialog locks up.
Correct me if I am wrong but Protel just started using IBIS models SPK6 for there signal simulation. Ted -Original Message- From: Mike Ingle [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 3:27 PM To: Protel EDA Forum Subject: Re: [PEDA] Signal Integrity dialog locks up. Hyperlynx sells a signal integrity/emi tool that is supposed to be great. I Use it before layout only, to set trace widths and look at signals vs diferent termination schemes. I have yet to successfully use the signal integrity tools in Protel. They don't seem, to be its shining star. The basic layout, and auto-router are OK, but certainly not up to Specctra standards. In summary, I think that the schamtic entry and board layout functionality of Protel is as good as anything I have seen, and by reading the correspondence on this list would say that the more expensive packages are not better in this respect. On the other hand, the addition of Specctra is wise for auto-routing. Do any other basic layout packages do a better auto-routing job? Just as a place to say this, I wish that there was a way that good FPGA tools were integrated w/ the schematic capture, package (w/ good footprints avail for layout). I spend most of my time enterering 200+ pin symbols into the schematic library, just to have to change them manually when I rev the part. mike -Original Message- From: Darryl Newberry [mailto:[EMAIL PROTECTED]] Sent: Tuesday, August 07, 2001 12:49 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Signal Integrity dialog locks up. OK, thanks everybody for your input on this issue. The list is a really great resource. The reality is I have about 6 board designs that have to go out for fast turn proto this week and hopefully go into a commercial UL/FCC/CE/USB ready product by September. I don't know what all YOU people do all day long, but my boss doesn't want me to sit on my fat hairy ass for hours waiting for $8000 bloatware to complete basic signal analysis. (No offense to those whose bosses do--and please tell me where to send my resume! ;-) ) In summary, after using Protel for about 4 weeks to TRY to get a lot of real work done, I have formed the opinion that it just basically sucks--lots of cutesy trees, tabs, windows, icons and menus, lots of feature-itis, but not much real engineering guts or ease of use. THE EMPEROR HAS NO CLOTHES!!! And yes I CAN talk because I've spent the last 10 years designing various commercial products with P-Cad, PADS, Accel/Tango EDA, and now Protel. About the only positive thing I can say about Protel right now is that I am glad that I wasn't the engineer who recommended purchasing two seats. Unfortunately I am more or less forced to use it. OK, it _is_ better than Xacto knife, Bishop Graphics, and a light table. ;-) My apologies to those who have an irrational emotional attachment to Protel. When I commit , I want results. I know it's not an apples-apples comparison, but Specctra V10 routed the entire board 100%, in 5 passes over 2 layers, with more or less fab-ready results, in about 20 seconds, using the default configuration. This gave me a warm fuzzy feeling, even when considering we blew almost $11K on it with all the bells and whistles. Now for another couple of questions: 1) Can anybody recommend a professional level SI/EMI simulator add-in/on that integrates with either Protel or Specctra--one that actually works? 2) Since I have to keep on using Protel, should I get a dual CPU workstation? What specs for W2K? Darryl Newberry Hardware Engineer Freedom Scientific, Inc 2850 SE Market Pl Stuart FL 34997 (561) 223-6443 http://www.freedomscientific.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] a lib. for everyone
I would like to try and stay with Wind Rivers standards. They have already done most of the leg work on this subject. I know most have a lot going on and I wanted everyone to have time to look over some of the documentation on Wind Rivers setup, and comment on the possible problems or conflicts they may see in there setup. As for the one who should be leading the group on this matter, my intentions where to make this a group project and have everyone openly voice there opinion and ideas. Everyone's concerns should be addressed no matter what they are, is that not why this group was set up in the first place? ***(I vote no leader)*** (IMO) I do not believe one person should be the deciding factor for new ideas or possible revisions brought on by other users or them selves (it makes it look like one is trying to take credit for someone else's idea/work). Mind you this was not my idea. I got the idea from Tom Hausherr from Wind River, after I sat in one of his white paper sessions at the IPC designers council symposium. What he said struck a cord and I felt it would be a very helpful tool for everyone in the group, someone new to Protel, or another designer using another CAD pkg to shorten design time. Lets face it we all work with father time on or backs to get a project out in time. (step off the soap box) Thank you, Ted -Original Message- From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]] Sent: Thursday, July 26, 2001 11:04 AM To: Protel EDA Forum Subject: Re: [PEDA] a lib. for everyone On 11:10 AM 7/26/2001 -0400, Bagotronix Tech Support wrote: >Does anyone know if the wildcard character '?' >is acceptable in footprint names? Good question. According to a Windriver document (Getting20%Started.doc in the autocad directory), under the sub-heading "Pads software decal list defaults", item 3 states that the "?" is illegal, along with other "standard" illegal characters * < > ; , "Decals" are "footprints", yes? (i'm kinda ignorant of what PADS folk call footprints) I believe that Ted said he basically wants to follow the standards previously set by the folks at Windriver, who have already begun the process for the PADS community specifically, but also for the EDA community at large by virtue of their having already solved many of the administrative questions. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] EMC question
Greg, We are using the AM186 on one of our boards with a 25MHz crystal. What I did was put the crystal as close to the microprocessor and put a ground plane under the crystal that covered the traces and filters for the crystals on the top layer. I also made sure the traces where the same length. It help do the reduce the harmonics to pass CE. Ted -Original Message- From: Greg Olson [mailto:[EMAIL PROTECTED]] Sent: Thursday, July 26, 2001 9:41 AM To: Protel EDA Forum Subject: [PEDA] EMC question Hi all.. I've got a 2.5"x3.5" plug on daughterboard which contains my processor, memory, flash, etc... The processor is a 20MHz AM186 driven by a 20MHz crystal. I just had this system in for FCC EMC testing and found that the 20MHz crystal is bleeding its harmonics (especially 80MHz) all over everything! It's getting onto the IO lines from the daughterboard to the main board and from there onto just about every wire leaving the enclosure! Can anyone give suggestions as to the best way to isolate this clock signal in a relatively tight space? This is a 4 layer board, top layer signal, next layer ground, then Vcc then signal again. Thanks in advance, Greg Olson DSX Access Systems * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] a lib. for everyone
AJ If you get a chance look over the Defining a CAD library at www.pcbstandards.com and see what wind river has set up for there standards. I thought it would be a good idea to try to stay with there standards as we could use there libraries and they could use ours. It would cut development time down considerably. Ted -Original Message- From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]] Sent: Wednesday, July 25, 2001 12:35 PM To: Protel EDA Forum Subject: Re: [PEDA] a lib. for everyone On 10:03 AM 7/25/2001 -0700, Abd ul-Rahman Lomax wrote: >At 09:29 AM 7/25/01 -0500, Ted Tontis wrote: > >> As designers we sometimes have to make the impossible happen, and we >>do make it happen. So why then all the negative remarks? > >All I know is that if you want to accomplish something valuable, get used to it. It is *much* easier to sit back and find fault with a proposal than to work out how to make it successful, and most people, or at least a sizable number, take the easy way. Actually, based on the thread so far, your "observation" is false. The majority of respondants in this group have had positive comments. Only two or three found outright fault with Ted's Tontis' proposal and denied any possibility of its fruition or their eventual use of such a library. >Obviously, I can't stop users from discussing the issue here No, you can't. Thanks Mark. I would urge other readers/writers to avoid the splintering that Mr Lomax is engineering within this group. Remember the old Roman trick: Divide and conquer. aj * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] a lib. for everyone
I started the thread on this subject. I knew the size of this project was going to be large, that is why I posted the thread in the first place. I wanted to see if anyone else would like to help or even if anyone wanted to have a large library system that was free. My idea was to get everyone who wanted to try and shorten there design time and get there input and ideas. I do not have 8500 parts in on library please give me some credit. "I said that I am working on importing 8500 parts into Protel from another cad system." There are other designers doing this and they would most likely trade footprints for footprints. The scope of this goes further then here, and the possibility to increase the library could come from other designers or as Mr. Lomax stated help from Protel. I am sure Protel is following this thread closely, if we where to take up this project Protel would be able to say we have the largest certified free library. That would boost there sales to unbelievable numbers. As designers we sometimes have to make the impossible happen, and we do make it happen. So why then all the negative remarks? Ted * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] a lib. for everyone
Dennis, What I meant to say is that Protel offers up to 32 signal layers, therefore the fence would be located on the 30th signal layer. since this is a conductive layer you can set design rules or clearance constraints for your components. It would solve the silk screen pad violations, help in design spacing for test points, and rules for rework or placement. When you are done laying out the board turn that layer off and your fence is gone. Thus avoiding generating gerber data for that layer. Sorry I should have explained my self in more detail. Ted -Original Message- From: Dennis Saputelli [mailto:[EMAIL PROTECTED]] Sent: Tuesday, July 24, 2001 12:01 PM To: Protel EDA Forum Subject: Re: [PEDA] a lib. for everyone wow, what ambition! can you pls explain: > 2 There is a conductive fence on the lowest layer as to avoid part placement > conflicts a little more? lowest layer = bottom layer? and how does conductive help? Dennis Saputelli Ted Tontis wrote: > > The standards are all ready set. I do not have control of them, this task > was put into motion sometime ago. If you want to look at the standards you > can at www.pcbstandards.com . again I have no control over the set > standards. > anyone who thinks this can not be done is sorry to say wrong. We as > designers make libraries every day. If we where to stick to the standards, > follow them as they have been written, and everyone puts some time in the > project the end result will be one large library that everyone will be able > to uses. Just think of the amount of time you will save if you did not have > to make a library. How many of us have the same foot prints in different > designers .ddb, or have no real standard in there company and your library > is a free for all. > > Here is a list of standards. > > 1 All parts must be in metric. > 2 There is a conductive fence on the lowest layer as to avoid part placement > conflicts > 3 for through hole parts the center is located on pin 1 > 4 for SMT parts center is located in the center of the part > 5 each part has an assembly drawing > 6 parts naming i.e.. Small Outline Packages, 7.8mm Lead Span (Pitch 0.65mm) > SOP78- Pin Qty > > There are more but you get the idea. The end result will benefit everyone in > the group, I am doing this in my free time and I wanted to make sure that > people would be interested before I dig in and get my hands dirty. I am > currently working on translating 8500 parts into this format. Look over the > standards and give me as much input weather it be positive or negative. I am > also working on getting a forum started or get on the existing one as the > project extends it self. > > Ted > -- ___ www.integratedcontrolsinc.comIntegrated Controls, Inc. tel: 415-647-04802851 21st Street fax: 415-647-3003San Francisco, CA 94110 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] a lib. for everyone
-Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Tuesday, July 24, 2001 1:03 AM To: Protel EDA Forum Subject: Re: [PEDA] a lib. for everyone Mr. Lomax >What I forsee is a system whereby a user wishes to use a part which is not >in the library we have created. He builds it, and he submits it. The part >is posted as unvalidated. Another user, certified by the user group for >this purpose, might check the part. The status of that part becomes >"checked, not validated." And then users who use the part will report their >experience with it, particularly with actual fab and assembly. Reports >regarding the part are tallied and ultimately the footprint is >automatically given validated status because of a multiplicity of >validations and an absence of complaints. (If there are validations *and* >complaints, the matter becomes more complicated, I won't go into that now.) >The key to this will be making the submission and retrieval and validation >of parts *easy*, so that no user is unduly burdened. Protel might >definitely help with that part. Ultimately the reporting mechanisms might >be built into client, with a tool that sends a footprint on command to a >configurable address, together with comment text. Mr. Lomax You are right on the money this is how the validation works. when a part is designed it goes in a special file on the web sight as a "not validated part". When a designer or Protel (if where lucky) can validate the part the name of the person who validated it is put on the part and it is then moved to the validated folder. I believe there is a lock on the folders, We as designers can not change parts we post them and someone else moves them to the validated and not validated folders. Ted * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] a lib. for everyone
The standards are all ready set. I do not have control of them, this task was put into motion sometime ago. If you want to look at the standards you can at www.pcbstandards.com . again I have no control over the set standards. anyone who thinks this can not be done is sorry to say wrong. We as designers make libraries every day. If we where to stick to the standards, follow them as they have been written, and everyone puts some time in the project the end result will be one large library that everyone will be able to uses. Just think of the amount of time you will save if you did not have to make a library. How many of us have the same foot prints in different designers .ddb, or have no real standard in there company and your library is a free for all. Here is a list of standards. 1 All parts must be in metric. 2 There is a conductive fence on the lowest layer as to avoid part placement conflicts 3 for through hole parts the center is located on pin 1 4 for SMT parts center is located in the center of the part 5 each part has an assembly drawing 6 parts naming i.e.. Small Outline Packages, 7.8mm Lead Span (Pitch 0.65mm) SOP78- Pin Qty There are more but you get the idea. The end result will benefit everyone in the group, I am doing this in my free time and I wanted to make sure that people would be interested before I dig in and get my hands dirty. I am currently working on translating 8500 parts into this format. Look over the standards and give me as much input weather it be positive or negative. I am also working on getting a forum started or get on the existing one as the project extends it self. Ted * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] a lib. for everyone
Would there be any interest in a PCB footprint lib. with all the parts you would ever need for free. I ask this because I am working on trying to get a large lib. in Protel. It would have the silk screen, a fence that would be on the last electrical layer to avoid component placement conflictions, assembly art work, pin 1 id. All parts would be in mm I welcome any input towards this idea weather it be good or bad. Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] importing power pcb files
I checked the archive for a thread regarding this but its not there. I want to take a power PCB v3.6 file and import it into Protel. I was told at one time this could be done? Thank you, Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] importing power pcb files
I checked the archive for a thread regarding this but its not there. I want to take a power PCB v3.6 file and import it into protel. I was told at one time this could be done? How far back does the archive go? is there a more extensive one, or am I looking at the wrong archive? Thank you, Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Gerber specification
Yesterday there was a thread on file formats for PCB manufacturers. Here is where you can find the gerber specification in .pdf format. http://www.barco.be/ets/data/rs274xc.pdf Regards, Ted Tontis C.I.D. Engage Networks 316 N. Milwaukee Street Suite 214 Milwaukee WI, 53202 PH 414-273-7600 ext. 7607 FX 414-273-7601 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] file formats for PCB manufacturers
I was at that same IPC designers conference. It was not a IPC conference but it was sponsored by the designers council which does not have a direct affiliation to IPC, they are there own entity, and just carry the IPC name. There where two topics that related to data transfer, one by Deter Bergman outlining GEN-CAM which is a internet based data transfer. I will not go into great detail on it but if interested here is the web sight www.gencam.org you probably will get a better description on what it really is. The other was from Patrick McGoff from Valor ODB++. The support for dropping gerber data is strong and it is slowly gaining support from the bare board manufactures. Right now we send gerber data for the bare board, to my understanding they basically have to relayout the board in there cam system to get what they need to produce the board. They are basically repeating what we have just done, and some times that's where changes or accidents could have been made. Tom Hausherr was a speaker on an unrelated subject but gave a actual testimony that a reputable board manufacture in TX has a bulletin board with CO. records for the quickest a board has been layed out. For gerber data it is 4 hours ODB++ 1 hr, when you look at that and consider the above the push for smart data is pretty good. It all comes down how fast do you want it, and can it cut the price of production. Just my 2c Ted -Original Message- From: Jim McGrath [mailto:[EMAIL PROTECTED]] Sent: Thursday, July 19, 2001 3:37 PM To: Protel EDA Forum Subject: Re: [PEDA] file formats for PCB manufacturers Brad, Unfortunately it has been my experience that IPC = Dollars. Maybe they have a vested interest and just want another thing to charge for. That's my take anyway. Regards, Jim McGrath CAD Connections Inc. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] 20H rule, Planes etc (Ex: perimeter stitched ground vi as question)
I never heard of the 20H rule, So I did a search on it. I found some very interesting articles on the subject, while I was searching I came across a article on X2Y technology. Has anyone used any of these devices? If so do they work as described and offer differential impedance within or close to the X2Y component? Ted -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: Thursday, July 12, 2001 7:55 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] 20H rule, Planes etc (Ex: perimeter stitched ground vi as question) Bruce, this is the manner in which I understand this issue. If I am wrong please correct me, I don't design antennas for a living and know very little about such. I do know that I have read certain descriptions of these problems and the proposed solutions but we all know there are bad solutions backed up by specific experimentations that prove the solution. This is the theory that I would apply to the situation. The manner that planes do not have noise fields between them is achieved 'theoretically' because you have coupled your planes together to near perfection through all of your properly selected, distributed and positioned power supply bypass capacitors. Effectively reducing the differential AC potentials between your planes to "0". Now that is the perfect world which doesn't exist but the real world differences should be relatively small if you have done your power distribution design correctly. Would the application of this to a trace (running parallel to your plane edge) not be exactly the opposite circumstance? There you have definite potential difference between the trace and the plane, much larger differentials then between your two planes. And thus if differentials between two planes with a little noise causes a dipole antenna effect, why would a trace with significantly larger differential not cause the same effect only stronger for the same relative length of the trace against the plane edge? This seems very clear to me but then I don't design antennas so what do I know. I only know that the article I read about traces and the 20H rule to plane edges most definitely showed the desired effect in the results arrived at with the field solvers. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: Bruce Walter [mailto:[EMAIL PROTECTED]] > Sent: Thursday, July 12, 2001 4:54 PM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] 20H rule, Planes etc (Ex: perimeter > stitched ground > vi as question) > > > My understanding of the 20H rule, was with regard to planes. > > If the planes have noise fields between them (I don't know > how this can be > avoided, regardless of component/trace/via placement), when > the planes end > equally at the edge of the board, this makes a nice dipole > antenna, and the > noise radiates off the edge of the board in a nice wide > pattern like you > would want from a dipole. > > By applying the 20H rule, you distort the field between the > two 'poles', and > the effective radiation is greatly reduced as this is a very > poor antenna. > > How well this applies to traces over a plane near the edge of > the board, I'm > not sure, but I would imagine the effect would be local, and > would only be > significant if there were a strong field between the two > conductors (poles). > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] "Trace" jumpers generate DRC violations
I tried it in SP5 and it didn't work I also just tried it in SP6 no go. There must be a dummy safe guard to prevent a person from shorting the nets completely. It would be great to just left click the track and decide weather to allow shorting or not. It's safe and easy. Where is the wish list located, I want to make a wish :) Ted -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: Thursday, July 12, 2001 3:38 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] "Trace" jumpers generate DRC violations Well Ted it is supposed to be possible through the Short Circuit Constraint in the Other Design Rules Tab. Last anybody ever tried it, it still didn't work but that was a little while ago. That might have been before SP6, I don't remember. Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -----Original Message- > From: Ted Tontis [mailto:[EMAIL PROTECTED]] > Sent: Thursday, July 12, 2001 1:29 PM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] "Trace" jumpers generate DRC violations > > > You would hope that with as many people who have had this > problem or needed > a work around, Protel would realize that they should add > something to the > design rules. Possibly a design rule that lets you have a > zero clearance > between a net. Or the ability to open the track attributes > and check a box > that lets you short them, without a DRC error. > > Ted > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] "Trace" jumpers generate DRC violations
You would hope that with as many people who have had this problem or needed a work around, Protel would realize that they should add something to the design rules. Possibly a design rule that lets you have a zero clearance between a net. Or the ability to open the track attributes and check a box that lets you short them, without a DRC error. Ted -Original Message- From: Brad Velander [mailto:[EMAIL PROTECTED]] Sent: Thursday, July 12, 2001 3:18 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] "Trace" jumpers generate DRC violations Steve, you can go to the Protel Yahoo group FAQ and there is a detailed methodology for accomplishing this task that was designed by Abd ul-Rahman. It involves placing two pads so close together that they are shorted because the gap cannot be etched away. Then you have to do one rule which stops this virtual short from causing violations. This methodology should at least tell you how to accomplish your particular pattern using similar means. URL: http://groups.yahoo.com/group/protel-users/files/protelfaq.html#work-arounds search for the section titled "solder jumper and cut patterns" by Abd ul-Rahman on 2000-08-21 01:53:22 PM Brad Velander, Lead PCB Designer, Norsat International Inc., #300 - 4401 Still Creek Dr., Burnaby, B.C., V5C 6G9. Tel. (604) 292-9089 direct Fax (604) 292-9010 website www.norsat.com > -Original Message- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] > Sent: Thursday, July 12, 2001 1:03 PM > To: Protel EDA Forum > Subject: [PEDA] "Trace" jumpers generate DRC violations > > > Protel is doing its job. I'm looking for a better way to do my job. > > I have a footprint which performs as a jumper for me. That > is, two pads > connected together by a trace. My schematic symbol for this > part is two pins > with different numbers. > > When I run a DRC on the board, Protel sees these pins shorted by the > footprint and generates errors because the schematic doesn't > have the two > pins connected. In fact, it generates Short Circuit and > Clearance Constraint > errors for each part. I'm forced to sort through each of > these errors. It > takes time and I risk the possibility of missing a real problem. > > I considered wiring the two pins of my schematic symbol > together; however, > this wouldn't produce my desired result. I want to connect > the two points > through the footprint I created. Further, if the connection > needs to be made > to a plane then Protel would automatically connected all the > points directly > to the plane. > > Is there another option? or Do I just need to suck it up do a > good job > reviewing these connections manually? > > > Thanks, > Steve Allen > Project Engineer > Manufacturing Services, Inc. > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
Mike, What standards did you purchase? I believe that if you are a IPC designer council member you can only purchase standards, visit seminars, and use your coupon on subjects related to design. So assembly stuff is out. Abd ul-Rahman, I just attended a IPC cert. course. There where a few people from Motorola, Northrop, and other companies that have defense contracts with the government. They told me that all of there designers have to be IPC cert. and that the MIL. standards are slowly being replaced by IPC standards, per some of there contracts. Most had been in the business for more than 15 years with feeling the need to be cert. Deter was our instructor and he had stated that in the future all designers will have to be cert. before they can get a job. Honestly I cant put much faith in information from some one who works for IPC regarding this information. By the way the advanced IPC cert. is going to be bataed this year. Ted -Original Message- From: Mike Reagan [mailto:[EMAIL PROTECTED]] Sent: Tuesday, July 10, 2001 6:23 AM To: Protel EDA Forum Subject: Re: [PEDA] Layer Stackup Info. I know what the website says, I also know what my hard earned money says... I just purchased manuals about 2 months ago and had to pay full price.Read my last post again , The IPC will not accept your coupon unless you are full member of the IPC, however they did honor the coupon from the designer's council in previous years. Mike Reagan - Original Message - From: Abd ul-Rahman Lomax <[EMAIL PROTECTED]> To: Protel EDA Forum <[EMAIL PROTECTED]> Sent: Tuesday, July 10, 2001 1:38 AM Subject: Re: [PEDA] Layer Stackup Info. > At 08:55 PM 7/9/01 -0400, Mike Reagan wrote: > > >I would like to correct you about the discount IPC offers. The coupon they > >issue to the designers council members is not redeemable, you must be an IPC > >member not a member of the designers council. They must have started this > >policy this year because I redeemed my coupons in the past, but his year > >they did not honor it when I purchased additional manuals. Have they > >honored yours? I had to pay full price. > > From the Designer's Council web site: > > "Free Designers Council Membership! > > Did you know that when you join or renew your IPC Designers Council > membership we give you a $50.00 coupon to be used towards attending a > workshop or seminar or the purchase of IPC documents? This is like getting > your IPC Designers Council membership for free! Also, up to three coupons > can be saved up to use towards seminars or workshops. That's $150.00 off > the price of a class! These are just some of the value added benefits that > Designers Council members receive." > > The DC site implies that one may "Save money on design by using IPC design > standards," listing this as a benefit of membership, but it is not explicit > that one receives the same discount as IPC members on publications. > > However, on the page about the certification packages, there is a list of > IPC publications for use in study for the exam, with "member" and > "nonmember" prices. The non-member prices are the same as are advertised to > the public. The member prices are half the nonmember prices. When I joined, > I got the $50 coupon plus I paid the member prices. I was told that this > was a benefit of membership. > > Perhaps only those specific publications are offered to DC members, which > would be a tad misleading > > [EMAIL PROTECTED] > Abdulrahman Lomax > P.O. Box 690 > El Verano, CA 95433 > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Layer Stackup Info.
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Re: [PEDA] Layer Stackup Info.
Jeff, I think you are referring to IPC- Sectional Design Standard for Rigid Organic Printed Boards. I do not have the standard in front of me, but I believe the tables you are looking for are in there. For a hard copy it is $15 member price and $30 for a non-member price. If you join the designers council you can buy the standards for PWB design at member prices. Regards, Ted -Original Message- From: Jeff Adolphs [mailto:[EMAIL PROTECTED]] Sent: Monday, July 09, 2001 8:22 AM To: Protel EDA Forum (E-mail) Subject: [PEDA] Layer Stackup Info. Hello, What IPC Standard shows core and prepreg sizes? I have IPC-6011, IPC-6012A, and IPC-2221 which do not have this information. ( at a IPC workshop I was shown some slash sheet that had the sizes and told it was in IPC-6011 but I don't see it there, I also got the impression I was an idiot for not having all the IPC standards --I don't work for a large company that buys everything and my company won't buy me $400 design guides!! It wasn't easy to get the standards I have and frustrating when I buy the wrong ones.) I have been told I should be telling on the Fab Layer the Layer Stackup Info. I have only been specifying two thicknesses 0.080 +/- 0.006" or 0.062 +/- 0.006". The problem is I don't know the core and prepreg sizes. The second problem is I don't know the PCB manufacturers stocked core and prepreg sizes. Finding out what cores and prepreg sizes are stocked at the PCB manufacturers will be time consuming and a pain in the $#&. I have had trouble with 0.080 +/- 0.006 PCBs coming in as 0.062 or 0.092 which is out of my specification. Sincerely, Jeff Adolphs Lake Shore Cryotronics, Inc. Westerville, Ohio, USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] BGA Design
What about Protel recently acquiring Tasking for 38 mill., or the recent partnership with P-CAD 2001 That will put a dent in you're pocket. Ted -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Friday, May 04, 2001 3:56 PM To: Protel EDA Forum Subject: Re: [PEDA] BGA Design At 09:06 AM 5/4/01 +0100, [EMAIL PROTECTED] wrote: >But, when talking about SPECCTRA, >did you find an alternative similarly mighty? I would appreciate to find >one, as we need to upgrade our SPECCTRA license just now and their prices >are extreme. How about Protel a few months from now? The rumor is that Protel will soon be issuing a service pack with a major autorouter overhaul. A Protel employee indicated to me that he had used it and it was comparable to Specctra. Now, this is *rumor.* My memory might be bad, the employee might be exaggerating. But I think any Protel licensee who is now considering Specctra should be aware of the possibility that this rumor is true. After all, the price is right. If it does come out as a service pack, it's free to existing licensees. It might explain the coming price rise. An improved router would definitely be worth $2K more. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] BGA Design
Emanuel, I use Protel, here is the forum email address http://groups.yahoo.com/group/protel-users/files/protelfaq.html If you can find out anything you need from layout problems to bug's. You will also get a faster response to your question then if you went to Protel directly. As for the set up for doing a ball grid in Protel, Do your fan out in the library and place the vias as well (if you plan to use the auto router, sometimes the tracks you lock have a tendency to move) Protel has a hard time with arcs as well. As for Spectra there are a few problems with importing the design when you have blind and buried vias. The forum archive can help you on that. If you use a lot of design rules have a lot of memory handy Protel will chew it up like a sumo wrestler at an all you can eat buffet. If you have any questions you can e-mail me and I will try to help all I can, but your best bet is to jump on the forum. [EMAIL PROTECTED] Ted T -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Friday, May 04, 2001 3:06 AM To: Protel EDA Forum Subject: Re: [PEDA] BGA Design Emanuel, some of the design rules export ok, others don't. Vias do, as for my experience. They don't translate back to Protel without problem, though, so you have to check and apply some glpbal changes to them after reimport, before you can do manual changes or ERC. So, I agree, it takes some pages of .do-file to write to be successful. But, when talking about SPECCTRA, did you find an alternative similarly mighty? I would appreciate to find one, as we need to upgrade our SPECCTRA license just now and their prices are extreme. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] BGA Design
Sorry to everyone I thought this post came from another forum the IPC tech net. Hey it's FRI day Ted T -Original Message- From: Ted Tontis [mailto:[EMAIL PROTECTED]] Sent: Friday, May 04, 2001 9:26 AM To: 'Protel EDA Forum' Subject: Re: [PEDA] BGA Design Emanuel, I use Protel, here is the forum email address http://groups.yahoo.com/group/protel-users/files/protelfaq.html If you can find out anything you need from layout problems to bug's. You will also get a faster response to your question then if you went to Protel directly. As for the set up for doing a ball grid in Protel, Do your fan out in the library and place the vias as well (if you plan to use the auto router, sometimes the tracks you lock have a tendency to move) Protel has a hard time with arcs as well. As for Spectra there are a few problems with importing the design when you have blind and buried vias. The forum archive can help you on that. If you use a lot of design rules have a lot of memory handy Protel will chew it up like a sumo wrestler at an all you can eat buffet. If you have any questions you can e-mail me and I will try to help all I can, but your best bet is to jump on the forum. [EMAIL PROTECTED] Ted T -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Friday, May 04, 2001 3:06 AM To: Protel EDA Forum Subject: Re: [PEDA] BGA Design Emanuel, some of the design rules export ok, others don't. Vias do, as for my experience. They don't translate back to Protel without problem, though, so you have to check and apply some glpbal changes to them after reimport, before you can do manual changes or ERC. So, I agree, it takes some pages of .do-file to write to be successful. But, when talking about SPECCTRA, did you find an alternative similarly mighty? I would appreciate to find one, as we need to upgrade our SPECCTRA license just now and their prices are extreme. Regards, Gisbert * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] importing DWG files
I want to thank everyone for the information. The Eagle file was in inches, and when I imported the file into Protel I left the default's on (which measured everything in mils). Taking Ian's advice I reimported the file in mm and everything measured out right. Thank you, Ted -Original Message- From: Jim McGrath [mailto:[EMAIL PROTECTED]] Sent: Tuesday, May 01, 2001 4:22 PM To: Protel EDA Forum Subject: Re: [PEDA] importing DWG files Ted, Is the Eagle file in mm and the Protel set to inches? I have seen this cause a problem. Regards, Jim Ted Tontis wrote: > I am trying to import a DWG file in to Protel. I have a board in Eagle and I > am trying to import the board out line and component placement into Protel. > When I import the file the scale is lost, The board increases in size. Is > there a way to import the drawing in the same scale it was originally drawn > in? > > Thank you, > > Ted Tontis > Engage Networks Inc. > [EMAIL PROTECTED] > PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Protel flyer in the mail.
I received the flyer too, It did not include the upgrade price. It was just the price increase of 99SE and the fact that they are offering camtastic with it. There was no mention of an upgrade, but I did talk to a sales rep a month or two ago and they informed me that Protel was working on something that should be released this month or the next. Did Protel offer a beta version of 99SE? Has anyone heard different? Ted -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Tuesday, May 01, 2001 3:34 PM To: Protel EDA Forum Subject: Re: [PEDA] Protel flyer in the mail. At 12:01 PM 5/1/01 -0700, Tony Karavidas wrote: >Has everyone received the price increase flyer from Protel? I wonder how >expensive our next 'upgrade' will be? I haven't. So how about sharing the information, Mr. Karavidas? Without that information, I'm going to guess that the next upgrade will be $1000 to $1500. Remember that Protel99/99SE was $995 at first, then on special for $695, then back to $995 until after the SE release, then the present $1495. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Crash While Netlisting
Gordon, I believe I have had this problem before, it related to my library files. I had a library active that did not have any information in it. It was empty, Every time I would try to produce a net list the computer would lock up. If I closed it reopened it I will still get the same results. good luck, Ted -Original Message- From: Le, Phan [mailto:[EMAIL PROTECTED]] Sent: Tuesday, May 01, 2001 12:11 PM To: 'Protel EDA Forum' Subject: Re: [PEDA] Crash While Netlisting Gordon, I found the same problem with memory leak & I increased virtual memory to 1G as well. The problem only occurs if you pour copper plane on complex board many time without closing Protel. As you pour copper plane, the memory increase but never get release it after the operation is done. Eventually, your computer will crash. Sound like leaky condo business. :) Cheers, Phan -Original Message- From: Gordon Price [mailto:[EMAIL PROTECTED]] Sent: Tuesday, May 01, 2001 09:18 To: 'Protel EDA Forum' Subject: Re: [PEDA] Crash While Netlisting Jim, Been there, got the hat, got the shirt! I found that the virtual disk swap space had to be increased on my machine to 1 gig.(using NT2000 professional) The problem is an apparent memory overflow and/or leaky code from hell.(otherwise known as BAD CODE!) From a professional point of view, I find it un-acceptable! The number of components/traces/vias and other mystery routing issues will make the problem surface at different design complexity levels. I also have a design where the schematic has 2 wires that will not show up on the board netlist, even after re-drawing them. Naturally they will not route if they are not on the netlist. I am on a mission to get PROTEL awareness of these nasty bugs! No luck yet! Good Luck, R. Gordon Price Director of Research Engineering Loronix Information Systems, Inc. (858) 523-9424 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] importing DWG files
I am trying to import a DWG file in to Protel. I have a board in Eagle and I am trying to import the board out line and component placement into Protel. When I import the file the scale is lost, The board increases in size. Is there a way to import the drawing in the same scale it was originally drawn in? Thank you, Ted Tontis Engage Networks Inc. [EMAIL PROTECTED] PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Memory Error
I am running Protel 99SE SPK6 on W2K. After closing Protel down and open another application that takes up a large amount of memory, I get a memory error. This is the first time I opened the task manager to see what was eating all the memory. I found Protel was still sucking memory even though it was closed. Any how I ended the process, shut down the computer and started it back up again. Opened Protel again did some work, saved it and closed it out, shut down windows again and the program still running window pops up. Is there a setting that I may have messed up that my be causing this? Has anyone experienced this before? Thank you in advance, Ted Tontis Engage Networks Inc. [EMAIL PROTECTED] PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Is anybody else getting double posts on all the posts?
not here Ted -Original Message- From: Michael Reynolds [mailto:[EMAIL PROTECTED]] Sent: Thursday, April 05, 2001 9:01 AM To: '[EMAIL PROTECTED] ' Subject: [PEDA] Is anybody else getting double posts on all the posts? Mike Reynolds Blazie Engineering, a division of Freedom Scientific 2850 SE Market Place Stuart, FL 34997 561-223-6443 FAX 561-223-6413 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] template graphics
Have you tried to import the graphic into a commonly used library? this way all you have to do is start a library and it is all ways there, click on the name and you can place it. When the sch. loads it can pull the graphic from the library. Ted -Original Message- From: Ian Middleton [mailto:[EMAIL PROTECTED]] Sent: Thursday, April 05, 2001 6:47 AM To: Protel EDA Forum Subject: Re: [PEDA] template graphics To solve this missing "graphics" problem I used the ploygon drawing tools to draw our company logo on the template sheets. This works every time. I also tried creating our company logo as a schematic component (so that it may be easily used elsewhere on schematics as needed) but that also fails in a similar way to the graphics on the template sheets. Ian > -Original Message- > From: Coleman, Tim [mailto:[EMAIL PROTECTED]] > Sent: 05 April 2001 10:58 > To: Protel EDA Forum > Subject: Re: [PEDA] template graphics > > > Dear Abdl, > > Like you I recongnise the need to chose the right tools. However MOST > engineers don't have a choice in the EDA tools the use, having > been selected > by someone else and a company with lots of investment in a certain tool is > not always keen to simly dump a tool for a better one. > > However, in my case and for the firt time ever, I was responsible for > finding a new EDA tool for the company, to replace an existing > older system. > I spent some time trying various different tools, looking at cost and > performance. Protel came out tops, it did all that ORCAD, it's nearest > rival, did and was cheeper! I was reallly pleased to find such a good EDA > tool at a good price. However it is not easy to find all the bugs (sorry > un-documented or un-implented features) in a 30 day period when you have a > bunch of other EDAs to review aswell. I am not so nieve to think > that there > is an EDA tool out there without some 'bugs' and I realise that test and > de-bugging cost time and money. I am just a little frustrated at > the number > of bugs that are being found by myself and my co-workers who use this tool > since we really started to use it. On balance I still stand by my choice. > Yesterday I had just too much crap coming my way because of Protel. > > In regard to my problem, I have copied all our engineers with a copy of > Company templates database and the requisit company logo graphic and told > them to place it in the system directory in its own template > directory. This > means that whenever and wherever a database is opened it looks for the > template and graphic and finds them where it expects to since all the > machines have the same set-up. > > Problem solved. > > TC > > -Original Message- > From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] > Sent: Thursday, April 05, 2001 12:35 AM > To: Protel EDA Forum > Subject: Re: [PEDA] template graphics > > > At 01:36 PM 4/4/01 +0100, you wrote: > > >Why is it that when I create a template with a company logo > graphic and use > >it for a schematic and then, when I send the databas to another > person, the > >graphic image is no longer on the schematic? I have loaded a copy of the > >graphic image into the DB but I can't make the browser point at stuff > inside > >the DB, only outside it. > > > >Anyone know what the problem is? anyone know what can be done to > solve it? > > > >The more I use this product the less satisfied I am with it. It's a bit > half > >baked. > > Perhaps, but more often it is we who are half-baked. > > In this case Protel does not embed the graphics into the file, > and it does > not look for a file in the database when placing the graphic. I'd agree > that it should do the second of these, but this is a missing > feature, not a > bug, per se. Send the logo graphic separately. > > The database format is new and it looks like the routines to look > inside a > database for a graphics file are simply not there. Since this has been > brought up before, perhaps we will see this in an upcoming service pack. > (If it hasn't already been fixed, I did not check, and the writer did not > say what SP level he has installed.) > > Protel has a choice of one of two things: it can spend the time and money > to make sure that everything is perfect before releasing the > product, or it > can release it with something short of perfection (i.e., with > undiscovered > problems that are not found in beta-test or that would take too long to > fix). I'm glad that they chose the second option, because if they had > chosen the first, the product would either have an astronomical > price, or, > more likely, it simply would not exist since the company would have gone > bankrupt long ago. > > I'm a craftsman; when something goes wrong, I don't blame my > tools. It's my > responsibility to choose tools adequate for the job, and to learn how to > use them, including all their quirks and foibles. And every tool > has these. > > If Protel were not readily and easily usable for accomplishing > its p
[PEDA] Arc's in the keepout
I have a design that has arc's in the keepout, and noticed that Protel will not recognize it exists. The only thing I can do is put temporary traces around the edge of the board and remove them after I am done with the design or auto router. Does anyone have a better idea to resolve this problem? Ted Tontis Engage Networks Inc. [EMAIL PROTECTED] PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] moving a component and tracks at the same time
I would like to move a component that has tracks attached to it. I would like to move them at the same time. I am trying to avoid replacing all the tracks and vias. Is this possible, has anyone tried this? I would appreciate any help that I could get. Thank you, Ted Tontis Engage Networks Inc. [EMAIL PROTECTED] PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Finding & Setting Test Points
Dave, The sights that are going to be your test points have to fall on the test point grid. If they do not you get a test point violation. You have to move the pad or via to the 1 mill grid, this will correct the problem you are seeing. Ted -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]] Sent: Monday, April 02, 2001 5:33 AM To: [EMAIL PROTECTED] Subject: [PEDA] Finding & Setting Test Points Hi, I'm currently having a lot of trouble setting test points on my current PCB. I've set up rules to allow a single test point per net, bottom layer only for SMD and thru-hole pads. The test point grid is set to 1mil. On selecting Find & Set Test Points from the Tools menu, a number of testpoints are set which adhere to the rules. I've noticed that on double clicking on these testpoints to view their properties and then closing the dialogue box using OK, the testpoint then appears as a Testpoint Style violation. Closing the dialogue box using Cancel does not cause a violation. Has anyone else experienced this problem? The reason for my wanting to view the properties of the set testpoints is that only 30 testpoints have been found out of 227. By viewing the properties I was hoping to determine the difference between vias set as testpoints and those not. As far as I can see there is no reason for the failure to set more testpoints. Am I wasting my time using feature? Cheers Dave CONFIDENTIALITY : This e-mail and any attachments are confidential and may be privileged. If you are not a named recipient, please notify the sender immediately and do not disclose the contents to another person, use it for any purpose or store or copy the information in any medium. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Memory Error
Thank you for the information I thought I was the only one. Ted -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED]] Sent: Monday, March 26, 2001 1:46 PM To: Protel EDA Forum Subject: Re: [PEDA] Memory Error I've seen this with Protel since the release of P98. It happens occasionally after quitting. The client99.exe will not release, even after a few minutes. The only thing you can do if it doesn't disappear after a few minutes is to kill the client99.exe process. Having your virtual / swap memory file set to at least double your system memory helps. I prefer 1023 megabytes on your fastest NTFS drive regardless of your system memory size. _ Brian Guralnick - Original Message ----- From: "Ted Tontis" <[EMAIL PROTECTED]> To: "Protel Forum (E-mail)" <[EMAIL PROTECTED]> Sent: Monday, March 26, 2001 2:20 PM Subject: [PEDA] Memory Error > I am running Protel 99SE SPK6 on W2K. After closing Protel down and > open another application that takes up a large amount of memory, I get a > memory error. This is the first time I opened the task manager to see what > was eating all the memory. I found Protel was still sucking memory even > though it was closed. Any how I ended the process, shut down the computer > and started it back up again. Opened Protel again did some work, saved it > and closed it out, shut down windows again and the program still running > window pops up. > Is there a setting that I may have messed up that my be causing > this? Has anyone experienced this before? > > Thank you in advance, > > Ted Tontis > Engage Networks Inc. > [EMAIL PROTECTED] > PH 414.273.7600 Ext. 7607<http://www.engagenet.com> > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Where did this come from "nobody@????.com"
was there a attachment? if not then it can not be a virus. Ted -Original Message- From: Brian Guralnick [mailto:[EMAIL PROTECTED]] Sent: Monday, March 26, 2001 1:48 PM To: Protel EDA Forum Subject: Re: [PEDA] Where did this come from "nobody@.com" No, sounds like a potential email virus which one of our members might have. _ Brian Guralnick - Original Message - From: "Jenkins, Charlie" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Monday, March 26, 2001 2:31 PM Subject: [PEDA] Where did this come from "nobody@.com" > Did anyone else get these emails? They slipped in under the "[PEDA]" filter > that grabs my list traffic. I got three emails with this as the from/to. > The message was a portion of the floating lic thread. One contained the > list, the other two from individuals. > No harm, just curious. > > Charlie Jenkins, Pioneer Standard > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Arc's in the keepout
The only other thing I tried to do was put a square keepout around the board and try to place a polygon plane on the outside of the board. I couldn't get it to work right. This is not a round board, it has three arcs both + and -, and I chose to use Arc Any Angle. I do not know if this has a different effect then using place an arc. Ted -Original Message- From: David Cary [mailto:[EMAIL PROTECTED]] Sent: Tuesday, March 27, 2001 12:04 PM To: Protel EDA Forum Subject: Re: [PEDA] Arc's in the keepout Ted Tontis <[EMAIL PROTECTED]> on 2001-03-27 09:21:49 AM noted: >I have a design that has arc's in the keepout, and noticed that >Protel will not recognize it exists. The only thing I can do is put >temporary traces around the edge of the board and remove them after I am >done with the design or auto router. >Does anyone have a better idea Sounds like a bug. I have a circular board, and my circular keepout blocks polygon pours just fine. Is the bug just in the autorouter, or does it also affect manual routing ? Just a work-around until Protel fixes this bug: Put temporary keep-out ``traces'' (a bunch of short, straight lines that approximate the curve) around the edge of the board, and leave them there. Click the "KeepOutLayer" tab near the bottom of the screen, then " P (Place) T (Interactive Routing) ", click on one end of the curve, hit Ctrl+Spacebar until you get the straight-line mode, then click click click on a few points along the curve; after you hit the end, "Esc Esc". I've been told that early versions of Autocad couldn't draw true circles -- it drew 32 sided polygons instead -- but most people never noticed that the "circles" weren't true circles. Have you played with layer-specific keepouts ? For example, pick the "BottomLayer" tab and use "P (Place) K (Keepout) T (track)" -- those tracks block stuff on the bottom layer, but let stuff on the top layer through. -- David Cary * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Memory Error
I have not contacted Protel regarding this problem because I have been running SP6 since it first came out and I have been running 99SE on W2K since I started using Protel. This is the first time I encountered the problem, I wanted to rule out the possibility it I was the cause of the problem. That's why before I posted the problem I reinstalled Protel and SP6 to rule myself out, then contact the group to make sure I was not the only one experiencing the problem. Nothing like telling Protel you have a possible bug, and there reply, read the owners manual, most likely user error. Ted -Original Message- From: Andrew J Jenkins [mailto:[EMAIL PROTECTED]] Sent: Monday, March 26, 2001 2:42 PM To: Protel EDA Forum Subject: Re: [PEDA] Memory Error On 01:20 PM 3/26/01 -0600, Ted Tontis said: > I am running Protel 99SE SPK6 on W2K. After closing Protel down and >open another application that takes up a large amount of memory, I get a >memory error. This is the first time I opened the task manager to see what >was eating all the memory. I found Protel was still sucking memory even >though it was closed. It was not, in fact closed, but had crashed. This actually happens quite often with Protel, at least under W95, NT4, and Win2k. I run into to it frequently, and I suspect that many others do, though I also suspect that they have no idea that it's happening most of the time. The program is choking on exit. IMO, it's just more of Delphi's questionable memory management (spelled: heap fragmentation errors galore) scheme at work, showing off it's prowess at causing problems. I know of only one other applications in my experience which shows the same proclivity towards these errors, and it is also written in...you guessed it...Delphi. "Programmers like it!" is not the same thing as "stable" or "dependable" or "enjoyed by the end-user". Hmm.. that one ought'a generate a few snarling flames... In terms of the immediate reoccurrence of this problem (which indeed I do NOT experience with any regularity), have you contacted Protel directly on the issue yet? If not, do so now. ! But first... On the chance that this problem has already been addressed by Protel, which service pack is your system operating under? I hope I am about to read "SP6, of course!" regards, Andrew J Jenkins. NCMR @ NASA-GRC [EMAIL PROTECTED] The opinions expressed herein are soley mine and do not represent the views of my employer, nor the views of its employer. This email and its content may not be redistributed to ANY third party for ANY reason without first securing a signed authorization from the author. Failure to abide by these terms may result in legal remediation against the offending party, at the sole discretion of the author. This is not public domain information. Standard commercial- use disclaimers apply. Commercial use requires author approval. If you cannot abide by the full aspect of this disclaimer, immediately delete the message, as you have no rights to its contents. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] PCB autoroute Net : unable to initialize
I have been able to route a single net, click on auto route, select route net, click on the net you want, and then select connection. Works every time. Hope this helps Ted -Original Message- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: Wednesday, March 28, 2001 6:07 AM To: Protel EDA Forum Subject: Re: [PEDA] PCB autoroute Net : unable to initialize On 09:56 AM 28/03/2001 +0100, Graziella COMISSO said: >Hello All! >When I'm trying to autouroute a single object :Net, component, connection. >I receive the following message >"Unable to initialize." >But If I select autouroute all, it's going right. >Does anyone can help me to understand what's wrong in my project? >Thank you.. > >Graziella I do not think that the autorouter options really work - apart from Route-All and that is touchy. I have had no success with anything but Route-All. (For me, Route-Area, if it starts, always routes the whole board). Don't blame yourself - blame the autorouter. I expect we will be seeing big improvements to this - as I would think Protel is falling behind in the autorouter area. But that doesn't help you. If anyone knows how to get anything but Route-all to go please tell us ... Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] BOM
There is a BITMAP importer that is on the download page for the Protel forum. If you have access to a scanner, print out your spreadsheet scan it in as a BITMAP and then import it into your PCB using the importer. I do not know of another way to save spreadsheets as Bitmap's. Ted -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Tuesday, March 20, 2001 8:09 PM To: Protel EDA Forum Subject: Re: [PEDA] BOM At 02:56 PM 3/20/01 -0600, [EMAIL PROTECTED] wrote: >I would like to create a Bill Of Materials from the schematic, and import >it directly into the assembly drawing. > >Is there a way to do this, and could someone please help. As others have said, there is no direct way, at least not as far as I am aware. If one has a way of importing a text file into .DXF, then .DXF could be imported into PCB. I'm assuming that the "assembly drawing" is to be prepared in PCB. It would also not be difficult to write a utility to convert a text file to a set of string primitives to be copied onto the assembly drawing. If all the formatting were done in a text or spreadsheet editor (including converting tabs into spaces, which Excel can easily do), the strings could simply be lifted from the text file, line by line, and popped into an ASCII format PCB file, which could then be loaded and copied into the assembly drawing. One does not need to know much about the Protel file format to do this. Just place a string in an empty PCB file, save it in the ASCII format, and open it with a text editor. The ASCII database is self-documenting. You could even do the insertion using Excel; no programming would be necessary. But I just print separate BOMs. It takes less time and is not necessarily less efficient. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] MM's VS Mils
If I may, when I have a data sheet that has been designed in mm and it is a fine pitch component I use a excel spread sheet to confirm the change over. Here is an example Millimeters Meters Inches Mil (0.001 in) 0.0011.000E-06 39.370E-060.039370 0.0022.000E-06 78.740E-060.078740 0.0033.000E-06 118.110E-06 0.118110I have not had a problem yet (knock on wood). For what it's worth, Ted -Original Message- From: Abd ul-Rahman Lomax [mailto:[EMAIL PROTECTED]] Sent: Thursday, March 15, 2001 1:58 PM To: Protel EDA Forum Subject: Re: [PEDA] MM's VS Mils At 08:41 PM 3/15/01 +1100, Les Grant wrote: >Perhaps I have missed something here but are you implying that >conversion from metric is exact but conversion from imperial is >approximate? 1 inch = 1000 mil = 25.4mm exactly, both ways. So conversion from inch to mm is exact. But what about the other way? If Protel supported divisors for distances, i.e., the use of fractions, then one could get exact conversions in both directions, it would not matter. It would not be difficult to implement that, by the way. One would break the dimension field into two fields; the default for the second field would be 1, but if it was present and was not one, dimensions would be converted by division. Remember that we are talking about database units, not necessarily what is displayed. However, Protel presently uses a database unit of a small decimal fraction of an inch. I think it is one microinch, but it might be smaller than that; I've done some experimentation with this, but I don't remember the results right now. Actually, the units are mils, but there is then three decimal place precision. For a while there, the database was floating point, which was interesting, but I think they changed it back. Metric dimensions (in mm) are translated into the database units by dividing them by 0.0254. So if I enter 1 mm, it will become 39.370 mils, which is pretty accurate. But it is not exact; an error of approximately 0.078 microinch is introduced, which is 0.002 mm. When the number is translated back into mm, it becomes 0.98 mm. That is only 2 nanometers off, but, especially when accumulated, it can knock the displayed mm measurements off, as we frequently see. However, the problem might also be addressed by intelligent rounding of the mm display. If the database precision is 1 microinch, we only have a real resolution in mm of 0.040 mm, so display of mm to three decimal places or beyond is meaningless. If the mm figures were rounded (not truncated) to two places I think that conversions within the 100 inch workspace would remain accurate; but I have not thoroughly investigated this. Intelligent rounding would avoid the necessity of changing and testing all the myriad routines which use locations. [EMAIL PROTECTED] Abdulrahman Lomax P.O. Box 690 El Verano, CA 95433 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] DRC error message
If the DRC is not set to write to a report, you will not get a DRC report. To set it up go into Design, select Design rule check, and see if there is a check box in the create report file. As for the protected file, are you running this on a network? If so someone maybe in the same file which would block you out, or you are not set up to save or change anything. Ted -Original Message- From: Roger McLain [mailto:[EMAIL PROTECTED]] Sent: Wednesday, March 14, 2001 10:49 AM To: Protel User's (E-mail) Subject: [PEDA] DRC error message After finishing a rather large surface mount board, I ran a DRC and received a error message "attempted to write or delete a protected file or directory" immediately before the program ran. After the DRC ran it did not give a report. Does anyone know why this message came up and why no report ? I'm using P98, SP3. Thanks. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Copy from/to PCB
You may want to try to using the save as, change the name of your new board, then export it to your desktop, and then import into your new data base. Ted -Original Message- From: Rudolf Schaffer [mailto:[EMAIL PROTECTED]] Sent: Tuesday, March 13, 2001 8:06 AM To: Protel EDA Forum Subject: Re: [PEDA] Copy from/to PCB Ian Wilson wrote: > > 1) Select everything you wish to copy: tracks, pads, vias, components, poly > pours etc. > 2) Ctrl-C or Ctrl-Ins (or Edit|Copy) to choose a reference point. > 3) go to the new location > 4) Edit|Paste Special... and ensure that Keep Net Names is selected. (If > panelising you may also want to check Allow Duplicate Designators.) > 5) Hit enter and position it where you want. > > There is one issue (at least) that can be a problem - copy and paste does > not copy the rules that apply to the entities you have copied. Such things > as plane expansions and polygon pour clearances etc. You can export the > rules from the original and import into the new - but if a rule refers to > something not in the new design (such as a specific pad) who knows what > Protel will do. Past form has suggested that defensive programming may not > be undertaken and there might be a nice crash - but then again maybe rule > importing is more robust than that - try it. > > Suggestion: I would like an extra option on the paste special menu - copy > all applicable rules. If you right click on an object in PCB you can get > it to list the applicable unary and binary rules - so Protel has already > solved the issue of working out what rules to copy. > > Ian, Thank very much you for your answer! I tried just before my call for help with Paste Special command but i received a lot of DRC and missing traces! I "just" forgotted to set the correct design rules and stack layer for my new design!!! For this reason, i totally agree with your suggestion to include all applicable rules as an option. (Maybe used layers could be activated if possible, as the source, like a starting default configuration ?) Best regards, Rudy ASGALIUM UNITEC SA Rue du Puits-Godet 8a CH-2000 NEUCHATEL tel +41 32 7240066 fax +41 32 7240078 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To join or leave this list visit: * http://www.techservinc.com/protelusers/subscrib.html * - or email - * mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] [PROTEL EDA USERS]: Autorouter recommendations.
[PEDA] [PROTEL EDA USERS]: is anyone getting my e-mails
I just received a e-mail I sent a week ago and it never made it through. Just wanted to make sure. Ted Tontis Design Engineer Engage Networks Inc. [EMAIL PROTECTED] PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the "reply" command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]'
Re: [PEDA] [PROTEL EDA USERS]: newbie can't get power and groundplanes to connect up
double click on the error mark and it will tell you what the error is. Have you checked to see if a junction point is in the wrong spot. I have made that mistake a couple of times and had a similar problem. Ted -Original Message- From: Gordon Price [mailto:[EMAIL PROTECTED]] Sent: Tuesday, February 27, 2001 3:06 PM To: Multiple recipients of list proteledausers Subject: RE: [PROTEL EDA USERS]: newbie can't get power and ground planes to connect up Colby, Thanks for the tip. I have 11 errors of which 7 are net names on short wires to pins on a FPGA that are not used yet. I figured these were safe and had nothing to do with my power plane and ground plane connectivity problems. Four of the errors are pins of an FPGA that go through wires clearly to a power ground symbol on the schematic. The error report says that the node EA21 can not be found for these 4 pins. I do not know what net EA21 is or why it is not "GND". If you double click on the ground symbol on the schematic, the box says that it is a member of net "GND", which is correct. My schematic now has little red circles with a red x inside on certain unconnected pins and some connected pins. What are these little red circles?? Error flages of some kind??? Is there a way to have 99SE re-figure everything from scratch? I am still stumped. Thanks, R. Gordon Price -Original Message- From: Colby - PowerStream [mailto:[EMAIL PROTECTED]] Sent: Tuesday, February 27, 2001 2:18 PM To: Multiple recipients of list proteledausers Subject: Re: [PROTEL EDA USERS]: newbie can't get power and ground planes to connect up Gordon, With the Synchronizer always do a Preview Changes before executing. When the Changes Tab pops up with the macro list you will see a Only Show Errors checkbox. Check this. There is also a report button to generate a report from this. If you still have trouble after you have checked the netlist errors post what you found. Also... not sure if this applies. But do not connect Power Ports directly to pins, always run a small piece of wire from the pin... I seem to remember it not connecting properly if conencted directly to the pin. Power Ports are essentially netlabels with a visual symbol for the power type chosen. -- Colby Siemer** Custom Battery Chargers ** Custom Power Supplies PowerStream Technology ** Custom UPS 140 S. Mountainway Drive ** Custom DC/DC Converters Orem Utah 84058 ** Power management electronics for OEMs http://www.PowerStream.com - Original Message - From: Gordon Price <[EMAIL PROTECTED]> To: Multiple recipients of list proteledausers <[EMAIL PROTECTED]> Sent: Tuesday, February 27, 2001 12:21 PM Subject: [PROTEL EDA USERS]: newbie can't get power and ground planes to connect up > Hi Everyone, > I thought I was paying close attention to all the chatter on this > net but apparently I have missed the boat again. I have a master schematic > and 4 (flat) sub schematics that globally reference the following net names > I have defined:(using 99SE SP6) > GND > +1.8V > +3.3V > +5V > When I go to update the PCB from the schematic, I get a macro error > that asks me if I want to continue.(Right here is where I would like to know > what the complaints are but I can't seem to find an error report) >If I continue I find that even though I don't see any missing parts or > footprints, that when I route the board, the ground and power planes that I > created in the layer stack manager do not connect up, but rather, ground > pins are connected by signal traces rather than to the planes. > The online help seems to talk about different conditions than what I > see on my dialogue boxes. When I try to edit the properties of the internal > power planes, the drop down box does not show the +3.3V net name or anything > for the power ground net GND. > Obviously, the macro errors at update time are the problem, but I > don't know how to view the errors or see what is really wrong. I have set up > my design rules and the board will route 100% and all the parts seem to ALL > be there. > I know Protel has it's own power and ground rules but I have not > made sense of them yet. I have set the net name on the power ground symbol > to "GND" and have used the power arrow symbol with the above net names. > One thing I have done is put power and ground pins on my schematic > library parts so I can see them on the schematic. I then place a net label > on a wire going to the power pin. I did not put a net label on the ground > symbol other than the properties box when you add a ground to the actual > schematic. > > Thanks, > R. Gordon Price > Director of Research Engineering > Loronix Information Systems, Inc. > Del Mar CA > [EMAIL PROTECTED] > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * > * This message sent by: P
[PEDA] [PROTEL EDA USERS]: Forum question
When I first signed up for this forum I received a daily archive that contained all the questions and answers from the group for that day. I did not receive daily e-mails that where posted from each member. I canceled my subscription to the group and rejoined, so that I could get the min to min updates. Now I no longer get the daily archive, Has anyone seen this before and is there a way to get that archive back and still have the constant e-mails? Ted Tontis Design Engineer Engage Networks Inc. [EMAIL PROTECTED] PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the "reply" command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
[PEDA] [PROTEL EDA USERS]: simulation software
My Co. decided to spring for some simulation software (thermo and signal integrity), and I wanted to get the group's thought's. 1. What is the best 2. What works with Protel (this is not requirement but would be nice) 3. How much 4. Price/Performance 5. The ability for the software to give advice on solving a trouble spot. You're advice would be greatly appreciated, I do not have the time to download trial software and test it myself. Who knows how long there pocket's will stay open for. Thank you, Ted Tontis Design Engineer Engage Networks Inc. [EMAIL PROTECTED] PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the "reply" command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
[PEDA] [PROTEL EDA USERS]: polygon pore
I disabled my global clearance constraint. Thanks for the help, Ted Tontis Design Engineer Engage Networks Inc. [EMAIL PROTECTED] PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the "reply" command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
[PEDA] [PROTEL EDA USERS]: Polygon plane problem
I think someone already covered this problem, I could not find the response to it. I am running 99SE with service pack 6 on windows 2k, I did my whole project on this setup. I am now trying to pore a polygon plane and I am not getting anywhere with it. When pored on the top layer of my board it fails to leave a gap between the vias and traces leading to other parts. when I double click on the pad or via on the plane I get a DRC error (short circuit) when I double click on the polygon (one trace of it) it has no net value. I have tried to pore it a number of times and still the same results. I imported the Ddb to a computer running 99SE service pack 5 and still I get the same results. I sent Protel a e-mail regarding this but I do not expect them to get right on it. I hope anyone might have a idea or something to help me get this problem fixed, they want to get this board into the proto shop some time this week. Thank you, Ted Tontis Design Engineer Engage Networks Inc. [EMAIL PROTECTED] PH 414.273.7600 Ext. 7607<http://www.engagenet.com> * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * This message sent by: PROTEL EDA USERS MAILING LIST * * Use the "reply" command in your email program to * respond to this message. * * To unsubscribe from this mailing list use the form at * the Association web site. You will need to give the same * email address you originally used to subscribe (do not * give an alias unless it was used to subscribe). * * Visit http://www.techservinc.com/protelusers/subscrib.html * to unsubscribe or to subscribe a new email address. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To leave the EDAFORUM discussion list, send a email with 'leave edaforum' in the body to '[EMAIL PROTECTED]' More Information : http://www.dolist.net
